1fbb6c848SEzequiel Garcia // SPDX-License-Identifier: GPL-2.0 2fbb6c848SEzequiel Garcia /* 3fbb6c848SEzequiel Garcia * Hantro VPU codec driver 4fbb6c848SEzequiel Garcia * 5fbb6c848SEzequiel Garcia * Copyright (C) 2018 Collabora, Ltd. 6fbb6c848SEzequiel Garcia * Copyright 2018 Google LLC. 7fbb6c848SEzequiel Garcia * Tomasz Figa <tfiga@chromium.org> 8fbb6c848SEzequiel Garcia * 9fbb6c848SEzequiel Garcia * Based on s5p-mfc driver by Samsung Electronics Co., Ltd. 10fbb6c848SEzequiel Garcia * Copyright (C) 2011 Samsung Electronics Co., Ltd. 11fbb6c848SEzequiel Garcia */ 12fbb6c848SEzequiel Garcia 13fbb6c848SEzequiel Garcia #include <linux/clk.h> 14fbb6c848SEzequiel Garcia #include <linux/module.h> 15fbb6c848SEzequiel Garcia #include <linux/of.h> 16fbb6c848SEzequiel Garcia #include <linux/platform_device.h> 17fbb6c848SEzequiel Garcia #include <linux/pm.h> 18fbb6c848SEzequiel Garcia #include <linux/pm_runtime.h> 19fbb6c848SEzequiel Garcia #include <linux/slab.h> 20fbb6c848SEzequiel Garcia #include <linux/videodev2.h> 21fbb6c848SEzequiel Garcia #include <linux/workqueue.h> 22fbb6c848SEzequiel Garcia #include <media/v4l2-event.h> 23fbb6c848SEzequiel Garcia #include <media/v4l2-mem2mem.h> 24fbb6c848SEzequiel Garcia #include <media/videobuf2-core.h> 25fbb6c848SEzequiel Garcia #include <media/videobuf2-vmalloc.h> 26fbb6c848SEzequiel Garcia 27fbb6c848SEzequiel Garcia #include "hantro_v4l2.h" 28fbb6c848SEzequiel Garcia #include "hantro.h" 29fbb6c848SEzequiel Garcia #include "hantro_hw.h" 30fbb6c848SEzequiel Garcia 31fbb6c848SEzequiel Garcia #define DRIVER_NAME "hantro-vpu" 32fbb6c848SEzequiel Garcia 33fbb6c848SEzequiel Garcia int hantro_debug; 34fbb6c848SEzequiel Garcia module_param_named(debug, hantro_debug, int, 0644); 35fbb6c848SEzequiel Garcia MODULE_PARM_DESC(debug, 36fbb6c848SEzequiel Garcia "Debug level - higher value produces more verbose messages"); 37fbb6c848SEzequiel Garcia 38fbb6c848SEzequiel Garcia void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id) 39fbb6c848SEzequiel Garcia { 40fbb6c848SEzequiel Garcia struct v4l2_ctrl *ctrl; 41fbb6c848SEzequiel Garcia 42fbb6c848SEzequiel Garcia ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id); 43fbb6c848SEzequiel Garcia return ctrl ? ctrl->p_cur.p : NULL; 44fbb6c848SEzequiel Garcia } 45fbb6c848SEzequiel Garcia 46fbb6c848SEzequiel Garcia dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts) 47fbb6c848SEzequiel Garcia { 48fbb6c848SEzequiel Garcia struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx); 49fbb6c848SEzequiel Garcia struct vb2_buffer *buf; 50fbb6c848SEzequiel Garcia 51fbb6c848SEzequiel Garcia buf = vb2_find_buffer(q, ts); 52fbb6c848SEzequiel Garcia if (!buf) 53fbb6c848SEzequiel Garcia return 0; 54fbb6c848SEzequiel Garcia return hantro_get_dec_buf_addr(ctx, buf); 55fbb6c848SEzequiel Garcia } 56fbb6c848SEzequiel Garcia 57fbb6c848SEzequiel Garcia static const struct v4l2_event hantro_eos_event = { 58fbb6c848SEzequiel Garcia .type = V4L2_EVENT_EOS 59fbb6c848SEzequiel Garcia }; 60fbb6c848SEzequiel Garcia 61fbb6c848SEzequiel Garcia static void hantro_job_finish_no_pm(struct hantro_dev *vpu, 62fbb6c848SEzequiel Garcia struct hantro_ctx *ctx, 63fbb6c848SEzequiel Garcia enum vb2_buffer_state result) 64fbb6c848SEzequiel Garcia { 65fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src, *dst; 66fbb6c848SEzequiel Garcia 67fbb6c848SEzequiel Garcia src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 68fbb6c848SEzequiel Garcia dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 69fbb6c848SEzequiel Garcia 70fbb6c848SEzequiel Garcia if (WARN_ON(!src)) 71fbb6c848SEzequiel Garcia return; 72fbb6c848SEzequiel Garcia if (WARN_ON(!dst)) 73fbb6c848SEzequiel Garcia return; 74fbb6c848SEzequiel Garcia 75fbb6c848SEzequiel Garcia src->sequence = ctx->sequence_out++; 76fbb6c848SEzequiel Garcia dst->sequence = ctx->sequence_cap++; 77fbb6c848SEzequiel Garcia 78fbb6c848SEzequiel Garcia if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) { 79fbb6c848SEzequiel Garcia dst->flags |= V4L2_BUF_FLAG_LAST; 80fbb6c848SEzequiel Garcia v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event); 81fbb6c848SEzequiel Garcia v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx); 82fbb6c848SEzequiel Garcia } 83fbb6c848SEzequiel Garcia 84fbb6c848SEzequiel Garcia v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx, 85fbb6c848SEzequiel Garcia result); 86fbb6c848SEzequiel Garcia } 87fbb6c848SEzequiel Garcia 88fbb6c848SEzequiel Garcia static void hantro_job_finish(struct hantro_dev *vpu, 89fbb6c848SEzequiel Garcia struct hantro_ctx *ctx, 90fbb6c848SEzequiel Garcia enum vb2_buffer_state result) 91fbb6c848SEzequiel Garcia { 92fbb6c848SEzequiel Garcia pm_runtime_mark_last_busy(vpu->dev); 93fbb6c848SEzequiel Garcia pm_runtime_put_autosuspend(vpu->dev); 94fbb6c848SEzequiel Garcia 95fbb6c848SEzequiel Garcia clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks); 96fbb6c848SEzequiel Garcia 97fbb6c848SEzequiel Garcia hantro_job_finish_no_pm(vpu, ctx, result); 98fbb6c848SEzequiel Garcia } 99fbb6c848SEzequiel Garcia 100fbb6c848SEzequiel Garcia void hantro_irq_done(struct hantro_dev *vpu, 101fbb6c848SEzequiel Garcia enum vb2_buffer_state result) 102fbb6c848SEzequiel Garcia { 103fbb6c848SEzequiel Garcia struct hantro_ctx *ctx = 104fbb6c848SEzequiel Garcia v4l2_m2m_get_curr_priv(vpu->m2m_dev); 105fbb6c848SEzequiel Garcia 106fbb6c848SEzequiel Garcia /* 107fbb6c848SEzequiel Garcia * If cancel_delayed_work returns false 108fbb6c848SEzequiel Garcia * the timeout expired. The watchdog is running, 109fbb6c848SEzequiel Garcia * and will take care of finishing the job. 110fbb6c848SEzequiel Garcia */ 111fbb6c848SEzequiel Garcia if (cancel_delayed_work(&vpu->watchdog_work)) { 112fbb6c848SEzequiel Garcia if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done) 113fbb6c848SEzequiel Garcia ctx->codec_ops->done(ctx); 114fbb6c848SEzequiel Garcia hantro_job_finish(vpu, ctx, result); 115fbb6c848SEzequiel Garcia } 116fbb6c848SEzequiel Garcia } 117fbb6c848SEzequiel Garcia 118fbb6c848SEzequiel Garcia void hantro_watchdog(struct work_struct *work) 119fbb6c848SEzequiel Garcia { 120fbb6c848SEzequiel Garcia struct hantro_dev *vpu; 121fbb6c848SEzequiel Garcia struct hantro_ctx *ctx; 122fbb6c848SEzequiel Garcia 123fbb6c848SEzequiel Garcia vpu = container_of(to_delayed_work(work), 124fbb6c848SEzequiel Garcia struct hantro_dev, watchdog_work); 125fbb6c848SEzequiel Garcia ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev); 126fbb6c848SEzequiel Garcia if (ctx) { 127fbb6c848SEzequiel Garcia vpu_err("frame processing timed out!\n"); 128fbb6c848SEzequiel Garcia ctx->codec_ops->reset(ctx); 129fbb6c848SEzequiel Garcia hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR); 130fbb6c848SEzequiel Garcia } 131fbb6c848SEzequiel Garcia } 132fbb6c848SEzequiel Garcia 133fbb6c848SEzequiel Garcia void hantro_start_prepare_run(struct hantro_ctx *ctx) 134fbb6c848SEzequiel Garcia { 135fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src_buf; 136fbb6c848SEzequiel Garcia 137fbb6c848SEzequiel Garcia src_buf = hantro_get_src_buf(ctx); 138fbb6c848SEzequiel Garcia v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req, 139fbb6c848SEzequiel Garcia &ctx->ctrl_handler); 140fbb6c848SEzequiel Garcia 141fbb6c848SEzequiel Garcia if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) { 142fbb6c848SEzequiel Garcia if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) 143fbb6c848SEzequiel Garcia hantro_postproc_enable(ctx); 144fbb6c848SEzequiel Garcia else 145fbb6c848SEzequiel Garcia hantro_postproc_disable(ctx); 146fbb6c848SEzequiel Garcia } 147fbb6c848SEzequiel Garcia } 148fbb6c848SEzequiel Garcia 149fbb6c848SEzequiel Garcia void hantro_end_prepare_run(struct hantro_ctx *ctx) 150fbb6c848SEzequiel Garcia { 151fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src_buf; 152fbb6c848SEzequiel Garcia 153fbb6c848SEzequiel Garcia if (!ctx->is_encoder && ctx->dev->variant->late_postproc) { 154fbb6c848SEzequiel Garcia if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt)) 155fbb6c848SEzequiel Garcia hantro_postproc_enable(ctx); 156fbb6c848SEzequiel Garcia else 157fbb6c848SEzequiel Garcia hantro_postproc_disable(ctx); 158fbb6c848SEzequiel Garcia } 159fbb6c848SEzequiel Garcia 160fbb6c848SEzequiel Garcia src_buf = hantro_get_src_buf(ctx); 161fbb6c848SEzequiel Garcia v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req, 162fbb6c848SEzequiel Garcia &ctx->ctrl_handler); 163fbb6c848SEzequiel Garcia 164fbb6c848SEzequiel Garcia /* Kick the watchdog. */ 165fbb6c848SEzequiel Garcia schedule_delayed_work(&ctx->dev->watchdog_work, 166fbb6c848SEzequiel Garcia msecs_to_jiffies(2000)); 167fbb6c848SEzequiel Garcia } 168fbb6c848SEzequiel Garcia 169fbb6c848SEzequiel Garcia static void device_run(void *priv) 170fbb6c848SEzequiel Garcia { 171fbb6c848SEzequiel Garcia struct hantro_ctx *ctx = priv; 172fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src, *dst; 173fbb6c848SEzequiel Garcia int ret; 174fbb6c848SEzequiel Garcia 175fbb6c848SEzequiel Garcia src = hantro_get_src_buf(ctx); 176fbb6c848SEzequiel Garcia dst = hantro_get_dst_buf(ctx); 177fbb6c848SEzequiel Garcia 178fbb6c848SEzequiel Garcia ret = pm_runtime_resume_and_get(ctx->dev->dev); 179fbb6c848SEzequiel Garcia if (ret < 0) 180fbb6c848SEzequiel Garcia goto err_cancel_job; 181fbb6c848SEzequiel Garcia 182fbb6c848SEzequiel Garcia ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks); 183fbb6c848SEzequiel Garcia if (ret) 184fbb6c848SEzequiel Garcia goto err_cancel_job; 185fbb6c848SEzequiel Garcia 186fbb6c848SEzequiel Garcia v4l2_m2m_buf_copy_metadata(src, dst, true); 187fbb6c848SEzequiel Garcia 188fbb6c848SEzequiel Garcia if (ctx->codec_ops->run(ctx)) 189fbb6c848SEzequiel Garcia goto err_cancel_job; 190fbb6c848SEzequiel Garcia 191fbb6c848SEzequiel Garcia return; 192fbb6c848SEzequiel Garcia 193fbb6c848SEzequiel Garcia err_cancel_job: 194fbb6c848SEzequiel Garcia hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR); 195fbb6c848SEzequiel Garcia } 196fbb6c848SEzequiel Garcia 197fbb6c848SEzequiel Garcia static const struct v4l2_m2m_ops vpu_m2m_ops = { 198fbb6c848SEzequiel Garcia .device_run = device_run, 199fbb6c848SEzequiel Garcia }; 200fbb6c848SEzequiel Garcia 201fbb6c848SEzequiel Garcia static int 202fbb6c848SEzequiel Garcia queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 203fbb6c848SEzequiel Garcia { 204fbb6c848SEzequiel Garcia struct hantro_ctx *ctx = priv; 205fbb6c848SEzequiel Garcia int ret; 206fbb6c848SEzequiel Garcia 207fbb6c848SEzequiel Garcia src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 208fbb6c848SEzequiel Garcia src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 209fbb6c848SEzequiel Garcia src_vq->drv_priv = ctx; 210fbb6c848SEzequiel Garcia src_vq->ops = &hantro_queue_ops; 211fbb6c848SEzequiel Garcia src_vq->mem_ops = &vb2_dma_contig_memops; 212fbb6c848SEzequiel Garcia 213fbb6c848SEzequiel Garcia /* 214fbb6c848SEzequiel Garcia * Driver does mostly sequential access, so sacrifice TLB efficiency 215fbb6c848SEzequiel Garcia * for faster allocation. Also, no CPU access on the source queue, 216fbb6c848SEzequiel Garcia * so no kernel mapping needed. 217fbb6c848SEzequiel Garcia */ 218fbb6c848SEzequiel Garcia src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES | 219fbb6c848SEzequiel Garcia DMA_ATTR_NO_KERNEL_MAPPING; 220fbb6c848SEzequiel Garcia src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 221fbb6c848SEzequiel Garcia src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 222fbb6c848SEzequiel Garcia src_vq->lock = &ctx->dev->vpu_mutex; 223fbb6c848SEzequiel Garcia src_vq->dev = ctx->dev->v4l2_dev.dev; 224fbb6c848SEzequiel Garcia src_vq->supports_requests = true; 225fbb6c848SEzequiel Garcia 226fbb6c848SEzequiel Garcia ret = vb2_queue_init(src_vq); 227fbb6c848SEzequiel Garcia if (ret) 228fbb6c848SEzequiel Garcia return ret; 229fbb6c848SEzequiel Garcia 230fbb6c848SEzequiel Garcia dst_vq->bidirectional = true; 231fbb6c848SEzequiel Garcia dst_vq->mem_ops = &vb2_dma_contig_memops; 232fbb6c848SEzequiel Garcia dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES; 233fbb6c848SEzequiel Garcia /* 234fbb6c848SEzequiel Garcia * The Kernel needs access to the JPEG destination buffer for the 235fbb6c848SEzequiel Garcia * JPEG encoder to fill in the JPEG headers. 236fbb6c848SEzequiel Garcia */ 237fbb6c848SEzequiel Garcia if (!ctx->is_encoder) 238fbb6c848SEzequiel Garcia dst_vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 239fbb6c848SEzequiel Garcia 240fbb6c848SEzequiel Garcia dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 241fbb6c848SEzequiel Garcia dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 242fbb6c848SEzequiel Garcia dst_vq->drv_priv = ctx; 243fbb6c848SEzequiel Garcia dst_vq->ops = &hantro_queue_ops; 244fbb6c848SEzequiel Garcia dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer); 245fbb6c848SEzequiel Garcia dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 246fbb6c848SEzequiel Garcia dst_vq->lock = &ctx->dev->vpu_mutex; 247fbb6c848SEzequiel Garcia dst_vq->dev = ctx->dev->v4l2_dev.dev; 248fbb6c848SEzequiel Garcia 249fbb6c848SEzequiel Garcia return vb2_queue_init(dst_vq); 250fbb6c848SEzequiel Garcia } 251fbb6c848SEzequiel Garcia 252fbb6c848SEzequiel Garcia static int hantro_try_ctrl(struct v4l2_ctrl *ctrl) 253fbb6c848SEzequiel Garcia { 254fbb6c848SEzequiel Garcia if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) { 255fbb6c848SEzequiel Garcia const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps; 256fbb6c848SEzequiel Garcia 257fbb6c848SEzequiel Garcia if (sps->chroma_format_idc > 1) 258fbb6c848SEzequiel Garcia /* Only 4:0:0 and 4:2:0 are supported */ 259fbb6c848SEzequiel Garcia return -EINVAL; 260fbb6c848SEzequiel Garcia if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8) 261fbb6c848SEzequiel Garcia /* Luma and chroma bit depth mismatch */ 262fbb6c848SEzequiel Garcia return -EINVAL; 263fbb6c848SEzequiel Garcia if (sps->bit_depth_luma_minus8 != 0) 264fbb6c848SEzequiel Garcia /* Only 8-bit is supported */ 265fbb6c848SEzequiel Garcia return -EINVAL; 266fbb6c848SEzequiel Garcia } else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) { 267fbb6c848SEzequiel Garcia const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; 268fbb6c848SEzequiel Garcia 269d040a24bSBenjamin Gaignard if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2) 270d040a24bSBenjamin Gaignard /* Only 8-bit and 10-bit are supported */ 271fbb6c848SEzequiel Garcia return -EINVAL; 272fbb6c848SEzequiel Garcia } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) { 273fbb6c848SEzequiel Garcia const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame; 274fbb6c848SEzequiel Garcia 275fbb6c848SEzequiel Garcia /* We only support profile 0 */ 276fbb6c848SEzequiel Garcia if (dec_params->profile != 0) 277fbb6c848SEzequiel Garcia return -EINVAL; 278fbb6c848SEzequiel Garcia } 279fbb6c848SEzequiel Garcia return 0; 280fbb6c848SEzequiel Garcia } 281fbb6c848SEzequiel Garcia 282fbb6c848SEzequiel Garcia static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl) 283fbb6c848SEzequiel Garcia { 284fbb6c848SEzequiel Garcia struct hantro_ctx *ctx; 285fbb6c848SEzequiel Garcia 286fbb6c848SEzequiel Garcia ctx = container_of(ctrl->handler, 287fbb6c848SEzequiel Garcia struct hantro_ctx, ctrl_handler); 288fbb6c848SEzequiel Garcia 289fbb6c848SEzequiel Garcia vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val); 290fbb6c848SEzequiel Garcia 291fbb6c848SEzequiel Garcia switch (ctrl->id) { 292fbb6c848SEzequiel Garcia case V4L2_CID_JPEG_COMPRESSION_QUALITY: 293fbb6c848SEzequiel Garcia ctx->jpeg_quality = ctrl->val; 294fbb6c848SEzequiel Garcia break; 295fbb6c848SEzequiel Garcia default: 296fbb6c848SEzequiel Garcia return -EINVAL; 297fbb6c848SEzequiel Garcia } 298fbb6c848SEzequiel Garcia 299fbb6c848SEzequiel Garcia return 0; 300fbb6c848SEzequiel Garcia } 301fbb6c848SEzequiel Garcia 302fbb6c848SEzequiel Garcia static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl) 303fbb6c848SEzequiel Garcia { 304fbb6c848SEzequiel Garcia struct hantro_ctx *ctx; 305fbb6c848SEzequiel Garcia 306fbb6c848SEzequiel Garcia ctx = container_of(ctrl->handler, 307fbb6c848SEzequiel Garcia struct hantro_ctx, ctrl_handler); 308fbb6c848SEzequiel Garcia 309fbb6c848SEzequiel Garcia switch (ctrl->id) { 3103d77e23cSBenjamin Gaignard case V4L2_CID_STATELESS_VP9_FRAME: { 3113d77e23cSBenjamin Gaignard int bit_depth = ctrl->p_new.p_vp9_frame->bit_depth; 3123d77e23cSBenjamin Gaignard 3133d77e23cSBenjamin Gaignard if (ctx->bit_depth == bit_depth) 3143d77e23cSBenjamin Gaignard return 0; 3153d77e23cSBenjamin Gaignard 3163d77e23cSBenjamin Gaignard return hantro_reset_raw_fmt(ctx, bit_depth); 3173d77e23cSBenjamin Gaignard } 318fbb6c848SEzequiel Garcia default: 319fbb6c848SEzequiel Garcia return -EINVAL; 320fbb6c848SEzequiel Garcia } 321fbb6c848SEzequiel Garcia 322fbb6c848SEzequiel Garcia return 0; 323fbb6c848SEzequiel Garcia } 324fbb6c848SEzequiel Garcia 3256aa3b9c5SBenjamin Gaignard static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl) 3266aa3b9c5SBenjamin Gaignard { 3276aa3b9c5SBenjamin Gaignard struct hantro_ctx *ctx; 3286aa3b9c5SBenjamin Gaignard 3296aa3b9c5SBenjamin Gaignard ctx = container_of(ctrl->handler, 3306aa3b9c5SBenjamin Gaignard struct hantro_ctx, ctrl_handler); 3316aa3b9c5SBenjamin Gaignard 3326aa3b9c5SBenjamin Gaignard switch (ctrl->id) { 333ac5d3db4SBenjamin Gaignard case V4L2_CID_STATELESS_HEVC_SPS: { 334ac5d3db4SBenjamin Gaignard const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps; 335ac5d3db4SBenjamin Gaignard int bit_depth = sps->bit_depth_luma_minus8 + 8; 336ac5d3db4SBenjamin Gaignard 337ac5d3db4SBenjamin Gaignard if (ctx->bit_depth == bit_depth) 338ac5d3db4SBenjamin Gaignard return 0; 339ac5d3db4SBenjamin Gaignard 340ac5d3db4SBenjamin Gaignard return hantro_reset_raw_fmt(ctx, bit_depth); 341ac5d3db4SBenjamin Gaignard } 3426aa3b9c5SBenjamin Gaignard default: 3436aa3b9c5SBenjamin Gaignard return -EINVAL; 3446aa3b9c5SBenjamin Gaignard } 3456aa3b9c5SBenjamin Gaignard 3466aa3b9c5SBenjamin Gaignard return 0; 3476aa3b9c5SBenjamin Gaignard } 3486aa3b9c5SBenjamin Gaignard 349fbb6c848SEzequiel Garcia static const struct v4l2_ctrl_ops hantro_ctrl_ops = { 350fbb6c848SEzequiel Garcia .try_ctrl = hantro_try_ctrl, 351fbb6c848SEzequiel Garcia }; 352fbb6c848SEzequiel Garcia 353fbb6c848SEzequiel Garcia static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = { 354fbb6c848SEzequiel Garcia .s_ctrl = hantro_jpeg_s_ctrl, 355fbb6c848SEzequiel Garcia }; 356fbb6c848SEzequiel Garcia 357fbb6c848SEzequiel Garcia static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = { 358fbb6c848SEzequiel Garcia .s_ctrl = hantro_vp9_s_ctrl, 359fbb6c848SEzequiel Garcia }; 360fbb6c848SEzequiel Garcia 3616aa3b9c5SBenjamin Gaignard static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = { 3626aa3b9c5SBenjamin Gaignard .try_ctrl = hantro_try_ctrl, 3636aa3b9c5SBenjamin Gaignard .s_ctrl = hantro_hevc_s_ctrl, 3646aa3b9c5SBenjamin Gaignard }; 3656aa3b9c5SBenjamin Gaignard 366fbb6c848SEzequiel Garcia #define HANTRO_JPEG_ACTIVE_MARKERS (V4L2_JPEG_ACTIVE_MARKER_APP0 | \ 367fbb6c848SEzequiel Garcia V4L2_JPEG_ACTIVE_MARKER_COM | \ 368fbb6c848SEzequiel Garcia V4L2_JPEG_ACTIVE_MARKER_DQT | \ 369fbb6c848SEzequiel Garcia V4L2_JPEG_ACTIVE_MARKER_DHT) 370fbb6c848SEzequiel Garcia 371fbb6c848SEzequiel Garcia static const struct hantro_ctrl controls[] = { 372fbb6c848SEzequiel Garcia { 373fbb6c848SEzequiel Garcia .codec = HANTRO_JPEG_ENCODER, 374fbb6c848SEzequiel Garcia .cfg = { 375fbb6c848SEzequiel Garcia .id = V4L2_CID_JPEG_COMPRESSION_QUALITY, 376fbb6c848SEzequiel Garcia .min = 5, 377fbb6c848SEzequiel Garcia .max = 100, 378fbb6c848SEzequiel Garcia .step = 1, 379fbb6c848SEzequiel Garcia .def = 50, 380fbb6c848SEzequiel Garcia .ops = &hantro_jpeg_ctrl_ops, 381fbb6c848SEzequiel Garcia }, 382fbb6c848SEzequiel Garcia }, { 383fbb6c848SEzequiel Garcia .codec = HANTRO_JPEG_ENCODER, 384fbb6c848SEzequiel Garcia .cfg = { 385fbb6c848SEzequiel Garcia .id = V4L2_CID_JPEG_ACTIVE_MARKER, 386fbb6c848SEzequiel Garcia .max = HANTRO_JPEG_ACTIVE_MARKERS, 387fbb6c848SEzequiel Garcia .def = HANTRO_JPEG_ACTIVE_MARKERS, 388fbb6c848SEzequiel Garcia /* 389fbb6c848SEzequiel Garcia * Changing the set of active markers/segments also 390fbb6c848SEzequiel Garcia * messes up the alignment of the JPEG header, which 391fbb6c848SEzequiel Garcia * is needed to allow the hardware to write directly 392fbb6c848SEzequiel Garcia * to the output buffer. Implementing this introduces 393fbb6c848SEzequiel Garcia * a lot of complexity for little gain, as the markers 394fbb6c848SEzequiel Garcia * enabled is already the minimum required set. 395fbb6c848SEzequiel Garcia */ 396fbb6c848SEzequiel Garcia .flags = V4L2_CTRL_FLAG_READ_ONLY, 397fbb6c848SEzequiel Garcia }, 398fbb6c848SEzequiel Garcia }, { 399fbb6c848SEzequiel Garcia .codec = HANTRO_MPEG2_DECODER, 400fbb6c848SEzequiel Garcia .cfg = { 401fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_MPEG2_SEQUENCE, 402fbb6c848SEzequiel Garcia }, 403fbb6c848SEzequiel Garcia }, { 404fbb6c848SEzequiel Garcia .codec = HANTRO_MPEG2_DECODER, 405fbb6c848SEzequiel Garcia .cfg = { 406fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_MPEG2_PICTURE, 407fbb6c848SEzequiel Garcia }, 408fbb6c848SEzequiel Garcia }, { 409fbb6c848SEzequiel Garcia .codec = HANTRO_MPEG2_DECODER, 410fbb6c848SEzequiel Garcia .cfg = { 411fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_MPEG2_QUANTISATION, 412fbb6c848SEzequiel Garcia }, 413fbb6c848SEzequiel Garcia }, { 414fbb6c848SEzequiel Garcia .codec = HANTRO_VP8_DECODER, 415fbb6c848SEzequiel Garcia .cfg = { 416fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_VP8_FRAME, 417fbb6c848SEzequiel Garcia }, 418fbb6c848SEzequiel Garcia }, { 419fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 420fbb6c848SEzequiel Garcia .cfg = { 421fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, 422fbb6c848SEzequiel Garcia }, 423fbb6c848SEzequiel Garcia }, { 424fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 425fbb6c848SEzequiel Garcia .cfg = { 426fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_SPS, 427fbb6c848SEzequiel Garcia .ops = &hantro_ctrl_ops, 428fbb6c848SEzequiel Garcia }, 429fbb6c848SEzequiel Garcia }, { 430fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 431fbb6c848SEzequiel Garcia .cfg = { 432fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_PPS, 433fbb6c848SEzequiel Garcia }, 434fbb6c848SEzequiel Garcia }, { 435fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 436fbb6c848SEzequiel Garcia .cfg = { 437fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX, 438fbb6c848SEzequiel Garcia }, 439fbb6c848SEzequiel Garcia }, { 440fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 441fbb6c848SEzequiel Garcia .cfg = { 442fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_DECODE_MODE, 443fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 444fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 445fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, 446fbb6c848SEzequiel Garcia }, 447fbb6c848SEzequiel Garcia }, { 448fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 449fbb6c848SEzequiel Garcia .cfg = { 450fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_START_CODE, 451fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 452fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 453fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, 454fbb6c848SEzequiel Garcia }, 455fbb6c848SEzequiel Garcia }, { 456fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER, 457fbb6c848SEzequiel Garcia .cfg = { 458fbb6c848SEzequiel Garcia .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, 459fbb6c848SEzequiel Garcia .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, 460fbb6c848SEzequiel Garcia .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, 461fbb6c848SEzequiel Garcia .menu_skip_mask = 462fbb6c848SEzequiel Garcia BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED), 463fbb6c848SEzequiel Garcia .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, 464fbb6c848SEzequiel Garcia } 465fbb6c848SEzequiel Garcia }, { 466fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 467fbb6c848SEzequiel Garcia .cfg = { 468fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE, 469fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 470fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 471fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED, 472fbb6c848SEzequiel Garcia }, 473fbb6c848SEzequiel Garcia }, { 474fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 475fbb6c848SEzequiel Garcia .cfg = { 476fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_START_CODE, 477fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 478fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 479fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B, 480fbb6c848SEzequiel Garcia }, 481fbb6c848SEzequiel Garcia }, { 482fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 483fbb6c848SEzequiel Garcia .cfg = { 484fbb6c848SEzequiel Garcia .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE, 485fbb6c848SEzequiel Garcia .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 486fbb6c848SEzequiel Garcia .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, 487fbb6c848SEzequiel Garcia .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, 488fbb6c848SEzequiel Garcia }, 489fbb6c848SEzequiel Garcia }, { 490fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 491fbb6c848SEzequiel Garcia .cfg = { 492fbb6c848SEzequiel Garcia .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL, 493fbb6c848SEzequiel Garcia .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1, 494fbb6c848SEzequiel Garcia .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1, 495fbb6c848SEzequiel Garcia }, 496fbb6c848SEzequiel Garcia }, { 497fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 498fbb6c848SEzequiel Garcia .cfg = { 499fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_SPS, 5006aa3b9c5SBenjamin Gaignard .ops = &hantro_hevc_ctrl_ops, 501fbb6c848SEzequiel Garcia }, 502fbb6c848SEzequiel Garcia }, { 503fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 504fbb6c848SEzequiel Garcia .cfg = { 505fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_PPS, 506fbb6c848SEzequiel Garcia }, 507fbb6c848SEzequiel Garcia }, { 508fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 509fbb6c848SEzequiel Garcia .cfg = { 510fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS, 511fbb6c848SEzequiel Garcia }, 512fbb6c848SEzequiel Garcia }, { 513fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER, 514fbb6c848SEzequiel Garcia .cfg = { 515fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX, 516fbb6c848SEzequiel Garcia }, 517fbb6c848SEzequiel Garcia }, { 518fbb6c848SEzequiel Garcia .codec = HANTRO_VP9_DECODER, 519fbb6c848SEzequiel Garcia .cfg = { 520fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_VP9_FRAME, 521fbb6c848SEzequiel Garcia .ops = &hantro_vp9_ctrl_ops, 522fbb6c848SEzequiel Garcia }, 523fbb6c848SEzequiel Garcia }, { 524fbb6c848SEzequiel Garcia .codec = HANTRO_VP9_DECODER, 525fbb6c848SEzequiel Garcia .cfg = { 526fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR, 527fbb6c848SEzequiel Garcia }, 528*53421e73SBenjamin Gaignard }, { 529*53421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER, 530*53421e73SBenjamin Gaignard .cfg = { 531*53421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_FRAME, 532*53421e73SBenjamin Gaignard }, 533*53421e73SBenjamin Gaignard }, { 534*53421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER, 535*53421e73SBenjamin Gaignard .cfg = { 536*53421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY, 537*53421e73SBenjamin Gaignard .dims = { V4L2_AV1_MAX_TILE_COUNT }, 538*53421e73SBenjamin Gaignard }, 539*53421e73SBenjamin Gaignard }, { 540*53421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER, 541*53421e73SBenjamin Gaignard .cfg = { 542*53421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_SEQUENCE, 543*53421e73SBenjamin Gaignard }, 544*53421e73SBenjamin Gaignard }, { 545*53421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER, 546*53421e73SBenjamin Gaignard .cfg = { 547*53421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_FILM_GRAIN, 548*53421e73SBenjamin Gaignard }, 549fbb6c848SEzequiel Garcia }, 550fbb6c848SEzequiel Garcia }; 551fbb6c848SEzequiel Garcia 552fbb6c848SEzequiel Garcia static int hantro_ctrls_setup(struct hantro_dev *vpu, 553fbb6c848SEzequiel Garcia struct hantro_ctx *ctx, 554fbb6c848SEzequiel Garcia int allowed_codecs) 555fbb6c848SEzequiel Garcia { 556fbb6c848SEzequiel Garcia int i, num_ctrls = ARRAY_SIZE(controls); 557fbb6c848SEzequiel Garcia 558fbb6c848SEzequiel Garcia v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls); 559fbb6c848SEzequiel Garcia 560fbb6c848SEzequiel Garcia for (i = 0; i < num_ctrls; i++) { 561fbb6c848SEzequiel Garcia if (!(allowed_codecs & controls[i].codec)) 562fbb6c848SEzequiel Garcia continue; 563fbb6c848SEzequiel Garcia 564fbb6c848SEzequiel Garcia v4l2_ctrl_new_custom(&ctx->ctrl_handler, 565fbb6c848SEzequiel Garcia &controls[i].cfg, NULL); 566fbb6c848SEzequiel Garcia if (ctx->ctrl_handler.error) { 567fbb6c848SEzequiel Garcia vpu_err("Adding control (%d) failed %d\n", 568fbb6c848SEzequiel Garcia controls[i].cfg.id, 569fbb6c848SEzequiel Garcia ctx->ctrl_handler.error); 570fbb6c848SEzequiel Garcia v4l2_ctrl_handler_free(&ctx->ctrl_handler); 571fbb6c848SEzequiel Garcia return ctx->ctrl_handler.error; 572fbb6c848SEzequiel Garcia } 573fbb6c848SEzequiel Garcia } 574fbb6c848SEzequiel Garcia return v4l2_ctrl_handler_setup(&ctx->ctrl_handler); 575fbb6c848SEzequiel Garcia } 576fbb6c848SEzequiel Garcia 577fbb6c848SEzequiel Garcia /* 578fbb6c848SEzequiel Garcia * V4L2 file operations. 579fbb6c848SEzequiel Garcia */ 580fbb6c848SEzequiel Garcia 581fbb6c848SEzequiel Garcia static int hantro_open(struct file *filp) 582fbb6c848SEzequiel Garcia { 583fbb6c848SEzequiel Garcia struct hantro_dev *vpu = video_drvdata(filp); 584fbb6c848SEzequiel Garcia struct video_device *vdev = video_devdata(filp); 585fbb6c848SEzequiel Garcia struct hantro_func *func = hantro_vdev_to_func(vdev); 586fbb6c848SEzequiel Garcia struct hantro_ctx *ctx; 587fbb6c848SEzequiel Garcia int allowed_codecs, ret; 588fbb6c848SEzequiel Garcia 589fbb6c848SEzequiel Garcia /* 590fbb6c848SEzequiel Garcia * We do not need any extra locking here, because we operate only 591fbb6c848SEzequiel Garcia * on local data here, except reading few fields from dev, which 592fbb6c848SEzequiel Garcia * do not change through device's lifetime (which is guaranteed by 593fbb6c848SEzequiel Garcia * reference on module from open()) and V4L2 internal objects (such 594fbb6c848SEzequiel Garcia * as vdev and ctx->fh), which have proper locking done in respective 595fbb6c848SEzequiel Garcia * helper functions used here. 596fbb6c848SEzequiel Garcia */ 597fbb6c848SEzequiel Garcia 598fbb6c848SEzequiel Garcia ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 599fbb6c848SEzequiel Garcia if (!ctx) 600fbb6c848SEzequiel Garcia return -ENOMEM; 601fbb6c848SEzequiel Garcia 602fbb6c848SEzequiel Garcia ctx->dev = vpu; 603fbb6c848SEzequiel Garcia if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) { 604fbb6c848SEzequiel Garcia allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS; 605fbb6c848SEzequiel Garcia ctx->is_encoder = true; 606fbb6c848SEzequiel Garcia } else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) { 607fbb6c848SEzequiel Garcia allowed_codecs = vpu->variant->codec & HANTRO_DECODERS; 608fbb6c848SEzequiel Garcia ctx->is_encoder = false; 609fbb6c848SEzequiel Garcia } else { 610fbb6c848SEzequiel Garcia ret = -ENODEV; 611fbb6c848SEzequiel Garcia goto err_ctx_free; 612fbb6c848SEzequiel Garcia } 613fbb6c848SEzequiel Garcia 614fbb6c848SEzequiel Garcia ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init); 615fbb6c848SEzequiel Garcia if (IS_ERR(ctx->fh.m2m_ctx)) { 616fbb6c848SEzequiel Garcia ret = PTR_ERR(ctx->fh.m2m_ctx); 617fbb6c848SEzequiel Garcia goto err_ctx_free; 618fbb6c848SEzequiel Garcia } 619fbb6c848SEzequiel Garcia 620fbb6c848SEzequiel Garcia v4l2_fh_init(&ctx->fh, vdev); 621fbb6c848SEzequiel Garcia filp->private_data = &ctx->fh; 622fbb6c848SEzequiel Garcia v4l2_fh_add(&ctx->fh); 623fbb6c848SEzequiel Garcia 624fbb6c848SEzequiel Garcia hantro_reset_fmts(ctx); 625fbb6c848SEzequiel Garcia 626fbb6c848SEzequiel Garcia ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs); 627fbb6c848SEzequiel Garcia if (ret) { 628fbb6c848SEzequiel Garcia vpu_err("Failed to set up controls\n"); 629fbb6c848SEzequiel Garcia goto err_fh_free; 630fbb6c848SEzequiel Garcia } 631fbb6c848SEzequiel Garcia ctx->fh.ctrl_handler = &ctx->ctrl_handler; 632fbb6c848SEzequiel Garcia 633fbb6c848SEzequiel Garcia return 0; 634fbb6c848SEzequiel Garcia 635fbb6c848SEzequiel Garcia err_fh_free: 636fbb6c848SEzequiel Garcia v4l2_fh_del(&ctx->fh); 637fbb6c848SEzequiel Garcia v4l2_fh_exit(&ctx->fh); 638fbb6c848SEzequiel Garcia err_ctx_free: 639fbb6c848SEzequiel Garcia kfree(ctx); 640fbb6c848SEzequiel Garcia return ret; 641fbb6c848SEzequiel Garcia } 642fbb6c848SEzequiel Garcia 643fbb6c848SEzequiel Garcia static int hantro_release(struct file *filp) 644fbb6c848SEzequiel Garcia { 645fbb6c848SEzequiel Garcia struct hantro_ctx *ctx = 646fbb6c848SEzequiel Garcia container_of(filp->private_data, struct hantro_ctx, fh); 647fbb6c848SEzequiel Garcia 648fbb6c848SEzequiel Garcia /* 649fbb6c848SEzequiel Garcia * No need for extra locking because this was the last reference 650fbb6c848SEzequiel Garcia * to this file. 651fbb6c848SEzequiel Garcia */ 652fbb6c848SEzequiel Garcia v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 653fbb6c848SEzequiel Garcia v4l2_fh_del(&ctx->fh); 654fbb6c848SEzequiel Garcia v4l2_fh_exit(&ctx->fh); 655fbb6c848SEzequiel Garcia v4l2_ctrl_handler_free(&ctx->ctrl_handler); 656fbb6c848SEzequiel Garcia kfree(ctx); 657fbb6c848SEzequiel Garcia 658fbb6c848SEzequiel Garcia return 0; 659fbb6c848SEzequiel Garcia } 660fbb6c848SEzequiel Garcia 661fbb6c848SEzequiel Garcia static const struct v4l2_file_operations hantro_fops = { 662fbb6c848SEzequiel Garcia .owner = THIS_MODULE, 663fbb6c848SEzequiel Garcia .open = hantro_open, 664fbb6c848SEzequiel Garcia .release = hantro_release, 665fbb6c848SEzequiel Garcia .poll = v4l2_m2m_fop_poll, 666fbb6c848SEzequiel Garcia .unlocked_ioctl = video_ioctl2, 667fbb6c848SEzequiel Garcia .mmap = v4l2_m2m_fop_mmap, 668fbb6c848SEzequiel Garcia }; 669fbb6c848SEzequiel Garcia 670fbb6c848SEzequiel Garcia static const struct of_device_id of_hantro_match[] = { 671fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP 672fbb6c848SEzequiel Garcia { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, }, 673fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, }, 674fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, }, 675fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, }, 676fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, }, 677fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, 678fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, }, 679fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, }, 680fbb6c848SEzequiel Garcia #endif 681fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_IMX8M 682fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, 683fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, 684fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, 685fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, 686fbb6c848SEzequiel Garcia #endif 687fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 688fbb6c848SEzequiel Garcia { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, }, 689fbb6c848SEzequiel Garcia #endif 690fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_SUNXI 691fbb6c848SEzequiel Garcia { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, 692fbb6c848SEzequiel Garcia #endif 693fbb6c848SEzequiel Garcia { /* sentinel */ } 694fbb6c848SEzequiel Garcia }; 695fbb6c848SEzequiel Garcia MODULE_DEVICE_TABLE(of, of_hantro_match); 696fbb6c848SEzequiel Garcia 697fbb6c848SEzequiel Garcia static int hantro_register_entity(struct media_device *mdev, 698fbb6c848SEzequiel Garcia struct media_entity *entity, 699fbb6c848SEzequiel Garcia const char *entity_name, 700fbb6c848SEzequiel Garcia struct media_pad *pads, int num_pads, 701fbb6c848SEzequiel Garcia int function, struct video_device *vdev) 702fbb6c848SEzequiel Garcia { 703fbb6c848SEzequiel Garcia char *name; 704fbb6c848SEzequiel Garcia int ret; 705fbb6c848SEzequiel Garcia 706fbb6c848SEzequiel Garcia entity->obj_type = MEDIA_ENTITY_TYPE_BASE; 707fbb6c848SEzequiel Garcia if (function == MEDIA_ENT_F_IO_V4L) { 708fbb6c848SEzequiel Garcia entity->info.dev.major = VIDEO_MAJOR; 709fbb6c848SEzequiel Garcia entity->info.dev.minor = vdev->minor; 710fbb6c848SEzequiel Garcia } 711fbb6c848SEzequiel Garcia 712fbb6c848SEzequiel Garcia name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name, 713fbb6c848SEzequiel Garcia entity_name); 714fbb6c848SEzequiel Garcia if (!name) 715fbb6c848SEzequiel Garcia return -ENOMEM; 716fbb6c848SEzequiel Garcia 717fbb6c848SEzequiel Garcia entity->name = name; 718fbb6c848SEzequiel Garcia entity->function = function; 719fbb6c848SEzequiel Garcia 720fbb6c848SEzequiel Garcia ret = media_entity_pads_init(entity, num_pads, pads); 721fbb6c848SEzequiel Garcia if (ret) 722fbb6c848SEzequiel Garcia return ret; 723fbb6c848SEzequiel Garcia 724fbb6c848SEzequiel Garcia ret = media_device_register_entity(mdev, entity); 725fbb6c848SEzequiel Garcia if (ret) 726fbb6c848SEzequiel Garcia return ret; 727fbb6c848SEzequiel Garcia 728fbb6c848SEzequiel Garcia return 0; 729fbb6c848SEzequiel Garcia } 730fbb6c848SEzequiel Garcia 731fbb6c848SEzequiel Garcia static int hantro_attach_func(struct hantro_dev *vpu, 732fbb6c848SEzequiel Garcia struct hantro_func *func) 733fbb6c848SEzequiel Garcia { 734fbb6c848SEzequiel Garcia struct media_device *mdev = &vpu->mdev; 735fbb6c848SEzequiel Garcia struct media_link *link; 736fbb6c848SEzequiel Garcia int ret; 737fbb6c848SEzequiel Garcia 738fbb6c848SEzequiel Garcia /* Create the three encoder entities with their pads */ 739fbb6c848SEzequiel Garcia func->source_pad.flags = MEDIA_PAD_FL_SOURCE; 740fbb6c848SEzequiel Garcia ret = hantro_register_entity(mdev, &func->vdev.entity, "source", 741fbb6c848SEzequiel Garcia &func->source_pad, 1, MEDIA_ENT_F_IO_V4L, 742fbb6c848SEzequiel Garcia &func->vdev); 743fbb6c848SEzequiel Garcia if (ret) 744fbb6c848SEzequiel Garcia return ret; 745fbb6c848SEzequiel Garcia 746fbb6c848SEzequiel Garcia func->proc_pads[0].flags = MEDIA_PAD_FL_SINK; 747fbb6c848SEzequiel Garcia func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE; 748fbb6c848SEzequiel Garcia ret = hantro_register_entity(mdev, &func->proc, "proc", 749fbb6c848SEzequiel Garcia func->proc_pads, 2, func->id, 750fbb6c848SEzequiel Garcia &func->vdev); 751fbb6c848SEzequiel Garcia if (ret) 752fbb6c848SEzequiel Garcia goto err_rel_entity0; 753fbb6c848SEzequiel Garcia 754fbb6c848SEzequiel Garcia func->sink_pad.flags = MEDIA_PAD_FL_SINK; 755fbb6c848SEzequiel Garcia ret = hantro_register_entity(mdev, &func->sink, "sink", 756fbb6c848SEzequiel Garcia &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L, 757fbb6c848SEzequiel Garcia &func->vdev); 758fbb6c848SEzequiel Garcia if (ret) 759fbb6c848SEzequiel Garcia goto err_rel_entity1; 760fbb6c848SEzequiel Garcia 761fbb6c848SEzequiel Garcia /* Connect the three entities */ 762fbb6c848SEzequiel Garcia ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0, 763fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE | 764fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED); 765fbb6c848SEzequiel Garcia if (ret) 766fbb6c848SEzequiel Garcia goto err_rel_entity2; 767fbb6c848SEzequiel Garcia 768fbb6c848SEzequiel Garcia ret = media_create_pad_link(&func->proc, 1, &func->sink, 0, 769fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE | 770fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED); 771fbb6c848SEzequiel Garcia if (ret) 772fbb6c848SEzequiel Garcia goto err_rm_links0; 773fbb6c848SEzequiel Garcia 774fbb6c848SEzequiel Garcia /* Create video interface */ 775fbb6c848SEzequiel Garcia func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO, 776fbb6c848SEzequiel Garcia 0, VIDEO_MAJOR, 777fbb6c848SEzequiel Garcia func->vdev.minor); 778fbb6c848SEzequiel Garcia if (!func->intf_devnode) { 779fbb6c848SEzequiel Garcia ret = -ENOMEM; 780fbb6c848SEzequiel Garcia goto err_rm_links1; 781fbb6c848SEzequiel Garcia } 782fbb6c848SEzequiel Garcia 783fbb6c848SEzequiel Garcia /* Connect the two DMA engines to the interface */ 784fbb6c848SEzequiel Garcia link = media_create_intf_link(&func->vdev.entity, 785fbb6c848SEzequiel Garcia &func->intf_devnode->intf, 786fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE | 787fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED); 788fbb6c848SEzequiel Garcia if (!link) { 789fbb6c848SEzequiel Garcia ret = -ENOMEM; 790fbb6c848SEzequiel Garcia goto err_rm_devnode; 791fbb6c848SEzequiel Garcia } 792fbb6c848SEzequiel Garcia 793fbb6c848SEzequiel Garcia link = media_create_intf_link(&func->sink, &func->intf_devnode->intf, 794fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE | 795fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED); 796fbb6c848SEzequiel Garcia if (!link) { 797fbb6c848SEzequiel Garcia ret = -ENOMEM; 798fbb6c848SEzequiel Garcia goto err_rm_devnode; 799fbb6c848SEzequiel Garcia } 800fbb6c848SEzequiel Garcia return 0; 801fbb6c848SEzequiel Garcia 802fbb6c848SEzequiel Garcia err_rm_devnode: 803fbb6c848SEzequiel Garcia media_devnode_remove(func->intf_devnode); 804fbb6c848SEzequiel Garcia 805fbb6c848SEzequiel Garcia err_rm_links1: 806fbb6c848SEzequiel Garcia media_entity_remove_links(&func->sink); 807fbb6c848SEzequiel Garcia 808fbb6c848SEzequiel Garcia err_rm_links0: 809fbb6c848SEzequiel Garcia media_entity_remove_links(&func->proc); 810fbb6c848SEzequiel Garcia media_entity_remove_links(&func->vdev.entity); 811fbb6c848SEzequiel Garcia 812fbb6c848SEzequiel Garcia err_rel_entity2: 813fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->sink); 814fbb6c848SEzequiel Garcia 815fbb6c848SEzequiel Garcia err_rel_entity1: 816fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->proc); 817fbb6c848SEzequiel Garcia 818fbb6c848SEzequiel Garcia err_rel_entity0: 819fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->vdev.entity); 820fbb6c848SEzequiel Garcia return ret; 821fbb6c848SEzequiel Garcia } 822fbb6c848SEzequiel Garcia 823fbb6c848SEzequiel Garcia static void hantro_detach_func(struct hantro_func *func) 824fbb6c848SEzequiel Garcia { 825fbb6c848SEzequiel Garcia media_devnode_remove(func->intf_devnode); 826fbb6c848SEzequiel Garcia media_entity_remove_links(&func->sink); 827fbb6c848SEzequiel Garcia media_entity_remove_links(&func->proc); 828fbb6c848SEzequiel Garcia media_entity_remove_links(&func->vdev.entity); 829fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->sink); 830fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->proc); 831fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->vdev.entity); 832fbb6c848SEzequiel Garcia } 833fbb6c848SEzequiel Garcia 834fbb6c848SEzequiel Garcia static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid) 835fbb6c848SEzequiel Garcia { 836fbb6c848SEzequiel Garcia const struct of_device_id *match; 837fbb6c848SEzequiel Garcia struct hantro_func *func; 838fbb6c848SEzequiel Garcia struct video_device *vfd; 839fbb6c848SEzequiel Garcia int ret; 840fbb6c848SEzequiel Garcia 841fbb6c848SEzequiel Garcia match = of_match_node(of_hantro_match, vpu->dev->of_node); 842fbb6c848SEzequiel Garcia func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL); 843fbb6c848SEzequiel Garcia if (!func) { 844fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n"); 845fbb6c848SEzequiel Garcia return -ENOMEM; 846fbb6c848SEzequiel Garcia } 847fbb6c848SEzequiel Garcia 848fbb6c848SEzequiel Garcia func->id = funcid; 849fbb6c848SEzequiel Garcia 850fbb6c848SEzequiel Garcia vfd = &func->vdev; 851fbb6c848SEzequiel Garcia vfd->fops = &hantro_fops; 852fbb6c848SEzequiel Garcia vfd->release = video_device_release_empty; 853fbb6c848SEzequiel Garcia vfd->lock = &vpu->vpu_mutex; 854fbb6c848SEzequiel Garcia vfd->v4l2_dev = &vpu->v4l2_dev; 855fbb6c848SEzequiel Garcia vfd->vfl_dir = VFL_DIR_M2M; 856fbb6c848SEzequiel Garcia vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE; 857fbb6c848SEzequiel Garcia vfd->ioctl_ops = &hantro_ioctl_ops; 858fbb6c848SEzequiel Garcia snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible, 859fbb6c848SEzequiel Garcia funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec"); 860fbb6c848SEzequiel Garcia 861fbb6c848SEzequiel Garcia if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) { 862fbb6c848SEzequiel Garcia vpu->encoder = func; 863fbb6c848SEzequiel Garcia } else { 864fbb6c848SEzequiel Garcia vpu->decoder = func; 865fbb6c848SEzequiel Garcia v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD); 866fbb6c848SEzequiel Garcia v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD); 867fbb6c848SEzequiel Garcia } 868fbb6c848SEzequiel Garcia 869fbb6c848SEzequiel Garcia video_set_drvdata(vfd, vpu); 870fbb6c848SEzequiel Garcia 871fbb6c848SEzequiel Garcia ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); 872fbb6c848SEzequiel Garcia if (ret) { 873fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n"); 874fbb6c848SEzequiel Garcia return ret; 875fbb6c848SEzequiel Garcia } 876fbb6c848SEzequiel Garcia 877fbb6c848SEzequiel Garcia ret = hantro_attach_func(vpu, func); 878fbb6c848SEzequiel Garcia if (ret) { 879fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, 880fbb6c848SEzequiel Garcia "Failed to attach functionality to the media device\n"); 881fbb6c848SEzequiel Garcia goto err_unreg_dev; 882fbb6c848SEzequiel Garcia } 883fbb6c848SEzequiel Garcia 884fbb6c848SEzequiel Garcia v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name, 885fbb6c848SEzequiel Garcia vfd->num); 886fbb6c848SEzequiel Garcia 887fbb6c848SEzequiel Garcia return 0; 888fbb6c848SEzequiel Garcia 889fbb6c848SEzequiel Garcia err_unreg_dev: 890fbb6c848SEzequiel Garcia video_unregister_device(vfd); 891fbb6c848SEzequiel Garcia return ret; 892fbb6c848SEzequiel Garcia } 893fbb6c848SEzequiel Garcia 894fbb6c848SEzequiel Garcia static int hantro_add_enc_func(struct hantro_dev *vpu) 895fbb6c848SEzequiel Garcia { 896fbb6c848SEzequiel Garcia if (!vpu->variant->enc_fmts) 897fbb6c848SEzequiel Garcia return 0; 898fbb6c848SEzequiel Garcia 899fbb6c848SEzequiel Garcia return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER); 900fbb6c848SEzequiel Garcia } 901fbb6c848SEzequiel Garcia 902fbb6c848SEzequiel Garcia static int hantro_add_dec_func(struct hantro_dev *vpu) 903fbb6c848SEzequiel Garcia { 904fbb6c848SEzequiel Garcia if (!vpu->variant->dec_fmts) 905fbb6c848SEzequiel Garcia return 0; 906fbb6c848SEzequiel Garcia 907fbb6c848SEzequiel Garcia return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER); 908fbb6c848SEzequiel Garcia } 909fbb6c848SEzequiel Garcia 910fbb6c848SEzequiel Garcia static void hantro_remove_func(struct hantro_dev *vpu, 911fbb6c848SEzequiel Garcia unsigned int funcid) 912fbb6c848SEzequiel Garcia { 913fbb6c848SEzequiel Garcia struct hantro_func *func; 914fbb6c848SEzequiel Garcia 915fbb6c848SEzequiel Garcia if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) 916fbb6c848SEzequiel Garcia func = vpu->encoder; 917fbb6c848SEzequiel Garcia else 918fbb6c848SEzequiel Garcia func = vpu->decoder; 919fbb6c848SEzequiel Garcia 920fbb6c848SEzequiel Garcia if (!func) 921fbb6c848SEzequiel Garcia return; 922fbb6c848SEzequiel Garcia 923fbb6c848SEzequiel Garcia hantro_detach_func(func); 924fbb6c848SEzequiel Garcia video_unregister_device(&func->vdev); 925fbb6c848SEzequiel Garcia } 926fbb6c848SEzequiel Garcia 927fbb6c848SEzequiel Garcia static void hantro_remove_enc_func(struct hantro_dev *vpu) 928fbb6c848SEzequiel Garcia { 929fbb6c848SEzequiel Garcia hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER); 930fbb6c848SEzequiel Garcia } 931fbb6c848SEzequiel Garcia 932fbb6c848SEzequiel Garcia static void hantro_remove_dec_func(struct hantro_dev *vpu) 933fbb6c848SEzequiel Garcia { 934fbb6c848SEzequiel Garcia hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER); 935fbb6c848SEzequiel Garcia } 936fbb6c848SEzequiel Garcia 937fbb6c848SEzequiel Garcia static const struct media_device_ops hantro_m2m_media_ops = { 938fbb6c848SEzequiel Garcia .req_validate = vb2_request_validate, 939fbb6c848SEzequiel Garcia .req_queue = v4l2_m2m_request_queue, 940fbb6c848SEzequiel Garcia }; 941fbb6c848SEzequiel Garcia 942fbb6c848SEzequiel Garcia static int hantro_probe(struct platform_device *pdev) 943fbb6c848SEzequiel Garcia { 944fbb6c848SEzequiel Garcia const struct of_device_id *match; 945fbb6c848SEzequiel Garcia struct hantro_dev *vpu; 946fbb6c848SEzequiel Garcia struct resource *res; 947fbb6c848SEzequiel Garcia int num_bases; 948fbb6c848SEzequiel Garcia int i, ret; 949fbb6c848SEzequiel Garcia 950fbb6c848SEzequiel Garcia vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL); 951fbb6c848SEzequiel Garcia if (!vpu) 952fbb6c848SEzequiel Garcia return -ENOMEM; 953fbb6c848SEzequiel Garcia 954fbb6c848SEzequiel Garcia vpu->dev = &pdev->dev; 955fbb6c848SEzequiel Garcia vpu->pdev = pdev; 956fbb6c848SEzequiel Garcia mutex_init(&vpu->vpu_mutex); 957fbb6c848SEzequiel Garcia spin_lock_init(&vpu->irqlock); 958fbb6c848SEzequiel Garcia 959fbb6c848SEzequiel Garcia match = of_match_node(of_hantro_match, pdev->dev.of_node); 960fbb6c848SEzequiel Garcia vpu->variant = match->data; 961fbb6c848SEzequiel Garcia 962fbb6c848SEzequiel Garcia /* 963fbb6c848SEzequiel Garcia * Support for nxp,imx8mq-vpu is kept for backwards compatibility 964fbb6c848SEzequiel Garcia * but it's deprecated. Please update your DTS file to use 965fbb6c848SEzequiel Garcia * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead. 966fbb6c848SEzequiel Garcia */ 967fbb6c848SEzequiel Garcia if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu")) 968fbb6c848SEzequiel Garcia dev_warn(&pdev->dev, "%s compatible is deprecated\n", 969fbb6c848SEzequiel Garcia match->compatible); 970fbb6c848SEzequiel Garcia 971fbb6c848SEzequiel Garcia INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog); 972fbb6c848SEzequiel Garcia 973fbb6c848SEzequiel Garcia vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks, 974fbb6c848SEzequiel Garcia sizeof(*vpu->clocks), GFP_KERNEL); 975fbb6c848SEzequiel Garcia if (!vpu->clocks) 976fbb6c848SEzequiel Garcia return -ENOMEM; 977fbb6c848SEzequiel Garcia 978fbb6c848SEzequiel Garcia if (vpu->variant->num_clocks > 1) { 979fbb6c848SEzequiel Garcia for (i = 0; i < vpu->variant->num_clocks; i++) 980fbb6c848SEzequiel Garcia vpu->clocks[i].id = vpu->variant->clk_names[i]; 981fbb6c848SEzequiel Garcia 982fbb6c848SEzequiel Garcia ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks, 983fbb6c848SEzequiel Garcia vpu->clocks); 984fbb6c848SEzequiel Garcia if (ret) 985fbb6c848SEzequiel Garcia return ret; 986fbb6c848SEzequiel Garcia } else { 987fbb6c848SEzequiel Garcia /* 988fbb6c848SEzequiel Garcia * If the driver has a single clk, chances are there will be no 989fbb6c848SEzequiel Garcia * actual name in the DT bindings. 990fbb6c848SEzequiel Garcia */ 991fbb6c848SEzequiel Garcia vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL); 992fbb6c848SEzequiel Garcia if (IS_ERR(vpu->clocks[0].clk)) 993fbb6c848SEzequiel Garcia return PTR_ERR(vpu->clocks[0].clk); 994fbb6c848SEzequiel Garcia } 995fbb6c848SEzequiel Garcia 9960b44232bSYe Xingchen vpu->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev); 997fbb6c848SEzequiel Garcia if (IS_ERR(vpu->resets)) 998fbb6c848SEzequiel Garcia return PTR_ERR(vpu->resets); 999fbb6c848SEzequiel Garcia 1000fbb6c848SEzequiel Garcia num_bases = vpu->variant->num_regs ?: 1; 1001fbb6c848SEzequiel Garcia vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases, 1002fbb6c848SEzequiel Garcia sizeof(*vpu->reg_bases), GFP_KERNEL); 1003fbb6c848SEzequiel Garcia if (!vpu->reg_bases) 1004fbb6c848SEzequiel Garcia return -ENOMEM; 1005fbb6c848SEzequiel Garcia 1006fbb6c848SEzequiel Garcia for (i = 0; i < num_bases; i++) { 1007fbb6c848SEzequiel Garcia res = vpu->variant->reg_names ? 1008fbb6c848SEzequiel Garcia platform_get_resource_byname(vpu->pdev, IORESOURCE_MEM, 1009fbb6c848SEzequiel Garcia vpu->variant->reg_names[i]) : 1010fbb6c848SEzequiel Garcia platform_get_resource(vpu->pdev, IORESOURCE_MEM, 0); 1011fbb6c848SEzequiel Garcia vpu->reg_bases[i] = devm_ioremap_resource(vpu->dev, res); 1012fbb6c848SEzequiel Garcia if (IS_ERR(vpu->reg_bases[i])) 1013fbb6c848SEzequiel Garcia return PTR_ERR(vpu->reg_bases[i]); 1014fbb6c848SEzequiel Garcia } 1015fbb6c848SEzequiel Garcia vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; 1016fbb6c848SEzequiel Garcia vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; 1017fbb6c848SEzequiel Garcia 1018fbb6c848SEzequiel Garcia /** 1019fbb6c848SEzequiel Garcia * TODO: Eventually allow taking advantage of full 64-bit address space. 1020fbb6c848SEzequiel Garcia * Until then we assume the MSB portion of buffers' base addresses is 1021fbb6c848SEzequiel Garcia * always 0 due to this masking operation. 1022fbb6c848SEzequiel Garcia */ 1023fbb6c848SEzequiel Garcia ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); 1024fbb6c848SEzequiel Garcia if (ret) { 1025fbb6c848SEzequiel Garcia dev_err(vpu->dev, "Could not set DMA coherent mask.\n"); 1026fbb6c848SEzequiel Garcia return ret; 1027fbb6c848SEzequiel Garcia } 1028fbb6c848SEzequiel Garcia vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); 1029fbb6c848SEzequiel Garcia 1030fbb6c848SEzequiel Garcia for (i = 0; i < vpu->variant->num_irqs; i++) { 1031fbb6c848SEzequiel Garcia const char *irq_name; 1032fbb6c848SEzequiel Garcia int irq; 1033fbb6c848SEzequiel Garcia 1034fbb6c848SEzequiel Garcia if (!vpu->variant->irqs[i].handler) 1035fbb6c848SEzequiel Garcia continue; 1036fbb6c848SEzequiel Garcia 1037fbb6c848SEzequiel Garcia if (vpu->variant->num_irqs > 1) { 1038fbb6c848SEzequiel Garcia irq_name = vpu->variant->irqs[i].name; 1039fbb6c848SEzequiel Garcia irq = platform_get_irq_byname(vpu->pdev, irq_name); 1040fbb6c848SEzequiel Garcia } else { 1041fbb6c848SEzequiel Garcia /* 1042fbb6c848SEzequiel Garcia * If the driver has a single IRQ, chances are there 1043fbb6c848SEzequiel Garcia * will be no actual name in the DT bindings. 1044fbb6c848SEzequiel Garcia */ 1045fbb6c848SEzequiel Garcia irq_name = "default"; 1046fbb6c848SEzequiel Garcia irq = platform_get_irq(vpu->pdev, 0); 1047fbb6c848SEzequiel Garcia } 1048fbb6c848SEzequiel Garcia if (irq <= 0) 1049fbb6c848SEzequiel Garcia return -ENXIO; 1050fbb6c848SEzequiel Garcia 1051fbb6c848SEzequiel Garcia ret = devm_request_irq(vpu->dev, irq, 1052fbb6c848SEzequiel Garcia vpu->variant->irqs[i].handler, 0, 1053fbb6c848SEzequiel Garcia dev_name(vpu->dev), vpu); 1054fbb6c848SEzequiel Garcia if (ret) { 1055fbb6c848SEzequiel Garcia dev_err(vpu->dev, "Could not request %s IRQ.\n", 1056fbb6c848SEzequiel Garcia irq_name); 1057fbb6c848SEzequiel Garcia return ret; 1058fbb6c848SEzequiel Garcia } 1059fbb6c848SEzequiel Garcia } 1060fbb6c848SEzequiel Garcia 1061fbb6c848SEzequiel Garcia if (vpu->variant->init) { 1062fbb6c848SEzequiel Garcia ret = vpu->variant->init(vpu); 1063fbb6c848SEzequiel Garcia if (ret) { 1064fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to init VPU hardware\n"); 1065fbb6c848SEzequiel Garcia return ret; 1066fbb6c848SEzequiel Garcia } 1067fbb6c848SEzequiel Garcia } 1068fbb6c848SEzequiel Garcia 1069fbb6c848SEzequiel Garcia pm_runtime_set_autosuspend_delay(vpu->dev, 100); 1070fbb6c848SEzequiel Garcia pm_runtime_use_autosuspend(vpu->dev); 1071fbb6c848SEzequiel Garcia pm_runtime_enable(vpu->dev); 1072fbb6c848SEzequiel Garcia 1073fbb6c848SEzequiel Garcia ret = reset_control_deassert(vpu->resets); 1074fbb6c848SEzequiel Garcia if (ret) { 1075fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to deassert resets\n"); 1076fbb6c848SEzequiel Garcia goto err_pm_disable; 1077fbb6c848SEzequiel Garcia } 1078fbb6c848SEzequiel Garcia 1079fbb6c848SEzequiel Garcia ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks); 1080fbb6c848SEzequiel Garcia if (ret) { 1081fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to prepare clocks\n"); 1082fbb6c848SEzequiel Garcia goto err_rst_assert; 1083fbb6c848SEzequiel Garcia } 1084fbb6c848SEzequiel Garcia 1085fbb6c848SEzequiel Garcia ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev); 1086fbb6c848SEzequiel Garcia if (ret) { 1087fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to register v4l2 device\n"); 1088fbb6c848SEzequiel Garcia goto err_clk_unprepare; 1089fbb6c848SEzequiel Garcia } 1090fbb6c848SEzequiel Garcia platform_set_drvdata(pdev, vpu); 1091fbb6c848SEzequiel Garcia 1092fbb6c848SEzequiel Garcia vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops); 1093fbb6c848SEzequiel Garcia if (IS_ERR(vpu->m2m_dev)) { 1094fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n"); 1095fbb6c848SEzequiel Garcia ret = PTR_ERR(vpu->m2m_dev); 1096fbb6c848SEzequiel Garcia goto err_v4l2_unreg; 1097fbb6c848SEzequiel Garcia } 1098fbb6c848SEzequiel Garcia 1099fbb6c848SEzequiel Garcia vpu->mdev.dev = vpu->dev; 1100fbb6c848SEzequiel Garcia strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model)); 1101fbb6c848SEzequiel Garcia media_device_init(&vpu->mdev); 1102fbb6c848SEzequiel Garcia vpu->mdev.ops = &hantro_m2m_media_ops; 1103fbb6c848SEzequiel Garcia vpu->v4l2_dev.mdev = &vpu->mdev; 1104fbb6c848SEzequiel Garcia 1105fbb6c848SEzequiel Garcia ret = hantro_add_enc_func(vpu); 1106fbb6c848SEzequiel Garcia if (ret) { 1107fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to register encoder\n"); 1108fbb6c848SEzequiel Garcia goto err_m2m_rel; 1109fbb6c848SEzequiel Garcia } 1110fbb6c848SEzequiel Garcia 1111fbb6c848SEzequiel Garcia ret = hantro_add_dec_func(vpu); 1112fbb6c848SEzequiel Garcia if (ret) { 1113fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to register decoder\n"); 1114fbb6c848SEzequiel Garcia goto err_rm_enc_func; 1115fbb6c848SEzequiel Garcia } 1116fbb6c848SEzequiel Garcia 1117fbb6c848SEzequiel Garcia ret = media_device_register(&vpu->mdev); 1118fbb6c848SEzequiel Garcia if (ret) { 1119fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n"); 1120fbb6c848SEzequiel Garcia goto err_rm_dec_func; 1121fbb6c848SEzequiel Garcia } 1122fbb6c848SEzequiel Garcia 1123fbb6c848SEzequiel Garcia return 0; 1124fbb6c848SEzequiel Garcia 1125fbb6c848SEzequiel Garcia err_rm_dec_func: 1126fbb6c848SEzequiel Garcia hantro_remove_dec_func(vpu); 1127fbb6c848SEzequiel Garcia err_rm_enc_func: 1128fbb6c848SEzequiel Garcia hantro_remove_enc_func(vpu); 1129fbb6c848SEzequiel Garcia err_m2m_rel: 1130fbb6c848SEzequiel Garcia media_device_cleanup(&vpu->mdev); 1131fbb6c848SEzequiel Garcia v4l2_m2m_release(vpu->m2m_dev); 1132fbb6c848SEzequiel Garcia err_v4l2_unreg: 1133fbb6c848SEzequiel Garcia v4l2_device_unregister(&vpu->v4l2_dev); 1134fbb6c848SEzequiel Garcia err_clk_unprepare: 1135fbb6c848SEzequiel Garcia clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); 1136fbb6c848SEzequiel Garcia err_rst_assert: 1137fbb6c848SEzequiel Garcia reset_control_assert(vpu->resets); 1138fbb6c848SEzequiel Garcia err_pm_disable: 1139fbb6c848SEzequiel Garcia pm_runtime_dont_use_autosuspend(vpu->dev); 1140fbb6c848SEzequiel Garcia pm_runtime_disable(vpu->dev); 1141fbb6c848SEzequiel Garcia return ret; 1142fbb6c848SEzequiel Garcia } 1143fbb6c848SEzequiel Garcia 1144b9294ba9SUwe Kleine-König static void hantro_remove(struct platform_device *pdev) 1145fbb6c848SEzequiel Garcia { 1146fbb6c848SEzequiel Garcia struct hantro_dev *vpu = platform_get_drvdata(pdev); 1147fbb6c848SEzequiel Garcia 1148fbb6c848SEzequiel Garcia v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name); 1149fbb6c848SEzequiel Garcia 1150fbb6c848SEzequiel Garcia media_device_unregister(&vpu->mdev); 1151fbb6c848SEzequiel Garcia hantro_remove_dec_func(vpu); 1152fbb6c848SEzequiel Garcia hantro_remove_enc_func(vpu); 1153fbb6c848SEzequiel Garcia media_device_cleanup(&vpu->mdev); 1154fbb6c848SEzequiel Garcia v4l2_m2m_release(vpu->m2m_dev); 1155fbb6c848SEzequiel Garcia v4l2_device_unregister(&vpu->v4l2_dev); 1156fbb6c848SEzequiel Garcia clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks); 1157fbb6c848SEzequiel Garcia reset_control_assert(vpu->resets); 1158fbb6c848SEzequiel Garcia pm_runtime_dont_use_autosuspend(vpu->dev); 1159fbb6c848SEzequiel Garcia pm_runtime_disable(vpu->dev); 1160fbb6c848SEzequiel Garcia } 1161fbb6c848SEzequiel Garcia 1162fbb6c848SEzequiel Garcia #ifdef CONFIG_PM 1163fbb6c848SEzequiel Garcia static int hantro_runtime_resume(struct device *dev) 1164fbb6c848SEzequiel Garcia { 1165fbb6c848SEzequiel Garcia struct hantro_dev *vpu = dev_get_drvdata(dev); 1166fbb6c848SEzequiel Garcia 1167fbb6c848SEzequiel Garcia if (vpu->variant->runtime_resume) 1168fbb6c848SEzequiel Garcia return vpu->variant->runtime_resume(vpu); 1169fbb6c848SEzequiel Garcia 1170fbb6c848SEzequiel Garcia return 0; 1171fbb6c848SEzequiel Garcia } 1172fbb6c848SEzequiel Garcia #endif 1173fbb6c848SEzequiel Garcia 1174fbb6c848SEzequiel Garcia static const struct dev_pm_ops hantro_pm_ops = { 1175fbb6c848SEzequiel Garcia SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1176fbb6c848SEzequiel Garcia pm_runtime_force_resume) 1177fbb6c848SEzequiel Garcia SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL) 1178fbb6c848SEzequiel Garcia }; 1179fbb6c848SEzequiel Garcia 1180fbb6c848SEzequiel Garcia static struct platform_driver hantro_driver = { 1181fbb6c848SEzequiel Garcia .probe = hantro_probe, 1182b9294ba9SUwe Kleine-König .remove_new = hantro_remove, 1183fbb6c848SEzequiel Garcia .driver = { 1184fbb6c848SEzequiel Garcia .name = DRIVER_NAME, 1185fbb6c848SEzequiel Garcia .of_match_table = of_match_ptr(of_hantro_match), 1186fbb6c848SEzequiel Garcia .pm = &hantro_pm_ops, 1187fbb6c848SEzequiel Garcia }, 1188fbb6c848SEzequiel Garcia }; 1189fbb6c848SEzequiel Garcia module_platform_driver(hantro_driver); 1190fbb6c848SEzequiel Garcia 1191fbb6c848SEzequiel Garcia MODULE_LICENSE("GPL v2"); 1192fbb6c848SEzequiel Garcia MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>"); 1193fbb6c848SEzequiel Garcia MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>"); 1194fbb6c848SEzequiel Garcia MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>"); 1195fbb6c848SEzequiel Garcia MODULE_DESCRIPTION("Hantro VPU codec driver"); 1196