1fbb6c848SEzequiel Garcia // SPDX-License-Identifier: GPL-2.0
2fbb6c848SEzequiel Garcia /*
3fbb6c848SEzequiel Garcia * Hantro VPU codec driver
4fbb6c848SEzequiel Garcia *
5fbb6c848SEzequiel Garcia * Copyright (C) 2018 Collabora, Ltd.
6fbb6c848SEzequiel Garcia * Copyright 2018 Google LLC.
7fbb6c848SEzequiel Garcia * Tomasz Figa <tfiga@chromium.org>
8fbb6c848SEzequiel Garcia *
9fbb6c848SEzequiel Garcia * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
10fbb6c848SEzequiel Garcia * Copyright (C) 2011 Samsung Electronics Co., Ltd.
11fbb6c848SEzequiel Garcia */
12fbb6c848SEzequiel Garcia
13fbb6c848SEzequiel Garcia #include <linux/clk.h>
14fbb6c848SEzequiel Garcia #include <linux/module.h>
15fbb6c848SEzequiel Garcia #include <linux/of.h>
16fbb6c848SEzequiel Garcia #include <linux/platform_device.h>
17fbb6c848SEzequiel Garcia #include <linux/pm.h>
18fbb6c848SEzequiel Garcia #include <linux/pm_runtime.h>
19fbb6c848SEzequiel Garcia #include <linux/slab.h>
20fbb6c848SEzequiel Garcia #include <linux/videodev2.h>
21fbb6c848SEzequiel Garcia #include <linux/workqueue.h>
22fbb6c848SEzequiel Garcia #include <media/v4l2-event.h>
23fbb6c848SEzequiel Garcia #include <media/v4l2-mem2mem.h>
24fbb6c848SEzequiel Garcia #include <media/videobuf2-core.h>
25fbb6c848SEzequiel Garcia #include <media/videobuf2-vmalloc.h>
26fbb6c848SEzequiel Garcia
27fbb6c848SEzequiel Garcia #include "hantro_v4l2.h"
28fbb6c848SEzequiel Garcia #include "hantro.h"
29fbb6c848SEzequiel Garcia #include "hantro_hw.h"
30fbb6c848SEzequiel Garcia
31fbb6c848SEzequiel Garcia #define DRIVER_NAME "hantro-vpu"
32fbb6c848SEzequiel Garcia
33fbb6c848SEzequiel Garcia int hantro_debug;
34fbb6c848SEzequiel Garcia module_param_named(debug, hantro_debug, int, 0644);
35fbb6c848SEzequiel Garcia MODULE_PARM_DESC(debug,
36fbb6c848SEzequiel Garcia "Debug level - higher value produces more verbose messages");
37fbb6c848SEzequiel Garcia
hantro_get_ctrl(struct hantro_ctx * ctx,u32 id)38fbb6c848SEzequiel Garcia void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id)
39fbb6c848SEzequiel Garcia {
40fbb6c848SEzequiel Garcia struct v4l2_ctrl *ctrl;
41fbb6c848SEzequiel Garcia
42fbb6c848SEzequiel Garcia ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id);
43fbb6c848SEzequiel Garcia return ctrl ? ctrl->p_cur.p : NULL;
44fbb6c848SEzequiel Garcia }
45fbb6c848SEzequiel Garcia
hantro_get_ref(struct hantro_ctx * ctx,u64 ts)46fbb6c848SEzequiel Garcia dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts)
47fbb6c848SEzequiel Garcia {
48fbb6c848SEzequiel Garcia struct vb2_queue *q = v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx);
49fbb6c848SEzequiel Garcia struct vb2_buffer *buf;
50fbb6c848SEzequiel Garcia
51fbb6c848SEzequiel Garcia buf = vb2_find_buffer(q, ts);
52fbb6c848SEzequiel Garcia if (!buf)
53fbb6c848SEzequiel Garcia return 0;
54fbb6c848SEzequiel Garcia return hantro_get_dec_buf_addr(ctx, buf);
55fbb6c848SEzequiel Garcia }
56fbb6c848SEzequiel Garcia
57fbb6c848SEzequiel Garcia static const struct v4l2_event hantro_eos_event = {
58fbb6c848SEzequiel Garcia .type = V4L2_EVENT_EOS
59fbb6c848SEzequiel Garcia };
60fbb6c848SEzequiel Garcia
hantro_job_finish_no_pm(struct hantro_dev * vpu,struct hantro_ctx * ctx,enum vb2_buffer_state result)61fbb6c848SEzequiel Garcia static void hantro_job_finish_no_pm(struct hantro_dev *vpu,
62fbb6c848SEzequiel Garcia struct hantro_ctx *ctx,
63fbb6c848SEzequiel Garcia enum vb2_buffer_state result)
64fbb6c848SEzequiel Garcia {
65fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src, *dst;
66fbb6c848SEzequiel Garcia
67fbb6c848SEzequiel Garcia src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
68fbb6c848SEzequiel Garcia dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
69fbb6c848SEzequiel Garcia
70fbb6c848SEzequiel Garcia if (WARN_ON(!src))
71fbb6c848SEzequiel Garcia return;
72fbb6c848SEzequiel Garcia if (WARN_ON(!dst))
73fbb6c848SEzequiel Garcia return;
74fbb6c848SEzequiel Garcia
75fbb6c848SEzequiel Garcia src->sequence = ctx->sequence_out++;
76fbb6c848SEzequiel Garcia dst->sequence = ctx->sequence_cap++;
77fbb6c848SEzequiel Garcia
78fbb6c848SEzequiel Garcia if (v4l2_m2m_is_last_draining_src_buf(ctx->fh.m2m_ctx, src)) {
79fbb6c848SEzequiel Garcia dst->flags |= V4L2_BUF_FLAG_LAST;
80fbb6c848SEzequiel Garcia v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event);
81fbb6c848SEzequiel Garcia v4l2_m2m_mark_stopped(ctx->fh.m2m_ctx);
82fbb6c848SEzequiel Garcia }
83fbb6c848SEzequiel Garcia
84fbb6c848SEzequiel Garcia v4l2_m2m_buf_done_and_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx,
85fbb6c848SEzequiel Garcia result);
86fbb6c848SEzequiel Garcia }
87fbb6c848SEzequiel Garcia
hantro_job_finish(struct hantro_dev * vpu,struct hantro_ctx * ctx,enum vb2_buffer_state result)88fbb6c848SEzequiel Garcia static void hantro_job_finish(struct hantro_dev *vpu,
89fbb6c848SEzequiel Garcia struct hantro_ctx *ctx,
90fbb6c848SEzequiel Garcia enum vb2_buffer_state result)
91fbb6c848SEzequiel Garcia {
92fbb6c848SEzequiel Garcia pm_runtime_mark_last_busy(vpu->dev);
93fbb6c848SEzequiel Garcia pm_runtime_put_autosuspend(vpu->dev);
94fbb6c848SEzequiel Garcia
95fbb6c848SEzequiel Garcia clk_bulk_disable(vpu->variant->num_clocks, vpu->clocks);
96fbb6c848SEzequiel Garcia
97fbb6c848SEzequiel Garcia hantro_job_finish_no_pm(vpu, ctx, result);
98fbb6c848SEzequiel Garcia }
99fbb6c848SEzequiel Garcia
hantro_irq_done(struct hantro_dev * vpu,enum vb2_buffer_state result)100fbb6c848SEzequiel Garcia void hantro_irq_done(struct hantro_dev *vpu,
101fbb6c848SEzequiel Garcia enum vb2_buffer_state result)
102fbb6c848SEzequiel Garcia {
103fbb6c848SEzequiel Garcia struct hantro_ctx *ctx =
104fbb6c848SEzequiel Garcia v4l2_m2m_get_curr_priv(vpu->m2m_dev);
105fbb6c848SEzequiel Garcia
106fbb6c848SEzequiel Garcia /*
107fbb6c848SEzequiel Garcia * If cancel_delayed_work returns false
108fbb6c848SEzequiel Garcia * the timeout expired. The watchdog is running,
109fbb6c848SEzequiel Garcia * and will take care of finishing the job.
110fbb6c848SEzequiel Garcia */
111fbb6c848SEzequiel Garcia if (cancel_delayed_work(&vpu->watchdog_work)) {
112fbb6c848SEzequiel Garcia if (result == VB2_BUF_STATE_DONE && ctx->codec_ops->done)
113fbb6c848SEzequiel Garcia ctx->codec_ops->done(ctx);
114fbb6c848SEzequiel Garcia hantro_job_finish(vpu, ctx, result);
115fbb6c848SEzequiel Garcia }
116fbb6c848SEzequiel Garcia }
117fbb6c848SEzequiel Garcia
hantro_watchdog(struct work_struct * work)118fbb6c848SEzequiel Garcia void hantro_watchdog(struct work_struct *work)
119fbb6c848SEzequiel Garcia {
120fbb6c848SEzequiel Garcia struct hantro_dev *vpu;
121fbb6c848SEzequiel Garcia struct hantro_ctx *ctx;
122fbb6c848SEzequiel Garcia
123fbb6c848SEzequiel Garcia vpu = container_of(to_delayed_work(work),
124fbb6c848SEzequiel Garcia struct hantro_dev, watchdog_work);
125fbb6c848SEzequiel Garcia ctx = v4l2_m2m_get_curr_priv(vpu->m2m_dev);
126fbb6c848SEzequiel Garcia if (ctx) {
127fbb6c848SEzequiel Garcia vpu_err("frame processing timed out!\n");
12824c06295SMarek Vasut if (ctx->codec_ops->reset)
129fbb6c848SEzequiel Garcia ctx->codec_ops->reset(ctx);
130fbb6c848SEzequiel Garcia hantro_job_finish(vpu, ctx, VB2_BUF_STATE_ERROR);
131fbb6c848SEzequiel Garcia }
132fbb6c848SEzequiel Garcia }
133fbb6c848SEzequiel Garcia
hantro_start_prepare_run(struct hantro_ctx * ctx)134fbb6c848SEzequiel Garcia void hantro_start_prepare_run(struct hantro_ctx *ctx)
135fbb6c848SEzequiel Garcia {
136fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src_buf;
137fbb6c848SEzequiel Garcia
138fbb6c848SEzequiel Garcia src_buf = hantro_get_src_buf(ctx);
139fbb6c848SEzequiel Garcia v4l2_ctrl_request_setup(src_buf->vb2_buf.req_obj.req,
140fbb6c848SEzequiel Garcia &ctx->ctrl_handler);
141fbb6c848SEzequiel Garcia
142fbb6c848SEzequiel Garcia if (!ctx->is_encoder && !ctx->dev->variant->late_postproc) {
143fbb6c848SEzequiel Garcia if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
144fbb6c848SEzequiel Garcia hantro_postproc_enable(ctx);
145fbb6c848SEzequiel Garcia else
146fbb6c848SEzequiel Garcia hantro_postproc_disable(ctx);
147fbb6c848SEzequiel Garcia }
148fbb6c848SEzequiel Garcia }
149fbb6c848SEzequiel Garcia
hantro_end_prepare_run(struct hantro_ctx * ctx)150fbb6c848SEzequiel Garcia void hantro_end_prepare_run(struct hantro_ctx *ctx)
151fbb6c848SEzequiel Garcia {
152fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src_buf;
153fbb6c848SEzequiel Garcia
154fbb6c848SEzequiel Garcia if (!ctx->is_encoder && ctx->dev->variant->late_postproc) {
155fbb6c848SEzequiel Garcia if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
156fbb6c848SEzequiel Garcia hantro_postproc_enable(ctx);
157fbb6c848SEzequiel Garcia else
158fbb6c848SEzequiel Garcia hantro_postproc_disable(ctx);
159fbb6c848SEzequiel Garcia }
160fbb6c848SEzequiel Garcia
161fbb6c848SEzequiel Garcia src_buf = hantro_get_src_buf(ctx);
162fbb6c848SEzequiel Garcia v4l2_ctrl_request_complete(src_buf->vb2_buf.req_obj.req,
163fbb6c848SEzequiel Garcia &ctx->ctrl_handler);
164fbb6c848SEzequiel Garcia
165fbb6c848SEzequiel Garcia /* Kick the watchdog. */
166fbb6c848SEzequiel Garcia schedule_delayed_work(&ctx->dev->watchdog_work,
167fbb6c848SEzequiel Garcia msecs_to_jiffies(2000));
168fbb6c848SEzequiel Garcia }
169fbb6c848SEzequiel Garcia
device_run(void * priv)170fbb6c848SEzequiel Garcia static void device_run(void *priv)
171fbb6c848SEzequiel Garcia {
172fbb6c848SEzequiel Garcia struct hantro_ctx *ctx = priv;
173fbb6c848SEzequiel Garcia struct vb2_v4l2_buffer *src, *dst;
174fbb6c848SEzequiel Garcia int ret;
175fbb6c848SEzequiel Garcia
176fbb6c848SEzequiel Garcia src = hantro_get_src_buf(ctx);
177fbb6c848SEzequiel Garcia dst = hantro_get_dst_buf(ctx);
178fbb6c848SEzequiel Garcia
179fbb6c848SEzequiel Garcia ret = pm_runtime_resume_and_get(ctx->dev->dev);
180fbb6c848SEzequiel Garcia if (ret < 0)
181fbb6c848SEzequiel Garcia goto err_cancel_job;
182fbb6c848SEzequiel Garcia
183fbb6c848SEzequiel Garcia ret = clk_bulk_enable(ctx->dev->variant->num_clocks, ctx->dev->clocks);
184fbb6c848SEzequiel Garcia if (ret)
185fbb6c848SEzequiel Garcia goto err_cancel_job;
186fbb6c848SEzequiel Garcia
187fbb6c848SEzequiel Garcia v4l2_m2m_buf_copy_metadata(src, dst, true);
188fbb6c848SEzequiel Garcia
189fbb6c848SEzequiel Garcia if (ctx->codec_ops->run(ctx))
190fbb6c848SEzequiel Garcia goto err_cancel_job;
191fbb6c848SEzequiel Garcia
192fbb6c848SEzequiel Garcia return;
193fbb6c848SEzequiel Garcia
194fbb6c848SEzequiel Garcia err_cancel_job:
195fbb6c848SEzequiel Garcia hantro_job_finish_no_pm(ctx->dev, ctx, VB2_BUF_STATE_ERROR);
196fbb6c848SEzequiel Garcia }
197fbb6c848SEzequiel Garcia
198fbb6c848SEzequiel Garcia static const struct v4l2_m2m_ops vpu_m2m_ops = {
199fbb6c848SEzequiel Garcia .device_run = device_run,
200fbb6c848SEzequiel Garcia };
201fbb6c848SEzequiel Garcia
202fbb6c848SEzequiel Garcia static int
queue_init(void * priv,struct vb2_queue * src_vq,struct vb2_queue * dst_vq)203fbb6c848SEzequiel Garcia queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
204fbb6c848SEzequiel Garcia {
205fbb6c848SEzequiel Garcia struct hantro_ctx *ctx = priv;
206fbb6c848SEzequiel Garcia int ret;
207fbb6c848SEzequiel Garcia
208fbb6c848SEzequiel Garcia src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
209fbb6c848SEzequiel Garcia src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
210fbb6c848SEzequiel Garcia src_vq->drv_priv = ctx;
211fbb6c848SEzequiel Garcia src_vq->ops = &hantro_queue_ops;
212fbb6c848SEzequiel Garcia src_vq->mem_ops = &vb2_dma_contig_memops;
213fbb6c848SEzequiel Garcia
214fbb6c848SEzequiel Garcia /*
215fbb6c848SEzequiel Garcia * Driver does mostly sequential access, so sacrifice TLB efficiency
216fbb6c848SEzequiel Garcia * for faster allocation. Also, no CPU access on the source queue,
217fbb6c848SEzequiel Garcia * so no kernel mapping needed.
218fbb6c848SEzequiel Garcia */
219fbb6c848SEzequiel Garcia src_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES |
220fbb6c848SEzequiel Garcia DMA_ATTR_NO_KERNEL_MAPPING;
221fbb6c848SEzequiel Garcia src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
222fbb6c848SEzequiel Garcia src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
223fbb6c848SEzequiel Garcia src_vq->lock = &ctx->dev->vpu_mutex;
224fbb6c848SEzequiel Garcia src_vq->dev = ctx->dev->v4l2_dev.dev;
225fbb6c848SEzequiel Garcia src_vq->supports_requests = true;
226fbb6c848SEzequiel Garcia
227fbb6c848SEzequiel Garcia ret = vb2_queue_init(src_vq);
228fbb6c848SEzequiel Garcia if (ret)
229fbb6c848SEzequiel Garcia return ret;
230fbb6c848SEzequiel Garcia
231fbb6c848SEzequiel Garcia dst_vq->bidirectional = true;
232fbb6c848SEzequiel Garcia dst_vq->mem_ops = &vb2_dma_contig_memops;
233fbb6c848SEzequiel Garcia dst_vq->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
234fbb6c848SEzequiel Garcia /*
235fbb6c848SEzequiel Garcia * The Kernel needs access to the JPEG destination buffer for the
236fbb6c848SEzequiel Garcia * JPEG encoder to fill in the JPEG headers.
237fbb6c848SEzequiel Garcia */
238fbb6c848SEzequiel Garcia if (!ctx->is_encoder)
239fbb6c848SEzequiel Garcia dst_vq->dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
240fbb6c848SEzequiel Garcia
241fbb6c848SEzequiel Garcia dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
242fbb6c848SEzequiel Garcia dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
243fbb6c848SEzequiel Garcia dst_vq->drv_priv = ctx;
244fbb6c848SEzequiel Garcia dst_vq->ops = &hantro_queue_ops;
245fbb6c848SEzequiel Garcia dst_vq->buf_struct_size = sizeof(struct hantro_decoded_buffer);
246fbb6c848SEzequiel Garcia dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
247fbb6c848SEzequiel Garcia dst_vq->lock = &ctx->dev->vpu_mutex;
248fbb6c848SEzequiel Garcia dst_vq->dev = ctx->dev->v4l2_dev.dev;
249fbb6c848SEzequiel Garcia
250fbb6c848SEzequiel Garcia return vb2_queue_init(dst_vq);
251fbb6c848SEzequiel Garcia }
252fbb6c848SEzequiel Garcia
hantro_try_ctrl(struct v4l2_ctrl * ctrl)253fbb6c848SEzequiel Garcia static int hantro_try_ctrl(struct v4l2_ctrl *ctrl)
254fbb6c848SEzequiel Garcia {
255fbb6c848SEzequiel Garcia if (ctrl->id == V4L2_CID_STATELESS_H264_SPS) {
256fbb6c848SEzequiel Garcia const struct v4l2_ctrl_h264_sps *sps = ctrl->p_new.p_h264_sps;
257fbb6c848SEzequiel Garcia
258fbb6c848SEzequiel Garcia if (sps->chroma_format_idc > 1)
259fbb6c848SEzequiel Garcia /* Only 4:0:0 and 4:2:0 are supported */
260fbb6c848SEzequiel Garcia return -EINVAL;
261fbb6c848SEzequiel Garcia if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
262fbb6c848SEzequiel Garcia /* Luma and chroma bit depth mismatch */
263fbb6c848SEzequiel Garcia return -EINVAL;
264fbb6c848SEzequiel Garcia if (sps->bit_depth_luma_minus8 != 0)
265fbb6c848SEzequiel Garcia /* Only 8-bit is supported */
266fbb6c848SEzequiel Garcia return -EINVAL;
267fbb6c848SEzequiel Garcia } else if (ctrl->id == V4L2_CID_STATELESS_HEVC_SPS) {
268fbb6c848SEzequiel Garcia const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
269fbb6c848SEzequiel Garcia
270d040a24bSBenjamin Gaignard if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
271d040a24bSBenjamin Gaignard /* Only 8-bit and 10-bit are supported */
272fbb6c848SEzequiel Garcia return -EINVAL;
273fbb6c848SEzequiel Garcia } else if (ctrl->id == V4L2_CID_STATELESS_VP9_FRAME) {
274fbb6c848SEzequiel Garcia const struct v4l2_ctrl_vp9_frame *dec_params = ctrl->p_new.p_vp9_frame;
275fbb6c848SEzequiel Garcia
276fbb6c848SEzequiel Garcia /* We only support profile 0 */
277fbb6c848SEzequiel Garcia if (dec_params->profile != 0)
278fbb6c848SEzequiel Garcia return -EINVAL;
2797040ed4eSBenjamin Gaignard } else if (ctrl->id == V4L2_CID_STATELESS_AV1_SEQUENCE) {
2807040ed4eSBenjamin Gaignard const struct v4l2_ctrl_av1_sequence *sequence = ctrl->p_new.p_av1_sequence;
2817040ed4eSBenjamin Gaignard
2827040ed4eSBenjamin Gaignard if (sequence->bit_depth != 8 && sequence->bit_depth != 10)
2837040ed4eSBenjamin Gaignard return -EINVAL;
284fbb6c848SEzequiel Garcia }
2857040ed4eSBenjamin Gaignard
286fbb6c848SEzequiel Garcia return 0;
287fbb6c848SEzequiel Garcia }
288fbb6c848SEzequiel Garcia
hantro_jpeg_s_ctrl(struct v4l2_ctrl * ctrl)289fbb6c848SEzequiel Garcia static int hantro_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
290fbb6c848SEzequiel Garcia {
291fbb6c848SEzequiel Garcia struct hantro_ctx *ctx;
292fbb6c848SEzequiel Garcia
293fbb6c848SEzequiel Garcia ctx = container_of(ctrl->handler,
294fbb6c848SEzequiel Garcia struct hantro_ctx, ctrl_handler);
295fbb6c848SEzequiel Garcia
296fbb6c848SEzequiel Garcia vpu_debug(1, "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
297fbb6c848SEzequiel Garcia
298fbb6c848SEzequiel Garcia switch (ctrl->id) {
299fbb6c848SEzequiel Garcia case V4L2_CID_JPEG_COMPRESSION_QUALITY:
300fbb6c848SEzequiel Garcia ctx->jpeg_quality = ctrl->val;
301fbb6c848SEzequiel Garcia break;
302fbb6c848SEzequiel Garcia default:
303fbb6c848SEzequiel Garcia return -EINVAL;
304fbb6c848SEzequiel Garcia }
305fbb6c848SEzequiel Garcia
306fbb6c848SEzequiel Garcia return 0;
307fbb6c848SEzequiel Garcia }
308fbb6c848SEzequiel Garcia
hantro_vp9_s_ctrl(struct v4l2_ctrl * ctrl)309fbb6c848SEzequiel Garcia static int hantro_vp9_s_ctrl(struct v4l2_ctrl *ctrl)
310fbb6c848SEzequiel Garcia {
311fbb6c848SEzequiel Garcia struct hantro_ctx *ctx;
312fbb6c848SEzequiel Garcia
313fbb6c848SEzequiel Garcia ctx = container_of(ctrl->handler,
314fbb6c848SEzequiel Garcia struct hantro_ctx, ctrl_handler);
315fbb6c848SEzequiel Garcia
316fbb6c848SEzequiel Garcia switch (ctrl->id) {
3173d77e23cSBenjamin Gaignard case V4L2_CID_STATELESS_VP9_FRAME: {
3183d77e23cSBenjamin Gaignard int bit_depth = ctrl->p_new.p_vp9_frame->bit_depth;
3193d77e23cSBenjamin Gaignard
3203d77e23cSBenjamin Gaignard if (ctx->bit_depth == bit_depth)
3213d77e23cSBenjamin Gaignard return 0;
3223d77e23cSBenjamin Gaignard
32380c7373aSBenjamin Gaignard return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC);
3243d77e23cSBenjamin Gaignard }
325fbb6c848SEzequiel Garcia default:
326fbb6c848SEzequiel Garcia return -EINVAL;
327fbb6c848SEzequiel Garcia }
328fbb6c848SEzequiel Garcia
329fbb6c848SEzequiel Garcia return 0;
330fbb6c848SEzequiel Garcia }
331fbb6c848SEzequiel Garcia
hantro_hevc_s_ctrl(struct v4l2_ctrl * ctrl)3326aa3b9c5SBenjamin Gaignard static int hantro_hevc_s_ctrl(struct v4l2_ctrl *ctrl)
3336aa3b9c5SBenjamin Gaignard {
3346aa3b9c5SBenjamin Gaignard struct hantro_ctx *ctx;
3356aa3b9c5SBenjamin Gaignard
3366aa3b9c5SBenjamin Gaignard ctx = container_of(ctrl->handler,
3376aa3b9c5SBenjamin Gaignard struct hantro_ctx, ctrl_handler);
3386aa3b9c5SBenjamin Gaignard
3396aa3b9c5SBenjamin Gaignard switch (ctrl->id) {
340ac5d3db4SBenjamin Gaignard case V4L2_CID_STATELESS_HEVC_SPS: {
341ac5d3db4SBenjamin Gaignard const struct v4l2_ctrl_hevc_sps *sps = ctrl->p_new.p_hevc_sps;
342ac5d3db4SBenjamin Gaignard int bit_depth = sps->bit_depth_luma_minus8 + 8;
343ac5d3db4SBenjamin Gaignard
344ac5d3db4SBenjamin Gaignard if (ctx->bit_depth == bit_depth)
345ac5d3db4SBenjamin Gaignard return 0;
346ac5d3db4SBenjamin Gaignard
34780c7373aSBenjamin Gaignard return hantro_reset_raw_fmt(ctx, bit_depth, HANTRO_AUTO_POSTPROC);
348ac5d3db4SBenjamin Gaignard }
3496aa3b9c5SBenjamin Gaignard default:
3506aa3b9c5SBenjamin Gaignard return -EINVAL;
3516aa3b9c5SBenjamin Gaignard }
3526aa3b9c5SBenjamin Gaignard
3536aa3b9c5SBenjamin Gaignard return 0;
3546aa3b9c5SBenjamin Gaignard }
3556aa3b9c5SBenjamin Gaignard
hantro_av1_s_ctrl(struct v4l2_ctrl * ctrl)3567040ed4eSBenjamin Gaignard static int hantro_av1_s_ctrl(struct v4l2_ctrl *ctrl)
3577040ed4eSBenjamin Gaignard {
3587040ed4eSBenjamin Gaignard struct hantro_ctx *ctx;
3597040ed4eSBenjamin Gaignard
3607040ed4eSBenjamin Gaignard ctx = container_of(ctrl->handler,
3617040ed4eSBenjamin Gaignard struct hantro_ctx, ctrl_handler);
3627040ed4eSBenjamin Gaignard
3637040ed4eSBenjamin Gaignard switch (ctrl->id) {
3647040ed4eSBenjamin Gaignard case V4L2_CID_STATELESS_AV1_SEQUENCE:
3657040ed4eSBenjamin Gaignard {
3667040ed4eSBenjamin Gaignard int bit_depth = ctrl->p_new.p_av1_sequence->bit_depth;
36780c7373aSBenjamin Gaignard bool need_postproc = HANTRO_AUTO_POSTPROC;
3687040ed4eSBenjamin Gaignard
36980c7373aSBenjamin Gaignard if (ctrl->p_new.p_av1_sequence->flags
37080c7373aSBenjamin Gaignard & V4L2_AV1_SEQUENCE_FLAG_FILM_GRAIN_PARAMS_PRESENT)
37180c7373aSBenjamin Gaignard need_postproc = HANTRO_FORCE_POSTPROC;
37280c7373aSBenjamin Gaignard
37380c7373aSBenjamin Gaignard if (ctx->bit_depth == bit_depth &&
37480c7373aSBenjamin Gaignard ctx->need_postproc == need_postproc)
3757040ed4eSBenjamin Gaignard return 0;
3767040ed4eSBenjamin Gaignard
37780c7373aSBenjamin Gaignard return hantro_reset_raw_fmt(ctx, bit_depth, need_postproc);
3787040ed4eSBenjamin Gaignard }
3797040ed4eSBenjamin Gaignard default:
3807040ed4eSBenjamin Gaignard return -EINVAL;
3817040ed4eSBenjamin Gaignard }
3827040ed4eSBenjamin Gaignard
3837040ed4eSBenjamin Gaignard return 0;
3847040ed4eSBenjamin Gaignard }
3857040ed4eSBenjamin Gaignard
386fbb6c848SEzequiel Garcia static const struct v4l2_ctrl_ops hantro_ctrl_ops = {
387fbb6c848SEzequiel Garcia .try_ctrl = hantro_try_ctrl,
388fbb6c848SEzequiel Garcia };
389fbb6c848SEzequiel Garcia
390fbb6c848SEzequiel Garcia static const struct v4l2_ctrl_ops hantro_jpeg_ctrl_ops = {
391fbb6c848SEzequiel Garcia .s_ctrl = hantro_jpeg_s_ctrl,
392fbb6c848SEzequiel Garcia };
393fbb6c848SEzequiel Garcia
394fbb6c848SEzequiel Garcia static const struct v4l2_ctrl_ops hantro_vp9_ctrl_ops = {
395fbb6c848SEzequiel Garcia .s_ctrl = hantro_vp9_s_ctrl,
396fbb6c848SEzequiel Garcia };
397fbb6c848SEzequiel Garcia
3986aa3b9c5SBenjamin Gaignard static const struct v4l2_ctrl_ops hantro_hevc_ctrl_ops = {
3996aa3b9c5SBenjamin Gaignard .try_ctrl = hantro_try_ctrl,
4006aa3b9c5SBenjamin Gaignard .s_ctrl = hantro_hevc_s_ctrl,
4016aa3b9c5SBenjamin Gaignard };
4026aa3b9c5SBenjamin Gaignard
4037040ed4eSBenjamin Gaignard static const struct v4l2_ctrl_ops hantro_av1_ctrl_ops = {
4047040ed4eSBenjamin Gaignard .try_ctrl = hantro_try_ctrl,
4057040ed4eSBenjamin Gaignard .s_ctrl = hantro_av1_s_ctrl,
4067040ed4eSBenjamin Gaignard };
4077040ed4eSBenjamin Gaignard
408fbb6c848SEzequiel Garcia #define HANTRO_JPEG_ACTIVE_MARKERS (V4L2_JPEG_ACTIVE_MARKER_APP0 | \
409fbb6c848SEzequiel Garcia V4L2_JPEG_ACTIVE_MARKER_COM | \
410fbb6c848SEzequiel Garcia V4L2_JPEG_ACTIVE_MARKER_DQT | \
411fbb6c848SEzequiel Garcia V4L2_JPEG_ACTIVE_MARKER_DHT)
412fbb6c848SEzequiel Garcia
413fbb6c848SEzequiel Garcia static const struct hantro_ctrl controls[] = {
414fbb6c848SEzequiel Garcia {
415fbb6c848SEzequiel Garcia .codec = HANTRO_JPEG_ENCODER,
416fbb6c848SEzequiel Garcia .cfg = {
417fbb6c848SEzequiel Garcia .id = V4L2_CID_JPEG_COMPRESSION_QUALITY,
418fbb6c848SEzequiel Garcia .min = 5,
419fbb6c848SEzequiel Garcia .max = 100,
420fbb6c848SEzequiel Garcia .step = 1,
421fbb6c848SEzequiel Garcia .def = 50,
422fbb6c848SEzequiel Garcia .ops = &hantro_jpeg_ctrl_ops,
423fbb6c848SEzequiel Garcia },
424fbb6c848SEzequiel Garcia }, {
425fbb6c848SEzequiel Garcia .codec = HANTRO_JPEG_ENCODER,
426fbb6c848SEzequiel Garcia .cfg = {
427fbb6c848SEzequiel Garcia .id = V4L2_CID_JPEG_ACTIVE_MARKER,
428fbb6c848SEzequiel Garcia .max = HANTRO_JPEG_ACTIVE_MARKERS,
429fbb6c848SEzequiel Garcia .def = HANTRO_JPEG_ACTIVE_MARKERS,
430fbb6c848SEzequiel Garcia /*
431fbb6c848SEzequiel Garcia * Changing the set of active markers/segments also
432fbb6c848SEzequiel Garcia * messes up the alignment of the JPEG header, which
433fbb6c848SEzequiel Garcia * is needed to allow the hardware to write directly
434fbb6c848SEzequiel Garcia * to the output buffer. Implementing this introduces
435fbb6c848SEzequiel Garcia * a lot of complexity for little gain, as the markers
436fbb6c848SEzequiel Garcia * enabled is already the minimum required set.
437fbb6c848SEzequiel Garcia */
438fbb6c848SEzequiel Garcia .flags = V4L2_CTRL_FLAG_READ_ONLY,
439fbb6c848SEzequiel Garcia },
440fbb6c848SEzequiel Garcia }, {
441fbb6c848SEzequiel Garcia .codec = HANTRO_MPEG2_DECODER,
442fbb6c848SEzequiel Garcia .cfg = {
443fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_MPEG2_SEQUENCE,
444fbb6c848SEzequiel Garcia },
445fbb6c848SEzequiel Garcia }, {
446fbb6c848SEzequiel Garcia .codec = HANTRO_MPEG2_DECODER,
447fbb6c848SEzequiel Garcia .cfg = {
448fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_MPEG2_PICTURE,
449fbb6c848SEzequiel Garcia },
450fbb6c848SEzequiel Garcia }, {
451fbb6c848SEzequiel Garcia .codec = HANTRO_MPEG2_DECODER,
452fbb6c848SEzequiel Garcia .cfg = {
453fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_MPEG2_QUANTISATION,
454fbb6c848SEzequiel Garcia },
455fbb6c848SEzequiel Garcia }, {
456fbb6c848SEzequiel Garcia .codec = HANTRO_VP8_DECODER,
457fbb6c848SEzequiel Garcia .cfg = {
458fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_VP8_FRAME,
459fbb6c848SEzequiel Garcia },
460fbb6c848SEzequiel Garcia }, {
461fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
462fbb6c848SEzequiel Garcia .cfg = {
463fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS,
464fbb6c848SEzequiel Garcia },
465fbb6c848SEzequiel Garcia }, {
466fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
467fbb6c848SEzequiel Garcia .cfg = {
468fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_SPS,
469fbb6c848SEzequiel Garcia .ops = &hantro_ctrl_ops,
470fbb6c848SEzequiel Garcia },
471fbb6c848SEzequiel Garcia }, {
472fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
473fbb6c848SEzequiel Garcia .cfg = {
474fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_PPS,
475fbb6c848SEzequiel Garcia },
476fbb6c848SEzequiel Garcia }, {
477fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
478fbb6c848SEzequiel Garcia .cfg = {
479fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_SCALING_MATRIX,
480fbb6c848SEzequiel Garcia },
481fbb6c848SEzequiel Garcia }, {
482fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
483fbb6c848SEzequiel Garcia .cfg = {
484fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_DECODE_MODE,
485fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
486fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
487fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED,
488fbb6c848SEzequiel Garcia },
489fbb6c848SEzequiel Garcia }, {
490fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
491fbb6c848SEzequiel Garcia .cfg = {
492fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_H264_START_CODE,
493fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
494fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
495fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B,
496fbb6c848SEzequiel Garcia },
497fbb6c848SEzequiel Garcia }, {
498fbb6c848SEzequiel Garcia .codec = HANTRO_H264_DECODER,
499fbb6c848SEzequiel Garcia .cfg = {
500fbb6c848SEzequiel Garcia .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE,
501fbb6c848SEzequiel Garcia .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE,
502fbb6c848SEzequiel Garcia .max = V4L2_MPEG_VIDEO_H264_PROFILE_HIGH,
503fbb6c848SEzequiel Garcia .menu_skip_mask =
504fbb6c848SEzequiel Garcia BIT(V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED),
505fbb6c848SEzequiel Garcia .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN,
506fbb6c848SEzequiel Garcia }
507fbb6c848SEzequiel Garcia }, {
508fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
509fbb6c848SEzequiel Garcia .cfg = {
510fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
511fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
512fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
513fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
514fbb6c848SEzequiel Garcia },
515fbb6c848SEzequiel Garcia }, {
516fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
517fbb6c848SEzequiel Garcia .cfg = {
518fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_START_CODE,
519fbb6c848SEzequiel Garcia .min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
520fbb6c848SEzequiel Garcia .max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
521fbb6c848SEzequiel Garcia .def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
522fbb6c848SEzequiel Garcia },
523fbb6c848SEzequiel Garcia }, {
524fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
525fbb6c848SEzequiel Garcia .cfg = {
526fbb6c848SEzequiel Garcia .id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
527fbb6c848SEzequiel Garcia .min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
528fbb6c848SEzequiel Garcia .max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
529fbb6c848SEzequiel Garcia .def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
530fbb6c848SEzequiel Garcia },
531fbb6c848SEzequiel Garcia }, {
532fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
533fbb6c848SEzequiel Garcia .cfg = {
534fbb6c848SEzequiel Garcia .id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
535fbb6c848SEzequiel Garcia .min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
536fbb6c848SEzequiel Garcia .max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
537fbb6c848SEzequiel Garcia },
538fbb6c848SEzequiel Garcia }, {
539fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
540fbb6c848SEzequiel Garcia .cfg = {
541fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_SPS,
5426aa3b9c5SBenjamin Gaignard .ops = &hantro_hevc_ctrl_ops,
543fbb6c848SEzequiel Garcia },
544fbb6c848SEzequiel Garcia }, {
545fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
546fbb6c848SEzequiel Garcia .cfg = {
547fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_PPS,
548fbb6c848SEzequiel Garcia },
549fbb6c848SEzequiel Garcia }, {
550fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
551fbb6c848SEzequiel Garcia .cfg = {
552fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
553fbb6c848SEzequiel Garcia },
554fbb6c848SEzequiel Garcia }, {
555fbb6c848SEzequiel Garcia .codec = HANTRO_HEVC_DECODER,
556fbb6c848SEzequiel Garcia .cfg = {
557fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
558fbb6c848SEzequiel Garcia },
559fbb6c848SEzequiel Garcia }, {
560fbb6c848SEzequiel Garcia .codec = HANTRO_VP9_DECODER,
561fbb6c848SEzequiel Garcia .cfg = {
562fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_VP9_FRAME,
563fbb6c848SEzequiel Garcia .ops = &hantro_vp9_ctrl_ops,
564fbb6c848SEzequiel Garcia },
565fbb6c848SEzequiel Garcia }, {
566fbb6c848SEzequiel Garcia .codec = HANTRO_VP9_DECODER,
567fbb6c848SEzequiel Garcia .cfg = {
568fbb6c848SEzequiel Garcia .id = V4L2_CID_STATELESS_VP9_COMPRESSED_HDR,
569fbb6c848SEzequiel Garcia },
57053421e73SBenjamin Gaignard }, {
57153421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER,
57253421e73SBenjamin Gaignard .cfg = {
57353421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_FRAME,
57453421e73SBenjamin Gaignard },
57553421e73SBenjamin Gaignard }, {
57653421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER,
57753421e73SBenjamin Gaignard .cfg = {
57853421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_TILE_GROUP_ENTRY,
57953421e73SBenjamin Gaignard .dims = { V4L2_AV1_MAX_TILE_COUNT },
58053421e73SBenjamin Gaignard },
58153421e73SBenjamin Gaignard }, {
58253421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER,
58353421e73SBenjamin Gaignard .cfg = {
58453421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_SEQUENCE,
5857040ed4eSBenjamin Gaignard .ops = &hantro_av1_ctrl_ops,
58653421e73SBenjamin Gaignard },
58753421e73SBenjamin Gaignard }, {
58853421e73SBenjamin Gaignard .codec = HANTRO_AV1_DECODER,
58953421e73SBenjamin Gaignard .cfg = {
59053421e73SBenjamin Gaignard .id = V4L2_CID_STATELESS_AV1_FILM_GRAIN,
59153421e73SBenjamin Gaignard },
592fbb6c848SEzequiel Garcia },
593fbb6c848SEzequiel Garcia };
594fbb6c848SEzequiel Garcia
hantro_ctrls_setup(struct hantro_dev * vpu,struct hantro_ctx * ctx,int allowed_codecs)595fbb6c848SEzequiel Garcia static int hantro_ctrls_setup(struct hantro_dev *vpu,
596fbb6c848SEzequiel Garcia struct hantro_ctx *ctx,
597fbb6c848SEzequiel Garcia int allowed_codecs)
598fbb6c848SEzequiel Garcia {
599fbb6c848SEzequiel Garcia int i, num_ctrls = ARRAY_SIZE(controls);
600fbb6c848SEzequiel Garcia
601fbb6c848SEzequiel Garcia v4l2_ctrl_handler_init(&ctx->ctrl_handler, num_ctrls);
602fbb6c848SEzequiel Garcia
603fbb6c848SEzequiel Garcia for (i = 0; i < num_ctrls; i++) {
604fbb6c848SEzequiel Garcia if (!(allowed_codecs & controls[i].codec))
605fbb6c848SEzequiel Garcia continue;
606fbb6c848SEzequiel Garcia
607fbb6c848SEzequiel Garcia v4l2_ctrl_new_custom(&ctx->ctrl_handler,
608fbb6c848SEzequiel Garcia &controls[i].cfg, NULL);
609fbb6c848SEzequiel Garcia if (ctx->ctrl_handler.error) {
610fbb6c848SEzequiel Garcia vpu_err("Adding control (%d) failed %d\n",
611fbb6c848SEzequiel Garcia controls[i].cfg.id,
612fbb6c848SEzequiel Garcia ctx->ctrl_handler.error);
613fbb6c848SEzequiel Garcia v4l2_ctrl_handler_free(&ctx->ctrl_handler);
614fbb6c848SEzequiel Garcia return ctx->ctrl_handler.error;
615fbb6c848SEzequiel Garcia }
616fbb6c848SEzequiel Garcia }
617fbb6c848SEzequiel Garcia return v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
618fbb6c848SEzequiel Garcia }
619fbb6c848SEzequiel Garcia
620fbb6c848SEzequiel Garcia /*
621fbb6c848SEzequiel Garcia * V4L2 file operations.
622fbb6c848SEzequiel Garcia */
623fbb6c848SEzequiel Garcia
hantro_open(struct file * filp)624fbb6c848SEzequiel Garcia static int hantro_open(struct file *filp)
625fbb6c848SEzequiel Garcia {
626fbb6c848SEzequiel Garcia struct hantro_dev *vpu = video_drvdata(filp);
627fbb6c848SEzequiel Garcia struct video_device *vdev = video_devdata(filp);
628fbb6c848SEzequiel Garcia struct hantro_func *func = hantro_vdev_to_func(vdev);
629fbb6c848SEzequiel Garcia struct hantro_ctx *ctx;
630fbb6c848SEzequiel Garcia int allowed_codecs, ret;
631fbb6c848SEzequiel Garcia
632fbb6c848SEzequiel Garcia /*
633fbb6c848SEzequiel Garcia * We do not need any extra locking here, because we operate only
634fbb6c848SEzequiel Garcia * on local data here, except reading few fields from dev, which
635fbb6c848SEzequiel Garcia * do not change through device's lifetime (which is guaranteed by
636fbb6c848SEzequiel Garcia * reference on module from open()) and V4L2 internal objects (such
637fbb6c848SEzequiel Garcia * as vdev and ctx->fh), which have proper locking done in respective
638fbb6c848SEzequiel Garcia * helper functions used here.
639fbb6c848SEzequiel Garcia */
640fbb6c848SEzequiel Garcia
641fbb6c848SEzequiel Garcia ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
642fbb6c848SEzequiel Garcia if (!ctx)
643fbb6c848SEzequiel Garcia return -ENOMEM;
644fbb6c848SEzequiel Garcia
645fbb6c848SEzequiel Garcia ctx->dev = vpu;
646fbb6c848SEzequiel Garcia if (func->id == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
647fbb6c848SEzequiel Garcia allowed_codecs = vpu->variant->codec & HANTRO_ENCODERS;
648fbb6c848SEzequiel Garcia ctx->is_encoder = true;
649fbb6c848SEzequiel Garcia } else if (func->id == MEDIA_ENT_F_PROC_VIDEO_DECODER) {
650fbb6c848SEzequiel Garcia allowed_codecs = vpu->variant->codec & HANTRO_DECODERS;
651fbb6c848SEzequiel Garcia ctx->is_encoder = false;
652fbb6c848SEzequiel Garcia } else {
653fbb6c848SEzequiel Garcia ret = -ENODEV;
654fbb6c848SEzequiel Garcia goto err_ctx_free;
655fbb6c848SEzequiel Garcia }
656fbb6c848SEzequiel Garcia
657fbb6c848SEzequiel Garcia ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(vpu->m2m_dev, ctx, queue_init);
658fbb6c848SEzequiel Garcia if (IS_ERR(ctx->fh.m2m_ctx)) {
659fbb6c848SEzequiel Garcia ret = PTR_ERR(ctx->fh.m2m_ctx);
660fbb6c848SEzequiel Garcia goto err_ctx_free;
661fbb6c848SEzequiel Garcia }
662fbb6c848SEzequiel Garcia
663fbb6c848SEzequiel Garcia v4l2_fh_init(&ctx->fh, vdev);
664fbb6c848SEzequiel Garcia filp->private_data = &ctx->fh;
665fbb6c848SEzequiel Garcia v4l2_fh_add(&ctx->fh);
666fbb6c848SEzequiel Garcia
667fbb6c848SEzequiel Garcia hantro_reset_fmts(ctx);
668fbb6c848SEzequiel Garcia
669fbb6c848SEzequiel Garcia ret = hantro_ctrls_setup(vpu, ctx, allowed_codecs);
670fbb6c848SEzequiel Garcia if (ret) {
671fbb6c848SEzequiel Garcia vpu_err("Failed to set up controls\n");
672fbb6c848SEzequiel Garcia goto err_fh_free;
673fbb6c848SEzequiel Garcia }
674fbb6c848SEzequiel Garcia ctx->fh.ctrl_handler = &ctx->ctrl_handler;
675fbb6c848SEzequiel Garcia
676fbb6c848SEzequiel Garcia return 0;
677fbb6c848SEzequiel Garcia
678fbb6c848SEzequiel Garcia err_fh_free:
679fbb6c848SEzequiel Garcia v4l2_fh_del(&ctx->fh);
680fbb6c848SEzequiel Garcia v4l2_fh_exit(&ctx->fh);
681fbb6c848SEzequiel Garcia err_ctx_free:
682fbb6c848SEzequiel Garcia kfree(ctx);
683fbb6c848SEzequiel Garcia return ret;
684fbb6c848SEzequiel Garcia }
685fbb6c848SEzequiel Garcia
hantro_release(struct file * filp)686fbb6c848SEzequiel Garcia static int hantro_release(struct file *filp)
687fbb6c848SEzequiel Garcia {
688fbb6c848SEzequiel Garcia struct hantro_ctx *ctx =
689fbb6c848SEzequiel Garcia container_of(filp->private_data, struct hantro_ctx, fh);
690fbb6c848SEzequiel Garcia
691fbb6c848SEzequiel Garcia /*
692fbb6c848SEzequiel Garcia * No need for extra locking because this was the last reference
693fbb6c848SEzequiel Garcia * to this file.
694fbb6c848SEzequiel Garcia */
695fbb6c848SEzequiel Garcia v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
696fbb6c848SEzequiel Garcia v4l2_fh_del(&ctx->fh);
697fbb6c848SEzequiel Garcia v4l2_fh_exit(&ctx->fh);
698fbb6c848SEzequiel Garcia v4l2_ctrl_handler_free(&ctx->ctrl_handler);
699fbb6c848SEzequiel Garcia kfree(ctx);
700fbb6c848SEzequiel Garcia
701fbb6c848SEzequiel Garcia return 0;
702fbb6c848SEzequiel Garcia }
703fbb6c848SEzequiel Garcia
704fbb6c848SEzequiel Garcia static const struct v4l2_file_operations hantro_fops = {
705fbb6c848SEzequiel Garcia .owner = THIS_MODULE,
706fbb6c848SEzequiel Garcia .open = hantro_open,
707fbb6c848SEzequiel Garcia .release = hantro_release,
708fbb6c848SEzequiel Garcia .poll = v4l2_m2m_fop_poll,
709fbb6c848SEzequiel Garcia .unlocked_ioctl = video_ioctl2,
710fbb6c848SEzequiel Garcia .mmap = v4l2_m2m_fop_mmap,
711fbb6c848SEzequiel Garcia };
712fbb6c848SEzequiel Garcia
713fbb6c848SEzequiel Garcia static const struct of_device_id of_hantro_match[] = {
714fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_ROCKCHIP
715fbb6c848SEzequiel Garcia { .compatible = "rockchip,px30-vpu", .data = &px30_vpu_variant, },
716fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3036-vpu", .data = &rk3036_vpu_variant, },
717fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3066-vpu", .data = &rk3066_vpu_variant, },
718fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3288-vpu", .data = &rk3288_vpu_variant, },
719fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3328-vpu", .data = &rk3328_vpu_variant, },
720fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, },
721fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3568-vepu", .data = &rk3568_vepu_variant, },
722fbb6c848SEzequiel Garcia { .compatible = "rockchip,rk3568-vpu", .data = &rk3568_vpu_variant, },
723003afda9SBenjamin Gaignard { .compatible = "rockchip,rk3588-av1-vpu", .data = &rk3588_vpu981_variant, },
724fbb6c848SEzequiel Garcia #endif
725fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_IMX8M
726fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, },
727fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, },
728fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant },
729fbb6c848SEzequiel Garcia { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant },
730fbb6c848SEzequiel Garcia #endif
731fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4
732fbb6c848SEzequiel Garcia { .compatible = "microchip,sama5d4-vdec", .data = &sama5d4_vdec_variant, },
733fbb6c848SEzequiel Garcia #endif
734fbb6c848SEzequiel Garcia #ifdef CONFIG_VIDEO_HANTRO_SUNXI
735fbb6c848SEzequiel Garcia { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, },
736fbb6c848SEzequiel Garcia #endif
737fbb6c848SEzequiel Garcia { /* sentinel */ }
738fbb6c848SEzequiel Garcia };
739fbb6c848SEzequiel Garcia MODULE_DEVICE_TABLE(of, of_hantro_match);
740fbb6c848SEzequiel Garcia
hantro_register_entity(struct media_device * mdev,struct media_entity * entity,const char * entity_name,struct media_pad * pads,int num_pads,int function,struct video_device * vdev)741fbb6c848SEzequiel Garcia static int hantro_register_entity(struct media_device *mdev,
742fbb6c848SEzequiel Garcia struct media_entity *entity,
743fbb6c848SEzequiel Garcia const char *entity_name,
744fbb6c848SEzequiel Garcia struct media_pad *pads, int num_pads,
745fbb6c848SEzequiel Garcia int function, struct video_device *vdev)
746fbb6c848SEzequiel Garcia {
747fbb6c848SEzequiel Garcia char *name;
748fbb6c848SEzequiel Garcia int ret;
749fbb6c848SEzequiel Garcia
750fbb6c848SEzequiel Garcia entity->obj_type = MEDIA_ENTITY_TYPE_BASE;
751fbb6c848SEzequiel Garcia if (function == MEDIA_ENT_F_IO_V4L) {
752fbb6c848SEzequiel Garcia entity->info.dev.major = VIDEO_MAJOR;
753fbb6c848SEzequiel Garcia entity->info.dev.minor = vdev->minor;
754fbb6c848SEzequiel Garcia }
755fbb6c848SEzequiel Garcia
756fbb6c848SEzequiel Garcia name = devm_kasprintf(mdev->dev, GFP_KERNEL, "%s-%s", vdev->name,
757fbb6c848SEzequiel Garcia entity_name);
758fbb6c848SEzequiel Garcia if (!name)
759fbb6c848SEzequiel Garcia return -ENOMEM;
760fbb6c848SEzequiel Garcia
761fbb6c848SEzequiel Garcia entity->name = name;
762fbb6c848SEzequiel Garcia entity->function = function;
763fbb6c848SEzequiel Garcia
764fbb6c848SEzequiel Garcia ret = media_entity_pads_init(entity, num_pads, pads);
765fbb6c848SEzequiel Garcia if (ret)
766fbb6c848SEzequiel Garcia return ret;
767fbb6c848SEzequiel Garcia
768fbb6c848SEzequiel Garcia ret = media_device_register_entity(mdev, entity);
769fbb6c848SEzequiel Garcia if (ret)
770fbb6c848SEzequiel Garcia return ret;
771fbb6c848SEzequiel Garcia
772fbb6c848SEzequiel Garcia return 0;
773fbb6c848SEzequiel Garcia }
774fbb6c848SEzequiel Garcia
hantro_attach_func(struct hantro_dev * vpu,struct hantro_func * func)775fbb6c848SEzequiel Garcia static int hantro_attach_func(struct hantro_dev *vpu,
776fbb6c848SEzequiel Garcia struct hantro_func *func)
777fbb6c848SEzequiel Garcia {
778fbb6c848SEzequiel Garcia struct media_device *mdev = &vpu->mdev;
779fbb6c848SEzequiel Garcia struct media_link *link;
780fbb6c848SEzequiel Garcia int ret;
781fbb6c848SEzequiel Garcia
782fbb6c848SEzequiel Garcia /* Create the three encoder entities with their pads */
783fbb6c848SEzequiel Garcia func->source_pad.flags = MEDIA_PAD_FL_SOURCE;
784fbb6c848SEzequiel Garcia ret = hantro_register_entity(mdev, &func->vdev.entity, "source",
785fbb6c848SEzequiel Garcia &func->source_pad, 1, MEDIA_ENT_F_IO_V4L,
786fbb6c848SEzequiel Garcia &func->vdev);
787fbb6c848SEzequiel Garcia if (ret)
788fbb6c848SEzequiel Garcia return ret;
789fbb6c848SEzequiel Garcia
790fbb6c848SEzequiel Garcia func->proc_pads[0].flags = MEDIA_PAD_FL_SINK;
791fbb6c848SEzequiel Garcia func->proc_pads[1].flags = MEDIA_PAD_FL_SOURCE;
792fbb6c848SEzequiel Garcia ret = hantro_register_entity(mdev, &func->proc, "proc",
793fbb6c848SEzequiel Garcia func->proc_pads, 2, func->id,
794fbb6c848SEzequiel Garcia &func->vdev);
795fbb6c848SEzequiel Garcia if (ret)
796fbb6c848SEzequiel Garcia goto err_rel_entity0;
797fbb6c848SEzequiel Garcia
798fbb6c848SEzequiel Garcia func->sink_pad.flags = MEDIA_PAD_FL_SINK;
799fbb6c848SEzequiel Garcia ret = hantro_register_entity(mdev, &func->sink, "sink",
800fbb6c848SEzequiel Garcia &func->sink_pad, 1, MEDIA_ENT_F_IO_V4L,
801fbb6c848SEzequiel Garcia &func->vdev);
802fbb6c848SEzequiel Garcia if (ret)
803fbb6c848SEzequiel Garcia goto err_rel_entity1;
804fbb6c848SEzequiel Garcia
805fbb6c848SEzequiel Garcia /* Connect the three entities */
806fbb6c848SEzequiel Garcia ret = media_create_pad_link(&func->vdev.entity, 0, &func->proc, 0,
807fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE |
808fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED);
809fbb6c848SEzequiel Garcia if (ret)
810fbb6c848SEzequiel Garcia goto err_rel_entity2;
811fbb6c848SEzequiel Garcia
812fbb6c848SEzequiel Garcia ret = media_create_pad_link(&func->proc, 1, &func->sink, 0,
813fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE |
814fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED);
815fbb6c848SEzequiel Garcia if (ret)
816fbb6c848SEzequiel Garcia goto err_rm_links0;
817fbb6c848SEzequiel Garcia
818fbb6c848SEzequiel Garcia /* Create video interface */
819fbb6c848SEzequiel Garcia func->intf_devnode = media_devnode_create(mdev, MEDIA_INTF_T_V4L_VIDEO,
820fbb6c848SEzequiel Garcia 0, VIDEO_MAJOR,
821fbb6c848SEzequiel Garcia func->vdev.minor);
822fbb6c848SEzequiel Garcia if (!func->intf_devnode) {
823fbb6c848SEzequiel Garcia ret = -ENOMEM;
824fbb6c848SEzequiel Garcia goto err_rm_links1;
825fbb6c848SEzequiel Garcia }
826fbb6c848SEzequiel Garcia
827fbb6c848SEzequiel Garcia /* Connect the two DMA engines to the interface */
828fbb6c848SEzequiel Garcia link = media_create_intf_link(&func->vdev.entity,
829fbb6c848SEzequiel Garcia &func->intf_devnode->intf,
830fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE |
831fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED);
832fbb6c848SEzequiel Garcia if (!link) {
833fbb6c848SEzequiel Garcia ret = -ENOMEM;
834fbb6c848SEzequiel Garcia goto err_rm_devnode;
835fbb6c848SEzequiel Garcia }
836fbb6c848SEzequiel Garcia
837fbb6c848SEzequiel Garcia link = media_create_intf_link(&func->sink, &func->intf_devnode->intf,
838fbb6c848SEzequiel Garcia MEDIA_LNK_FL_IMMUTABLE |
839fbb6c848SEzequiel Garcia MEDIA_LNK_FL_ENABLED);
840fbb6c848SEzequiel Garcia if (!link) {
841fbb6c848SEzequiel Garcia ret = -ENOMEM;
842fbb6c848SEzequiel Garcia goto err_rm_devnode;
843fbb6c848SEzequiel Garcia }
844fbb6c848SEzequiel Garcia return 0;
845fbb6c848SEzequiel Garcia
846fbb6c848SEzequiel Garcia err_rm_devnode:
847fbb6c848SEzequiel Garcia media_devnode_remove(func->intf_devnode);
848fbb6c848SEzequiel Garcia
849fbb6c848SEzequiel Garcia err_rm_links1:
850fbb6c848SEzequiel Garcia media_entity_remove_links(&func->sink);
851fbb6c848SEzequiel Garcia
852fbb6c848SEzequiel Garcia err_rm_links0:
853fbb6c848SEzequiel Garcia media_entity_remove_links(&func->proc);
854fbb6c848SEzequiel Garcia media_entity_remove_links(&func->vdev.entity);
855fbb6c848SEzequiel Garcia
856fbb6c848SEzequiel Garcia err_rel_entity2:
857fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->sink);
858fbb6c848SEzequiel Garcia
859fbb6c848SEzequiel Garcia err_rel_entity1:
860fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->proc);
861fbb6c848SEzequiel Garcia
862fbb6c848SEzequiel Garcia err_rel_entity0:
863fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->vdev.entity);
864fbb6c848SEzequiel Garcia return ret;
865fbb6c848SEzequiel Garcia }
866fbb6c848SEzequiel Garcia
hantro_detach_func(struct hantro_func * func)867fbb6c848SEzequiel Garcia static void hantro_detach_func(struct hantro_func *func)
868fbb6c848SEzequiel Garcia {
869fbb6c848SEzequiel Garcia media_devnode_remove(func->intf_devnode);
870fbb6c848SEzequiel Garcia media_entity_remove_links(&func->sink);
871fbb6c848SEzequiel Garcia media_entity_remove_links(&func->proc);
872fbb6c848SEzequiel Garcia media_entity_remove_links(&func->vdev.entity);
873fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->sink);
874fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->proc);
875fbb6c848SEzequiel Garcia media_device_unregister_entity(&func->vdev.entity);
876fbb6c848SEzequiel Garcia }
877fbb6c848SEzequiel Garcia
hantro_add_func(struct hantro_dev * vpu,unsigned int funcid)878fbb6c848SEzequiel Garcia static int hantro_add_func(struct hantro_dev *vpu, unsigned int funcid)
879fbb6c848SEzequiel Garcia {
880fbb6c848SEzequiel Garcia const struct of_device_id *match;
881fbb6c848SEzequiel Garcia struct hantro_func *func;
882fbb6c848SEzequiel Garcia struct video_device *vfd;
883fbb6c848SEzequiel Garcia int ret;
884fbb6c848SEzequiel Garcia
885fbb6c848SEzequiel Garcia match = of_match_node(of_hantro_match, vpu->dev->of_node);
886fbb6c848SEzequiel Garcia func = devm_kzalloc(vpu->dev, sizeof(*func), GFP_KERNEL);
887fbb6c848SEzequiel Garcia if (!func) {
888fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to allocate video device\n");
889fbb6c848SEzequiel Garcia return -ENOMEM;
890fbb6c848SEzequiel Garcia }
891fbb6c848SEzequiel Garcia
892fbb6c848SEzequiel Garcia func->id = funcid;
893fbb6c848SEzequiel Garcia
894fbb6c848SEzequiel Garcia vfd = &func->vdev;
895fbb6c848SEzequiel Garcia vfd->fops = &hantro_fops;
896fbb6c848SEzequiel Garcia vfd->release = video_device_release_empty;
897fbb6c848SEzequiel Garcia vfd->lock = &vpu->vpu_mutex;
898fbb6c848SEzequiel Garcia vfd->v4l2_dev = &vpu->v4l2_dev;
899fbb6c848SEzequiel Garcia vfd->vfl_dir = VFL_DIR_M2M;
900fbb6c848SEzequiel Garcia vfd->device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_M2M_MPLANE;
901fbb6c848SEzequiel Garcia vfd->ioctl_ops = &hantro_ioctl_ops;
902fbb6c848SEzequiel Garcia snprintf(vfd->name, sizeof(vfd->name), "%s-%s", match->compatible,
903fbb6c848SEzequiel Garcia funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER ? "enc" : "dec");
904fbb6c848SEzequiel Garcia
905fbb6c848SEzequiel Garcia if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER) {
906fbb6c848SEzequiel Garcia vpu->encoder = func;
907*682588d3SPaul Kocialkowski v4l2_disable_ioctl(vfd, VIDIOC_TRY_DECODER_CMD);
908*682588d3SPaul Kocialkowski v4l2_disable_ioctl(vfd, VIDIOC_DECODER_CMD);
909fbb6c848SEzequiel Garcia } else {
910fbb6c848SEzequiel Garcia vpu->decoder = func;
911fbb6c848SEzequiel Garcia v4l2_disable_ioctl(vfd, VIDIOC_TRY_ENCODER_CMD);
912fbb6c848SEzequiel Garcia v4l2_disable_ioctl(vfd, VIDIOC_ENCODER_CMD);
913fbb6c848SEzequiel Garcia }
914fbb6c848SEzequiel Garcia
915fbb6c848SEzequiel Garcia video_set_drvdata(vfd, vpu);
916fbb6c848SEzequiel Garcia
917fbb6c848SEzequiel Garcia ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1);
918fbb6c848SEzequiel Garcia if (ret) {
919fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to register video device\n");
920fbb6c848SEzequiel Garcia return ret;
921fbb6c848SEzequiel Garcia }
922fbb6c848SEzequiel Garcia
923fbb6c848SEzequiel Garcia ret = hantro_attach_func(vpu, func);
924fbb6c848SEzequiel Garcia if (ret) {
925fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev,
926fbb6c848SEzequiel Garcia "Failed to attach functionality to the media device\n");
927fbb6c848SEzequiel Garcia goto err_unreg_dev;
928fbb6c848SEzequiel Garcia }
929fbb6c848SEzequiel Garcia
930fbb6c848SEzequiel Garcia v4l2_info(&vpu->v4l2_dev, "registered %s as /dev/video%d\n", vfd->name,
931fbb6c848SEzequiel Garcia vfd->num);
932fbb6c848SEzequiel Garcia
933fbb6c848SEzequiel Garcia return 0;
934fbb6c848SEzequiel Garcia
935fbb6c848SEzequiel Garcia err_unreg_dev:
936fbb6c848SEzequiel Garcia video_unregister_device(vfd);
937fbb6c848SEzequiel Garcia return ret;
938fbb6c848SEzequiel Garcia }
939fbb6c848SEzequiel Garcia
hantro_add_enc_func(struct hantro_dev * vpu)940fbb6c848SEzequiel Garcia static int hantro_add_enc_func(struct hantro_dev *vpu)
941fbb6c848SEzequiel Garcia {
942fbb6c848SEzequiel Garcia if (!vpu->variant->enc_fmts)
943fbb6c848SEzequiel Garcia return 0;
944fbb6c848SEzequiel Garcia
945fbb6c848SEzequiel Garcia return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
946fbb6c848SEzequiel Garcia }
947fbb6c848SEzequiel Garcia
hantro_add_dec_func(struct hantro_dev * vpu)948fbb6c848SEzequiel Garcia static int hantro_add_dec_func(struct hantro_dev *vpu)
949fbb6c848SEzequiel Garcia {
950fbb6c848SEzequiel Garcia if (!vpu->variant->dec_fmts)
951fbb6c848SEzequiel Garcia return 0;
952fbb6c848SEzequiel Garcia
953fbb6c848SEzequiel Garcia return hantro_add_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
954fbb6c848SEzequiel Garcia }
955fbb6c848SEzequiel Garcia
hantro_remove_func(struct hantro_dev * vpu,unsigned int funcid)956fbb6c848SEzequiel Garcia static void hantro_remove_func(struct hantro_dev *vpu,
957fbb6c848SEzequiel Garcia unsigned int funcid)
958fbb6c848SEzequiel Garcia {
959fbb6c848SEzequiel Garcia struct hantro_func *func;
960fbb6c848SEzequiel Garcia
961fbb6c848SEzequiel Garcia if (funcid == MEDIA_ENT_F_PROC_VIDEO_ENCODER)
962fbb6c848SEzequiel Garcia func = vpu->encoder;
963fbb6c848SEzequiel Garcia else
964fbb6c848SEzequiel Garcia func = vpu->decoder;
965fbb6c848SEzequiel Garcia
966fbb6c848SEzequiel Garcia if (!func)
967fbb6c848SEzequiel Garcia return;
968fbb6c848SEzequiel Garcia
969fbb6c848SEzequiel Garcia hantro_detach_func(func);
970fbb6c848SEzequiel Garcia video_unregister_device(&func->vdev);
971fbb6c848SEzequiel Garcia }
972fbb6c848SEzequiel Garcia
hantro_remove_enc_func(struct hantro_dev * vpu)973fbb6c848SEzequiel Garcia static void hantro_remove_enc_func(struct hantro_dev *vpu)
974fbb6c848SEzequiel Garcia {
975fbb6c848SEzequiel Garcia hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_ENCODER);
976fbb6c848SEzequiel Garcia }
977fbb6c848SEzequiel Garcia
hantro_remove_dec_func(struct hantro_dev * vpu)978fbb6c848SEzequiel Garcia static void hantro_remove_dec_func(struct hantro_dev *vpu)
979fbb6c848SEzequiel Garcia {
980fbb6c848SEzequiel Garcia hantro_remove_func(vpu, MEDIA_ENT_F_PROC_VIDEO_DECODER);
981fbb6c848SEzequiel Garcia }
982fbb6c848SEzequiel Garcia
983fbb6c848SEzequiel Garcia static const struct media_device_ops hantro_m2m_media_ops = {
984fbb6c848SEzequiel Garcia .req_validate = vb2_request_validate,
985fbb6c848SEzequiel Garcia .req_queue = v4l2_m2m_request_queue,
986fbb6c848SEzequiel Garcia };
987fbb6c848SEzequiel Garcia
hantro_probe(struct platform_device * pdev)988fbb6c848SEzequiel Garcia static int hantro_probe(struct platform_device *pdev)
989fbb6c848SEzequiel Garcia {
990fbb6c848SEzequiel Garcia const struct of_device_id *match;
991fbb6c848SEzequiel Garcia struct hantro_dev *vpu;
992fbb6c848SEzequiel Garcia int num_bases;
993fbb6c848SEzequiel Garcia int i, ret;
994fbb6c848SEzequiel Garcia
995fbb6c848SEzequiel Garcia vpu = devm_kzalloc(&pdev->dev, sizeof(*vpu), GFP_KERNEL);
996fbb6c848SEzequiel Garcia if (!vpu)
997fbb6c848SEzequiel Garcia return -ENOMEM;
998fbb6c848SEzequiel Garcia
999fbb6c848SEzequiel Garcia vpu->dev = &pdev->dev;
1000fbb6c848SEzequiel Garcia vpu->pdev = pdev;
1001fbb6c848SEzequiel Garcia mutex_init(&vpu->vpu_mutex);
1002fbb6c848SEzequiel Garcia spin_lock_init(&vpu->irqlock);
1003fbb6c848SEzequiel Garcia
1004fbb6c848SEzequiel Garcia match = of_match_node(of_hantro_match, pdev->dev.of_node);
1005fbb6c848SEzequiel Garcia vpu->variant = match->data;
1006fbb6c848SEzequiel Garcia
1007fbb6c848SEzequiel Garcia /*
1008fbb6c848SEzequiel Garcia * Support for nxp,imx8mq-vpu is kept for backwards compatibility
1009fbb6c848SEzequiel Garcia * but it's deprecated. Please update your DTS file to use
1010fbb6c848SEzequiel Garcia * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead.
1011fbb6c848SEzequiel Garcia */
1012fbb6c848SEzequiel Garcia if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu"))
1013fbb6c848SEzequiel Garcia dev_warn(&pdev->dev, "%s compatible is deprecated\n",
1014fbb6c848SEzequiel Garcia match->compatible);
1015fbb6c848SEzequiel Garcia
1016fbb6c848SEzequiel Garcia INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog);
1017fbb6c848SEzequiel Garcia
1018fbb6c848SEzequiel Garcia vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks,
1019fbb6c848SEzequiel Garcia sizeof(*vpu->clocks), GFP_KERNEL);
1020fbb6c848SEzequiel Garcia if (!vpu->clocks)
1021fbb6c848SEzequiel Garcia return -ENOMEM;
1022fbb6c848SEzequiel Garcia
1023fbb6c848SEzequiel Garcia if (vpu->variant->num_clocks > 1) {
1024fbb6c848SEzequiel Garcia for (i = 0; i < vpu->variant->num_clocks; i++)
1025fbb6c848SEzequiel Garcia vpu->clocks[i].id = vpu->variant->clk_names[i];
1026fbb6c848SEzequiel Garcia
1027fbb6c848SEzequiel Garcia ret = devm_clk_bulk_get(&pdev->dev, vpu->variant->num_clocks,
1028fbb6c848SEzequiel Garcia vpu->clocks);
1029fbb6c848SEzequiel Garcia if (ret)
1030fbb6c848SEzequiel Garcia return ret;
1031fbb6c848SEzequiel Garcia } else {
1032fbb6c848SEzequiel Garcia /*
1033fbb6c848SEzequiel Garcia * If the driver has a single clk, chances are there will be no
1034fbb6c848SEzequiel Garcia * actual name in the DT bindings.
1035fbb6c848SEzequiel Garcia */
1036fbb6c848SEzequiel Garcia vpu->clocks[0].clk = devm_clk_get(&pdev->dev, NULL);
1037fbb6c848SEzequiel Garcia if (IS_ERR(vpu->clocks[0].clk))
1038fbb6c848SEzequiel Garcia return PTR_ERR(vpu->clocks[0].clk);
1039fbb6c848SEzequiel Garcia }
1040fbb6c848SEzequiel Garcia
10410b44232bSYe Xingchen vpu->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);
1042fbb6c848SEzequiel Garcia if (IS_ERR(vpu->resets))
1043fbb6c848SEzequiel Garcia return PTR_ERR(vpu->resets);
1044fbb6c848SEzequiel Garcia
1045fbb6c848SEzequiel Garcia num_bases = vpu->variant->num_regs ?: 1;
1046fbb6c848SEzequiel Garcia vpu->reg_bases = devm_kcalloc(&pdev->dev, num_bases,
1047fbb6c848SEzequiel Garcia sizeof(*vpu->reg_bases), GFP_KERNEL);
1048fbb6c848SEzequiel Garcia if (!vpu->reg_bases)
1049fbb6c848SEzequiel Garcia return -ENOMEM;
1050fbb6c848SEzequiel Garcia
1051fbb6c848SEzequiel Garcia for (i = 0; i < num_bases; i++) {
10523490891fSYangtao Li vpu->reg_bases[i] = vpu->variant->reg_names ?
10533490891fSYangtao Li devm_platform_ioremap_resource_byname(pdev, vpu->variant->reg_names[i]) :
10543490891fSYangtao Li devm_platform_ioremap_resource(pdev, 0);
1055fbb6c848SEzequiel Garcia if (IS_ERR(vpu->reg_bases[i]))
1056fbb6c848SEzequiel Garcia return PTR_ERR(vpu->reg_bases[i]);
1057fbb6c848SEzequiel Garcia }
1058fbb6c848SEzequiel Garcia vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset;
1059fbb6c848SEzequiel Garcia vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset;
1060fbb6c848SEzequiel Garcia
1061fbb6c848SEzequiel Garcia /**
1062fbb6c848SEzequiel Garcia * TODO: Eventually allow taking advantage of full 64-bit address space.
1063fbb6c848SEzequiel Garcia * Until then we assume the MSB portion of buffers' base addresses is
1064fbb6c848SEzequiel Garcia * always 0 due to this masking operation.
1065fbb6c848SEzequiel Garcia */
1066fbb6c848SEzequiel Garcia ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32));
1067fbb6c848SEzequiel Garcia if (ret) {
1068fbb6c848SEzequiel Garcia dev_err(vpu->dev, "Could not set DMA coherent mask.\n");
1069fbb6c848SEzequiel Garcia return ret;
1070fbb6c848SEzequiel Garcia }
1071fbb6c848SEzequiel Garcia vb2_dma_contig_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32));
1072fbb6c848SEzequiel Garcia
1073fbb6c848SEzequiel Garcia for (i = 0; i < vpu->variant->num_irqs; i++) {
1074fbb6c848SEzequiel Garcia const char *irq_name;
1075fbb6c848SEzequiel Garcia int irq;
1076fbb6c848SEzequiel Garcia
1077fbb6c848SEzequiel Garcia if (!vpu->variant->irqs[i].handler)
1078fbb6c848SEzequiel Garcia continue;
1079fbb6c848SEzequiel Garcia
1080fbb6c848SEzequiel Garcia if (vpu->variant->num_irqs > 1) {
1081fbb6c848SEzequiel Garcia irq_name = vpu->variant->irqs[i].name;
1082fbb6c848SEzequiel Garcia irq = platform_get_irq_byname(vpu->pdev, irq_name);
1083fbb6c848SEzequiel Garcia } else {
1084fbb6c848SEzequiel Garcia /*
1085fbb6c848SEzequiel Garcia * If the driver has a single IRQ, chances are there
1086fbb6c848SEzequiel Garcia * will be no actual name in the DT bindings.
1087fbb6c848SEzequiel Garcia */
1088fbb6c848SEzequiel Garcia irq_name = "default";
1089fbb6c848SEzequiel Garcia irq = platform_get_irq(vpu->pdev, 0);
1090fbb6c848SEzequiel Garcia }
1091f312dc7cSRuan Jinjie if (irq < 0)
1092f312dc7cSRuan Jinjie return irq;
1093fbb6c848SEzequiel Garcia
1094fbb6c848SEzequiel Garcia ret = devm_request_irq(vpu->dev, irq,
1095fbb6c848SEzequiel Garcia vpu->variant->irqs[i].handler, 0,
1096fbb6c848SEzequiel Garcia dev_name(vpu->dev), vpu);
1097fbb6c848SEzequiel Garcia if (ret) {
1098fbb6c848SEzequiel Garcia dev_err(vpu->dev, "Could not request %s IRQ.\n",
1099fbb6c848SEzequiel Garcia irq_name);
1100fbb6c848SEzequiel Garcia return ret;
1101fbb6c848SEzequiel Garcia }
1102fbb6c848SEzequiel Garcia }
1103fbb6c848SEzequiel Garcia
1104fbb6c848SEzequiel Garcia if (vpu->variant->init) {
1105fbb6c848SEzequiel Garcia ret = vpu->variant->init(vpu);
1106fbb6c848SEzequiel Garcia if (ret) {
1107fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to init VPU hardware\n");
1108fbb6c848SEzequiel Garcia return ret;
1109fbb6c848SEzequiel Garcia }
1110fbb6c848SEzequiel Garcia }
1111fbb6c848SEzequiel Garcia
1112fbb6c848SEzequiel Garcia pm_runtime_set_autosuspend_delay(vpu->dev, 100);
1113fbb6c848SEzequiel Garcia pm_runtime_use_autosuspend(vpu->dev);
1114fbb6c848SEzequiel Garcia pm_runtime_enable(vpu->dev);
1115fbb6c848SEzequiel Garcia
1116fbb6c848SEzequiel Garcia ret = reset_control_deassert(vpu->resets);
1117fbb6c848SEzequiel Garcia if (ret) {
1118fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to deassert resets\n");
1119fbb6c848SEzequiel Garcia goto err_pm_disable;
1120fbb6c848SEzequiel Garcia }
1121fbb6c848SEzequiel Garcia
1122fbb6c848SEzequiel Garcia ret = clk_bulk_prepare(vpu->variant->num_clocks, vpu->clocks);
1123fbb6c848SEzequiel Garcia if (ret) {
1124fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to prepare clocks\n");
1125fbb6c848SEzequiel Garcia goto err_rst_assert;
1126fbb6c848SEzequiel Garcia }
1127fbb6c848SEzequiel Garcia
1128fbb6c848SEzequiel Garcia ret = v4l2_device_register(&pdev->dev, &vpu->v4l2_dev);
1129fbb6c848SEzequiel Garcia if (ret) {
1130fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to register v4l2 device\n");
1131fbb6c848SEzequiel Garcia goto err_clk_unprepare;
1132fbb6c848SEzequiel Garcia }
1133fbb6c848SEzequiel Garcia platform_set_drvdata(pdev, vpu);
1134fbb6c848SEzequiel Garcia
1135fbb6c848SEzequiel Garcia vpu->m2m_dev = v4l2_m2m_init(&vpu_m2m_ops);
1136fbb6c848SEzequiel Garcia if (IS_ERR(vpu->m2m_dev)) {
1137fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to init mem2mem device\n");
1138fbb6c848SEzequiel Garcia ret = PTR_ERR(vpu->m2m_dev);
1139fbb6c848SEzequiel Garcia goto err_v4l2_unreg;
1140fbb6c848SEzequiel Garcia }
1141fbb6c848SEzequiel Garcia
1142fbb6c848SEzequiel Garcia vpu->mdev.dev = vpu->dev;
1143fbb6c848SEzequiel Garcia strscpy(vpu->mdev.model, DRIVER_NAME, sizeof(vpu->mdev.model));
1144fbb6c848SEzequiel Garcia media_device_init(&vpu->mdev);
1145fbb6c848SEzequiel Garcia vpu->mdev.ops = &hantro_m2m_media_ops;
1146fbb6c848SEzequiel Garcia vpu->v4l2_dev.mdev = &vpu->mdev;
1147fbb6c848SEzequiel Garcia
1148fbb6c848SEzequiel Garcia ret = hantro_add_enc_func(vpu);
1149fbb6c848SEzequiel Garcia if (ret) {
1150fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to register encoder\n");
1151fbb6c848SEzequiel Garcia goto err_m2m_rel;
1152fbb6c848SEzequiel Garcia }
1153fbb6c848SEzequiel Garcia
1154fbb6c848SEzequiel Garcia ret = hantro_add_dec_func(vpu);
1155fbb6c848SEzequiel Garcia if (ret) {
1156fbb6c848SEzequiel Garcia dev_err(&pdev->dev, "Failed to register decoder\n");
1157fbb6c848SEzequiel Garcia goto err_rm_enc_func;
1158fbb6c848SEzequiel Garcia }
1159fbb6c848SEzequiel Garcia
1160fbb6c848SEzequiel Garcia ret = media_device_register(&vpu->mdev);
1161fbb6c848SEzequiel Garcia if (ret) {
1162fbb6c848SEzequiel Garcia v4l2_err(&vpu->v4l2_dev, "Failed to register mem2mem media device\n");
1163fbb6c848SEzequiel Garcia goto err_rm_dec_func;
1164fbb6c848SEzequiel Garcia }
1165fbb6c848SEzequiel Garcia
1166fbb6c848SEzequiel Garcia return 0;
1167fbb6c848SEzequiel Garcia
1168fbb6c848SEzequiel Garcia err_rm_dec_func:
1169fbb6c848SEzequiel Garcia hantro_remove_dec_func(vpu);
1170fbb6c848SEzequiel Garcia err_rm_enc_func:
1171fbb6c848SEzequiel Garcia hantro_remove_enc_func(vpu);
1172fbb6c848SEzequiel Garcia err_m2m_rel:
1173fbb6c848SEzequiel Garcia media_device_cleanup(&vpu->mdev);
1174fbb6c848SEzequiel Garcia v4l2_m2m_release(vpu->m2m_dev);
1175fbb6c848SEzequiel Garcia err_v4l2_unreg:
1176fbb6c848SEzequiel Garcia v4l2_device_unregister(&vpu->v4l2_dev);
1177fbb6c848SEzequiel Garcia err_clk_unprepare:
1178fbb6c848SEzequiel Garcia clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1179fbb6c848SEzequiel Garcia err_rst_assert:
1180fbb6c848SEzequiel Garcia reset_control_assert(vpu->resets);
1181fbb6c848SEzequiel Garcia err_pm_disable:
1182fbb6c848SEzequiel Garcia pm_runtime_dont_use_autosuspend(vpu->dev);
1183fbb6c848SEzequiel Garcia pm_runtime_disable(vpu->dev);
1184fbb6c848SEzequiel Garcia return ret;
1185fbb6c848SEzequiel Garcia }
1186fbb6c848SEzequiel Garcia
hantro_remove(struct platform_device * pdev)1187b9294ba9SUwe Kleine-König static void hantro_remove(struct platform_device *pdev)
1188fbb6c848SEzequiel Garcia {
1189fbb6c848SEzequiel Garcia struct hantro_dev *vpu = platform_get_drvdata(pdev);
1190fbb6c848SEzequiel Garcia
1191fbb6c848SEzequiel Garcia v4l2_info(&vpu->v4l2_dev, "Removing %s\n", pdev->name);
1192fbb6c848SEzequiel Garcia
1193fbb6c848SEzequiel Garcia media_device_unregister(&vpu->mdev);
1194fbb6c848SEzequiel Garcia hantro_remove_dec_func(vpu);
1195fbb6c848SEzequiel Garcia hantro_remove_enc_func(vpu);
1196fbb6c848SEzequiel Garcia media_device_cleanup(&vpu->mdev);
1197fbb6c848SEzequiel Garcia v4l2_m2m_release(vpu->m2m_dev);
1198fbb6c848SEzequiel Garcia v4l2_device_unregister(&vpu->v4l2_dev);
1199fbb6c848SEzequiel Garcia clk_bulk_unprepare(vpu->variant->num_clocks, vpu->clocks);
1200fbb6c848SEzequiel Garcia reset_control_assert(vpu->resets);
1201fbb6c848SEzequiel Garcia pm_runtime_dont_use_autosuspend(vpu->dev);
1202fbb6c848SEzequiel Garcia pm_runtime_disable(vpu->dev);
1203fbb6c848SEzequiel Garcia }
1204fbb6c848SEzequiel Garcia
1205fbb6c848SEzequiel Garcia #ifdef CONFIG_PM
hantro_runtime_resume(struct device * dev)1206fbb6c848SEzequiel Garcia static int hantro_runtime_resume(struct device *dev)
1207fbb6c848SEzequiel Garcia {
1208fbb6c848SEzequiel Garcia struct hantro_dev *vpu = dev_get_drvdata(dev);
1209fbb6c848SEzequiel Garcia
1210fbb6c848SEzequiel Garcia if (vpu->variant->runtime_resume)
1211fbb6c848SEzequiel Garcia return vpu->variant->runtime_resume(vpu);
1212fbb6c848SEzequiel Garcia
1213fbb6c848SEzequiel Garcia return 0;
1214fbb6c848SEzequiel Garcia }
1215fbb6c848SEzequiel Garcia #endif
1216fbb6c848SEzequiel Garcia
1217fbb6c848SEzequiel Garcia static const struct dev_pm_ops hantro_pm_ops = {
1218fbb6c848SEzequiel Garcia SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1219fbb6c848SEzequiel Garcia pm_runtime_force_resume)
1220fbb6c848SEzequiel Garcia SET_RUNTIME_PM_OPS(NULL, hantro_runtime_resume, NULL)
1221fbb6c848SEzequiel Garcia };
1222fbb6c848SEzequiel Garcia
1223fbb6c848SEzequiel Garcia static struct platform_driver hantro_driver = {
1224fbb6c848SEzequiel Garcia .probe = hantro_probe,
1225b9294ba9SUwe Kleine-König .remove_new = hantro_remove,
1226fbb6c848SEzequiel Garcia .driver = {
1227fbb6c848SEzequiel Garcia .name = DRIVER_NAME,
1228b34434d4SKrzysztof Kozlowski .of_match_table = of_hantro_match,
1229fbb6c848SEzequiel Garcia .pm = &hantro_pm_ops,
1230fbb6c848SEzequiel Garcia },
1231fbb6c848SEzequiel Garcia };
1232fbb6c848SEzequiel Garcia module_platform_driver(hantro_driver);
1233fbb6c848SEzequiel Garcia
1234fbb6c848SEzequiel Garcia MODULE_LICENSE("GPL v2");
1235fbb6c848SEzequiel Garcia MODULE_AUTHOR("Alpha Lin <Alpha.Lin@Rock-Chips.com>");
1236fbb6c848SEzequiel Garcia MODULE_AUTHOR("Tomasz Figa <tfiga@chromium.org>");
1237fbb6c848SEzequiel Garcia MODULE_AUTHOR("Ezequiel Garcia <ezequiel@collabora.com>");
1238fbb6c848SEzequiel Garcia MODULE_DESCRIPTION("Hantro VPU codec driver");
1239