1fbb6c848SEzequiel Garcia /* SPDX-License-Identifier: GPL-2.0 */
2fbb6c848SEzequiel Garcia /*
3fbb6c848SEzequiel Garcia * Hantro VPU codec driver
4fbb6c848SEzequiel Garcia *
5fbb6c848SEzequiel Garcia * Copyright 2018 Google LLC.
6fbb6c848SEzequiel Garcia * Tomasz Figa <tfiga@chromium.org>
7fbb6c848SEzequiel Garcia *
8fbb6c848SEzequiel Garcia * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9fbb6c848SEzequiel Garcia * Copyright (C) 2011 Samsung Electronics Co., Ltd.
10fbb6c848SEzequiel Garcia */
11fbb6c848SEzequiel Garcia
12fbb6c848SEzequiel Garcia #ifndef HANTRO_H_
13fbb6c848SEzequiel Garcia #define HANTRO_H_
14fbb6c848SEzequiel Garcia
15fbb6c848SEzequiel Garcia #include <linux/platform_device.h>
16fbb6c848SEzequiel Garcia #include <linux/videodev2.h>
17fbb6c848SEzequiel Garcia #include <linux/wait.h>
18fbb6c848SEzequiel Garcia #include <linux/clk.h>
19fbb6c848SEzequiel Garcia #include <linux/reset.h>
20fbb6c848SEzequiel Garcia
21fbb6c848SEzequiel Garcia #include <media/v4l2-ctrls.h>
22fbb6c848SEzequiel Garcia #include <media/v4l2-device.h>
23fbb6c848SEzequiel Garcia #include <media/v4l2-ioctl.h>
24fbb6c848SEzequiel Garcia #include <media/v4l2-mem2mem.h>
25fbb6c848SEzequiel Garcia #include <media/videobuf2-core.h>
26fbb6c848SEzequiel Garcia #include <media/videobuf2-dma-contig.h>
27fbb6c848SEzequiel Garcia
28fbb6c848SEzequiel Garcia #include "hantro_hw.h"
29fbb6c848SEzequiel Garcia
30fbb6c848SEzequiel Garcia struct hantro_ctx;
31fbb6c848SEzequiel Garcia struct hantro_codec_ops;
32fbb6c848SEzequiel Garcia struct hantro_postproc_ops;
33fbb6c848SEzequiel Garcia
34fbb6c848SEzequiel Garcia #define HANTRO_JPEG_ENCODER BIT(0)
35fbb6c848SEzequiel Garcia #define HANTRO_ENCODERS 0x0000ffff
36fbb6c848SEzequiel Garcia #define HANTRO_MPEG2_DECODER BIT(16)
37fbb6c848SEzequiel Garcia #define HANTRO_VP8_DECODER BIT(17)
38fbb6c848SEzequiel Garcia #define HANTRO_H264_DECODER BIT(18)
39fbb6c848SEzequiel Garcia #define HANTRO_HEVC_DECODER BIT(19)
40fbb6c848SEzequiel Garcia #define HANTRO_VP9_DECODER BIT(20)
4153421e73SBenjamin Gaignard #define HANTRO_AV1_DECODER BIT(21)
42fbb6c848SEzequiel Garcia #define HANTRO_DECODERS 0xffff0000
43fbb6c848SEzequiel Garcia
44fbb6c848SEzequiel Garcia /**
45fbb6c848SEzequiel Garcia * struct hantro_irq - irq handler and name
46fbb6c848SEzequiel Garcia *
47fbb6c848SEzequiel Garcia * @name: irq name for device tree lookup
48fbb6c848SEzequiel Garcia * @handler: interrupt handler
49fbb6c848SEzequiel Garcia */
50fbb6c848SEzequiel Garcia struct hantro_irq {
51fbb6c848SEzequiel Garcia const char *name;
52fbb6c848SEzequiel Garcia irqreturn_t (*handler)(int irq, void *priv);
53fbb6c848SEzequiel Garcia };
54fbb6c848SEzequiel Garcia
55fbb6c848SEzequiel Garcia /**
56fbb6c848SEzequiel Garcia * struct hantro_variant - information about VPU hardware variant
57fbb6c848SEzequiel Garcia *
58fbb6c848SEzequiel Garcia * @enc_offset: Offset from VPU base to encoder registers.
59fbb6c848SEzequiel Garcia * @dec_offset: Offset from VPU base to decoder registers.
60fbb6c848SEzequiel Garcia * @enc_fmts: Encoder formats.
61fbb6c848SEzequiel Garcia * @num_enc_fmts: Number of encoder formats.
62fbb6c848SEzequiel Garcia * @dec_fmts: Decoder formats.
63fbb6c848SEzequiel Garcia * @num_dec_fmts: Number of decoder formats.
64fbb6c848SEzequiel Garcia * @postproc_fmts: Post-processor formats.
65fbb6c848SEzequiel Garcia * @num_postproc_fmts: Number of post-processor formats.
66fbb6c848SEzequiel Garcia * @postproc_ops: Post-processor ops.
67fbb6c848SEzequiel Garcia * @codec: Supported codecs
68fbb6c848SEzequiel Garcia * @codec_ops: Codec ops.
69fbb6c848SEzequiel Garcia * @init: Initialize hardware, optional.
70fbb6c848SEzequiel Garcia * @runtime_resume: reenable hardware after power gating, optional.
71fbb6c848SEzequiel Garcia * @irqs: array of irq names and interrupt handlers
72fbb6c848SEzequiel Garcia * @num_irqs: number of irqs in the array
73fbb6c848SEzequiel Garcia * @clk_names: array of clock names
74fbb6c848SEzequiel Garcia * @num_clocks: number of clocks in the array
75fbb6c848SEzequiel Garcia * @reg_names: array of register range names
76fbb6c848SEzequiel Garcia * @num_regs: number of register range names in the array
77fbb6c848SEzequiel Garcia * @double_buffer: core needs double buffering
78fbb6c848SEzequiel Garcia * @legacy_regs: core uses legacy register set
79fbb6c848SEzequiel Garcia * @late_postproc: postproc must be set up at the end of the job
80fbb6c848SEzequiel Garcia */
81fbb6c848SEzequiel Garcia struct hantro_variant {
82fbb6c848SEzequiel Garcia unsigned int enc_offset;
83fbb6c848SEzequiel Garcia unsigned int dec_offset;
84fbb6c848SEzequiel Garcia const struct hantro_fmt *enc_fmts;
85fbb6c848SEzequiel Garcia unsigned int num_enc_fmts;
86fbb6c848SEzequiel Garcia const struct hantro_fmt *dec_fmts;
87fbb6c848SEzequiel Garcia unsigned int num_dec_fmts;
88fbb6c848SEzequiel Garcia const struct hantro_fmt *postproc_fmts;
89fbb6c848SEzequiel Garcia unsigned int num_postproc_fmts;
90fbb6c848SEzequiel Garcia const struct hantro_postproc_ops *postproc_ops;
91fbb6c848SEzequiel Garcia unsigned int codec;
92fbb6c848SEzequiel Garcia const struct hantro_codec_ops *codec_ops;
93fbb6c848SEzequiel Garcia int (*init)(struct hantro_dev *vpu);
94fbb6c848SEzequiel Garcia int (*runtime_resume)(struct hantro_dev *vpu);
95fbb6c848SEzequiel Garcia const struct hantro_irq *irqs;
96fbb6c848SEzequiel Garcia int num_irqs;
97fbb6c848SEzequiel Garcia const char * const *clk_names;
98fbb6c848SEzequiel Garcia int num_clocks;
99fbb6c848SEzequiel Garcia const char * const *reg_names;
100fbb6c848SEzequiel Garcia int num_regs;
101fbb6c848SEzequiel Garcia unsigned int double_buffer : 1;
102fbb6c848SEzequiel Garcia unsigned int legacy_regs : 1;
103fbb6c848SEzequiel Garcia unsigned int late_postproc : 1;
104fbb6c848SEzequiel Garcia };
105fbb6c848SEzequiel Garcia
106fbb6c848SEzequiel Garcia /**
107fbb6c848SEzequiel Garcia * enum hantro_codec_mode - codec operating mode.
108fbb6c848SEzequiel Garcia * @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
109fbb6c848SEzequiel Garcia * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
110fbb6c848SEzequiel Garcia * @HANTRO_MODE_H264_DEC: H264 decoder.
111fbb6c848SEzequiel Garcia * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
112fbb6c848SEzequiel Garcia * @HANTRO_MODE_VP8_DEC: VP8 decoder.
113fbb6c848SEzequiel Garcia * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
114fbb6c848SEzequiel Garcia * @HANTRO_MODE_VP9_DEC: VP9 decoder.
11553421e73SBenjamin Gaignard * @HANTRO_MODE_AV1_DEC: AV1 decoder
116fbb6c848SEzequiel Garcia */
117fbb6c848SEzequiel Garcia enum hantro_codec_mode {
118fbb6c848SEzequiel Garcia HANTRO_MODE_NONE = -1,
119fbb6c848SEzequiel Garcia HANTRO_MODE_JPEG_ENC,
120fbb6c848SEzequiel Garcia HANTRO_MODE_H264_DEC,
121fbb6c848SEzequiel Garcia HANTRO_MODE_MPEG2_DEC,
122fbb6c848SEzequiel Garcia HANTRO_MODE_VP8_DEC,
123fbb6c848SEzequiel Garcia HANTRO_MODE_HEVC_DEC,
124fbb6c848SEzequiel Garcia HANTRO_MODE_VP9_DEC,
12553421e73SBenjamin Gaignard HANTRO_MODE_AV1_DEC,
126fbb6c848SEzequiel Garcia };
127fbb6c848SEzequiel Garcia
128fbb6c848SEzequiel Garcia /*
129fbb6c848SEzequiel Garcia * struct hantro_ctrl - helper type to declare supported controls
130fbb6c848SEzequiel Garcia * @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
131fbb6c848SEzequiel Garcia * @cfg: control configuration
132fbb6c848SEzequiel Garcia */
133fbb6c848SEzequiel Garcia struct hantro_ctrl {
134fbb6c848SEzequiel Garcia unsigned int codec;
135fbb6c848SEzequiel Garcia struct v4l2_ctrl_config cfg;
136fbb6c848SEzequiel Garcia };
137fbb6c848SEzequiel Garcia
138fbb6c848SEzequiel Garcia /*
139fbb6c848SEzequiel Garcia * struct hantro_func - Hantro VPU functionality
140fbb6c848SEzequiel Garcia *
141fbb6c848SEzequiel Garcia * @id: processing functionality ID (can be
142fbb6c848SEzequiel Garcia * %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
143fbb6c848SEzequiel Garcia * %MEDIA_ENT_F_PROC_VIDEO_DECODER)
144fbb6c848SEzequiel Garcia * @vdev: &struct video_device that exposes the encoder or
145fbb6c848SEzequiel Garcia * decoder functionality
146fbb6c848SEzequiel Garcia * @source_pad: &struct media_pad with the source pad.
147fbb6c848SEzequiel Garcia * @sink: &struct media_entity pointer with the sink entity
148fbb6c848SEzequiel Garcia * @sink_pad: &struct media_pad with the sink pad.
149fbb6c848SEzequiel Garcia * @proc: &struct media_entity pointer with the M2M device itself.
150fbb6c848SEzequiel Garcia * @proc_pads: &struct media_pad with the @proc pads.
151fbb6c848SEzequiel Garcia * @intf_devnode: &struct media_intf devnode pointer with the interface
152fbb6c848SEzequiel Garcia * with controls the M2M device.
153fbb6c848SEzequiel Garcia *
154fbb6c848SEzequiel Garcia * Contains everything needed to attach the video device to the media device.
155fbb6c848SEzequiel Garcia */
156fbb6c848SEzequiel Garcia struct hantro_func {
157fbb6c848SEzequiel Garcia unsigned int id;
158fbb6c848SEzequiel Garcia struct video_device vdev;
159fbb6c848SEzequiel Garcia struct media_pad source_pad;
160fbb6c848SEzequiel Garcia struct media_entity sink;
161fbb6c848SEzequiel Garcia struct media_pad sink_pad;
162fbb6c848SEzequiel Garcia struct media_entity proc;
163fbb6c848SEzequiel Garcia struct media_pad proc_pads[2];
164fbb6c848SEzequiel Garcia struct media_intf_devnode *intf_devnode;
165fbb6c848SEzequiel Garcia };
166fbb6c848SEzequiel Garcia
167fbb6c848SEzequiel Garcia static inline struct hantro_func *
hantro_vdev_to_func(struct video_device * vdev)168fbb6c848SEzequiel Garcia hantro_vdev_to_func(struct video_device *vdev)
169fbb6c848SEzequiel Garcia {
170fbb6c848SEzequiel Garcia return container_of(vdev, struct hantro_func, vdev);
171fbb6c848SEzequiel Garcia }
172fbb6c848SEzequiel Garcia
173fbb6c848SEzequiel Garcia /**
174fbb6c848SEzequiel Garcia * struct hantro_dev - driver data
175fbb6c848SEzequiel Garcia * @v4l2_dev: V4L2 device to register video devices for.
176fbb6c848SEzequiel Garcia * @m2m_dev: mem2mem device associated to this device.
177fbb6c848SEzequiel Garcia * @mdev: media device associated to this device.
178fbb6c848SEzequiel Garcia * @encoder: encoder functionality.
179fbb6c848SEzequiel Garcia * @decoder: decoder functionality.
180fbb6c848SEzequiel Garcia * @pdev: Pointer to VPU platform device.
181fbb6c848SEzequiel Garcia * @dev: Pointer to device for convenient logging using
182fbb6c848SEzequiel Garcia * dev_ macros.
183fbb6c848SEzequiel Garcia * @clocks: Array of clock handles.
184fbb6c848SEzequiel Garcia * @resets: Array of reset handles.
185fbb6c848SEzequiel Garcia * @reg_bases: Mapped addresses of VPU registers.
186fbb6c848SEzequiel Garcia * @enc_base: Mapped address of VPU encoder register for convenience.
187fbb6c848SEzequiel Garcia * @dec_base: Mapped address of VPU decoder register for convenience.
188fbb6c848SEzequiel Garcia * @ctrl_base: Mapped address of VPU control block.
189fbb6c848SEzequiel Garcia * @vpu_mutex: Mutex to synchronize V4L2 calls.
190fbb6c848SEzequiel Garcia * @irqlock: Spinlock to synchronize access to data structures
191fbb6c848SEzequiel Garcia * shared with interrupt handlers.
192fbb6c848SEzequiel Garcia * @variant: Hardware variant-specific parameters.
193fbb6c848SEzequiel Garcia * @watchdog_work: Delayed work for hardware timeout handling.
194fbb6c848SEzequiel Garcia */
195fbb6c848SEzequiel Garcia struct hantro_dev {
196fbb6c848SEzequiel Garcia struct v4l2_device v4l2_dev;
197fbb6c848SEzequiel Garcia struct v4l2_m2m_dev *m2m_dev;
198fbb6c848SEzequiel Garcia struct media_device mdev;
199fbb6c848SEzequiel Garcia struct hantro_func *encoder;
200fbb6c848SEzequiel Garcia struct hantro_func *decoder;
201fbb6c848SEzequiel Garcia struct platform_device *pdev;
202fbb6c848SEzequiel Garcia struct device *dev;
203fbb6c848SEzequiel Garcia struct clk_bulk_data *clocks;
204fbb6c848SEzequiel Garcia struct reset_control *resets;
205fbb6c848SEzequiel Garcia void __iomem **reg_bases;
206fbb6c848SEzequiel Garcia void __iomem *enc_base;
207fbb6c848SEzequiel Garcia void __iomem *dec_base;
208fbb6c848SEzequiel Garcia void __iomem *ctrl_base;
209fbb6c848SEzequiel Garcia
210fbb6c848SEzequiel Garcia struct mutex vpu_mutex; /* video_device lock */
211fbb6c848SEzequiel Garcia spinlock_t irqlock;
212fbb6c848SEzequiel Garcia const struct hantro_variant *variant;
213fbb6c848SEzequiel Garcia struct delayed_work watchdog_work;
214fbb6c848SEzequiel Garcia };
215fbb6c848SEzequiel Garcia
216fbb6c848SEzequiel Garcia /**
217fbb6c848SEzequiel Garcia * struct hantro_ctx - Context (instance) private data.
218fbb6c848SEzequiel Garcia *
219fbb6c848SEzequiel Garcia * @dev: VPU driver data to which the context belongs.
220fbb6c848SEzequiel Garcia * @fh: V4L2 file handler.
221fbb6c848SEzequiel Garcia * @is_encoder: Decoder or encoder context?
222fbb6c848SEzequiel Garcia *
223fbb6c848SEzequiel Garcia * @sequence_cap: Sequence counter for capture queue
224fbb6c848SEzequiel Garcia * @sequence_out: Sequence counter for output queue
225fbb6c848SEzequiel Garcia *
226fbb6c848SEzequiel Garcia * @vpu_src_fmt: Descriptor of active source format.
227fbb6c848SEzequiel Garcia * @src_fmt: V4L2 pixel format of active source format.
228fbb6c848SEzequiel Garcia * @vpu_dst_fmt: Descriptor of active destination format.
229fbb6c848SEzequiel Garcia * @dst_fmt: V4L2 pixel format of active destination format.
230fbb6c848SEzequiel Garcia *
231fbb6c848SEzequiel Garcia * @ctrl_handler: Control handler used to register controls.
232fbb6c848SEzequiel Garcia * @jpeg_quality: User-specified JPEG compression quality.
233fbb6c848SEzequiel Garcia * @bit_depth: Bit depth of current frame
23480c7373aSBenjamin Gaignard * @need_postproc: Set to true if the bitstream features require to
23580c7373aSBenjamin Gaignard * use the post-processor.
236fbb6c848SEzequiel Garcia *
237fbb6c848SEzequiel Garcia * @codec_ops: Set of operations related to codec mode.
238fbb6c848SEzequiel Garcia * @postproc: Post-processing context.
239fbb6c848SEzequiel Garcia * @h264_dec: H.264-decoding context.
240fbb6c848SEzequiel Garcia * @jpeg_enc: JPEG-encoding context.
241fbb6c848SEzequiel Garcia * @mpeg2_dec: MPEG-2-decoding context.
242fbb6c848SEzequiel Garcia * @vp8_dec: VP8-decoding context.
243fbb6c848SEzequiel Garcia * @hevc_dec: HEVC-decoding context.
244fbb6c848SEzequiel Garcia * @vp9_dec: VP9-decoding context.
245c0d0e579SBenjamin Gaignard * @av1_dec: AV1-decoding context.
246fbb6c848SEzequiel Garcia */
247fbb6c848SEzequiel Garcia struct hantro_ctx {
248fbb6c848SEzequiel Garcia struct hantro_dev *dev;
249fbb6c848SEzequiel Garcia struct v4l2_fh fh;
250fbb6c848SEzequiel Garcia bool is_encoder;
251fbb6c848SEzequiel Garcia
252fbb6c848SEzequiel Garcia u32 sequence_cap;
253fbb6c848SEzequiel Garcia u32 sequence_out;
254fbb6c848SEzequiel Garcia
255fbb6c848SEzequiel Garcia const struct hantro_fmt *vpu_src_fmt;
256fbb6c848SEzequiel Garcia struct v4l2_pix_format_mplane src_fmt;
257fbb6c848SEzequiel Garcia const struct hantro_fmt *vpu_dst_fmt;
258fbb6c848SEzequiel Garcia struct v4l2_pix_format_mplane dst_fmt;
259fbb6c848SEzequiel Garcia
260fbb6c848SEzequiel Garcia struct v4l2_ctrl_handler ctrl_handler;
261fbb6c848SEzequiel Garcia int jpeg_quality;
262fbb6c848SEzequiel Garcia int bit_depth;
263fbb6c848SEzequiel Garcia
264fbb6c848SEzequiel Garcia const struct hantro_codec_ops *codec_ops;
265fbb6c848SEzequiel Garcia struct hantro_postproc_ctx postproc;
26680c7373aSBenjamin Gaignard bool need_postproc;
267fbb6c848SEzequiel Garcia
268fbb6c848SEzequiel Garcia /* Specific for particular codec modes. */
269fbb6c848SEzequiel Garcia union {
270fbb6c848SEzequiel Garcia struct hantro_h264_dec_hw_ctx h264_dec;
271fbb6c848SEzequiel Garcia struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
272fbb6c848SEzequiel Garcia struct hantro_vp8_dec_hw_ctx vp8_dec;
273fbb6c848SEzequiel Garcia struct hantro_hevc_dec_hw_ctx hevc_dec;
274fbb6c848SEzequiel Garcia struct hantro_vp9_dec_hw_ctx vp9_dec;
275c0d0e579SBenjamin Gaignard struct hantro_av1_dec_hw_ctx av1_dec;
276fbb6c848SEzequiel Garcia };
277fbb6c848SEzequiel Garcia };
278fbb6c848SEzequiel Garcia
279fbb6c848SEzequiel Garcia /**
280fbb6c848SEzequiel Garcia * struct hantro_fmt - information about supported video formats.
281fbb6c848SEzequiel Garcia * @name: Human readable name of the format.
282fbb6c848SEzequiel Garcia * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
283fbb6c848SEzequiel Garcia * @codec_mode: Codec mode related to this format. See
284fbb6c848SEzequiel Garcia * enum hantro_codec_mode.
285fbb6c848SEzequiel Garcia * @header_size: Optional header size. Currently used by JPEG encoder.
286fbb6c848SEzequiel Garcia * @max_depth: Maximum depth, for bitstream formats
287fbb6c848SEzequiel Garcia * @enc_fmt: Format identifier for encoder registers.
288fbb6c848SEzequiel Garcia * @frmsize: Supported range of frame sizes (only for bitstream formats).
289fbb6c848SEzequiel Garcia * @postprocessed: Indicates if this format needs the post-processor.
290fbb6c848SEzequiel Garcia * @match_depth: Indicates if format bit depth must match video bit depth
291fbb6c848SEzequiel Garcia */
292fbb6c848SEzequiel Garcia struct hantro_fmt {
293fbb6c848SEzequiel Garcia char *name;
294fbb6c848SEzequiel Garcia u32 fourcc;
295fbb6c848SEzequiel Garcia enum hantro_codec_mode codec_mode;
296fbb6c848SEzequiel Garcia int header_size;
297fbb6c848SEzequiel Garcia int max_depth;
298fbb6c848SEzequiel Garcia enum hantro_enc_fmt enc_fmt;
299fbb6c848SEzequiel Garcia struct v4l2_frmsize_stepwise frmsize;
300fbb6c848SEzequiel Garcia bool postprocessed;
301fbb6c848SEzequiel Garcia bool match_depth;
302fbb6c848SEzequiel Garcia };
303fbb6c848SEzequiel Garcia
304fbb6c848SEzequiel Garcia struct hantro_reg {
305fbb6c848SEzequiel Garcia u32 base;
306fbb6c848SEzequiel Garcia u32 shift;
307fbb6c848SEzequiel Garcia u32 mask;
308fbb6c848SEzequiel Garcia };
309fbb6c848SEzequiel Garcia
310fbb6c848SEzequiel Garcia struct hantro_postproc_regs {
311fbb6c848SEzequiel Garcia struct hantro_reg pipeline_en;
312fbb6c848SEzequiel Garcia struct hantro_reg max_burst;
313fbb6c848SEzequiel Garcia struct hantro_reg clk_gate;
314fbb6c848SEzequiel Garcia struct hantro_reg out_swap32;
315fbb6c848SEzequiel Garcia struct hantro_reg out_endian;
316fbb6c848SEzequiel Garcia struct hantro_reg out_luma_base;
317fbb6c848SEzequiel Garcia struct hantro_reg input_width;
318fbb6c848SEzequiel Garcia struct hantro_reg input_height;
319fbb6c848SEzequiel Garcia struct hantro_reg output_width;
320fbb6c848SEzequiel Garcia struct hantro_reg output_height;
321fbb6c848SEzequiel Garcia struct hantro_reg input_fmt;
322fbb6c848SEzequiel Garcia struct hantro_reg output_fmt;
323fbb6c848SEzequiel Garcia struct hantro_reg orig_width;
324fbb6c848SEzequiel Garcia struct hantro_reg display_width;
325fbb6c848SEzequiel Garcia };
326fbb6c848SEzequiel Garcia
327fbb6c848SEzequiel Garcia struct hantro_vp9_decoded_buffer_info {
328fbb6c848SEzequiel Garcia /* Info needed when the decoded frame serves as a reference frame. */
329fbb6c848SEzequiel Garcia unsigned short width;
330fbb6c848SEzequiel Garcia unsigned short height;
331fbb6c848SEzequiel Garcia u32 bit_depth : 4;
332fbb6c848SEzequiel Garcia };
333fbb6c848SEzequiel Garcia
334fbb6c848SEzequiel Garcia struct hantro_decoded_buffer {
335fbb6c848SEzequiel Garcia /* Must be the first field in this struct. */
336fbb6c848SEzequiel Garcia struct v4l2_m2m_buffer base;
337fbb6c848SEzequiel Garcia
338fbb6c848SEzequiel Garcia union {
339fbb6c848SEzequiel Garcia struct hantro_vp9_decoded_buffer_info vp9;
340fbb6c848SEzequiel Garcia };
341fbb6c848SEzequiel Garcia };
342fbb6c848SEzequiel Garcia
343fbb6c848SEzequiel Garcia /* Logging helpers */
344fbb6c848SEzequiel Garcia
345fbb6c848SEzequiel Garcia /**
346fbb6c848SEzequiel Garcia * DOC: hantro_debug: Module parameter to control level of debugging messages.
347fbb6c848SEzequiel Garcia *
348fbb6c848SEzequiel Garcia * Level of debugging messages can be controlled by bits of
349fbb6c848SEzequiel Garcia * module parameter called "debug". Meaning of particular
350fbb6c848SEzequiel Garcia * bits is as follows:
351fbb6c848SEzequiel Garcia *
352fbb6c848SEzequiel Garcia * bit 0 - global information: mode, size, init, release
353fbb6c848SEzequiel Garcia * bit 1 - each run start/result information
354fbb6c848SEzequiel Garcia * bit 2 - contents of small controls from userspace
355fbb6c848SEzequiel Garcia * bit 3 - contents of big controls from userspace
356fbb6c848SEzequiel Garcia * bit 4 - detail fmt, ctrl, buffer q/dq information
357fbb6c848SEzequiel Garcia * bit 5 - detail function enter/leave trace information
358fbb6c848SEzequiel Garcia * bit 6 - register write/read information
359fbb6c848SEzequiel Garcia */
360fbb6c848SEzequiel Garcia extern int hantro_debug;
361fbb6c848SEzequiel Garcia
362fbb6c848SEzequiel Garcia #define vpu_debug(level, fmt, args...) \
363fbb6c848SEzequiel Garcia do { \
364fbb6c848SEzequiel Garcia if (hantro_debug & BIT(level)) \
365fbb6c848SEzequiel Garcia pr_info("%s:%d: " fmt, \
366fbb6c848SEzequiel Garcia __func__, __LINE__, ##args); \
367fbb6c848SEzequiel Garcia } while (0)
368fbb6c848SEzequiel Garcia
369fbb6c848SEzequiel Garcia #define vpu_err(fmt, args...) \
370fbb6c848SEzequiel Garcia pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
371fbb6c848SEzequiel Garcia
372fbb6c848SEzequiel Garcia /* Structure access helpers. */
fh_to_ctx(struct v4l2_fh * fh)3737ee8acd1SArnd Bergmann static __always_inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
374fbb6c848SEzequiel Garcia {
375fbb6c848SEzequiel Garcia return container_of(fh, struct hantro_ctx, fh);
376fbb6c848SEzequiel Garcia }
377fbb6c848SEzequiel Garcia
378fbb6c848SEzequiel Garcia /* Register accessors. */
vepu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)3797ee8acd1SArnd Bergmann static __always_inline void vepu_write_relaxed(struct hantro_dev *vpu,
380fbb6c848SEzequiel Garcia u32 val, u32 reg)
381fbb6c848SEzequiel Garcia {
382fbb6c848SEzequiel Garcia vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
383fbb6c848SEzequiel Garcia writel_relaxed(val, vpu->enc_base + reg);
384fbb6c848SEzequiel Garcia }
385fbb6c848SEzequiel Garcia
vepu_write(struct hantro_dev * vpu,u32 val,u32 reg)3867ee8acd1SArnd Bergmann static __always_inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
387fbb6c848SEzequiel Garcia {
388fbb6c848SEzequiel Garcia vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
389fbb6c848SEzequiel Garcia writel(val, vpu->enc_base + reg);
390fbb6c848SEzequiel Garcia }
391fbb6c848SEzequiel Garcia
vepu_read(struct hantro_dev * vpu,u32 reg)3927ee8acd1SArnd Bergmann static __always_inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
393fbb6c848SEzequiel Garcia {
394fbb6c848SEzequiel Garcia u32 val = readl(vpu->enc_base + reg);
395fbb6c848SEzequiel Garcia
396fbb6c848SEzequiel Garcia vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
397fbb6c848SEzequiel Garcia return val;
398fbb6c848SEzequiel Garcia }
399fbb6c848SEzequiel Garcia
vdpu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)4007ee8acd1SArnd Bergmann static __always_inline void vdpu_write_relaxed(struct hantro_dev *vpu,
401fbb6c848SEzequiel Garcia u32 val, u32 reg)
402fbb6c848SEzequiel Garcia {
403fbb6c848SEzequiel Garcia vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
404fbb6c848SEzequiel Garcia writel_relaxed(val, vpu->dec_base + reg);
405fbb6c848SEzequiel Garcia }
406fbb6c848SEzequiel Garcia
vdpu_write(struct hantro_dev * vpu,u32 val,u32 reg)4077ee8acd1SArnd Bergmann static __always_inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
408fbb6c848SEzequiel Garcia {
409fbb6c848SEzequiel Garcia vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
410fbb6c848SEzequiel Garcia writel(val, vpu->dec_base + reg);
411fbb6c848SEzequiel Garcia }
412fbb6c848SEzequiel Garcia
hantro_write_addr(struct hantro_dev * vpu,unsigned long offset,dma_addr_t addr)4137ee8acd1SArnd Bergmann static __always_inline void hantro_write_addr(struct hantro_dev *vpu,
414fbb6c848SEzequiel Garcia unsigned long offset,
415fbb6c848SEzequiel Garcia dma_addr_t addr)
416fbb6c848SEzequiel Garcia {
417fbb6c848SEzequiel Garcia vdpu_write(vpu, addr & 0xffffffff, offset);
418fbb6c848SEzequiel Garcia }
419fbb6c848SEzequiel Garcia
vdpu_read(struct hantro_dev * vpu,u32 reg)4207ee8acd1SArnd Bergmann static __always_inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
421fbb6c848SEzequiel Garcia {
422fbb6c848SEzequiel Garcia u32 val = readl(vpu->dec_base + reg);
423fbb6c848SEzequiel Garcia
424fbb6c848SEzequiel Garcia vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
425fbb6c848SEzequiel Garcia return val;
426fbb6c848SEzequiel Garcia }
427fbb6c848SEzequiel Garcia
vdpu_read_mask(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)4287ee8acd1SArnd Bergmann static __always_inline u32 vdpu_read_mask(struct hantro_dev *vpu,
429fbb6c848SEzequiel Garcia const struct hantro_reg *reg,
430fbb6c848SEzequiel Garcia u32 val)
431fbb6c848SEzequiel Garcia {
432fbb6c848SEzequiel Garcia u32 v;
433fbb6c848SEzequiel Garcia
434fbb6c848SEzequiel Garcia v = vdpu_read(vpu, reg->base);
435fbb6c848SEzequiel Garcia v &= ~(reg->mask << reg->shift);
436fbb6c848SEzequiel Garcia v |= ((val & reg->mask) << reg->shift);
437fbb6c848SEzequiel Garcia return v;
438fbb6c848SEzequiel Garcia }
439fbb6c848SEzequiel Garcia
hantro_reg_write(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)4407ee8acd1SArnd Bergmann static __always_inline void hantro_reg_write(struct hantro_dev *vpu,
441fbb6c848SEzequiel Garcia const struct hantro_reg *reg,
442fbb6c848SEzequiel Garcia u32 val)
443fbb6c848SEzequiel Garcia {
444*0cb1d9c8SArnd Bergmann vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
445fbb6c848SEzequiel Garcia }
446fbb6c848SEzequiel Garcia
hantro_reg_write_relaxed(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)447*0cb1d9c8SArnd Bergmann static __always_inline void hantro_reg_write_relaxed(struct hantro_dev *vpu,
448fbb6c848SEzequiel Garcia const struct hantro_reg *reg,
449fbb6c848SEzequiel Garcia u32 val)
450fbb6c848SEzequiel Garcia {
451*0cb1d9c8SArnd Bergmann vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
452fbb6c848SEzequiel Garcia }
453fbb6c848SEzequiel Garcia
454fbb6c848SEzequiel Garcia void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
455fbb6c848SEzequiel Garcia dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
456fbb6c848SEzequiel Garcia
457fbb6c848SEzequiel Garcia static inline struct vb2_v4l2_buffer *
hantro_get_src_buf(struct hantro_ctx * ctx)458fbb6c848SEzequiel Garcia hantro_get_src_buf(struct hantro_ctx *ctx)
459fbb6c848SEzequiel Garcia {
460fbb6c848SEzequiel Garcia return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
461fbb6c848SEzequiel Garcia }
462fbb6c848SEzequiel Garcia
463fbb6c848SEzequiel Garcia static inline struct vb2_v4l2_buffer *
hantro_get_dst_buf(struct hantro_ctx * ctx)464fbb6c848SEzequiel Garcia hantro_get_dst_buf(struct hantro_ctx *ctx)
465fbb6c848SEzequiel Garcia {
466fbb6c848SEzequiel Garcia return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
467fbb6c848SEzequiel Garcia }
468fbb6c848SEzequiel Garcia
469fbb6c848SEzequiel Garcia bool hantro_needs_postproc(const struct hantro_ctx *ctx,
470fbb6c848SEzequiel Garcia const struct hantro_fmt *fmt);
471fbb6c848SEzequiel Garcia
472fbb6c848SEzequiel Garcia static inline dma_addr_t
hantro_get_dec_buf_addr(struct hantro_ctx * ctx,struct vb2_buffer * vb)473fbb6c848SEzequiel Garcia hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
474fbb6c848SEzequiel Garcia {
475fbb6c848SEzequiel Garcia if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
476fbb6c848SEzequiel Garcia return ctx->postproc.dec_q[vb->index].dma;
477fbb6c848SEzequiel Garcia return vb2_dma_contig_plane_dma_addr(vb, 0);
478fbb6c848SEzequiel Garcia }
479fbb6c848SEzequiel Garcia
480fbb6c848SEzequiel Garcia static inline struct hantro_decoded_buffer *
vb2_to_hantro_decoded_buf(struct vb2_buffer * buf)481fbb6c848SEzequiel Garcia vb2_to_hantro_decoded_buf(struct vb2_buffer *buf)
482fbb6c848SEzequiel Garcia {
483fbb6c848SEzequiel Garcia return container_of(buf, struct hantro_decoded_buffer, base.vb.vb2_buf);
484fbb6c848SEzequiel Garcia }
485fbb6c848SEzequiel Garcia
486fbb6c848SEzequiel Garcia void hantro_postproc_disable(struct hantro_ctx *ctx);
487fbb6c848SEzequiel Garcia void hantro_postproc_enable(struct hantro_ctx *ctx);
488fbb6c848SEzequiel Garcia void hantro_postproc_free(struct hantro_ctx *ctx);
489fbb6c848SEzequiel Garcia int hantro_postproc_alloc(struct hantro_ctx *ctx);
490fbb6c848SEzequiel Garcia int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
491fbb6c848SEzequiel Garcia struct v4l2_frmsizeenum *fsize);
492fbb6c848SEzequiel Garcia
493fbb6c848SEzequiel Garcia #endif /* HANTRO_H_ */
494