1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2013 Texas Instruments Inc. 4 * 5 * David Griego, <dagriego@biglakesoftware.com> 6 * Dale Farnsworth, <dale@farnsworth.org> 7 * Archit Taneja, <archit@ti.com> 8 */ 9 10 #ifndef _TI_VPDMA_PRIV_H_ 11 #define _TI_VPDMA_PRIV_H_ 12 13 /* 14 * VPDMA Register offsets 15 */ 16 17 /* Top level */ 18 #define VPDMA_PID 0x00 19 #define VPDMA_LIST_ADDR 0x04 20 #define VPDMA_LIST_ATTR 0x08 21 #define VPDMA_LIST_STAT_SYNC 0x0c 22 #define VPDMA_BG_RGB 0x18 23 #define VPDMA_BG_YUV 0x1c 24 #define VPDMA_SETUP 0x30 25 #define VPDMA_MAX_SIZE1 0x34 26 #define VPDMA_MAX_SIZE2 0x38 27 #define VPDMA_MAX_SIZE3 0x3c 28 #define VPDMA_MAX_SIZE_WIDTH_MASK 0xffff 29 #define VPDMA_MAX_SIZE_WIDTH_SHFT 16 30 #define VPDMA_MAX_SIZE_HEIGHT_MASK 0xffff 31 #define VPDMA_MAX_SIZE_HEIGHT_SHFT 0 32 33 /* Interrupts */ 34 #define VPDMA_INT_CHAN_STAT(grp) (0x40 + grp * 8) 35 #define VPDMA_INT_CHAN_MASK(grp) (VPDMA_INT_CHAN_STAT(grp) + 4) 36 #define VPDMA_INT_CLIENT0_STAT 0x78 37 #define VPDMA_INT_CLIENT0_MASK 0x7c 38 #define VPDMA_INT_CLIENT1_STAT 0x80 39 #define VPDMA_INT_CLIENT1_MASK 0x84 40 #define VPDMA_INT_LIST0_STAT 0x88 41 #define VPDMA_INT_LIST0_MASK 0x8c 42 43 #define VPDMA_INTX_OFFSET 0x50 44 45 #define VPDMA_PERFMON(i) (0x200 + i * 4) 46 47 /* VIP/VPE client registers */ 48 #define VPDMA_DEI_CHROMA1_CSTAT 0x0300 49 #define VPDMA_DEI_LUMA1_CSTAT 0x0304 50 #define VPDMA_DEI_LUMA2_CSTAT 0x0308 51 #define VPDMA_DEI_CHROMA2_CSTAT 0x030c 52 #define VPDMA_DEI_LUMA3_CSTAT 0x0310 53 #define VPDMA_DEI_CHROMA3_CSTAT 0x0314 54 #define VPDMA_DEI_MV_IN_CSTAT 0x0330 55 #define VPDMA_DEI_MV_OUT_CSTAT 0x033c 56 #define VPDMA_VIP_LO_Y_CSTAT 0x0388 57 #define VPDMA_VIP_LO_UV_CSTAT 0x038c 58 #define VPDMA_VIP_UP_Y_CSTAT 0x0390 59 #define VPDMA_VIP_UP_UV_CSTAT 0x0394 60 #define VPDMA_VPI_CTL_CSTAT 0x03d0 61 62 /* Reg field info for VPDMA_CLIENT_CSTAT registers */ 63 #define VPDMA_CSTAT_LINE_MODE_MASK 0x03 64 #define VPDMA_CSTAT_LINE_MODE_SHIFT 8 65 #define VPDMA_CSTAT_FRAME_START_MASK 0xf 66 #define VPDMA_CSTAT_FRAME_START_SHIFT 10 67 68 #define VPDMA_LIST_NUM_MASK 0x07 69 #define VPDMA_LIST_NUM_SHFT 24 70 #define VPDMA_LIST_STOP_SHFT 20 71 #define VPDMA_LIST_RDY_MASK 0x01 72 #define VPDMA_LIST_RDY_SHFT 19 73 #define VPDMA_LIST_TYPE_MASK 0x03 74 #define VPDMA_LIST_TYPE_SHFT 16 75 #define VPDMA_LIST_SIZE_MASK 0xffff 76 77 /* 78 * The YUV data type definition below are taken from 79 * both the TRM and i839 Errata information. 80 * Use the correct data type considering byte 81 * reordering of components. 82 * 83 * Also since the single use of "C" in the 422 case 84 * to mean "Cr" (i.e. V component). It was decided 85 * to explicitly label them CR to remove any confusion. 86 * Bear in mind that the type label refer to the memory 87 * packed order (LSB - MSB). 88 */ 89 #define DATA_TYPE_Y444 0x0 90 #define DATA_TYPE_Y422 0x1 91 #define DATA_TYPE_Y420 0x2 92 #define DATA_TYPE_C444 0x4 93 #define DATA_TYPE_C422 0x5 94 #define DATA_TYPE_C420 0x6 95 #define DATA_TYPE_CB420 0x16 96 #define DATA_TYPE_YC444 0x8 97 #define DATA_TYPE_YCB422 0x7 98 #define DATA_TYPE_YCR422 0x17 99 #define DATA_TYPE_CBY422 0x27 100 #define DATA_TYPE_CRY422 0x37 101 102 /* 103 * The RGB data type definition below are defined 104 * to follow Errata i819. 105 * The initial values were taken from: 106 * VPDMA_data_type_mapping_v0.2vayu_c.pdf 107 * But some of the ARGB definition appeared to be wrong 108 * in the document also. As they would yield RGBA instead. 109 * They have been corrected based on experimentation. 110 */ 111 #define DATA_TYPE_RGB16_565 0x10 112 #define DATA_TYPE_ARGB_1555 0x13 113 #define DATA_TYPE_ARGB_4444 0x14 114 #define DATA_TYPE_RGBA_5551 0x11 115 #define DATA_TYPE_RGBA_4444 0x12 116 #define DATA_TYPE_ARGB24_6666 0x18 117 #define DATA_TYPE_RGB24_888 0x16 118 #define DATA_TYPE_ARGB32_8888 0x17 119 #define DATA_TYPE_RGBA24_6666 0x15 120 #define DATA_TYPE_RGBA32_8888 0x19 121 #define DATA_TYPE_BGR16_565 0x0 122 #define DATA_TYPE_ABGR_1555 0x3 123 #define DATA_TYPE_ABGR_4444 0x4 124 #define DATA_TYPE_BGRA_5551 0x1 125 #define DATA_TYPE_BGRA_4444 0x2 126 #define DATA_TYPE_ABGR24_6666 0x8 127 #define DATA_TYPE_BGR24_888 0x6 128 #define DATA_TYPE_ABGR32_8888 0x7 129 #define DATA_TYPE_BGRA24_6666 0x5 130 #define DATA_TYPE_BGRA32_8888 0x9 131 132 #define DATA_TYPE_MV 0x3 133 134 /* VPDMA channel numbers, some are common between VIP/VPE and appear twice */ 135 #define VPE_CHAN_NUM_LUMA1_IN 0 136 #define VPE_CHAN_NUM_CHROMA1_IN 1 137 #define VPE_CHAN_NUM_LUMA2_IN 2 138 #define VPE_CHAN_NUM_CHROMA2_IN 3 139 #define VPE_CHAN_NUM_LUMA3_IN 4 140 #define VPE_CHAN_NUM_CHROMA3_IN 5 141 #define VPE_CHAN_NUM_MV_IN 12 142 #define VPE_CHAN_NUM_MV_OUT 15 143 #define VIP1_CHAN_NUM_MULT_PORT_A_SRC0 38 144 #define VIP1_CHAN_NUM_MULT_ANC_A_SRC0 70 145 #define VPE_CHAN_NUM_LUMA_OUT 102 146 #define VPE_CHAN_NUM_CHROMA_OUT 103 147 #define VIP1_CHAN_NUM_PORT_A_LUMA 102 148 #define VIP1_CHAN_NUM_PORT_A_CHROMA 103 149 #define VPE_CHAN_NUM_RGB_OUT 106 150 #define VIP1_CHAN_NUM_PORT_A_RGB 106 151 #define VIP1_CHAN_NUM_PORT_B_RGB 107 152 /* 153 * a VPDMA address data block payload for a configuration descriptor needs to 154 * have each sub block length as a multiple of 16 bytes. Therefore, the overall 155 * size of the payload also needs to be a multiple of 16 bytes. The sub block 156 * lengths should be ensured to be aligned by the VPDMA user. 157 */ 158 #define VPDMA_ADB_SIZE_ALIGN 0x0f 159 160 /* 161 * data transfer descriptor 162 */ 163 struct vpdma_dtd { 164 u32 type_ctl_stride; 165 union { 166 u32 xfer_length_height; 167 u32 w1; 168 }; 169 u32 start_addr; 170 u32 pkt_ctl; 171 union { 172 u32 frame_width_height; /* inbound */ 173 u32 desc_write_addr; /* outbound */ 174 }; 175 union { 176 u32 start_h_v; /* inbound */ 177 u32 max_width_height; /* outbound */ 178 }; 179 u32 client_attr0; 180 u32 client_attr1; 181 }; 182 183 /* Data Transfer Descriptor specifics */ 184 #define DTD_NO_NOTIFY 0 185 #define DTD_NOTIFY 1 186 187 #define DTD_PKT_TYPE 0xa 188 #define DTD_DIR_IN 0 189 #define DTD_DIR_OUT 1 190 191 /* type_ctl_stride */ 192 #define DTD_DATA_TYPE_MASK 0x3f 193 #define DTD_DATA_TYPE_SHFT 26 194 #define DTD_NOTIFY_MASK 0x01 195 #define DTD_NOTIFY_SHFT 25 196 #define DTD_FIELD_MASK 0x01 197 #define DTD_FIELD_SHFT 24 198 #define DTD_1D_MASK 0x01 199 #define DTD_1D_SHFT 23 200 #define DTD_EVEN_LINE_SKIP_MASK 0x01 201 #define DTD_EVEN_LINE_SKIP_SHFT 20 202 #define DTD_ODD_LINE_SKIP_MASK 0x01 203 #define DTD_ODD_LINE_SKIP_SHFT 16 204 #define DTD_LINE_STRIDE_MASK 0xffff 205 #define DTD_LINE_STRIDE_SHFT 0 206 207 /* xfer_length_height */ 208 #define DTD_LINE_LENGTH_MASK 0xffff 209 #define DTD_LINE_LENGTH_SHFT 16 210 #define DTD_XFER_HEIGHT_MASK 0xffff 211 #define DTD_XFER_HEIGHT_SHFT 0 212 213 /* pkt_ctl */ 214 #define DTD_PKT_TYPE_MASK 0x1f 215 #define DTD_PKT_TYPE_SHFT 27 216 #define DTD_MODE_MASK 0x01 217 #define DTD_MODE_SHFT 26 218 #define DTD_DIR_MASK 0x01 219 #define DTD_DIR_SHFT 25 220 #define DTD_CHAN_MASK 0x01ff 221 #define DTD_CHAN_SHFT 16 222 #define DTD_PRI_MASK 0x0f 223 #define DTD_PRI_SHFT 9 224 #define DTD_NEXT_CHAN_MASK 0x01ff 225 #define DTD_NEXT_CHAN_SHFT 0 226 227 /* frame_width_height */ 228 #define DTD_FRAME_WIDTH_MASK 0xffff 229 #define DTD_FRAME_WIDTH_SHFT 16 230 #define DTD_FRAME_HEIGHT_MASK 0xffff 231 #define DTD_FRAME_HEIGHT_SHFT 0 232 233 /* start_h_v */ 234 #define DTD_H_START_MASK 0xffff 235 #define DTD_H_START_SHFT 16 236 #define DTD_V_START_MASK 0xffff 237 #define DTD_V_START_SHFT 0 238 239 #define DTD_DESC_START_MASK 0xffffffe0 240 #define DTD_DESC_START_SHIFT 5 241 #define DTD_WRITE_DESC_MASK 0x01 242 #define DTD_WRITE_DESC_SHIFT 2 243 #define DTD_DROP_DATA_MASK 0x01 244 #define DTD_DROP_DATA_SHIFT 1 245 #define DTD_USE_DESC_MASK 0x01 246 #define DTD_USE_DESC_SHIFT 0 247 248 /* max_width_height */ 249 #define DTD_MAX_WIDTH_MASK 0x07 250 #define DTD_MAX_WIDTH_SHFT 4 251 #define DTD_MAX_HEIGHT_MASK 0x07 252 #define DTD_MAX_HEIGHT_SHFT 0 253 254 static inline u32 dtd_type_ctl_stride(int type, bool notify, int field, 255 bool one_d, bool even_line_skip, bool odd_line_skip, 256 int line_stride) 257 { 258 return (type << DTD_DATA_TYPE_SHFT) | (notify << DTD_NOTIFY_SHFT) | 259 (field << DTD_FIELD_SHFT) | (one_d << DTD_1D_SHFT) | 260 (even_line_skip << DTD_EVEN_LINE_SKIP_SHFT) | 261 (odd_line_skip << DTD_ODD_LINE_SKIP_SHFT) | 262 line_stride; 263 } 264 265 static inline u32 dtd_xfer_length_height(int line_length, int xfer_height) 266 { 267 return (line_length << DTD_LINE_LENGTH_SHFT) | xfer_height; 268 } 269 270 static inline u32 dtd_pkt_ctl(bool mode, bool dir, int chan, int pri, 271 int next_chan) 272 { 273 return (DTD_PKT_TYPE << DTD_PKT_TYPE_SHFT) | (mode << DTD_MODE_SHFT) | 274 (dir << DTD_DIR_SHFT) | (chan << DTD_CHAN_SHFT) | 275 (pri << DTD_PRI_SHFT) | next_chan; 276 } 277 278 static inline u32 dtd_frame_width_height(int width, int height) 279 { 280 return (width << DTD_FRAME_WIDTH_SHFT) | height; 281 } 282 283 static inline u32 dtd_desc_write_addr(unsigned int addr, bool write_desc, 284 bool drop_data, bool use_desc) 285 { 286 return (addr & DTD_DESC_START_MASK) | 287 (write_desc << DTD_WRITE_DESC_SHIFT) | 288 (drop_data << DTD_DROP_DATA_SHIFT) | 289 use_desc; 290 } 291 292 static inline u32 dtd_start_h_v(int h_start, int v_start) 293 { 294 return (h_start << DTD_H_START_SHFT) | v_start; 295 } 296 297 static inline u32 dtd_max_width_height(int max_width, int max_height) 298 { 299 return (max_width << DTD_MAX_WIDTH_SHFT) | max_height; 300 } 301 302 static inline int dtd_get_data_type(struct vpdma_dtd *dtd) 303 { 304 return dtd->type_ctl_stride >> DTD_DATA_TYPE_SHFT; 305 } 306 307 static inline bool dtd_get_notify(struct vpdma_dtd *dtd) 308 { 309 return (dtd->type_ctl_stride >> DTD_NOTIFY_SHFT) & DTD_NOTIFY_MASK; 310 } 311 312 static inline int dtd_get_field(struct vpdma_dtd *dtd) 313 { 314 return (dtd->type_ctl_stride >> DTD_FIELD_SHFT) & DTD_FIELD_MASK; 315 } 316 317 static inline bool dtd_get_1d(struct vpdma_dtd *dtd) 318 { 319 return (dtd->type_ctl_stride >> DTD_1D_SHFT) & DTD_1D_MASK; 320 } 321 322 static inline bool dtd_get_even_line_skip(struct vpdma_dtd *dtd) 323 { 324 return (dtd->type_ctl_stride >> DTD_EVEN_LINE_SKIP_SHFT) 325 & DTD_EVEN_LINE_SKIP_MASK; 326 } 327 328 static inline bool dtd_get_odd_line_skip(struct vpdma_dtd *dtd) 329 { 330 return (dtd->type_ctl_stride >> DTD_ODD_LINE_SKIP_SHFT) 331 & DTD_ODD_LINE_SKIP_MASK; 332 } 333 334 static inline int dtd_get_line_stride(struct vpdma_dtd *dtd) 335 { 336 return dtd->type_ctl_stride & DTD_LINE_STRIDE_MASK; 337 } 338 339 static inline int dtd_get_line_length(struct vpdma_dtd *dtd) 340 { 341 return dtd->xfer_length_height >> DTD_LINE_LENGTH_SHFT; 342 } 343 344 static inline int dtd_get_xfer_height(struct vpdma_dtd *dtd) 345 { 346 return dtd->xfer_length_height & DTD_XFER_HEIGHT_MASK; 347 } 348 349 static inline int dtd_get_pkt_type(struct vpdma_dtd *dtd) 350 { 351 return dtd->pkt_ctl >> DTD_PKT_TYPE_SHFT; 352 } 353 354 static inline bool dtd_get_mode(struct vpdma_dtd *dtd) 355 { 356 return (dtd->pkt_ctl >> DTD_MODE_SHFT) & DTD_MODE_MASK; 357 } 358 359 static inline bool dtd_get_dir(struct vpdma_dtd *dtd) 360 { 361 return (dtd->pkt_ctl >> DTD_DIR_SHFT) & DTD_DIR_MASK; 362 } 363 364 static inline int dtd_get_chan(struct vpdma_dtd *dtd) 365 { 366 return (dtd->pkt_ctl >> DTD_CHAN_SHFT) & DTD_CHAN_MASK; 367 } 368 369 static inline int dtd_get_priority(struct vpdma_dtd *dtd) 370 { 371 return (dtd->pkt_ctl >> DTD_PRI_SHFT) & DTD_PRI_MASK; 372 } 373 374 static inline int dtd_get_next_chan(struct vpdma_dtd *dtd) 375 { 376 return (dtd->pkt_ctl >> DTD_NEXT_CHAN_SHFT) & DTD_NEXT_CHAN_MASK; 377 } 378 379 static inline int dtd_get_frame_width(struct vpdma_dtd *dtd) 380 { 381 return dtd->frame_width_height >> DTD_FRAME_WIDTH_SHFT; 382 } 383 384 static inline int dtd_get_frame_height(struct vpdma_dtd *dtd) 385 { 386 return dtd->frame_width_height & DTD_FRAME_HEIGHT_MASK; 387 } 388 389 static inline int dtd_get_desc_write_addr(struct vpdma_dtd *dtd) 390 { 391 return dtd->desc_write_addr & DTD_DESC_START_MASK; 392 } 393 394 static inline bool dtd_get_write_desc(struct vpdma_dtd *dtd) 395 { 396 return (dtd->desc_write_addr >> DTD_WRITE_DESC_SHIFT) & 397 DTD_WRITE_DESC_MASK; 398 } 399 400 static inline bool dtd_get_drop_data(struct vpdma_dtd *dtd) 401 { 402 return (dtd->desc_write_addr >> DTD_DROP_DATA_SHIFT) & 403 DTD_DROP_DATA_MASK; 404 } 405 406 static inline bool dtd_get_use_desc(struct vpdma_dtd *dtd) 407 { 408 return dtd->desc_write_addr & DTD_USE_DESC_MASK; 409 } 410 411 static inline int dtd_get_h_start(struct vpdma_dtd *dtd) 412 { 413 return dtd->start_h_v >> DTD_H_START_SHFT; 414 } 415 416 static inline int dtd_get_v_start(struct vpdma_dtd *dtd) 417 { 418 return dtd->start_h_v & DTD_V_START_MASK; 419 } 420 421 static inline int dtd_get_max_width(struct vpdma_dtd *dtd) 422 { 423 return (dtd->max_width_height >> DTD_MAX_WIDTH_SHFT) & 424 DTD_MAX_WIDTH_MASK; 425 } 426 427 static inline int dtd_get_max_height(struct vpdma_dtd *dtd) 428 { 429 return (dtd->max_width_height >> DTD_MAX_HEIGHT_SHFT) & 430 DTD_MAX_HEIGHT_MASK; 431 } 432 433 /* 434 * configuration descriptor 435 */ 436 struct vpdma_cfd { 437 union { 438 u32 dest_addr_offset; 439 u32 w0; 440 }; 441 union { 442 u32 block_len; /* in words */ 443 u32 w1; 444 }; 445 u32 payload_addr; 446 u32 ctl_payload_len; /* in words */ 447 }; 448 449 /* Configuration descriptor specifics */ 450 451 #define CFD_PKT_TYPE 0xb 452 453 #define CFD_DIRECT 1 454 #define CFD_INDIRECT 0 455 #define CFD_CLS_ADB 0 456 #define CFD_CLS_BLOCK 1 457 458 /* block_len */ 459 #define CFD__BLOCK_LEN_MASK 0xffff 460 #define CFD__BLOCK_LEN_SHFT 0 461 462 /* ctl_payload_len */ 463 #define CFD_PKT_TYPE_MASK 0x1f 464 #define CFD_PKT_TYPE_SHFT 27 465 #define CFD_DIRECT_MASK 0x01 466 #define CFD_DIRECT_SHFT 26 467 #define CFD_CLASS_MASK 0x03 468 #define CFD_CLASS_SHFT 24 469 #define CFD_DEST_MASK 0xff 470 #define CFD_DEST_SHFT 16 471 #define CFD_PAYLOAD_LEN_MASK 0xffff 472 #define CFD_PAYLOAD_LEN_SHFT 0 473 474 static inline u32 cfd_pkt_payload_len(bool direct, int cls, int dest, 475 int payload_len) 476 { 477 return (CFD_PKT_TYPE << CFD_PKT_TYPE_SHFT) | 478 (direct << CFD_DIRECT_SHFT) | 479 (cls << CFD_CLASS_SHFT) | 480 (dest << CFD_DEST_SHFT) | 481 payload_len; 482 } 483 484 static inline int cfd_get_pkt_type(struct vpdma_cfd *cfd) 485 { 486 return cfd->ctl_payload_len >> CFD_PKT_TYPE_SHFT; 487 } 488 489 static inline bool cfd_get_direct(struct vpdma_cfd *cfd) 490 { 491 return (cfd->ctl_payload_len >> CFD_DIRECT_SHFT) & CFD_DIRECT_MASK; 492 } 493 494 static inline bool cfd_get_class(struct vpdma_cfd *cfd) 495 { 496 return (cfd->ctl_payload_len >> CFD_CLASS_SHFT) & CFD_CLASS_MASK; 497 } 498 499 static inline int cfd_get_dest(struct vpdma_cfd *cfd) 500 { 501 return (cfd->ctl_payload_len >> CFD_DEST_SHFT) & CFD_DEST_MASK; 502 } 503 504 static inline int cfd_get_payload_len(struct vpdma_cfd *cfd) 505 { 506 return cfd->ctl_payload_len & CFD_PAYLOAD_LEN_MASK; 507 } 508 509 /* 510 * control descriptor 511 */ 512 struct vpdma_ctd { 513 union { 514 u32 timer_value; 515 u32 list_addr; 516 u32 w0; 517 }; 518 union { 519 u32 pixel_line_count; 520 u32 list_size; 521 u32 w1; 522 }; 523 union { 524 u32 event; 525 u32 fid_ctl; 526 u32 w2; 527 }; 528 u32 type_source_ctl; 529 }; 530 531 /* control descriptor types */ 532 #define CTD_TYPE_SYNC_ON_CLIENT 0 533 #define CTD_TYPE_SYNC_ON_LIST 1 534 #define CTD_TYPE_SYNC_ON_EXT 2 535 #define CTD_TYPE_SYNC_ON_LM_TIMER 3 536 #define CTD_TYPE_SYNC_ON_CHANNEL 4 537 #define CTD_TYPE_CHNG_CLIENT_IRQ 5 538 #define CTD_TYPE_SEND_IRQ 6 539 #define CTD_TYPE_RELOAD_LIST 7 540 #define CTD_TYPE_ABORT_CHANNEL 8 541 542 #define CTD_PKT_TYPE 0xc 543 544 /* timer_value */ 545 #define CTD_TIMER_VALUE_MASK 0xffff 546 #define CTD_TIMER_VALUE_SHFT 0 547 548 /* pixel_line_count */ 549 #define CTD_PIXEL_COUNT_MASK 0xffff 550 #define CTD_PIXEL_COUNT_SHFT 16 551 #define CTD_LINE_COUNT_MASK 0xffff 552 #define CTD_LINE_COUNT_SHFT 0 553 554 /* list_size */ 555 #define CTD_LIST_SIZE_MASK 0xffff 556 #define CTD_LIST_SIZE_SHFT 0 557 558 /* event */ 559 #define CTD_EVENT_MASK 0x0f 560 #define CTD_EVENT_SHFT 0 561 562 /* fid_ctl */ 563 #define CTD_FID2_MASK 0x03 564 #define CTD_FID2_SHFT 4 565 #define CTD_FID1_MASK 0x03 566 #define CTD_FID1_SHFT 2 567 #define CTD_FID0_MASK 0x03 568 #define CTD_FID0_SHFT 0 569 570 /* type_source_ctl */ 571 #define CTD_PKT_TYPE_MASK 0x1f 572 #define CTD_PKT_TYPE_SHFT 27 573 #define CTD_SOURCE_MASK 0xff 574 #define CTD_SOURCE_SHFT 16 575 #define CTD_CONTROL_MASK 0x0f 576 #define CTD_CONTROL_SHFT 0 577 578 static inline u32 ctd_pixel_line_count(int pixel_count, int line_count) 579 { 580 return (pixel_count << CTD_PIXEL_COUNT_SHFT) | line_count; 581 } 582 583 static inline u32 ctd_set_fid_ctl(int fid0, int fid1, int fid2) 584 { 585 return (fid2 << CTD_FID2_SHFT) | (fid1 << CTD_FID1_SHFT) | fid0; 586 } 587 588 static inline u32 ctd_type_source_ctl(int source, int control) 589 { 590 return (CTD_PKT_TYPE << CTD_PKT_TYPE_SHFT) | 591 (source << CTD_SOURCE_SHFT) | control; 592 } 593 594 static inline u32 ctd_get_pixel_count(struct vpdma_ctd *ctd) 595 { 596 return ctd->pixel_line_count >> CTD_PIXEL_COUNT_SHFT; 597 } 598 599 static inline int ctd_get_line_count(struct vpdma_ctd *ctd) 600 { 601 return ctd->pixel_line_count & CTD_LINE_COUNT_MASK; 602 } 603 604 static inline int ctd_get_event(struct vpdma_ctd *ctd) 605 { 606 return ctd->event & CTD_EVENT_MASK; 607 } 608 609 static inline int ctd_get_fid2_ctl(struct vpdma_ctd *ctd) 610 { 611 return (ctd->fid_ctl >> CTD_FID2_SHFT) & CTD_FID2_MASK; 612 } 613 614 static inline int ctd_get_fid1_ctl(struct vpdma_ctd *ctd) 615 { 616 return (ctd->fid_ctl >> CTD_FID1_SHFT) & CTD_FID1_MASK; 617 } 618 619 static inline int ctd_get_fid0_ctl(struct vpdma_ctd *ctd) 620 { 621 return ctd->fid_ctl & CTD_FID2_MASK; 622 } 623 624 static inline int ctd_get_pkt_type(struct vpdma_ctd *ctd) 625 { 626 return ctd->type_source_ctl >> CTD_PKT_TYPE_SHFT; 627 } 628 629 static inline int ctd_get_source(struct vpdma_ctd *ctd) 630 { 631 return (ctd->type_source_ctl >> CTD_SOURCE_SHFT) & CTD_SOURCE_MASK; 632 } 633 634 static inline int ctd_get_ctl(struct vpdma_ctd *ctd) 635 { 636 return ctd->type_source_ctl & CTD_CONTROL_MASK; 637 } 638 639 #endif 640