1*407965e2SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */ 2*407965e2SMauro Carvalho Chehab /* 3*407965e2SMauro Carvalho Chehab * TI AM437x Image Sensor Interface Registers 4*407965e2SMauro Carvalho Chehab * 5*407965e2SMauro Carvalho Chehab * Copyright (C) 2013 - 2014 Texas Instruments, Inc. 6*407965e2SMauro Carvalho Chehab * 7*407965e2SMauro Carvalho Chehab * Benoit Parrot <bparrot@ti.com> 8*407965e2SMauro Carvalho Chehab * Lad, Prabhakar <prabhakar.csengg@gmail.com> 9*407965e2SMauro Carvalho Chehab */ 10*407965e2SMauro Carvalho Chehab 11*407965e2SMauro Carvalho Chehab #ifndef AM437X_VPFE_REGS_H 12*407965e2SMauro Carvalho Chehab #define AM437X_VPFE_REGS_H 13*407965e2SMauro Carvalho Chehab 14*407965e2SMauro Carvalho Chehab /* VPFE module register offset */ 15*407965e2SMauro Carvalho Chehab #define VPFE_REVISION 0x0 16*407965e2SMauro Carvalho Chehab #define VPFE_PCR 0x4 17*407965e2SMauro Carvalho Chehab #define VPFE_SYNMODE 0x8 18*407965e2SMauro Carvalho Chehab #define VPFE_HD_VD_WID 0xc 19*407965e2SMauro Carvalho Chehab #define VPFE_PIX_LINES 0x10 20*407965e2SMauro Carvalho Chehab #define VPFE_HORZ_INFO 0x14 21*407965e2SMauro Carvalho Chehab #define VPFE_VERT_START 0x18 22*407965e2SMauro Carvalho Chehab #define VPFE_VERT_LINES 0x1c 23*407965e2SMauro Carvalho Chehab #define VPFE_CULLING 0x20 24*407965e2SMauro Carvalho Chehab #define VPFE_HSIZE_OFF 0x24 25*407965e2SMauro Carvalho Chehab #define VPFE_SDOFST 0x28 26*407965e2SMauro Carvalho Chehab #define VPFE_SDR_ADDR 0x2c 27*407965e2SMauro Carvalho Chehab #define VPFE_CLAMP 0x30 28*407965e2SMauro Carvalho Chehab #define VPFE_DCSUB 0x34 29*407965e2SMauro Carvalho Chehab #define VPFE_COLPTN 0x38 30*407965e2SMauro Carvalho Chehab #define VPFE_BLKCMP 0x3c 31*407965e2SMauro Carvalho Chehab #define VPFE_VDINT 0x48 32*407965e2SMauro Carvalho Chehab #define VPFE_ALAW 0x4c 33*407965e2SMauro Carvalho Chehab #define VPFE_REC656IF 0x50 34*407965e2SMauro Carvalho Chehab #define VPFE_CCDCFG 0x54 35*407965e2SMauro Carvalho Chehab #define VPFE_DMA_CNTL 0x98 36*407965e2SMauro Carvalho Chehab #define VPFE_SYSCONFIG 0x104 37*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG 0x108 38*407965e2SMauro Carvalho Chehab #define VPFE_IRQ_EOI 0x110 39*407965e2SMauro Carvalho Chehab #define VPFE_IRQ_STS_RAW 0x114 40*407965e2SMauro Carvalho Chehab #define VPFE_IRQ_STS 0x118 41*407965e2SMauro Carvalho Chehab #define VPFE_IRQ_EN_SET 0x11c 42*407965e2SMauro Carvalho Chehab #define VPFE_IRQ_EN_CLR 0x120 43*407965e2SMauro Carvalho Chehab #define VPFE_REG_END 0x124 44*407965e2SMauro Carvalho Chehab 45*407965e2SMauro Carvalho Chehab /* Define bit fields within selected registers */ 46*407965e2SMauro Carvalho Chehab #define VPFE_FID_POL_MASK 1 47*407965e2SMauro Carvalho Chehab #define VPFE_FID_POL_SHIFT 4 48*407965e2SMauro Carvalho Chehab #define VPFE_HD_POL_MASK 1 49*407965e2SMauro Carvalho Chehab #define VPFE_HD_POL_SHIFT 3 50*407965e2SMauro Carvalho Chehab #define VPFE_VD_POL_MASK 1 51*407965e2SMauro Carvalho Chehab #define VPFE_VD_POL_SHIFT 2 52*407965e2SMauro Carvalho Chehab #define VPFE_HSIZE_OFF_MASK 0xffffffe0 53*407965e2SMauro Carvalho Chehab #define VPFE_32BYTE_ALIGN_VAL 31 54*407965e2SMauro Carvalho Chehab #define VPFE_FRM_FMT_MASK 0x1 55*407965e2SMauro Carvalho Chehab #define VPFE_FRM_FMT_SHIFT 7 56*407965e2SMauro Carvalho Chehab #define VPFE_DATA_SZ_MASK 7 57*407965e2SMauro Carvalho Chehab #define VPFE_DATA_SZ_SHIFT 8 58*407965e2SMauro Carvalho Chehab #define VPFE_PIX_FMT_MASK 3 59*407965e2SMauro Carvalho Chehab #define VPFE_PIX_FMT_SHIFT 12 60*407965e2SMauro Carvalho Chehab #define VPFE_VP2SDR_DISABLE 0xfffbffff 61*407965e2SMauro Carvalho Chehab #define VPFE_WEN_ENABLE BIT(17) 62*407965e2SMauro Carvalho Chehab #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff 63*407965e2SMauro Carvalho Chehab #define VPFE_VDHDEN_ENABLE BIT(16) 64*407965e2SMauro Carvalho Chehab #define VPFE_LPF_ENABLE BIT(14) 65*407965e2SMauro Carvalho Chehab #define VPFE_ALAW_ENABLE BIT(3) 66*407965e2SMauro Carvalho Chehab #define VPFE_ALAW_GAMMA_WD_MASK 7 67*407965e2SMauro Carvalho Chehab #define VPFE_BLK_CLAMP_ENABLE BIT(31) 68*407965e2SMauro Carvalho Chehab #define VPFE_BLK_SGAIN_MASK 0x1f 69*407965e2SMauro Carvalho Chehab #define VPFE_BLK_ST_PXL_MASK 0x7fff 70*407965e2SMauro Carvalho Chehab #define VPFE_BLK_ST_PXL_SHIFT 10 71*407965e2SMauro Carvalho Chehab #define VPFE_BLK_SAMPLE_LN_MASK 7 72*407965e2SMauro Carvalho Chehab #define VPFE_BLK_SAMPLE_LN_SHIFT 28 73*407965e2SMauro Carvalho Chehab #define VPFE_BLK_SAMPLE_LINE_MASK 7 74*407965e2SMauro Carvalho Chehab #define VPFE_BLK_SAMPLE_LINE_SHIFT 25 75*407965e2SMauro Carvalho Chehab #define VPFE_BLK_DC_SUB_MASK 0x03fff 76*407965e2SMauro Carvalho Chehab #define VPFE_BLK_COMP_MASK 0xff 77*407965e2SMauro Carvalho Chehab #define VPFE_BLK_COMP_GB_COMP_SHIFT 8 78*407965e2SMauro Carvalho Chehab #define VPFE_BLK_COMP_GR_COMP_SHIFT 16 79*407965e2SMauro Carvalho Chehab #define VPFE_BLK_COMP_R_COMP_SHIFT 24 80*407965e2SMauro Carvalho Chehab #define VPFE_LATCH_ON_VSYNC_DISABLE BIT(15) 81*407965e2SMauro Carvalho Chehab #define VPFE_DATA_PACK_ENABLE BIT(11) 82*407965e2SMauro Carvalho Chehab #define VPFE_HORZ_INFO_SPH_SHIFT 16 83*407965e2SMauro Carvalho Chehab #define VPFE_VERT_START_SLV0_SHIFT 16 84*407965e2SMauro Carvalho Chehab #define VPFE_VDINT_VDINT0_SHIFT 16 85*407965e2SMauro Carvalho Chehab #define VPFE_VDINT_VDINT1_MASK 0xffff 86*407965e2SMauro Carvalho Chehab #define VPFE_PPC_RAW 1 87*407965e2SMauro Carvalho Chehab #define VPFE_DCSUB_DEFAULT_VAL 0 88*407965e2SMauro Carvalho Chehab #define VPFE_CLAMP_DEFAULT_VAL 0 89*407965e2SMauro Carvalho Chehab #define VPFE_COLPTN_VAL 0xbb11bb11 90*407965e2SMauro Carvalho Chehab #define VPFE_TWO_BYTES_PER_PIXEL 2 91*407965e2SMauro Carvalho Chehab #define VPFE_INTERLACED_IMAGE_INVERT 0x4b6d 92*407965e2SMauro Carvalho Chehab #define VPFE_INTERLACED_NO_IMAGE_INVERT 0x0249 93*407965e2SMauro Carvalho Chehab #define VPFE_PROGRESSIVE_IMAGE_INVERT 0x4000 94*407965e2SMauro Carvalho Chehab #define VPFE_PROGRESSIVE_NO_IMAGE_INVERT 0 95*407965e2SMauro Carvalho Chehab #define VPFE_INTERLACED_HEIGHT_SHIFT 1 96*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_INPMOD_SHIFT 12 97*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_INPMOD_MASK 3 98*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_8BITS (7 << 8) 99*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_10BITS (6 << 8) 100*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_11BITS (5 << 8) 101*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_12BITS (4 << 8) 102*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_13BITS (3 << 8) 103*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_14BITS (2 << 8) 104*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_15BITS (1 << 8) 105*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_16BITS (0 << 8) 106*407965e2SMauro Carvalho Chehab #define VPFE_SYN_FLDMODE_MASK 1 107*407965e2SMauro Carvalho Chehab #define VPFE_SYN_FLDMODE_SHIFT 7 108*407965e2SMauro Carvalho Chehab #define VPFE_REC656IF_BT656_EN 3 109*407965e2SMauro Carvalho Chehab #define VPFE_SYN_MODE_VD_POL_NEGATIVE BIT(2) 110*407965e2SMauro Carvalho Chehab #define VPFE_CCDCFG_Y8POS_SHIFT 11 111*407965e2SMauro Carvalho Chehab #define VPFE_CCDCFG_BW656_10BIT BIT(5) 112*407965e2SMauro Carvalho Chehab #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 113*407965e2SMauro Carvalho Chehab #define VPFE_NO_CULLING 0xffff00ff 114*407965e2SMauro Carvalho Chehab #define VPFE_VDINT0 BIT(0) 115*407965e2SMauro Carvalho Chehab #define VPFE_VDINT1 BIT(1) 116*407965e2SMauro Carvalho Chehab #define VPFE_VDINT2 BIT(2) 117*407965e2SMauro Carvalho Chehab #define VPFE_DMA_CNTL_OVERFLOW BIT(31) 118*407965e2SMauro Carvalho Chehab 119*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_PCLK_INV_SHIFT 0 120*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_PCLK_INV_MASK 1 121*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_PCLK_INV_NOT_INV 0 122*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_PCLK_INV_INV 1 123*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_EN_SHIFT 1 124*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_EN_MASK 2 125*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_EN_DISABLE 0 126*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_EN_ENABLE 1 127*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_ST_SHIFT 2 128*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_ST_MASK 4 129*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_ST_OCP_ACTIVE 0 130*407965e2SMauro Carvalho Chehab #define VPFE_CONFIG_ST_OCP_STANDBY 1 131*407965e2SMauro Carvalho Chehab 132*407965e2SMauro Carvalho Chehab #endif /* AM437X_VPFE_REGS_H */ 133