1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for STM32 Digital Camera Memory Interface 4 * 5 * Copyright (C) STMicroelectronics SA 2017 6 * Authors: Yannick Fertre <yannick.fertre@st.com> 7 * Hugues Fruchet <hugues.fruchet@st.com> 8 * for STMicroelectronics. 9 * 10 * This driver is based on atmel_isi.c 11 * 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/completion.h> 16 #include <linux/delay.h> 17 #include <linux/dmaengine.h> 18 #include <linux/init.h> 19 #include <linux/interrupt.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/of_device.h> 24 #include <linux/of_graph.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/reset.h> 29 #include <linux/videodev2.h> 30 31 #include <media/v4l2-ctrls.h> 32 #include <media/v4l2-dev.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-event.h> 35 #include <media/v4l2-fwnode.h> 36 #include <media/v4l2-image-sizes.h> 37 #include <media/v4l2-ioctl.h> 38 #include <media/v4l2-rect.h> 39 #include <media/videobuf2-dma-contig.h> 40 41 #define DRV_NAME "stm32-dcmi" 42 43 /* Registers offset for DCMI */ 44 #define DCMI_CR 0x00 /* Control Register */ 45 #define DCMI_SR 0x04 /* Status Register */ 46 #define DCMI_RIS 0x08 /* Raw Interrupt Status register */ 47 #define DCMI_IER 0x0C /* Interrupt Enable Register */ 48 #define DCMI_MIS 0x10 /* Masked Interrupt Status register */ 49 #define DCMI_ICR 0x14 /* Interrupt Clear Register */ 50 #define DCMI_ESCR 0x18 /* Embedded Synchronization Code Register */ 51 #define DCMI_ESUR 0x1C /* Embedded Synchronization Unmask Register */ 52 #define DCMI_CWSTRT 0x20 /* Crop Window STaRT */ 53 #define DCMI_CWSIZE 0x24 /* Crop Window SIZE */ 54 #define DCMI_DR 0x28 /* Data Register */ 55 #define DCMI_IDR 0x2C /* IDentifier Register */ 56 57 /* Bits definition for control register (DCMI_CR) */ 58 #define CR_CAPTURE BIT(0) 59 #define CR_CM BIT(1) 60 #define CR_CROP BIT(2) 61 #define CR_JPEG BIT(3) 62 #define CR_ESS BIT(4) 63 #define CR_PCKPOL BIT(5) 64 #define CR_HSPOL BIT(6) 65 #define CR_VSPOL BIT(7) 66 #define CR_FCRC_0 BIT(8) 67 #define CR_FCRC_1 BIT(9) 68 #define CR_EDM_0 BIT(10) 69 #define CR_EDM_1 BIT(11) 70 #define CR_ENABLE BIT(14) 71 72 /* Bits definition for status register (DCMI_SR) */ 73 #define SR_HSYNC BIT(0) 74 #define SR_VSYNC BIT(1) 75 #define SR_FNE BIT(2) 76 77 /* 78 * Bits definition for interrupt registers 79 * (DCMI_RIS, DCMI_IER, DCMI_MIS, DCMI_ICR) 80 */ 81 #define IT_FRAME BIT(0) 82 #define IT_OVR BIT(1) 83 #define IT_ERR BIT(2) 84 #define IT_VSYNC BIT(3) 85 #define IT_LINE BIT(4) 86 87 enum state { 88 STOPPED = 0, 89 WAIT_FOR_BUFFER, 90 RUNNING, 91 }; 92 93 #define MIN_WIDTH 16U 94 #define MAX_WIDTH 2592U 95 #define MIN_HEIGHT 16U 96 #define MAX_HEIGHT 2592U 97 98 #define TIMEOUT_MS 1000 99 100 #define OVERRUN_ERROR_THRESHOLD 3 101 102 struct dcmi_format { 103 u32 fourcc; 104 u32 mbus_code; 105 u8 bpp; 106 }; 107 108 struct dcmi_framesize { 109 u32 width; 110 u32 height; 111 }; 112 113 struct dcmi_buf { 114 struct vb2_v4l2_buffer vb; 115 bool prepared; 116 struct sg_table sgt; 117 size_t size; 118 struct list_head list; 119 }; 120 121 struct stm32_dcmi { 122 /* Protects the access of variables shared within the interrupt */ 123 spinlock_t irqlock; 124 struct device *dev; 125 void __iomem *regs; 126 struct resource *res; 127 struct reset_control *rstc; 128 int sequence; 129 struct list_head buffers; 130 struct dcmi_buf *active; 131 int irq; 132 133 struct v4l2_device v4l2_dev; 134 struct video_device *vdev; 135 struct v4l2_async_notifier notifier; 136 struct v4l2_subdev *source; 137 struct v4l2_format fmt; 138 struct v4l2_rect crop; 139 bool do_crop; 140 141 const struct dcmi_format **sd_formats; 142 unsigned int num_of_sd_formats; 143 const struct dcmi_format *sd_format; 144 struct dcmi_framesize *sd_framesizes; 145 unsigned int num_of_sd_framesizes; 146 struct dcmi_framesize sd_framesize; 147 struct v4l2_rect sd_bounds; 148 149 /* Protect this data structure */ 150 struct mutex lock; 151 struct vb2_queue queue; 152 153 struct v4l2_mbus_config_parallel bus; 154 enum v4l2_mbus_type bus_type; 155 struct completion complete; 156 struct clk *mclk; 157 enum state state; 158 struct dma_chan *dma_chan; 159 dma_cookie_t dma_cookie; 160 u32 dma_max_burst; 161 u32 misr; 162 int errors_count; 163 int overrun_count; 164 int buffers_count; 165 166 /* Ensure DMA operations atomicity */ 167 struct mutex dma_lock; 168 169 struct media_device mdev; 170 struct media_pad vid_cap_pad; 171 struct media_pipeline pipeline; 172 }; 173 174 static inline struct stm32_dcmi *notifier_to_dcmi(struct v4l2_async_notifier *n) 175 { 176 return container_of(n, struct stm32_dcmi, notifier); 177 } 178 179 static inline u32 reg_read(void __iomem *base, u32 reg) 180 { 181 return readl_relaxed(base + reg); 182 } 183 184 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 185 { 186 writel_relaxed(val, base + reg); 187 } 188 189 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 190 { 191 reg_write(base, reg, reg_read(base, reg) | mask); 192 } 193 194 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 195 { 196 reg_write(base, reg, reg_read(base, reg) & ~mask); 197 } 198 199 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf); 200 201 static void dcmi_buffer_done(struct stm32_dcmi *dcmi, 202 struct dcmi_buf *buf, 203 size_t bytesused, 204 int err) 205 { 206 struct vb2_v4l2_buffer *vbuf; 207 208 if (!buf) 209 return; 210 211 list_del_init(&buf->list); 212 213 vbuf = &buf->vb; 214 215 vbuf->sequence = dcmi->sequence++; 216 vbuf->field = V4L2_FIELD_NONE; 217 vbuf->vb2_buf.timestamp = ktime_get_ns(); 218 vb2_set_plane_payload(&vbuf->vb2_buf, 0, bytesused); 219 vb2_buffer_done(&vbuf->vb2_buf, 220 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE); 221 dev_dbg(dcmi->dev, "buffer[%d] done seq=%d, bytesused=%zu\n", 222 vbuf->vb2_buf.index, vbuf->sequence, bytesused); 223 224 dcmi->buffers_count++; 225 dcmi->active = NULL; 226 } 227 228 static int dcmi_restart_capture(struct stm32_dcmi *dcmi) 229 { 230 struct dcmi_buf *buf; 231 232 spin_lock_irq(&dcmi->irqlock); 233 234 if (dcmi->state != RUNNING) { 235 spin_unlock_irq(&dcmi->irqlock); 236 return -EINVAL; 237 } 238 239 /* Restart a new DMA transfer with next buffer */ 240 if (list_empty(&dcmi->buffers)) { 241 dev_dbg(dcmi->dev, "Capture restart is deferred to next buffer queueing\n"); 242 dcmi->state = WAIT_FOR_BUFFER; 243 spin_unlock_irq(&dcmi->irqlock); 244 return 0; 245 } 246 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list); 247 dcmi->active = buf; 248 249 spin_unlock_irq(&dcmi->irqlock); 250 251 return dcmi_start_capture(dcmi, buf); 252 } 253 254 static void dcmi_dma_callback(void *param) 255 { 256 struct stm32_dcmi *dcmi = (struct stm32_dcmi *)param; 257 struct dma_tx_state state; 258 enum dma_status status; 259 struct dcmi_buf *buf = dcmi->active; 260 261 spin_lock_irq(&dcmi->irqlock); 262 263 /* Check DMA status */ 264 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); 265 266 switch (status) { 267 case DMA_IN_PROGRESS: 268 dev_dbg(dcmi->dev, "%s: Received DMA_IN_PROGRESS\n", __func__); 269 break; 270 case DMA_PAUSED: 271 dev_err(dcmi->dev, "%s: Received DMA_PAUSED\n", __func__); 272 break; 273 case DMA_ERROR: 274 dev_err(dcmi->dev, "%s: Received DMA_ERROR\n", __func__); 275 276 /* Return buffer to V4L2 in error state */ 277 dcmi_buffer_done(dcmi, buf, 0, -EIO); 278 break; 279 case DMA_COMPLETE: 280 dev_dbg(dcmi->dev, "%s: Received DMA_COMPLETE\n", __func__); 281 282 /* Return buffer to V4L2 */ 283 dcmi_buffer_done(dcmi, buf, buf->size, 0); 284 285 spin_unlock_irq(&dcmi->irqlock); 286 287 /* Restart capture */ 288 if (dcmi_restart_capture(dcmi)) 289 dev_err(dcmi->dev, "%s: Cannot restart capture on DMA complete\n", 290 __func__); 291 return; 292 default: 293 dev_err(dcmi->dev, "%s: Received unknown status\n", __func__); 294 break; 295 } 296 297 spin_unlock_irq(&dcmi->irqlock); 298 } 299 300 static int dcmi_start_dma(struct stm32_dcmi *dcmi, 301 struct dcmi_buf *buf) 302 { 303 struct dma_async_tx_descriptor *desc = NULL; 304 struct dma_slave_config config; 305 int ret; 306 307 memset(&config, 0, sizeof(config)); 308 309 config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR; 310 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 311 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 312 config.dst_maxburst = 4; 313 314 /* Configure DMA channel */ 315 ret = dmaengine_slave_config(dcmi->dma_chan, &config); 316 if (ret < 0) { 317 dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n", 318 __func__, ret); 319 return ret; 320 } 321 322 /* 323 * Avoid call of dmaengine_terminate_sync() between 324 * dmaengine_prep_slave_single() and dmaengine_submit() 325 * by locking the whole DMA submission sequence 326 */ 327 mutex_lock(&dcmi->dma_lock); 328 329 /* Prepare a DMA transaction */ 330 desc = dmaengine_prep_slave_sg(dcmi->dma_chan, buf->sgt.sgl, buf->sgt.nents, 331 DMA_DEV_TO_MEM, 332 DMA_PREP_INTERRUPT); 333 if (!desc) { 334 dev_err(dcmi->dev, "%s: DMA dmaengine_prep_slave_sg failed\n", __func__); 335 mutex_unlock(&dcmi->dma_lock); 336 return -EINVAL; 337 } 338 339 /* Set completion callback routine for notification */ 340 desc->callback = dcmi_dma_callback; 341 desc->callback_param = dcmi; 342 343 /* Push current DMA transaction in the pending queue */ 344 dcmi->dma_cookie = dmaengine_submit(desc); 345 if (dma_submit_error(dcmi->dma_cookie)) { 346 dev_err(dcmi->dev, "%s: DMA submission failed\n", __func__); 347 mutex_unlock(&dcmi->dma_lock); 348 return -ENXIO; 349 } 350 351 mutex_unlock(&dcmi->dma_lock); 352 353 dma_async_issue_pending(dcmi->dma_chan); 354 355 return 0; 356 } 357 358 static int dcmi_start_capture(struct stm32_dcmi *dcmi, struct dcmi_buf *buf) 359 { 360 int ret; 361 362 if (!buf) 363 return -EINVAL; 364 365 ret = dcmi_start_dma(dcmi, buf); 366 if (ret) { 367 dcmi->errors_count++; 368 return ret; 369 } 370 371 /* Enable capture */ 372 reg_set(dcmi->regs, DCMI_CR, CR_CAPTURE); 373 374 return 0; 375 } 376 377 static void dcmi_set_crop(struct stm32_dcmi *dcmi) 378 { 379 u32 size, start; 380 381 /* Crop resolution */ 382 size = ((dcmi->crop.height - 1) << 16) | 383 ((dcmi->crop.width << 1) - 1); 384 reg_write(dcmi->regs, DCMI_CWSIZE, size); 385 386 /* Crop start point */ 387 start = ((dcmi->crop.top) << 16) | 388 ((dcmi->crop.left << 1)); 389 reg_write(dcmi->regs, DCMI_CWSTRT, start); 390 391 dev_dbg(dcmi->dev, "Cropping to %ux%u@%u:%u\n", 392 dcmi->crop.width, dcmi->crop.height, 393 dcmi->crop.left, dcmi->crop.top); 394 395 /* Enable crop */ 396 reg_set(dcmi->regs, DCMI_CR, CR_CROP); 397 } 398 399 static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) 400 { 401 struct dma_tx_state state; 402 enum dma_status status; 403 struct dcmi_buf *buf = dcmi->active; 404 405 if (!buf) 406 return; 407 408 /* 409 * Because of variable JPEG buffer size sent by sensor, 410 * DMA transfer never completes due to transfer size never reached. 411 * In order to ensure that all the JPEG data are transferred 412 * in active buffer memory, DMA is drained. 413 * Then DMA tx status gives the amount of data transferred 414 * to memory, which is then returned to V4L2 through the active 415 * buffer payload. 416 */ 417 418 /* Drain DMA */ 419 dmaengine_synchronize(dcmi->dma_chan); 420 421 /* Get DMA residue to get JPEG size */ 422 status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); 423 if (status != DMA_ERROR && state.residue < buf->size) { 424 /* Return JPEG buffer to V4L2 with received JPEG buffer size */ 425 dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0); 426 } else { 427 dcmi->errors_count++; 428 dev_err(dcmi->dev, "%s: Cannot get JPEG size from DMA\n", 429 __func__); 430 /* Return JPEG buffer to V4L2 in ERROR state */ 431 dcmi_buffer_done(dcmi, buf, 0, -EIO); 432 } 433 434 /* Abort DMA operation */ 435 dmaengine_terminate_sync(dcmi->dma_chan); 436 437 /* Restart capture */ 438 if (dcmi_restart_capture(dcmi)) 439 dev_err(dcmi->dev, "%s: Cannot restart capture on JPEG received\n", 440 __func__); 441 } 442 443 static irqreturn_t dcmi_irq_thread(int irq, void *arg) 444 { 445 struct stm32_dcmi *dcmi = arg; 446 447 spin_lock_irq(&dcmi->irqlock); 448 449 if (dcmi->misr & IT_OVR) { 450 dcmi->overrun_count++; 451 if (dcmi->overrun_count > OVERRUN_ERROR_THRESHOLD) 452 dcmi->errors_count++; 453 } 454 if (dcmi->misr & IT_ERR) 455 dcmi->errors_count++; 456 457 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG && 458 dcmi->misr & IT_FRAME) { 459 /* JPEG received */ 460 spin_unlock_irq(&dcmi->irqlock); 461 dcmi_process_jpeg(dcmi); 462 return IRQ_HANDLED; 463 } 464 465 spin_unlock_irq(&dcmi->irqlock); 466 return IRQ_HANDLED; 467 } 468 469 static irqreturn_t dcmi_irq_callback(int irq, void *arg) 470 { 471 struct stm32_dcmi *dcmi = arg; 472 unsigned long flags; 473 474 spin_lock_irqsave(&dcmi->irqlock, flags); 475 476 dcmi->misr = reg_read(dcmi->regs, DCMI_MIS); 477 478 /* Clear interrupt */ 479 reg_set(dcmi->regs, DCMI_ICR, IT_FRAME | IT_OVR | IT_ERR); 480 481 spin_unlock_irqrestore(&dcmi->irqlock, flags); 482 483 return IRQ_WAKE_THREAD; 484 } 485 486 static int dcmi_queue_setup(struct vb2_queue *vq, 487 unsigned int *nbuffers, 488 unsigned int *nplanes, 489 unsigned int sizes[], 490 struct device *alloc_devs[]) 491 { 492 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq); 493 unsigned int size; 494 495 size = dcmi->fmt.fmt.pix.sizeimage; 496 497 /* Make sure the image size is large enough */ 498 if (*nplanes) 499 return sizes[0] < size ? -EINVAL : 0; 500 501 *nplanes = 1; 502 sizes[0] = size; 503 504 dev_dbg(dcmi->dev, "Setup queue, count=%d, size=%d\n", 505 *nbuffers, size); 506 507 return 0; 508 } 509 510 static int dcmi_buf_init(struct vb2_buffer *vb) 511 { 512 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 513 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb); 514 515 INIT_LIST_HEAD(&buf->list); 516 517 return 0; 518 } 519 520 static int dcmi_buf_prepare(struct vb2_buffer *vb) 521 { 522 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue); 523 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 524 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb); 525 unsigned long size; 526 unsigned int num_sgs = 1; 527 dma_addr_t dma_buf; 528 struct scatterlist *sg; 529 int i, ret; 530 531 size = dcmi->fmt.fmt.pix.sizeimage; 532 533 if (vb2_plane_size(vb, 0) < size) { 534 dev_err(dcmi->dev, "%s data will not fit into plane (%lu < %lu)\n", 535 __func__, vb2_plane_size(vb, 0), size); 536 return -EINVAL; 537 } 538 539 vb2_set_plane_payload(vb, 0, size); 540 541 if (!buf->prepared) { 542 /* Get memory addresses */ 543 buf->size = vb2_plane_size(&buf->vb.vb2_buf, 0); 544 if (buf->size > dcmi->dma_max_burst) 545 num_sgs = DIV_ROUND_UP(buf->size, dcmi->dma_max_burst); 546 547 ret = sg_alloc_table(&buf->sgt, num_sgs, GFP_ATOMIC); 548 if (ret) { 549 dev_err(dcmi->dev, "sg table alloc failed\n"); 550 return ret; 551 } 552 553 dma_buf = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0); 554 555 dev_dbg(dcmi->dev, "buffer[%d] phy=%pad size=%zu\n", 556 vb->index, &dma_buf, buf->size); 557 558 for_each_sg(buf->sgt.sgl, sg, num_sgs, i) { 559 size_t bytes = min_t(size_t, size, dcmi->dma_max_burst); 560 561 sg_dma_address(sg) = dma_buf; 562 sg_dma_len(sg) = bytes; 563 dma_buf += bytes; 564 size -= bytes; 565 } 566 567 buf->prepared = true; 568 569 vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size); 570 } 571 572 return 0; 573 } 574 575 static void dcmi_buf_queue(struct vb2_buffer *vb) 576 { 577 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vb->vb2_queue); 578 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 579 struct dcmi_buf *buf = container_of(vbuf, struct dcmi_buf, vb); 580 581 spin_lock_irq(&dcmi->irqlock); 582 583 /* Enqueue to video buffers list */ 584 list_add_tail(&buf->list, &dcmi->buffers); 585 586 if (dcmi->state == WAIT_FOR_BUFFER) { 587 dcmi->state = RUNNING; 588 dcmi->active = buf; 589 590 dev_dbg(dcmi->dev, "Starting capture on buffer[%d] queued\n", 591 buf->vb.vb2_buf.index); 592 593 spin_unlock_irq(&dcmi->irqlock); 594 if (dcmi_start_capture(dcmi, buf)) 595 dev_err(dcmi->dev, "%s: Cannot restart capture on overflow or error\n", 596 __func__); 597 return; 598 } 599 600 spin_unlock_irq(&dcmi->irqlock); 601 } 602 603 static struct media_entity *dcmi_find_source(struct stm32_dcmi *dcmi) 604 { 605 struct media_entity *entity = &dcmi->vdev->entity; 606 struct media_pad *pad; 607 608 /* Walk searching for entity having no sink */ 609 while (1) { 610 pad = &entity->pads[0]; 611 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 612 break; 613 614 pad = media_entity_remote_pad(pad); 615 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 616 break; 617 618 entity = pad->entity; 619 } 620 621 return entity; 622 } 623 624 static int dcmi_pipeline_s_fmt(struct stm32_dcmi *dcmi, 625 struct v4l2_subdev_state *sd_state, 626 struct v4l2_subdev_format *format) 627 { 628 struct media_entity *entity = &dcmi->source->entity; 629 struct v4l2_subdev *subdev; 630 struct media_pad *sink_pad = NULL; 631 struct media_pad *src_pad = NULL; 632 struct media_pad *pad = NULL; 633 struct v4l2_subdev_format fmt = *format; 634 bool found = false; 635 int ret; 636 637 /* 638 * Starting from sensor subdevice, walk within 639 * pipeline and set format on each subdevice 640 */ 641 while (1) { 642 unsigned int i; 643 644 /* Search if current entity has a source pad */ 645 for (i = 0; i < entity->num_pads; i++) { 646 pad = &entity->pads[i]; 647 if (pad->flags & MEDIA_PAD_FL_SOURCE) { 648 src_pad = pad; 649 found = true; 650 break; 651 } 652 } 653 if (!found) 654 break; 655 656 subdev = media_entity_to_v4l2_subdev(entity); 657 658 /* Propagate format on sink pad if any, otherwise source pad */ 659 if (sink_pad) 660 pad = sink_pad; 661 662 dev_dbg(dcmi->dev, "\"%s\":%d pad format set to 0x%x %ux%u\n", 663 subdev->name, pad->index, format->format.code, 664 format->format.width, format->format.height); 665 666 fmt.pad = pad->index; 667 ret = v4l2_subdev_call(subdev, pad, set_fmt, sd_state, &fmt); 668 if (ret < 0) { 669 dev_err(dcmi->dev, "%s: Failed to set format 0x%x %ux%u on \"%s\":%d pad (%d)\n", 670 __func__, format->format.code, 671 format->format.width, format->format.height, 672 subdev->name, pad->index, ret); 673 return ret; 674 } 675 676 if (fmt.format.code != format->format.code || 677 fmt.format.width != format->format.width || 678 fmt.format.height != format->format.height) { 679 dev_dbg(dcmi->dev, "\"%s\":%d pad format has been changed to 0x%x %ux%u\n", 680 subdev->name, pad->index, fmt.format.code, 681 fmt.format.width, fmt.format.height); 682 } 683 684 /* Walk to next entity */ 685 sink_pad = media_entity_remote_pad(src_pad); 686 if (!sink_pad || !is_media_entity_v4l2_subdev(sink_pad->entity)) 687 break; 688 689 entity = sink_pad->entity; 690 } 691 *format = fmt; 692 693 return 0; 694 } 695 696 static int dcmi_pipeline_s_stream(struct stm32_dcmi *dcmi, int state) 697 { 698 struct media_entity *entity = &dcmi->vdev->entity; 699 struct v4l2_subdev *subdev; 700 struct media_pad *pad; 701 int ret; 702 703 /* Start/stop all entities within pipeline */ 704 while (1) { 705 pad = &entity->pads[0]; 706 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 707 break; 708 709 pad = media_entity_remote_pad(pad); 710 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 711 break; 712 713 entity = pad->entity; 714 subdev = media_entity_to_v4l2_subdev(entity); 715 716 ret = v4l2_subdev_call(subdev, video, s_stream, state); 717 if (ret < 0 && ret != -ENOIOCTLCMD) { 718 dev_err(dcmi->dev, "%s: \"%s\" failed to %s streaming (%d)\n", 719 __func__, subdev->name, 720 state ? "start" : "stop", ret); 721 return ret; 722 } 723 724 dev_dbg(dcmi->dev, "\"%s\" is %s\n", 725 subdev->name, state ? "started" : "stopped"); 726 } 727 728 return 0; 729 } 730 731 static int dcmi_pipeline_start(struct stm32_dcmi *dcmi) 732 { 733 return dcmi_pipeline_s_stream(dcmi, 1); 734 } 735 736 static void dcmi_pipeline_stop(struct stm32_dcmi *dcmi) 737 { 738 dcmi_pipeline_s_stream(dcmi, 0); 739 } 740 741 static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) 742 { 743 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq); 744 struct dcmi_buf *buf, *node; 745 u32 val = 0; 746 int ret; 747 748 ret = pm_runtime_resume_and_get(dcmi->dev); 749 if (ret < 0) { 750 dev_err(dcmi->dev, "%s: Failed to start streaming, cannot get sync (%d)\n", 751 __func__, ret); 752 goto err_unlocked; 753 } 754 755 ret = media_pipeline_start(&dcmi->vdev->entity, &dcmi->pipeline); 756 if (ret < 0) { 757 dev_err(dcmi->dev, "%s: Failed to start streaming, media pipeline start error (%d)\n", 758 __func__, ret); 759 goto err_pm_put; 760 } 761 762 ret = dcmi_pipeline_start(dcmi); 763 if (ret) 764 goto err_media_pipeline_stop; 765 766 spin_lock_irq(&dcmi->irqlock); 767 768 /* Set bus width */ 769 switch (dcmi->bus.bus_width) { 770 case 14: 771 val |= CR_EDM_0 | CR_EDM_1; 772 break; 773 case 12: 774 val |= CR_EDM_1; 775 break; 776 case 10: 777 val |= CR_EDM_0; 778 break; 779 default: 780 /* Set bus width to 8 bits by default */ 781 break; 782 } 783 784 /* Set vertical synchronization polarity */ 785 if (dcmi->bus.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) 786 val |= CR_VSPOL; 787 788 /* Set horizontal synchronization polarity */ 789 if (dcmi->bus.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) 790 val |= CR_HSPOL; 791 792 /* Set pixel clock polarity */ 793 if (dcmi->bus.flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 794 val |= CR_PCKPOL; 795 796 /* 797 * BT656 embedded synchronisation bus mode. 798 * 799 * Default SAV/EAV mode is supported here with default codes 800 * SAV=0xff000080 & EAV=0xff00009d. 801 * With DCMI this means LSC=SAV=0x80 & LEC=EAV=0x9d. 802 */ 803 if (dcmi->bus_type == V4L2_MBUS_BT656) { 804 val |= CR_ESS; 805 806 /* Unmask all codes */ 807 reg_write(dcmi->regs, DCMI_ESUR, 0xffffffff);/* FEC:LEC:LSC:FSC */ 808 809 /* Trig on LSC=0x80 & LEC=0x9d codes, ignore FSC and FEC */ 810 reg_write(dcmi->regs, DCMI_ESCR, 0xff9d80ff);/* FEC:LEC:LSC:FSC */ 811 } 812 813 reg_write(dcmi->regs, DCMI_CR, val); 814 815 /* Set crop */ 816 if (dcmi->do_crop) 817 dcmi_set_crop(dcmi); 818 819 /* Enable jpeg capture */ 820 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG) 821 reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */ 822 823 /* Enable dcmi */ 824 reg_set(dcmi->regs, DCMI_CR, CR_ENABLE); 825 826 dcmi->sequence = 0; 827 dcmi->errors_count = 0; 828 dcmi->overrun_count = 0; 829 dcmi->buffers_count = 0; 830 831 /* 832 * Start transfer if at least one buffer has been queued, 833 * otherwise transfer is deferred at buffer queueing 834 */ 835 if (list_empty(&dcmi->buffers)) { 836 dev_dbg(dcmi->dev, "Start streaming is deferred to next buffer queueing\n"); 837 dcmi->state = WAIT_FOR_BUFFER; 838 spin_unlock_irq(&dcmi->irqlock); 839 return 0; 840 } 841 842 buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list); 843 dcmi->active = buf; 844 845 dcmi->state = RUNNING; 846 847 dev_dbg(dcmi->dev, "Start streaming, starting capture\n"); 848 849 spin_unlock_irq(&dcmi->irqlock); 850 ret = dcmi_start_capture(dcmi, buf); 851 if (ret) { 852 dev_err(dcmi->dev, "%s: Start streaming failed, cannot start capture\n", 853 __func__); 854 goto err_pipeline_stop; 855 } 856 857 /* Enable interruptions */ 858 if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG) 859 reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); 860 else 861 reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR); 862 863 return 0; 864 865 err_pipeline_stop: 866 dcmi_pipeline_stop(dcmi); 867 868 err_media_pipeline_stop: 869 media_pipeline_stop(&dcmi->vdev->entity); 870 871 err_pm_put: 872 pm_runtime_put(dcmi->dev); 873 err_unlocked: 874 spin_lock_irq(&dcmi->irqlock); 875 /* 876 * Return all buffers to vb2 in QUEUED state. 877 * This will give ownership back to userspace 878 */ 879 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) { 880 list_del_init(&buf->list); 881 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_QUEUED); 882 } 883 dcmi->active = NULL; 884 spin_unlock_irq(&dcmi->irqlock); 885 886 return ret; 887 } 888 889 static void dcmi_stop_streaming(struct vb2_queue *vq) 890 { 891 struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq); 892 struct dcmi_buf *buf, *node; 893 894 dcmi_pipeline_stop(dcmi); 895 896 media_pipeline_stop(&dcmi->vdev->entity); 897 898 spin_lock_irq(&dcmi->irqlock); 899 900 /* Disable interruptions */ 901 reg_clear(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); 902 903 /* Disable DCMI */ 904 reg_clear(dcmi->regs, DCMI_CR, CR_ENABLE); 905 906 /* Return all queued buffers to vb2 in ERROR state */ 907 list_for_each_entry_safe(buf, node, &dcmi->buffers, list) { 908 list_del_init(&buf->list); 909 vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); 910 } 911 912 dcmi->active = NULL; 913 dcmi->state = STOPPED; 914 915 spin_unlock_irq(&dcmi->irqlock); 916 917 /* Stop all pending DMA operations */ 918 mutex_lock(&dcmi->dma_lock); 919 dmaengine_terminate_sync(dcmi->dma_chan); 920 mutex_unlock(&dcmi->dma_lock); 921 922 pm_runtime_put(dcmi->dev); 923 924 if (dcmi->errors_count) 925 dev_warn(dcmi->dev, "Some errors found while streaming: errors=%d (overrun=%d), buffers=%d\n", 926 dcmi->errors_count, dcmi->overrun_count, 927 dcmi->buffers_count); 928 dev_dbg(dcmi->dev, "Stop streaming, errors=%d (overrun=%d), buffers=%d\n", 929 dcmi->errors_count, dcmi->overrun_count, 930 dcmi->buffers_count); 931 } 932 933 static const struct vb2_ops dcmi_video_qops = { 934 .queue_setup = dcmi_queue_setup, 935 .buf_init = dcmi_buf_init, 936 .buf_prepare = dcmi_buf_prepare, 937 .buf_queue = dcmi_buf_queue, 938 .start_streaming = dcmi_start_streaming, 939 .stop_streaming = dcmi_stop_streaming, 940 .wait_prepare = vb2_ops_wait_prepare, 941 .wait_finish = vb2_ops_wait_finish, 942 }; 943 944 static int dcmi_g_fmt_vid_cap(struct file *file, void *priv, 945 struct v4l2_format *fmt) 946 { 947 struct stm32_dcmi *dcmi = video_drvdata(file); 948 949 *fmt = dcmi->fmt; 950 951 return 0; 952 } 953 954 static const struct dcmi_format *find_format_by_fourcc(struct stm32_dcmi *dcmi, 955 unsigned int fourcc) 956 { 957 unsigned int num_formats = dcmi->num_of_sd_formats; 958 const struct dcmi_format *fmt; 959 unsigned int i; 960 961 for (i = 0; i < num_formats; i++) { 962 fmt = dcmi->sd_formats[i]; 963 if (fmt->fourcc == fourcc) 964 return fmt; 965 } 966 967 return NULL; 968 } 969 970 static void __find_outer_frame_size(struct stm32_dcmi *dcmi, 971 struct v4l2_pix_format *pix, 972 struct dcmi_framesize *framesize) 973 { 974 struct dcmi_framesize *match = NULL; 975 unsigned int i; 976 unsigned int min_err = UINT_MAX; 977 978 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) { 979 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i]; 980 int w_err = (fsize->width - pix->width); 981 int h_err = (fsize->height - pix->height); 982 int err = w_err + h_err; 983 984 if (w_err >= 0 && h_err >= 0 && err < min_err) { 985 min_err = err; 986 match = fsize; 987 } 988 } 989 if (!match) 990 match = &dcmi->sd_framesizes[0]; 991 992 *framesize = *match; 993 } 994 995 static int dcmi_try_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f, 996 const struct dcmi_format **sd_format, 997 struct dcmi_framesize *sd_framesize) 998 { 999 const struct dcmi_format *sd_fmt; 1000 struct dcmi_framesize sd_fsize; 1001 struct v4l2_pix_format *pix = &f->fmt.pix; 1002 struct v4l2_subdev_pad_config pad_cfg; 1003 struct v4l2_subdev_state pad_state = { 1004 .pads = &pad_cfg 1005 }; 1006 struct v4l2_subdev_format format = { 1007 .which = V4L2_SUBDEV_FORMAT_TRY, 1008 }; 1009 bool do_crop; 1010 int ret; 1011 1012 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat); 1013 if (!sd_fmt) { 1014 if (!dcmi->num_of_sd_formats) 1015 return -ENODATA; 1016 1017 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1]; 1018 pix->pixelformat = sd_fmt->fourcc; 1019 } 1020 1021 /* Limit to hardware capabilities */ 1022 pix->width = clamp(pix->width, MIN_WIDTH, MAX_WIDTH); 1023 pix->height = clamp(pix->height, MIN_HEIGHT, MAX_HEIGHT); 1024 1025 /* No crop if JPEG is requested */ 1026 do_crop = dcmi->do_crop && (pix->pixelformat != V4L2_PIX_FMT_JPEG); 1027 1028 if (do_crop && dcmi->num_of_sd_framesizes) { 1029 struct dcmi_framesize outer_sd_fsize; 1030 /* 1031 * If crop is requested and sensor have discrete frame sizes, 1032 * select the frame size that is just larger than request 1033 */ 1034 __find_outer_frame_size(dcmi, pix, &outer_sd_fsize); 1035 pix->width = outer_sd_fsize.width; 1036 pix->height = outer_sd_fsize.height; 1037 } 1038 1039 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code); 1040 ret = v4l2_subdev_call(dcmi->source, pad, set_fmt, 1041 &pad_state, &format); 1042 if (ret < 0) 1043 return ret; 1044 1045 /* Update pix regarding to what sensor can do */ 1046 v4l2_fill_pix_format(pix, &format.format); 1047 1048 /* Save resolution that sensor can actually do */ 1049 sd_fsize.width = pix->width; 1050 sd_fsize.height = pix->height; 1051 1052 if (do_crop) { 1053 struct v4l2_rect c = dcmi->crop; 1054 struct v4l2_rect max_rect; 1055 1056 /* 1057 * Adjust crop by making the intersection between 1058 * format resolution request and crop request 1059 */ 1060 max_rect.top = 0; 1061 max_rect.left = 0; 1062 max_rect.width = pix->width; 1063 max_rect.height = pix->height; 1064 v4l2_rect_map_inside(&c, &max_rect); 1065 c.top = clamp_t(s32, c.top, 0, pix->height - c.height); 1066 c.left = clamp_t(s32, c.left, 0, pix->width - c.width); 1067 dcmi->crop = c; 1068 1069 /* Adjust format resolution request to crop */ 1070 pix->width = dcmi->crop.width; 1071 pix->height = dcmi->crop.height; 1072 } 1073 1074 pix->field = V4L2_FIELD_NONE; 1075 pix->bytesperline = pix->width * sd_fmt->bpp; 1076 pix->sizeimage = pix->bytesperline * pix->height; 1077 1078 if (sd_format) 1079 *sd_format = sd_fmt; 1080 if (sd_framesize) 1081 *sd_framesize = sd_fsize; 1082 1083 return 0; 1084 } 1085 1086 static int dcmi_set_fmt(struct stm32_dcmi *dcmi, struct v4l2_format *f) 1087 { 1088 struct v4l2_subdev_format format = { 1089 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1090 }; 1091 const struct dcmi_format *sd_format; 1092 struct dcmi_framesize sd_framesize; 1093 struct v4l2_mbus_framefmt *mf = &format.format; 1094 struct v4l2_pix_format *pix = &f->fmt.pix; 1095 int ret; 1096 1097 /* 1098 * Try format, fmt.width/height could have been changed 1099 * to match sensor capability or crop request 1100 * sd_format & sd_framesize will contain what subdev 1101 * can do for this request. 1102 */ 1103 ret = dcmi_try_fmt(dcmi, f, &sd_format, &sd_framesize); 1104 if (ret) 1105 return ret; 1106 1107 /* Disable crop if JPEG is requested or BT656 bus is selected */ 1108 if (pix->pixelformat == V4L2_PIX_FMT_JPEG && 1109 dcmi->bus_type != V4L2_MBUS_BT656) 1110 dcmi->do_crop = false; 1111 1112 /* pix to mbus format */ 1113 v4l2_fill_mbus_format(mf, pix, 1114 sd_format->mbus_code); 1115 mf->width = sd_framesize.width; 1116 mf->height = sd_framesize.height; 1117 1118 ret = dcmi_pipeline_s_fmt(dcmi, NULL, &format); 1119 if (ret < 0) 1120 return ret; 1121 1122 dev_dbg(dcmi->dev, "Sensor format set to 0x%x %ux%u\n", 1123 mf->code, mf->width, mf->height); 1124 dev_dbg(dcmi->dev, "Buffer format set to %4.4s %ux%u\n", 1125 (char *)&pix->pixelformat, 1126 pix->width, pix->height); 1127 1128 dcmi->fmt = *f; 1129 dcmi->sd_format = sd_format; 1130 dcmi->sd_framesize = sd_framesize; 1131 1132 return 0; 1133 } 1134 1135 static int dcmi_s_fmt_vid_cap(struct file *file, void *priv, 1136 struct v4l2_format *f) 1137 { 1138 struct stm32_dcmi *dcmi = video_drvdata(file); 1139 1140 if (vb2_is_streaming(&dcmi->queue)) 1141 return -EBUSY; 1142 1143 return dcmi_set_fmt(dcmi, f); 1144 } 1145 1146 static int dcmi_try_fmt_vid_cap(struct file *file, void *priv, 1147 struct v4l2_format *f) 1148 { 1149 struct stm32_dcmi *dcmi = video_drvdata(file); 1150 1151 return dcmi_try_fmt(dcmi, f, NULL, NULL); 1152 } 1153 1154 static int dcmi_enum_fmt_vid_cap(struct file *file, void *priv, 1155 struct v4l2_fmtdesc *f) 1156 { 1157 struct stm32_dcmi *dcmi = video_drvdata(file); 1158 1159 if (f->index >= dcmi->num_of_sd_formats) 1160 return -EINVAL; 1161 1162 f->pixelformat = dcmi->sd_formats[f->index]->fourcc; 1163 return 0; 1164 } 1165 1166 static int dcmi_get_sensor_format(struct stm32_dcmi *dcmi, 1167 struct v4l2_pix_format *pix) 1168 { 1169 struct v4l2_subdev_format fmt = { 1170 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1171 }; 1172 int ret; 1173 1174 ret = v4l2_subdev_call(dcmi->source, pad, get_fmt, NULL, &fmt); 1175 if (ret) 1176 return ret; 1177 1178 v4l2_fill_pix_format(pix, &fmt.format); 1179 1180 return 0; 1181 } 1182 1183 static int dcmi_set_sensor_format(struct stm32_dcmi *dcmi, 1184 struct v4l2_pix_format *pix) 1185 { 1186 const struct dcmi_format *sd_fmt; 1187 struct v4l2_subdev_format format = { 1188 .which = V4L2_SUBDEV_FORMAT_TRY, 1189 }; 1190 struct v4l2_subdev_pad_config pad_cfg; 1191 struct v4l2_subdev_state pad_state = { 1192 .pads = &pad_cfg 1193 }; 1194 int ret; 1195 1196 sd_fmt = find_format_by_fourcc(dcmi, pix->pixelformat); 1197 if (!sd_fmt) { 1198 if (!dcmi->num_of_sd_formats) 1199 return -ENODATA; 1200 1201 sd_fmt = dcmi->sd_formats[dcmi->num_of_sd_formats - 1]; 1202 pix->pixelformat = sd_fmt->fourcc; 1203 } 1204 1205 v4l2_fill_mbus_format(&format.format, pix, sd_fmt->mbus_code); 1206 ret = v4l2_subdev_call(dcmi->source, pad, set_fmt, 1207 &pad_state, &format); 1208 if (ret < 0) 1209 return ret; 1210 1211 return 0; 1212 } 1213 1214 static int dcmi_get_sensor_bounds(struct stm32_dcmi *dcmi, 1215 struct v4l2_rect *r) 1216 { 1217 struct v4l2_subdev_selection bounds = { 1218 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1219 .target = V4L2_SEL_TGT_CROP_BOUNDS, 1220 }; 1221 unsigned int max_width, max_height, max_pixsize; 1222 struct v4l2_pix_format pix; 1223 unsigned int i; 1224 int ret; 1225 1226 /* 1227 * Get sensor bounds first 1228 */ 1229 ret = v4l2_subdev_call(dcmi->source, pad, get_selection, 1230 NULL, &bounds); 1231 if (!ret) 1232 *r = bounds.r; 1233 if (ret != -ENOIOCTLCMD) 1234 return ret; 1235 1236 /* 1237 * If selection is not implemented, 1238 * fallback by enumerating sensor frame sizes 1239 * and take the largest one 1240 */ 1241 max_width = 0; 1242 max_height = 0; 1243 max_pixsize = 0; 1244 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) { 1245 struct dcmi_framesize *fsize = &dcmi->sd_framesizes[i]; 1246 unsigned int pixsize = fsize->width * fsize->height; 1247 1248 if (pixsize > max_pixsize) { 1249 max_pixsize = pixsize; 1250 max_width = fsize->width; 1251 max_height = fsize->height; 1252 } 1253 } 1254 if (max_pixsize > 0) { 1255 r->top = 0; 1256 r->left = 0; 1257 r->width = max_width; 1258 r->height = max_height; 1259 return 0; 1260 } 1261 1262 /* 1263 * If frame sizes enumeration is not implemented, 1264 * fallback by getting current sensor frame size 1265 */ 1266 ret = dcmi_get_sensor_format(dcmi, &pix); 1267 if (ret) 1268 return ret; 1269 1270 r->top = 0; 1271 r->left = 0; 1272 r->width = pix.width; 1273 r->height = pix.height; 1274 1275 return 0; 1276 } 1277 1278 static int dcmi_g_selection(struct file *file, void *fh, 1279 struct v4l2_selection *s) 1280 { 1281 struct stm32_dcmi *dcmi = video_drvdata(file); 1282 1283 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1284 return -EINVAL; 1285 1286 switch (s->target) { 1287 case V4L2_SEL_TGT_CROP_DEFAULT: 1288 case V4L2_SEL_TGT_CROP_BOUNDS: 1289 s->r = dcmi->sd_bounds; 1290 return 0; 1291 case V4L2_SEL_TGT_CROP: 1292 if (dcmi->do_crop) { 1293 s->r = dcmi->crop; 1294 } else { 1295 s->r.top = 0; 1296 s->r.left = 0; 1297 s->r.width = dcmi->fmt.fmt.pix.width; 1298 s->r.height = dcmi->fmt.fmt.pix.height; 1299 } 1300 break; 1301 default: 1302 return -EINVAL; 1303 } 1304 1305 return 0; 1306 } 1307 1308 static int dcmi_s_selection(struct file *file, void *priv, 1309 struct v4l2_selection *s) 1310 { 1311 struct stm32_dcmi *dcmi = video_drvdata(file); 1312 struct v4l2_rect r = s->r; 1313 struct v4l2_rect max_rect; 1314 struct v4l2_pix_format pix; 1315 1316 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE || 1317 s->target != V4L2_SEL_TGT_CROP) 1318 return -EINVAL; 1319 1320 /* Reset sensor resolution to max resolution */ 1321 pix.pixelformat = dcmi->fmt.fmt.pix.pixelformat; 1322 pix.width = dcmi->sd_bounds.width; 1323 pix.height = dcmi->sd_bounds.height; 1324 dcmi_set_sensor_format(dcmi, &pix); 1325 1326 /* 1327 * Make the intersection between 1328 * sensor resolution 1329 * and crop request 1330 */ 1331 max_rect.top = 0; 1332 max_rect.left = 0; 1333 max_rect.width = pix.width; 1334 max_rect.height = pix.height; 1335 v4l2_rect_map_inside(&r, &max_rect); 1336 r.top = clamp_t(s32, r.top, 0, pix.height - r.height); 1337 r.left = clamp_t(s32, r.left, 0, pix.width - r.width); 1338 1339 if (!(r.top == dcmi->sd_bounds.top && 1340 r.left == dcmi->sd_bounds.left && 1341 r.width == dcmi->sd_bounds.width && 1342 r.height == dcmi->sd_bounds.height)) { 1343 /* Crop if request is different than sensor resolution */ 1344 dcmi->do_crop = true; 1345 dcmi->crop = r; 1346 dev_dbg(dcmi->dev, "s_selection: crop %ux%u@(%u,%u) from %ux%u\n", 1347 r.width, r.height, r.left, r.top, 1348 pix.width, pix.height); 1349 } else { 1350 /* Disable crop */ 1351 dcmi->do_crop = false; 1352 dev_dbg(dcmi->dev, "s_selection: crop is disabled\n"); 1353 } 1354 1355 s->r = r; 1356 return 0; 1357 } 1358 1359 static int dcmi_querycap(struct file *file, void *priv, 1360 struct v4l2_capability *cap) 1361 { 1362 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); 1363 strscpy(cap->card, "STM32 Camera Memory Interface", 1364 sizeof(cap->card)); 1365 strscpy(cap->bus_info, "platform:dcmi", sizeof(cap->bus_info)); 1366 return 0; 1367 } 1368 1369 static int dcmi_enum_input(struct file *file, void *priv, 1370 struct v4l2_input *i) 1371 { 1372 if (i->index != 0) 1373 return -EINVAL; 1374 1375 i->type = V4L2_INPUT_TYPE_CAMERA; 1376 strscpy(i->name, "Camera", sizeof(i->name)); 1377 return 0; 1378 } 1379 1380 static int dcmi_g_input(struct file *file, void *priv, unsigned int *i) 1381 { 1382 *i = 0; 1383 return 0; 1384 } 1385 1386 static int dcmi_s_input(struct file *file, void *priv, unsigned int i) 1387 { 1388 if (i > 0) 1389 return -EINVAL; 1390 return 0; 1391 } 1392 1393 static int dcmi_enum_framesizes(struct file *file, void *fh, 1394 struct v4l2_frmsizeenum *fsize) 1395 { 1396 struct stm32_dcmi *dcmi = video_drvdata(file); 1397 const struct dcmi_format *sd_fmt; 1398 struct v4l2_subdev_frame_size_enum fse = { 1399 .index = fsize->index, 1400 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1401 }; 1402 int ret; 1403 1404 sd_fmt = find_format_by_fourcc(dcmi, fsize->pixel_format); 1405 if (!sd_fmt) 1406 return -EINVAL; 1407 1408 fse.code = sd_fmt->mbus_code; 1409 1410 ret = v4l2_subdev_call(dcmi->source, pad, enum_frame_size, 1411 NULL, &fse); 1412 if (ret) 1413 return ret; 1414 1415 fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; 1416 fsize->discrete.width = fse.max_width; 1417 fsize->discrete.height = fse.max_height; 1418 1419 return 0; 1420 } 1421 1422 static int dcmi_g_parm(struct file *file, void *priv, 1423 struct v4l2_streamparm *p) 1424 { 1425 struct stm32_dcmi *dcmi = video_drvdata(file); 1426 1427 return v4l2_g_parm_cap(video_devdata(file), dcmi->source, p); 1428 } 1429 1430 static int dcmi_s_parm(struct file *file, void *priv, 1431 struct v4l2_streamparm *p) 1432 { 1433 struct stm32_dcmi *dcmi = video_drvdata(file); 1434 1435 return v4l2_s_parm_cap(video_devdata(file), dcmi->source, p); 1436 } 1437 1438 static int dcmi_enum_frameintervals(struct file *file, void *fh, 1439 struct v4l2_frmivalenum *fival) 1440 { 1441 struct stm32_dcmi *dcmi = video_drvdata(file); 1442 const struct dcmi_format *sd_fmt; 1443 struct v4l2_subdev_frame_interval_enum fie = { 1444 .index = fival->index, 1445 .width = fival->width, 1446 .height = fival->height, 1447 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1448 }; 1449 int ret; 1450 1451 sd_fmt = find_format_by_fourcc(dcmi, fival->pixel_format); 1452 if (!sd_fmt) 1453 return -EINVAL; 1454 1455 fie.code = sd_fmt->mbus_code; 1456 1457 ret = v4l2_subdev_call(dcmi->source, pad, 1458 enum_frame_interval, NULL, &fie); 1459 if (ret) 1460 return ret; 1461 1462 fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; 1463 fival->discrete = fie.interval; 1464 1465 return 0; 1466 } 1467 1468 static const struct of_device_id stm32_dcmi_of_match[] = { 1469 { .compatible = "st,stm32-dcmi"}, 1470 { /* end node */ }, 1471 }; 1472 MODULE_DEVICE_TABLE(of, stm32_dcmi_of_match); 1473 1474 static int dcmi_open(struct file *file) 1475 { 1476 struct stm32_dcmi *dcmi = video_drvdata(file); 1477 struct v4l2_subdev *sd = dcmi->source; 1478 int ret; 1479 1480 if (mutex_lock_interruptible(&dcmi->lock)) 1481 return -ERESTARTSYS; 1482 1483 ret = v4l2_fh_open(file); 1484 if (ret < 0) 1485 goto unlock; 1486 1487 if (!v4l2_fh_is_singular_file(file)) 1488 goto fh_rel; 1489 1490 ret = v4l2_subdev_call(sd, core, s_power, 1); 1491 if (ret < 0 && ret != -ENOIOCTLCMD) 1492 goto fh_rel; 1493 1494 ret = dcmi_set_fmt(dcmi, &dcmi->fmt); 1495 if (ret) 1496 v4l2_subdev_call(sd, core, s_power, 0); 1497 fh_rel: 1498 if (ret) 1499 v4l2_fh_release(file); 1500 unlock: 1501 mutex_unlock(&dcmi->lock); 1502 return ret; 1503 } 1504 1505 static int dcmi_release(struct file *file) 1506 { 1507 struct stm32_dcmi *dcmi = video_drvdata(file); 1508 struct v4l2_subdev *sd = dcmi->source; 1509 bool fh_singular; 1510 int ret; 1511 1512 mutex_lock(&dcmi->lock); 1513 1514 fh_singular = v4l2_fh_is_singular_file(file); 1515 1516 ret = _vb2_fop_release(file, NULL); 1517 1518 if (fh_singular) 1519 v4l2_subdev_call(sd, core, s_power, 0); 1520 1521 mutex_unlock(&dcmi->lock); 1522 1523 return ret; 1524 } 1525 1526 static const struct v4l2_ioctl_ops dcmi_ioctl_ops = { 1527 .vidioc_querycap = dcmi_querycap, 1528 1529 .vidioc_try_fmt_vid_cap = dcmi_try_fmt_vid_cap, 1530 .vidioc_g_fmt_vid_cap = dcmi_g_fmt_vid_cap, 1531 .vidioc_s_fmt_vid_cap = dcmi_s_fmt_vid_cap, 1532 .vidioc_enum_fmt_vid_cap = dcmi_enum_fmt_vid_cap, 1533 .vidioc_g_selection = dcmi_g_selection, 1534 .vidioc_s_selection = dcmi_s_selection, 1535 1536 .vidioc_enum_input = dcmi_enum_input, 1537 .vidioc_g_input = dcmi_g_input, 1538 .vidioc_s_input = dcmi_s_input, 1539 1540 .vidioc_g_parm = dcmi_g_parm, 1541 .vidioc_s_parm = dcmi_s_parm, 1542 1543 .vidioc_enum_framesizes = dcmi_enum_framesizes, 1544 .vidioc_enum_frameintervals = dcmi_enum_frameintervals, 1545 1546 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1547 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1548 .vidioc_querybuf = vb2_ioctl_querybuf, 1549 .vidioc_qbuf = vb2_ioctl_qbuf, 1550 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1551 .vidioc_expbuf = vb2_ioctl_expbuf, 1552 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1553 .vidioc_streamon = vb2_ioctl_streamon, 1554 .vidioc_streamoff = vb2_ioctl_streamoff, 1555 1556 .vidioc_log_status = v4l2_ctrl_log_status, 1557 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1558 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1559 }; 1560 1561 static const struct v4l2_file_operations dcmi_fops = { 1562 .owner = THIS_MODULE, 1563 .unlocked_ioctl = video_ioctl2, 1564 .open = dcmi_open, 1565 .release = dcmi_release, 1566 .poll = vb2_fop_poll, 1567 .mmap = vb2_fop_mmap, 1568 #ifndef CONFIG_MMU 1569 .get_unmapped_area = vb2_fop_get_unmapped_area, 1570 #endif 1571 .read = vb2_fop_read, 1572 }; 1573 1574 static int dcmi_set_default_fmt(struct stm32_dcmi *dcmi) 1575 { 1576 struct v4l2_format f = { 1577 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, 1578 .fmt.pix = { 1579 .width = CIF_WIDTH, 1580 .height = CIF_HEIGHT, 1581 .field = V4L2_FIELD_NONE, 1582 .pixelformat = dcmi->sd_formats[0]->fourcc, 1583 }, 1584 }; 1585 int ret; 1586 1587 ret = dcmi_try_fmt(dcmi, &f, NULL, NULL); 1588 if (ret) 1589 return ret; 1590 dcmi->sd_format = dcmi->sd_formats[0]; 1591 dcmi->fmt = f; 1592 return 0; 1593 } 1594 1595 /* 1596 * FIXME: For the time being we only support subdevices 1597 * which expose RGB & YUV "parallel form" mbus code (_2X8). 1598 * Nevertheless, this allows to support serial source subdevices 1599 * and serial to parallel bridges which conform to this. 1600 */ 1601 static const struct dcmi_format dcmi_formats[] = { 1602 { 1603 .fourcc = V4L2_PIX_FMT_RGB565, 1604 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE, 1605 .bpp = 2, 1606 }, { 1607 .fourcc = V4L2_PIX_FMT_YUYV, 1608 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 1609 .bpp = 2, 1610 }, { 1611 .fourcc = V4L2_PIX_FMT_UYVY, 1612 .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, 1613 .bpp = 2, 1614 }, { 1615 .fourcc = V4L2_PIX_FMT_JPEG, 1616 .mbus_code = MEDIA_BUS_FMT_JPEG_1X8, 1617 .bpp = 1, 1618 }, { 1619 .fourcc = V4L2_PIX_FMT_SBGGR8, 1620 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 1621 .bpp = 1, 1622 }, { 1623 .fourcc = V4L2_PIX_FMT_SGBRG8, 1624 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, 1625 .bpp = 1, 1626 }, { 1627 .fourcc = V4L2_PIX_FMT_SGRBG8, 1628 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, 1629 .bpp = 1, 1630 }, { 1631 .fourcc = V4L2_PIX_FMT_SRGGB8, 1632 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, 1633 .bpp = 1, 1634 }, 1635 }; 1636 1637 static int dcmi_formats_init(struct stm32_dcmi *dcmi) 1638 { 1639 const struct dcmi_format *sd_fmts[ARRAY_SIZE(dcmi_formats)]; 1640 unsigned int num_fmts = 0, i, j; 1641 struct v4l2_subdev *subdev = dcmi->source; 1642 struct v4l2_subdev_mbus_code_enum mbus_code = { 1643 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1644 }; 1645 1646 while (!v4l2_subdev_call(subdev, pad, enum_mbus_code, 1647 NULL, &mbus_code)) { 1648 for (i = 0; i < ARRAY_SIZE(dcmi_formats); i++) { 1649 if (dcmi_formats[i].mbus_code != mbus_code.code) 1650 continue; 1651 1652 /* Exclude JPEG if BT656 bus is selected */ 1653 if (dcmi_formats[i].fourcc == V4L2_PIX_FMT_JPEG && 1654 dcmi->bus_type == V4L2_MBUS_BT656) 1655 continue; 1656 1657 /* Code supported, have we got this fourcc yet? */ 1658 for (j = 0; j < num_fmts; j++) 1659 if (sd_fmts[j]->fourcc == 1660 dcmi_formats[i].fourcc) { 1661 /* Already available */ 1662 dev_dbg(dcmi->dev, "Skipping fourcc/code: %4.4s/0x%x\n", 1663 (char *)&sd_fmts[j]->fourcc, 1664 mbus_code.code); 1665 break; 1666 } 1667 if (j == num_fmts) { 1668 /* New */ 1669 sd_fmts[num_fmts++] = dcmi_formats + i; 1670 dev_dbg(dcmi->dev, "Supported fourcc/code: %4.4s/0x%x\n", 1671 (char *)&sd_fmts[num_fmts - 1]->fourcc, 1672 sd_fmts[num_fmts - 1]->mbus_code); 1673 } 1674 } 1675 mbus_code.index++; 1676 } 1677 1678 if (!num_fmts) 1679 return -ENXIO; 1680 1681 dcmi->num_of_sd_formats = num_fmts; 1682 dcmi->sd_formats = devm_kcalloc(dcmi->dev, 1683 num_fmts, sizeof(struct dcmi_format *), 1684 GFP_KERNEL); 1685 if (!dcmi->sd_formats) { 1686 dev_err(dcmi->dev, "Could not allocate memory\n"); 1687 return -ENOMEM; 1688 } 1689 1690 memcpy(dcmi->sd_formats, sd_fmts, 1691 num_fmts * sizeof(struct dcmi_format *)); 1692 dcmi->sd_format = dcmi->sd_formats[0]; 1693 1694 return 0; 1695 } 1696 1697 static int dcmi_framesizes_init(struct stm32_dcmi *dcmi) 1698 { 1699 unsigned int num_fsize = 0; 1700 struct v4l2_subdev *subdev = dcmi->source; 1701 struct v4l2_subdev_frame_size_enum fse = { 1702 .which = V4L2_SUBDEV_FORMAT_ACTIVE, 1703 .code = dcmi->sd_format->mbus_code, 1704 }; 1705 unsigned int ret; 1706 unsigned int i; 1707 1708 /* Allocate discrete framesizes array */ 1709 while (!v4l2_subdev_call(subdev, pad, enum_frame_size, 1710 NULL, &fse)) 1711 fse.index++; 1712 1713 num_fsize = fse.index; 1714 if (!num_fsize) 1715 return 0; 1716 1717 dcmi->num_of_sd_framesizes = num_fsize; 1718 dcmi->sd_framesizes = devm_kcalloc(dcmi->dev, num_fsize, 1719 sizeof(struct dcmi_framesize), 1720 GFP_KERNEL); 1721 if (!dcmi->sd_framesizes) { 1722 dev_err(dcmi->dev, "Could not allocate memory\n"); 1723 return -ENOMEM; 1724 } 1725 1726 /* Fill array with sensor supported framesizes */ 1727 dev_dbg(dcmi->dev, "Sensor supports %u frame sizes:\n", num_fsize); 1728 for (i = 0; i < dcmi->num_of_sd_framesizes; i++) { 1729 fse.index = i; 1730 ret = v4l2_subdev_call(subdev, pad, enum_frame_size, 1731 NULL, &fse); 1732 if (ret) 1733 return ret; 1734 dcmi->sd_framesizes[fse.index].width = fse.max_width; 1735 dcmi->sd_framesizes[fse.index].height = fse.max_height; 1736 dev_dbg(dcmi->dev, "%ux%u\n", fse.max_width, fse.max_height); 1737 } 1738 1739 return 0; 1740 } 1741 1742 static int dcmi_graph_notify_complete(struct v4l2_async_notifier *notifier) 1743 { 1744 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier); 1745 int ret; 1746 1747 /* 1748 * Now that the graph is complete, 1749 * we search for the source subdevice 1750 * in order to expose it through V4L2 interface 1751 */ 1752 dcmi->source = media_entity_to_v4l2_subdev(dcmi_find_source(dcmi)); 1753 if (!dcmi->source) { 1754 dev_err(dcmi->dev, "Source subdevice not found\n"); 1755 return -ENODEV; 1756 } 1757 1758 dcmi->vdev->ctrl_handler = dcmi->source->ctrl_handler; 1759 1760 ret = dcmi_formats_init(dcmi); 1761 if (ret) { 1762 dev_err(dcmi->dev, "No supported mediabus format found\n"); 1763 return ret; 1764 } 1765 1766 ret = dcmi_framesizes_init(dcmi); 1767 if (ret) { 1768 dev_err(dcmi->dev, "Could not initialize framesizes\n"); 1769 return ret; 1770 } 1771 1772 ret = dcmi_get_sensor_bounds(dcmi, &dcmi->sd_bounds); 1773 if (ret) { 1774 dev_err(dcmi->dev, "Could not get sensor bounds\n"); 1775 return ret; 1776 } 1777 1778 ret = dcmi_set_default_fmt(dcmi); 1779 if (ret) { 1780 dev_err(dcmi->dev, "Could not set default format\n"); 1781 return ret; 1782 } 1783 1784 ret = devm_request_threaded_irq(dcmi->dev, dcmi->irq, dcmi_irq_callback, 1785 dcmi_irq_thread, IRQF_ONESHOT, 1786 dev_name(dcmi->dev), dcmi); 1787 if (ret) { 1788 dev_err(dcmi->dev, "Unable to request irq %d\n", dcmi->irq); 1789 return ret; 1790 } 1791 1792 return 0; 1793 } 1794 1795 static void dcmi_graph_notify_unbind(struct v4l2_async_notifier *notifier, 1796 struct v4l2_subdev *sd, 1797 struct v4l2_async_subdev *asd) 1798 { 1799 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier); 1800 1801 dev_dbg(dcmi->dev, "Removing %s\n", video_device_node_name(dcmi->vdev)); 1802 1803 /* Checks internally if vdev has been init or not */ 1804 video_unregister_device(dcmi->vdev); 1805 } 1806 1807 static int dcmi_graph_notify_bound(struct v4l2_async_notifier *notifier, 1808 struct v4l2_subdev *subdev, 1809 struct v4l2_async_subdev *asd) 1810 { 1811 struct stm32_dcmi *dcmi = notifier_to_dcmi(notifier); 1812 unsigned int ret; 1813 int src_pad; 1814 1815 dev_dbg(dcmi->dev, "Subdev \"%s\" bound\n", subdev->name); 1816 1817 /* 1818 * Link this sub-device to DCMI, it could be 1819 * a parallel camera sensor or a bridge 1820 */ 1821 src_pad = media_entity_get_fwnode_pad(&subdev->entity, 1822 subdev->fwnode, 1823 MEDIA_PAD_FL_SOURCE); 1824 1825 ret = media_create_pad_link(&subdev->entity, src_pad, 1826 &dcmi->vdev->entity, 0, 1827 MEDIA_LNK_FL_IMMUTABLE | 1828 MEDIA_LNK_FL_ENABLED); 1829 if (ret) 1830 dev_err(dcmi->dev, "Failed to create media pad link with subdev \"%s\"\n", 1831 subdev->name); 1832 else 1833 dev_dbg(dcmi->dev, "DCMI is now linked to \"%s\"\n", 1834 subdev->name); 1835 1836 return ret; 1837 } 1838 1839 static const struct v4l2_async_notifier_operations dcmi_graph_notify_ops = { 1840 .bound = dcmi_graph_notify_bound, 1841 .unbind = dcmi_graph_notify_unbind, 1842 .complete = dcmi_graph_notify_complete, 1843 }; 1844 1845 static int dcmi_graph_init(struct stm32_dcmi *dcmi) 1846 { 1847 struct v4l2_async_subdev *asd; 1848 struct device_node *ep; 1849 int ret; 1850 1851 ep = of_graph_get_next_endpoint(dcmi->dev->of_node, NULL); 1852 if (!ep) { 1853 dev_err(dcmi->dev, "Failed to get next endpoint\n"); 1854 return -EINVAL; 1855 } 1856 1857 v4l2_async_nf_init(&dcmi->notifier); 1858 1859 asd = v4l2_async_nf_add_fwnode_remote(&dcmi->notifier, 1860 of_fwnode_handle(ep), 1861 struct v4l2_async_subdev); 1862 1863 of_node_put(ep); 1864 1865 if (IS_ERR(asd)) { 1866 dev_err(dcmi->dev, "Failed to add subdev notifier\n"); 1867 return PTR_ERR(asd); 1868 } 1869 1870 dcmi->notifier.ops = &dcmi_graph_notify_ops; 1871 1872 ret = v4l2_async_nf_register(&dcmi->v4l2_dev, &dcmi->notifier); 1873 if (ret < 0) { 1874 dev_err(dcmi->dev, "Failed to register notifier\n"); 1875 v4l2_async_nf_cleanup(&dcmi->notifier); 1876 return ret; 1877 } 1878 1879 return 0; 1880 } 1881 1882 static int dcmi_probe(struct platform_device *pdev) 1883 { 1884 struct device_node *np = pdev->dev.of_node; 1885 const struct of_device_id *match = NULL; 1886 struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; 1887 struct stm32_dcmi *dcmi; 1888 struct vb2_queue *q; 1889 struct dma_chan *chan; 1890 struct dma_slave_caps caps; 1891 struct clk *mclk; 1892 int irq; 1893 int ret = 0; 1894 1895 match = of_match_device(of_match_ptr(stm32_dcmi_of_match), &pdev->dev); 1896 if (!match) { 1897 dev_err(&pdev->dev, "Could not find a match in devicetree\n"); 1898 return -ENODEV; 1899 } 1900 1901 dcmi = devm_kzalloc(&pdev->dev, sizeof(struct stm32_dcmi), GFP_KERNEL); 1902 if (!dcmi) 1903 return -ENOMEM; 1904 1905 dcmi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1906 if (IS_ERR(dcmi->rstc)) { 1907 if (PTR_ERR(dcmi->rstc) != -EPROBE_DEFER) 1908 dev_err(&pdev->dev, "Could not get reset control\n"); 1909 1910 return PTR_ERR(dcmi->rstc); 1911 } 1912 1913 /* Get bus characteristics from devicetree */ 1914 np = of_graph_get_next_endpoint(np, NULL); 1915 if (!np) { 1916 dev_err(&pdev->dev, "Could not find the endpoint\n"); 1917 return -ENODEV; 1918 } 1919 1920 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &ep); 1921 of_node_put(np); 1922 if (ret) { 1923 dev_err(&pdev->dev, "Could not parse the endpoint\n"); 1924 return ret; 1925 } 1926 1927 if (ep.bus_type == V4L2_MBUS_CSI2_DPHY) { 1928 dev_err(&pdev->dev, "CSI bus not supported\n"); 1929 return -ENODEV; 1930 } 1931 1932 if (ep.bus_type == V4L2_MBUS_BT656 && 1933 ep.bus.parallel.bus_width != 8) { 1934 dev_err(&pdev->dev, "BT656 bus conflicts with %u bits bus width (8 bits required)\n", 1935 ep.bus.parallel.bus_width); 1936 return -ENODEV; 1937 } 1938 1939 dcmi->bus.flags = ep.bus.parallel.flags; 1940 dcmi->bus.bus_width = ep.bus.parallel.bus_width; 1941 dcmi->bus.data_shift = ep.bus.parallel.data_shift; 1942 dcmi->bus_type = ep.bus_type; 1943 1944 irq = platform_get_irq(pdev, 0); 1945 if (irq <= 0) 1946 return irq ? irq : -ENXIO; 1947 1948 dcmi->irq = irq; 1949 1950 dcmi->res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1951 if (!dcmi->res) { 1952 dev_err(&pdev->dev, "Could not get resource\n"); 1953 return -ENODEV; 1954 } 1955 1956 dcmi->regs = devm_ioremap_resource(&pdev->dev, dcmi->res); 1957 if (IS_ERR(dcmi->regs)) { 1958 dev_err(&pdev->dev, "Could not map registers\n"); 1959 return PTR_ERR(dcmi->regs); 1960 } 1961 1962 mclk = devm_clk_get(&pdev->dev, "mclk"); 1963 if (IS_ERR(mclk)) { 1964 if (PTR_ERR(mclk) != -EPROBE_DEFER) 1965 dev_err(&pdev->dev, "Unable to get mclk\n"); 1966 return PTR_ERR(mclk); 1967 } 1968 1969 chan = dma_request_chan(&pdev->dev, "tx"); 1970 if (IS_ERR(chan)) { 1971 ret = PTR_ERR(chan); 1972 if (ret != -EPROBE_DEFER) 1973 dev_err(&pdev->dev, 1974 "Failed to request DMA channel: %d\n", ret); 1975 return ret; 1976 } 1977 1978 dcmi->dma_max_burst = UINT_MAX; 1979 ret = dma_get_slave_caps(chan, &caps); 1980 if (!ret && caps.max_sg_burst) 1981 dcmi->dma_max_burst = caps.max_sg_burst * DMA_SLAVE_BUSWIDTH_4_BYTES; 1982 1983 spin_lock_init(&dcmi->irqlock); 1984 mutex_init(&dcmi->lock); 1985 mutex_init(&dcmi->dma_lock); 1986 init_completion(&dcmi->complete); 1987 INIT_LIST_HEAD(&dcmi->buffers); 1988 1989 dcmi->dev = &pdev->dev; 1990 dcmi->mclk = mclk; 1991 dcmi->state = STOPPED; 1992 dcmi->dma_chan = chan; 1993 1994 q = &dcmi->queue; 1995 1996 dcmi->v4l2_dev.mdev = &dcmi->mdev; 1997 1998 /* Initialize media device */ 1999 strscpy(dcmi->mdev.model, DRV_NAME, sizeof(dcmi->mdev.model)); 2000 dcmi->mdev.dev = &pdev->dev; 2001 media_device_init(&dcmi->mdev); 2002 2003 /* Initialize the top-level structure */ 2004 ret = v4l2_device_register(&pdev->dev, &dcmi->v4l2_dev); 2005 if (ret) 2006 goto err_media_device_cleanup; 2007 2008 dcmi->vdev = video_device_alloc(); 2009 if (!dcmi->vdev) { 2010 ret = -ENOMEM; 2011 goto err_device_unregister; 2012 } 2013 2014 /* Video node */ 2015 dcmi->vdev->fops = &dcmi_fops; 2016 dcmi->vdev->v4l2_dev = &dcmi->v4l2_dev; 2017 dcmi->vdev->queue = &dcmi->queue; 2018 strscpy(dcmi->vdev->name, KBUILD_MODNAME, sizeof(dcmi->vdev->name)); 2019 dcmi->vdev->release = video_device_release; 2020 dcmi->vdev->ioctl_ops = &dcmi_ioctl_ops; 2021 dcmi->vdev->lock = &dcmi->lock; 2022 dcmi->vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING | 2023 V4L2_CAP_READWRITE; 2024 video_set_drvdata(dcmi->vdev, dcmi); 2025 2026 /* Media entity pads */ 2027 dcmi->vid_cap_pad.flags = MEDIA_PAD_FL_SINK; 2028 ret = media_entity_pads_init(&dcmi->vdev->entity, 2029 1, &dcmi->vid_cap_pad); 2030 if (ret) { 2031 dev_err(dcmi->dev, "Failed to init media entity pad\n"); 2032 goto err_device_release; 2033 } 2034 dcmi->vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT; 2035 2036 ret = video_register_device(dcmi->vdev, VFL_TYPE_VIDEO, -1); 2037 if (ret) { 2038 dev_err(dcmi->dev, "Failed to register video device\n"); 2039 goto err_media_entity_cleanup; 2040 } 2041 2042 dev_dbg(dcmi->dev, "Device registered as %s\n", 2043 video_device_node_name(dcmi->vdev)); 2044 2045 /* Buffer queue */ 2046 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 2047 q->io_modes = VB2_MMAP | VB2_READ | VB2_DMABUF; 2048 q->lock = &dcmi->lock; 2049 q->drv_priv = dcmi; 2050 q->buf_struct_size = sizeof(struct dcmi_buf); 2051 q->ops = &dcmi_video_qops; 2052 q->mem_ops = &vb2_dma_contig_memops; 2053 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 2054 q->min_buffers_needed = 2; 2055 q->dev = &pdev->dev; 2056 2057 ret = vb2_queue_init(q); 2058 if (ret < 0) { 2059 dev_err(&pdev->dev, "Failed to initialize vb2 queue\n"); 2060 goto err_media_entity_cleanup; 2061 } 2062 2063 ret = dcmi_graph_init(dcmi); 2064 if (ret < 0) 2065 goto err_media_entity_cleanup; 2066 2067 /* Reset device */ 2068 ret = reset_control_assert(dcmi->rstc); 2069 if (ret) { 2070 dev_err(&pdev->dev, "Failed to assert the reset line\n"); 2071 goto err_cleanup; 2072 } 2073 2074 usleep_range(3000, 5000); 2075 2076 ret = reset_control_deassert(dcmi->rstc); 2077 if (ret) { 2078 dev_err(&pdev->dev, "Failed to deassert the reset line\n"); 2079 goto err_cleanup; 2080 } 2081 2082 dev_info(&pdev->dev, "Probe done\n"); 2083 2084 platform_set_drvdata(pdev, dcmi); 2085 2086 pm_runtime_enable(&pdev->dev); 2087 2088 return 0; 2089 2090 err_cleanup: 2091 v4l2_async_nf_cleanup(&dcmi->notifier); 2092 err_media_entity_cleanup: 2093 media_entity_cleanup(&dcmi->vdev->entity); 2094 err_device_release: 2095 video_device_release(dcmi->vdev); 2096 err_device_unregister: 2097 v4l2_device_unregister(&dcmi->v4l2_dev); 2098 err_media_device_cleanup: 2099 media_device_cleanup(&dcmi->mdev); 2100 dma_release_channel(dcmi->dma_chan); 2101 2102 return ret; 2103 } 2104 2105 static int dcmi_remove(struct platform_device *pdev) 2106 { 2107 struct stm32_dcmi *dcmi = platform_get_drvdata(pdev); 2108 2109 pm_runtime_disable(&pdev->dev); 2110 2111 v4l2_async_nf_unregister(&dcmi->notifier); 2112 v4l2_async_nf_cleanup(&dcmi->notifier); 2113 media_entity_cleanup(&dcmi->vdev->entity); 2114 v4l2_device_unregister(&dcmi->v4l2_dev); 2115 media_device_cleanup(&dcmi->mdev); 2116 2117 dma_release_channel(dcmi->dma_chan); 2118 2119 return 0; 2120 } 2121 2122 static __maybe_unused int dcmi_runtime_suspend(struct device *dev) 2123 { 2124 struct stm32_dcmi *dcmi = dev_get_drvdata(dev); 2125 2126 clk_disable_unprepare(dcmi->mclk); 2127 2128 return 0; 2129 } 2130 2131 static __maybe_unused int dcmi_runtime_resume(struct device *dev) 2132 { 2133 struct stm32_dcmi *dcmi = dev_get_drvdata(dev); 2134 int ret; 2135 2136 ret = clk_prepare_enable(dcmi->mclk); 2137 if (ret) 2138 dev_err(dev, "%s: Failed to prepare_enable clock\n", __func__); 2139 2140 return ret; 2141 } 2142 2143 static __maybe_unused int dcmi_suspend(struct device *dev) 2144 { 2145 /* disable clock */ 2146 pm_runtime_force_suspend(dev); 2147 2148 /* change pinctrl state */ 2149 pinctrl_pm_select_sleep_state(dev); 2150 2151 return 0; 2152 } 2153 2154 static __maybe_unused int dcmi_resume(struct device *dev) 2155 { 2156 /* restore pinctl default state */ 2157 pinctrl_pm_select_default_state(dev); 2158 2159 /* clock enable */ 2160 pm_runtime_force_resume(dev); 2161 2162 return 0; 2163 } 2164 2165 static const struct dev_pm_ops dcmi_pm_ops = { 2166 SET_SYSTEM_SLEEP_PM_OPS(dcmi_suspend, dcmi_resume) 2167 SET_RUNTIME_PM_OPS(dcmi_runtime_suspend, 2168 dcmi_runtime_resume, NULL) 2169 }; 2170 2171 static struct platform_driver stm32_dcmi_driver = { 2172 .probe = dcmi_probe, 2173 .remove = dcmi_remove, 2174 .driver = { 2175 .name = DRV_NAME, 2176 .of_match_table = of_match_ptr(stm32_dcmi_of_match), 2177 .pm = &dcmi_pm_ops, 2178 }, 2179 }; 2180 2181 module_platform_driver(stm32_dcmi_driver); 2182 2183 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 2184 MODULE_AUTHOR("Hugues Fruchet <hugues.fruchet@st.com>"); 2185 MODULE_DESCRIPTION("STMicroelectronics STM32 Digital Camera Memory Interface driver"); 2186 MODULE_LICENSE("GPL"); 2187