1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * c8sectpfe-core.c - C8SECTPFE STi DVB driver 4 * 5 * Copyright (c) STMicroelectronics 2015 6 * 7 * Author:Peter Bennett <peter.bennett@st.com> 8 * Peter Griffin <peter.griffin@linaro.org> 9 * 10 */ 11 #include <linux/atomic.h> 12 #include <linux/clk.h> 13 #include <linux/completion.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dvb/dmx.h> 18 #include <linux/dvb/frontend.h> 19 #include <linux/errno.h> 20 #include <linux/firmware.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/module.h> 25 #include <linux/of_gpio.h> 26 #include <linux/of_platform.h> 27 #include <linux/platform_device.h> 28 #include <linux/usb.h> 29 #include <linux/slab.h> 30 #include <linux/time.h> 31 #include <linux/wait.h> 32 #include <linux/pinctrl/pinctrl.h> 33 34 #include "c8sectpfe-core.h" 35 #include "c8sectpfe-common.h" 36 #include "c8sectpfe-debugfs.h" 37 #include <media/dmxdev.h> 38 #include <media/dvb_demux.h> 39 #include <media/dvb_frontend.h> 40 #include <media/dvb_net.h> 41 42 #define FIRMWARE_MEMDMA "pti_memdma_h407.elf" 43 MODULE_FIRMWARE(FIRMWARE_MEMDMA); 44 45 #define PID_TABLE_SIZE 1024 46 #define POLL_MSECS 50 47 48 static int load_c8sectpfe_fw(struct c8sectpfei *fei); 49 50 #define TS_PKT_SIZE 188 51 #define HEADER_SIZE (4) 52 #define PACKET_SIZE (TS_PKT_SIZE+HEADER_SIZE) 53 54 #define FEI_ALIGNMENT (32) 55 /* hw requires minimum of 8*PACKET_SIZE and padded to 8byte boundary */ 56 #define FEI_BUFFER_SIZE (8*PACKET_SIZE*340) 57 58 #define FIFO_LEN 1024 59 60 static void c8sectpfe_timer_interrupt(struct timer_list *t) 61 { 62 struct c8sectpfei *fei = from_timer(fei, t, timer); 63 struct channel_info *channel; 64 int chan_num; 65 66 /* iterate through input block channels */ 67 for (chan_num = 0; chan_num < fei->tsin_count; chan_num++) { 68 channel = fei->channel_data[chan_num]; 69 70 /* is this descriptor initialised and TP enabled */ 71 if (channel->irec && readl(channel->irec + DMA_PRDS_TPENABLE)) 72 tasklet_schedule(&channel->tsklet); 73 } 74 75 fei->timer.expires = jiffies + msecs_to_jiffies(POLL_MSECS); 76 add_timer(&fei->timer); 77 } 78 79 static void channel_swdemux_tsklet(struct tasklet_struct *t) 80 { 81 struct channel_info *channel = from_tasklet(channel, t, tsklet); 82 struct c8sectpfei *fei; 83 unsigned long wp, rp; 84 int pos, num_packets, n, size; 85 u8 *buf; 86 87 if (unlikely(!channel || !channel->irec)) 88 return; 89 90 fei = channel->fei; 91 92 wp = readl(channel->irec + DMA_PRDS_BUSWP_TP(0)); 93 rp = readl(channel->irec + DMA_PRDS_BUSRP_TP(0)); 94 95 pos = rp - channel->back_buffer_busaddr; 96 97 /* has it wrapped */ 98 if (wp < rp) 99 wp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE; 100 101 size = wp - rp; 102 num_packets = size / PACKET_SIZE; 103 104 /* manage cache so data is visible to CPU */ 105 dma_sync_single_for_cpu(fei->dev, 106 rp, 107 size, 108 DMA_FROM_DEVICE); 109 110 buf = channel->back_buffer_aligned; 111 112 dev_dbg(fei->dev, 113 "chan=%d channel=%p num_packets = %d, buf = %p, pos = 0x%x\n\trp=0x%lx, wp=0x%lx\n", 114 channel->tsin_id, channel, num_packets, buf, pos, rp, wp); 115 116 for (n = 0; n < num_packets; n++) { 117 dvb_dmx_swfilter_packets( 118 &fei->c8sectpfe[0]-> 119 demux[channel->demux_mapping].dvb_demux, 120 &buf[pos], 1); 121 122 pos += PACKET_SIZE; 123 } 124 125 /* advance the read pointer */ 126 if (wp == (channel->back_buffer_busaddr + FEI_BUFFER_SIZE)) 127 writel(channel->back_buffer_busaddr, channel->irec + 128 DMA_PRDS_BUSRP_TP(0)); 129 else 130 writel(wp, channel->irec + DMA_PRDS_BUSRP_TP(0)); 131 } 132 133 static int c8sectpfe_start_feed(struct dvb_demux_feed *dvbdmxfeed) 134 { 135 struct dvb_demux *demux = dvbdmxfeed->demux; 136 struct stdemux *stdemux = (struct stdemux *)demux->priv; 137 struct c8sectpfei *fei = stdemux->c8sectpfei; 138 struct channel_info *channel; 139 u32 tmp; 140 unsigned long *bitmap; 141 int ret; 142 143 switch (dvbdmxfeed->type) { 144 case DMX_TYPE_TS: 145 break; 146 case DMX_TYPE_SEC: 147 break; 148 default: 149 dev_err(fei->dev, "%s:%d Error bailing\n" 150 , __func__, __LINE__); 151 return -EINVAL; 152 } 153 154 if (dvbdmxfeed->type == DMX_TYPE_TS) { 155 switch (dvbdmxfeed->pes_type) { 156 case DMX_PES_VIDEO: 157 case DMX_PES_AUDIO: 158 case DMX_PES_TELETEXT: 159 case DMX_PES_PCR: 160 case DMX_PES_OTHER: 161 break; 162 default: 163 dev_err(fei->dev, "%s:%d Error bailing\n" 164 , __func__, __LINE__); 165 return -EINVAL; 166 } 167 } 168 169 if (!atomic_read(&fei->fw_loaded)) { 170 ret = load_c8sectpfe_fw(fei); 171 if (ret) 172 return ret; 173 } 174 175 mutex_lock(&fei->lock); 176 177 channel = fei->channel_data[stdemux->tsin_index]; 178 179 bitmap = channel->pid_buffer_aligned; 180 181 /* 8192 is a special PID */ 182 if (dvbdmxfeed->pid == 8192) { 183 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); 184 tmp &= ~C8SECTPFE_PID_ENABLE; 185 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); 186 187 } else { 188 bitmap_set(bitmap, dvbdmxfeed->pid, 1); 189 } 190 191 /* manage cache so PID bitmap is visible to HW */ 192 dma_sync_single_for_device(fei->dev, 193 channel->pid_buffer_busaddr, 194 PID_TABLE_SIZE, 195 DMA_TO_DEVICE); 196 197 channel->active = 1; 198 199 if (fei->global_feed_count == 0) { 200 fei->timer.expires = jiffies + 201 msecs_to_jiffies(msecs_to_jiffies(POLL_MSECS)); 202 203 add_timer(&fei->timer); 204 } 205 206 if (stdemux->running_feed_count == 0) { 207 208 dev_dbg(fei->dev, "Starting channel=%p\n", channel); 209 210 tasklet_setup(&channel->tsklet, channel_swdemux_tsklet); 211 212 /* Reset the internal inputblock sram pointers */ 213 writel(channel->fifo, 214 fei->io + C8SECTPFE_IB_BUFF_STRT(channel->tsin_id)); 215 writel(channel->fifo + FIFO_LEN - 1, 216 fei->io + C8SECTPFE_IB_BUFF_END(channel->tsin_id)); 217 218 writel(channel->fifo, 219 fei->io + C8SECTPFE_IB_READ_PNT(channel->tsin_id)); 220 writel(channel->fifo, 221 fei->io + C8SECTPFE_IB_WRT_PNT(channel->tsin_id)); 222 223 224 /* reset read / write memdma ptrs for this channel */ 225 writel(channel->back_buffer_busaddr, channel->irec + 226 DMA_PRDS_BUSBASE_TP(0)); 227 228 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1; 229 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0)); 230 231 writel(channel->back_buffer_busaddr, channel->irec + 232 DMA_PRDS_BUSWP_TP(0)); 233 234 /* Issue a reset and enable InputBlock */ 235 writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET 236 , fei->io + C8SECTPFE_IB_SYS(channel->tsin_id)); 237 238 /* and enable the tp */ 239 writel(0x1, channel->irec + DMA_PRDS_TPENABLE); 240 241 dev_dbg(fei->dev, "%s:%d Starting DMA feed on stdemux=%p\n" 242 , __func__, __LINE__, stdemux); 243 } 244 245 stdemux->running_feed_count++; 246 fei->global_feed_count++; 247 248 mutex_unlock(&fei->lock); 249 250 return 0; 251 } 252 253 static int c8sectpfe_stop_feed(struct dvb_demux_feed *dvbdmxfeed) 254 { 255 256 struct dvb_demux *demux = dvbdmxfeed->demux; 257 struct stdemux *stdemux = (struct stdemux *)demux->priv; 258 struct c8sectpfei *fei = stdemux->c8sectpfei; 259 struct channel_info *channel; 260 int idlereq; 261 u32 tmp; 262 int ret; 263 unsigned long *bitmap; 264 265 if (!atomic_read(&fei->fw_loaded)) { 266 ret = load_c8sectpfe_fw(fei); 267 if (ret) 268 return ret; 269 } 270 271 mutex_lock(&fei->lock); 272 273 channel = fei->channel_data[stdemux->tsin_index]; 274 275 bitmap = channel->pid_buffer_aligned; 276 277 if (dvbdmxfeed->pid == 8192) { 278 tmp = readl(fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); 279 tmp |= C8SECTPFE_PID_ENABLE; 280 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); 281 } else { 282 bitmap_clear(bitmap, dvbdmxfeed->pid, 1); 283 } 284 285 /* manage cache so data is visible to HW */ 286 dma_sync_single_for_device(fei->dev, 287 channel->pid_buffer_busaddr, 288 PID_TABLE_SIZE, 289 DMA_TO_DEVICE); 290 291 if (--stdemux->running_feed_count == 0) { 292 293 channel = fei->channel_data[stdemux->tsin_index]; 294 295 /* TP re-configuration on page 168 of functional spec */ 296 297 /* disable IB (prevents more TS data going to memdma) */ 298 writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id)); 299 300 /* disable this channels descriptor */ 301 writel(0, channel->irec + DMA_PRDS_TPENABLE); 302 303 tasklet_disable(&channel->tsklet); 304 305 /* now request memdma channel goes idle */ 306 idlereq = (1 << channel->tsin_id) | IDLEREQ; 307 writel(idlereq, fei->io + DMA_IDLE_REQ); 308 309 /* wait for idle irq handler to signal completion */ 310 ret = wait_for_completion_timeout(&channel->idle_completion, 311 msecs_to_jiffies(100)); 312 313 if (ret == 0) 314 dev_warn(fei->dev, 315 "Timeout waiting for idle irq on tsin%d\n", 316 channel->tsin_id); 317 318 reinit_completion(&channel->idle_completion); 319 320 /* reset read / write ptrs for this channel */ 321 322 writel(channel->back_buffer_busaddr, 323 channel->irec + DMA_PRDS_BUSBASE_TP(0)); 324 325 tmp = channel->back_buffer_busaddr + FEI_BUFFER_SIZE - 1; 326 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0)); 327 328 writel(channel->back_buffer_busaddr, 329 channel->irec + DMA_PRDS_BUSWP_TP(0)); 330 331 dev_dbg(fei->dev, 332 "%s:%d stopping DMA feed on stdemux=%p channel=%d\n", 333 __func__, __LINE__, stdemux, channel->tsin_id); 334 335 /* turn off all PIDS in the bitmap */ 336 memset(channel->pid_buffer_aligned, 0, PID_TABLE_SIZE); 337 338 /* manage cache so data is visible to HW */ 339 dma_sync_single_for_device(fei->dev, 340 channel->pid_buffer_busaddr, 341 PID_TABLE_SIZE, 342 DMA_TO_DEVICE); 343 344 channel->active = 0; 345 } 346 347 if (--fei->global_feed_count == 0) { 348 dev_dbg(fei->dev, "%s:%d global_feed_count=%d\n" 349 , __func__, __LINE__, fei->global_feed_count); 350 351 del_timer(&fei->timer); 352 } 353 354 mutex_unlock(&fei->lock); 355 356 return 0; 357 } 358 359 static struct channel_info *find_channel(struct c8sectpfei *fei, int tsin_num) 360 { 361 int i; 362 363 for (i = 0; i < C8SECTPFE_MAX_TSIN_CHAN; i++) { 364 if (!fei->channel_data[i]) 365 continue; 366 367 if (fei->channel_data[i]->tsin_id == tsin_num) 368 return fei->channel_data[i]; 369 } 370 371 return NULL; 372 } 373 374 static void c8sectpfe_getconfig(struct c8sectpfei *fei) 375 { 376 struct c8sectpfe_hw *hw = &fei->hw_stats; 377 378 hw->num_ib = readl(fei->io + SYS_CFG_NUM_IB); 379 hw->num_mib = readl(fei->io + SYS_CFG_NUM_MIB); 380 hw->num_swts = readl(fei->io + SYS_CFG_NUM_SWTS); 381 hw->num_tsout = readl(fei->io + SYS_CFG_NUM_TSOUT); 382 hw->num_ccsc = readl(fei->io + SYS_CFG_NUM_CCSC); 383 hw->num_ram = readl(fei->io + SYS_CFG_NUM_RAM); 384 hw->num_tp = readl(fei->io + SYS_CFG_NUM_TP); 385 386 dev_info(fei->dev, "C8SECTPFE hw supports the following:\n"); 387 dev_info(fei->dev, "Input Blocks: %d\n", hw->num_ib); 388 dev_info(fei->dev, "Merged Input Blocks: %d\n", hw->num_mib); 389 dev_info(fei->dev, "Software Transport Stream Inputs: %d\n" 390 , hw->num_swts); 391 dev_info(fei->dev, "Transport Stream Output: %d\n", hw->num_tsout); 392 dev_info(fei->dev, "Cable Card Converter: %d\n", hw->num_ccsc); 393 dev_info(fei->dev, "RAMs supported by C8SECTPFE: %d\n", hw->num_ram); 394 dev_info(fei->dev, "Tango TPs supported by C8SECTPFE: %d\n" 395 , hw->num_tp); 396 } 397 398 static irqreturn_t c8sectpfe_idle_irq_handler(int irq, void *priv) 399 { 400 struct c8sectpfei *fei = priv; 401 struct channel_info *chan; 402 int bit; 403 unsigned long tmp = readl(fei->io + DMA_IDLE_REQ); 404 405 /* page 168 of functional spec: Clear the idle request 406 by writing 0 to the C8SECTPFE_DMA_IDLE_REQ register. */ 407 408 /* signal idle completion */ 409 for_each_set_bit(bit, &tmp, fei->hw_stats.num_ib) { 410 411 chan = find_channel(fei, bit); 412 413 if (chan) 414 complete(&chan->idle_completion); 415 } 416 417 writel(0, fei->io + DMA_IDLE_REQ); 418 419 return IRQ_HANDLED; 420 } 421 422 423 static void free_input_block(struct c8sectpfei *fei, struct channel_info *tsin) 424 { 425 if (!fei || !tsin) 426 return; 427 428 if (tsin->back_buffer_busaddr) 429 if (!dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) 430 dma_unmap_single(fei->dev, tsin->back_buffer_busaddr, 431 FEI_BUFFER_SIZE, DMA_BIDIRECTIONAL); 432 433 kfree(tsin->back_buffer_start); 434 435 if (tsin->pid_buffer_busaddr) 436 if (!dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) 437 dma_unmap_single(fei->dev, tsin->pid_buffer_busaddr, 438 PID_TABLE_SIZE, DMA_BIDIRECTIONAL); 439 440 kfree(tsin->pid_buffer_start); 441 } 442 443 #define MAX_NAME 20 444 445 static int configure_memdma_and_inputblock(struct c8sectpfei *fei, 446 struct channel_info *tsin) 447 { 448 int ret; 449 u32 tmp; 450 char tsin_pin_name[MAX_NAME]; 451 452 if (!fei || !tsin) 453 return -EINVAL; 454 455 dev_dbg(fei->dev, "%s:%d Configuring channel=%p tsin=%d\n" 456 , __func__, __LINE__, tsin, tsin->tsin_id); 457 458 init_completion(&tsin->idle_completion); 459 460 tsin->back_buffer_start = kzalloc(FEI_BUFFER_SIZE + FEI_ALIGNMENT, GFP_KERNEL); 461 if (!tsin->back_buffer_start) { 462 ret = -ENOMEM; 463 goto err_unmap; 464 } 465 466 /* Ensure backbuffer is 32byte aligned */ 467 tsin->back_buffer_aligned = tsin->back_buffer_start + FEI_ALIGNMENT; 468 469 tsin->back_buffer_aligned = PTR_ALIGN(tsin->back_buffer_aligned, FEI_ALIGNMENT); 470 471 tsin->back_buffer_busaddr = dma_map_single(fei->dev, 472 tsin->back_buffer_aligned, 473 FEI_BUFFER_SIZE, 474 DMA_BIDIRECTIONAL); 475 476 if (dma_mapping_error(fei->dev, tsin->back_buffer_busaddr)) { 477 dev_err(fei->dev, "failed to map back_buffer\n"); 478 ret = -EFAULT; 479 goto err_unmap; 480 } 481 482 /* 483 * The pid buffer can be configured (in hw) for byte or bit 484 * per pid. By powers of deduction we conclude stih407 family 485 * is configured (at SoC design stage) for bit per pid. 486 */ 487 tsin->pid_buffer_start = kzalloc(PID_TABLE_SIZE + PID_TABLE_SIZE, GFP_KERNEL); 488 if (!tsin->pid_buffer_start) { 489 ret = -ENOMEM; 490 goto err_unmap; 491 } 492 493 /* 494 * PID buffer needs to be aligned to size of the pid table 495 * which at bit per pid is 1024 bytes (8192 pids / 8). 496 * PIDF_BASE register enforces this alignment when writing 497 * the register. 498 */ 499 500 tsin->pid_buffer_aligned = tsin->pid_buffer_start + PID_TABLE_SIZE; 501 502 tsin->pid_buffer_aligned = PTR_ALIGN(tsin->pid_buffer_aligned, PID_TABLE_SIZE); 503 504 tsin->pid_buffer_busaddr = dma_map_single(fei->dev, 505 tsin->pid_buffer_aligned, 506 PID_TABLE_SIZE, 507 DMA_BIDIRECTIONAL); 508 509 if (dma_mapping_error(fei->dev, tsin->pid_buffer_busaddr)) { 510 dev_err(fei->dev, "failed to map pid_bitmap\n"); 511 ret = -EFAULT; 512 goto err_unmap; 513 } 514 515 /* manage cache so pid bitmap is visible to HW */ 516 dma_sync_single_for_device(fei->dev, 517 tsin->pid_buffer_busaddr, 518 PID_TABLE_SIZE, 519 DMA_TO_DEVICE); 520 521 snprintf(tsin_pin_name, MAX_NAME, "tsin%d-%s", tsin->tsin_id, 522 (tsin->serial_not_parallel ? "serial" : "parallel")); 523 524 tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name); 525 if (IS_ERR(tsin->pstate)) { 526 dev_err(fei->dev, "%s: pinctrl_lookup_state couldn't find %s state\n" 527 , __func__, tsin_pin_name); 528 ret = PTR_ERR(tsin->pstate); 529 goto err_unmap; 530 } 531 532 ret = pinctrl_select_state(fei->pinctrl, tsin->pstate); 533 534 if (ret) { 535 dev_err(fei->dev, "%s: pinctrl_select_state failed\n" 536 , __func__); 537 goto err_unmap; 538 } 539 540 /* Enable this input block */ 541 tmp = readl(fei->io + SYS_INPUT_CLKEN); 542 tmp |= BIT(tsin->tsin_id); 543 writel(tmp, fei->io + SYS_INPUT_CLKEN); 544 545 if (tsin->serial_not_parallel) 546 tmp |= C8SECTPFE_SERIAL_NOT_PARALLEL; 547 548 if (tsin->invert_ts_clk) 549 tmp |= C8SECTPFE_INVERT_TSCLK; 550 551 if (tsin->async_not_sync) 552 tmp |= C8SECTPFE_ASYNC_NOT_SYNC; 553 554 tmp |= C8SECTPFE_ALIGN_BYTE_SOP | C8SECTPFE_BYTE_ENDIANNESS_MSB; 555 556 writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id)); 557 558 writel(C8SECTPFE_SYNC(0x9) | 559 C8SECTPFE_DROP(0x9) | 560 C8SECTPFE_TOKEN(0x47), 561 fei->io + C8SECTPFE_IB_SYNCLCKDRP_CFG(tsin->tsin_id)); 562 563 writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id)); 564 565 /* Place the FIFO's at the end of the irec descriptors */ 566 567 tsin->fifo = (tsin->tsin_id * FIFO_LEN); 568 569 writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)); 570 writel(tsin->fifo + FIFO_LEN - 1, 571 fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id)); 572 573 writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)); 574 writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)); 575 576 writel(tsin->pid_buffer_busaddr, 577 fei->io + PIDF_BASE(tsin->tsin_id)); 578 579 dev_dbg(fei->dev, "chan=%d PIDF_BASE=0x%x pid_bus_addr=%pad\n", 580 tsin->tsin_id, readl(fei->io + PIDF_BASE(tsin->tsin_id)), 581 &tsin->pid_buffer_busaddr); 582 583 /* Configure and enable HW PID filtering */ 584 585 /* 586 * The PID value is created by assembling the first 8 bytes of 587 * the TS packet into a 64-bit word in big-endian format. A 588 * slice of that 64-bit word is taken from 589 * (PID_OFFSET+PID_NUM_BITS-1) to PID_OFFSET. 590 */ 591 tmp = (C8SECTPFE_PID_ENABLE | C8SECTPFE_PID_NUMBITS(13) 592 | C8SECTPFE_PID_OFFSET(40)); 593 594 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id)); 595 596 dev_dbg(fei->dev, "chan=%d setting wp: %d, rp: %d, buf: %d-%d\n", 597 tsin->tsin_id, 598 readl(fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)), 599 readl(fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)), 600 readl(fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)), 601 readl(fei->io + C8SECTPFE_IB_BUFF_END(tsin->tsin_id))); 602 603 /* Get base addpress of pointer record block from DMEM */ 604 tsin->irec = fei->io + DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 605 readl(fei->io + DMA_PTRREC_BASE); 606 607 /* fill out pointer record data structure */ 608 609 /* advance pointer record block to our channel */ 610 tsin->irec += (tsin->tsin_id * DMA_PRDS_SIZE); 611 612 writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE); 613 614 writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP); 615 616 writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE); 617 618 writel(0x1, tsin->irec + DMA_PRDS_TPENABLE); 619 620 /* read/write pointers with physical bus address */ 621 622 writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0)); 623 624 tmp = tsin->back_buffer_busaddr + FEI_BUFFER_SIZE - 1; 625 writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0)); 626 627 writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0)); 628 writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0)); 629 630 /* initialize tasklet */ 631 tasklet_setup(&tsin->tsklet, channel_swdemux_tsklet); 632 633 return 0; 634 635 err_unmap: 636 free_input_block(fei, tsin); 637 return ret; 638 } 639 640 static irqreturn_t c8sectpfe_error_irq_handler(int irq, void *priv) 641 { 642 struct c8sectpfei *fei = priv; 643 644 dev_err(fei->dev, "%s: error handling not yet implemented\n" 645 , __func__); 646 647 /* 648 * TODO FIXME we should detect some error conditions here 649 * and ideally do something about them! 650 */ 651 652 return IRQ_HANDLED; 653 } 654 655 static int c8sectpfe_probe(struct platform_device *pdev) 656 { 657 struct device *dev = &pdev->dev; 658 struct device_node *child, *np = dev->of_node; 659 struct c8sectpfei *fei; 660 struct resource *res; 661 int ret, index = 0; 662 struct channel_info *tsin; 663 664 /* Allocate the c8sectpfei structure */ 665 fei = devm_kzalloc(dev, sizeof(struct c8sectpfei), GFP_KERNEL); 666 if (!fei) 667 return -ENOMEM; 668 669 fei->dev = dev; 670 671 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "c8sectpfe"); 672 fei->io = devm_ioremap_resource(dev, res); 673 if (IS_ERR(fei->io)) 674 return PTR_ERR(fei->io); 675 676 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 677 "c8sectpfe-ram"); 678 fei->sram = devm_ioremap_resource(dev, res); 679 if (IS_ERR(fei->sram)) 680 return PTR_ERR(fei->sram); 681 682 fei->sram_size = resource_size(res); 683 684 fei->idle_irq = platform_get_irq_byname(pdev, "c8sectpfe-idle-irq"); 685 if (fei->idle_irq < 0) 686 return fei->idle_irq; 687 688 fei->error_irq = platform_get_irq_byname(pdev, "c8sectpfe-error-irq"); 689 if (fei->error_irq < 0) 690 return fei->error_irq; 691 692 platform_set_drvdata(pdev, fei); 693 694 fei->c8sectpfeclk = devm_clk_get(dev, "c8sectpfe"); 695 if (IS_ERR(fei->c8sectpfeclk)) { 696 dev_err(dev, "c8sectpfe clk not found\n"); 697 return PTR_ERR(fei->c8sectpfeclk); 698 } 699 700 ret = clk_prepare_enable(fei->c8sectpfeclk); 701 if (ret) { 702 dev_err(dev, "Failed to enable c8sectpfe clock\n"); 703 return ret; 704 } 705 706 /* to save power disable all IP's (on by default) */ 707 writel(0, fei->io + SYS_INPUT_CLKEN); 708 709 /* Enable memdma clock */ 710 writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN); 711 712 /* clear internal sram */ 713 memset_io(fei->sram, 0x0, fei->sram_size); 714 715 c8sectpfe_getconfig(fei); 716 717 ret = devm_request_irq(dev, fei->idle_irq, c8sectpfe_idle_irq_handler, 718 0, "c8sectpfe-idle-irq", fei); 719 if (ret) { 720 dev_err(dev, "Can't register c8sectpfe-idle-irq IRQ.\n"); 721 goto err_clk_disable; 722 } 723 724 ret = devm_request_irq(dev, fei->error_irq, 725 c8sectpfe_error_irq_handler, 0, 726 "c8sectpfe-error-irq", fei); 727 if (ret) { 728 dev_err(dev, "Can't register c8sectpfe-error-irq IRQ.\n"); 729 goto err_clk_disable; 730 } 731 732 fei->tsin_count = of_get_child_count(np); 733 734 if (fei->tsin_count > C8SECTPFE_MAX_TSIN_CHAN || 735 fei->tsin_count > fei->hw_stats.num_ib) { 736 737 dev_err(dev, "More tsin declared than exist on SoC!\n"); 738 ret = -EINVAL; 739 goto err_clk_disable; 740 } 741 742 fei->pinctrl = devm_pinctrl_get(dev); 743 744 if (IS_ERR(fei->pinctrl)) { 745 dev_err(dev, "Error getting tsin pins\n"); 746 ret = PTR_ERR(fei->pinctrl); 747 goto err_clk_disable; 748 } 749 750 for_each_child_of_node(np, child) { 751 struct device_node *i2c_bus; 752 753 fei->channel_data[index] = devm_kzalloc(dev, 754 sizeof(struct channel_info), 755 GFP_KERNEL); 756 757 if (!fei->channel_data[index]) { 758 ret = -ENOMEM; 759 goto err_node_put; 760 } 761 762 tsin = fei->channel_data[index]; 763 764 tsin->fei = fei; 765 766 ret = of_property_read_u32(child, "tsin-num", &tsin->tsin_id); 767 if (ret) { 768 dev_err(&pdev->dev, "No tsin_num found\n"); 769 goto err_node_put; 770 } 771 772 /* sanity check value */ 773 if (tsin->tsin_id > fei->hw_stats.num_ib) { 774 dev_err(&pdev->dev, 775 "tsin-num %d specified greater than number\n\tof input block hw in SoC! (%d)", 776 tsin->tsin_id, fei->hw_stats.num_ib); 777 ret = -EINVAL; 778 goto err_node_put; 779 } 780 781 tsin->invert_ts_clk = of_property_read_bool(child, 782 "invert-ts-clk"); 783 784 tsin->serial_not_parallel = of_property_read_bool(child, 785 "serial-not-parallel"); 786 787 tsin->async_not_sync = of_property_read_bool(child, 788 "async-not-sync"); 789 790 ret = of_property_read_u32(child, "dvb-card", 791 &tsin->dvb_card); 792 if (ret) { 793 dev_err(&pdev->dev, "No dvb-card found\n"); 794 goto err_node_put; 795 } 796 797 i2c_bus = of_parse_phandle(child, "i2c-bus", 0); 798 if (!i2c_bus) { 799 dev_err(&pdev->dev, "No i2c-bus found\n"); 800 ret = -ENODEV; 801 goto err_node_put; 802 } 803 tsin->i2c_adapter = 804 of_find_i2c_adapter_by_node(i2c_bus); 805 if (!tsin->i2c_adapter) { 806 dev_err(&pdev->dev, "No i2c adapter found\n"); 807 of_node_put(i2c_bus); 808 ret = -ENODEV; 809 goto err_node_put; 810 } 811 of_node_put(i2c_bus); 812 813 tsin->rst_gpio = of_get_named_gpio(child, "reset-gpios", 0); 814 815 ret = gpio_is_valid(tsin->rst_gpio); 816 if (!ret) { 817 dev_err(dev, 818 "reset gpio for tsin%d not valid (gpio=%d)\n", 819 tsin->tsin_id, tsin->rst_gpio); 820 ret = -EINVAL; 821 goto err_node_put; 822 } 823 824 ret = devm_gpio_request_one(dev, tsin->rst_gpio, 825 GPIOF_OUT_INIT_LOW, "NIM reset"); 826 if (ret && ret != -EBUSY) { 827 dev_err(dev, "Can't request tsin%d reset gpio\n" 828 , fei->channel_data[index]->tsin_id); 829 goto err_node_put; 830 } 831 832 if (!ret) { 833 /* toggle reset lines */ 834 gpio_direction_output(tsin->rst_gpio, 0); 835 usleep_range(3500, 5000); 836 gpio_direction_output(tsin->rst_gpio, 1); 837 usleep_range(3000, 5000); 838 } 839 840 tsin->demux_mapping = index; 841 842 dev_dbg(fei->dev, 843 "channel=%p n=%d tsin_num=%d, invert-ts-clk=%d\n\tserial-not-parallel=%d pkt-clk-valid=%d dvb-card=%d\n", 844 fei->channel_data[index], index, 845 tsin->tsin_id, tsin->invert_ts_clk, 846 tsin->serial_not_parallel, tsin->async_not_sync, 847 tsin->dvb_card); 848 849 index++; 850 } 851 852 /* Setup timer interrupt */ 853 timer_setup(&fei->timer, c8sectpfe_timer_interrupt, 0); 854 855 mutex_init(&fei->lock); 856 857 /* Get the configuration information about the tuners */ 858 ret = c8sectpfe_tuner_register_frontend(&fei->c8sectpfe[0], 859 (void *)fei, 860 c8sectpfe_start_feed, 861 c8sectpfe_stop_feed); 862 if (ret) { 863 dev_err(dev, "c8sectpfe_tuner_register_frontend failed (%d)\n", 864 ret); 865 goto err_clk_disable; 866 } 867 868 c8sectpfe_debugfs_init(fei); 869 870 return 0; 871 872 err_node_put: 873 of_node_put(child); 874 err_clk_disable: 875 clk_disable_unprepare(fei->c8sectpfeclk); 876 return ret; 877 } 878 879 static int c8sectpfe_remove(struct platform_device *pdev) 880 { 881 struct c8sectpfei *fei = platform_get_drvdata(pdev); 882 struct channel_info *channel; 883 int i; 884 885 wait_for_completion(&fei->fw_ack); 886 887 c8sectpfe_tuner_unregister_frontend(fei->c8sectpfe[0], fei); 888 889 /* 890 * Now loop through and un-configure each of the InputBlock resources 891 */ 892 for (i = 0; i < fei->tsin_count; i++) { 893 channel = fei->channel_data[i]; 894 free_input_block(fei, channel); 895 } 896 897 c8sectpfe_debugfs_exit(fei); 898 899 dev_info(fei->dev, "Stopping memdma SLIM core\n"); 900 if (readl(fei->io + DMA_CPU_RUN)) 901 writel(0x0, fei->io + DMA_CPU_RUN); 902 903 /* unclock all internal IP's */ 904 if (readl(fei->io + SYS_INPUT_CLKEN)) 905 writel(0, fei->io + SYS_INPUT_CLKEN); 906 907 if (readl(fei->io + SYS_OTHER_CLKEN)) 908 writel(0, fei->io + SYS_OTHER_CLKEN); 909 910 clk_disable_unprepare(fei->c8sectpfeclk); 911 912 return 0; 913 } 914 915 916 static int configure_channels(struct c8sectpfei *fei) 917 { 918 int index = 0, ret; 919 struct device_node *child, *np = fei->dev->of_node; 920 921 /* iterate round each tsin and configure memdma descriptor and IB hw */ 922 for_each_child_of_node(np, child) { 923 ret = configure_memdma_and_inputblock(fei, 924 fei->channel_data[index]); 925 if (ret) { 926 dev_err(fei->dev, 927 "configure_memdma_and_inputblock failed\n"); 928 goto err_unmap; 929 } 930 index++; 931 } 932 933 return 0; 934 935 err_unmap: 936 while (--index >= 0) 937 free_input_block(fei, fei->channel_data[index]); 938 939 return ret; 940 } 941 942 static int 943 c8sectpfe_elf_sanity_check(struct c8sectpfei *fei, const struct firmware *fw) 944 { 945 struct elf32_hdr *ehdr; 946 char class; 947 948 if (!fw) { 949 dev_err(fei->dev, "failed to load %s\n", FIRMWARE_MEMDMA); 950 return -EINVAL; 951 } 952 953 if (fw->size < sizeof(struct elf32_hdr)) { 954 dev_err(fei->dev, "Image is too small\n"); 955 return -EINVAL; 956 } 957 958 ehdr = (struct elf32_hdr *)fw->data; 959 960 /* We only support ELF32 at this point */ 961 class = ehdr->e_ident[EI_CLASS]; 962 if (class != ELFCLASS32) { 963 dev_err(fei->dev, "Unsupported class: %d\n", class); 964 return -EINVAL; 965 } 966 967 if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB) { 968 dev_err(fei->dev, "Unsupported firmware endianness\n"); 969 return -EINVAL; 970 } 971 972 if (fw->size < ehdr->e_shoff + sizeof(struct elf32_shdr)) { 973 dev_err(fei->dev, "Image is too small\n"); 974 return -EINVAL; 975 } 976 977 if (memcmp(ehdr->e_ident, ELFMAG, SELFMAG)) { 978 dev_err(fei->dev, "Image is corrupted (bad magic)\n"); 979 return -EINVAL; 980 } 981 982 /* Check ELF magic */ 983 ehdr = (Elf32_Ehdr *)fw->data; 984 if (ehdr->e_ident[EI_MAG0] != ELFMAG0 || 985 ehdr->e_ident[EI_MAG1] != ELFMAG1 || 986 ehdr->e_ident[EI_MAG2] != ELFMAG2 || 987 ehdr->e_ident[EI_MAG3] != ELFMAG3) { 988 dev_err(fei->dev, "Invalid ELF magic\n"); 989 return -EINVAL; 990 } 991 992 if (ehdr->e_type != ET_EXEC) { 993 dev_err(fei->dev, "Unsupported ELF header type\n"); 994 return -EINVAL; 995 } 996 997 if (ehdr->e_phoff > fw->size) { 998 dev_err(fei->dev, "Firmware size is too small\n"); 999 return -EINVAL; 1000 } 1001 1002 return 0; 1003 } 1004 1005 1006 static void load_imem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr, 1007 const struct firmware *fw, u8 __iomem *dest, 1008 int seg_num) 1009 { 1010 const u8 *imem_src = fw->data + phdr->p_offset; 1011 int i; 1012 1013 /* 1014 * For IMEM segments, the segment contains 24-bit 1015 * instructions which must be padded to 32-bit 1016 * instructions before being written. The written 1017 * segment is padded with NOP instructions. 1018 */ 1019 1020 dev_dbg(fei->dev, 1021 "Loading IMEM segment %d 0x%08x\n\t (0x%x bytes) -> 0x%p (0x%x bytes)\n", 1022 seg_num, phdr->p_paddr, phdr->p_filesz, dest, 1023 phdr->p_memsz + phdr->p_memsz / 3); 1024 1025 for (i = 0; i < phdr->p_filesz; i++) { 1026 1027 writeb(readb((void __iomem *)imem_src), (void __iomem *)dest); 1028 1029 /* Every 3 bytes, add an additional 1030 * padding zero in destination */ 1031 if (i % 3 == 2) { 1032 dest++; 1033 writeb(0x00, (void __iomem *)dest); 1034 } 1035 1036 dest++; 1037 imem_src++; 1038 } 1039 } 1040 1041 static void load_dmem_segment(struct c8sectpfei *fei, Elf32_Phdr *phdr, 1042 const struct firmware *fw, u8 __iomem *dst, int seg_num) 1043 { 1044 /* 1045 * For DMEM segments copy the segment data from the ELF 1046 * file and pad segment with zeroes 1047 */ 1048 1049 dev_dbg(fei->dev, 1050 "Loading DMEM segment %d 0x%08x\n\t(0x%x bytes) -> 0x%p (0x%x bytes)\n", 1051 seg_num, phdr->p_paddr, phdr->p_filesz, 1052 dst, phdr->p_memsz); 1053 1054 memcpy((void __force *)dst, (void *)fw->data + phdr->p_offset, 1055 phdr->p_filesz); 1056 1057 memset((void __force *)dst + phdr->p_filesz, 0, 1058 phdr->p_memsz - phdr->p_filesz); 1059 } 1060 1061 static int load_slim_core_fw(const struct firmware *fw, struct c8sectpfei *fei) 1062 { 1063 Elf32_Ehdr *ehdr; 1064 Elf32_Phdr *phdr; 1065 u8 __iomem *dst; 1066 int err = 0, i; 1067 1068 if (!fw || !fei) 1069 return -EINVAL; 1070 1071 ehdr = (Elf32_Ehdr *)fw->data; 1072 phdr = (Elf32_Phdr *)(fw->data + ehdr->e_phoff); 1073 1074 /* go through the available ELF segments */ 1075 for (i = 0; i < ehdr->e_phnum; i++, phdr++) { 1076 1077 /* Only consider LOAD segments */ 1078 if (phdr->p_type != PT_LOAD) 1079 continue; 1080 1081 /* 1082 * Check segment is contained within the fw->data buffer 1083 */ 1084 if (phdr->p_offset + phdr->p_filesz > fw->size) { 1085 dev_err(fei->dev, 1086 "Segment %d is outside of firmware file\n", i); 1087 err = -EINVAL; 1088 break; 1089 } 1090 1091 /* 1092 * MEMDMA IMEM has executable flag set, otherwise load 1093 * this segment into DMEM. 1094 * 1095 */ 1096 1097 if (phdr->p_flags & PF_X) { 1098 dst = (u8 __iomem *) fei->io + DMA_MEMDMA_IMEM; 1099 /* 1100 * The Slim ELF file uses 32-bit word addressing for 1101 * load offsets. 1102 */ 1103 dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int); 1104 load_imem_segment(fei, phdr, fw, dst, i); 1105 } else { 1106 dst = (u8 __iomem *) fei->io + DMA_MEMDMA_DMEM; 1107 /* 1108 * The Slim ELF file uses 32-bit word addressing for 1109 * load offsets. 1110 */ 1111 dst += (phdr->p_paddr & 0xFFFFF) * sizeof(unsigned int); 1112 load_dmem_segment(fei, phdr, fw, dst, i); 1113 } 1114 } 1115 1116 release_firmware(fw); 1117 return err; 1118 } 1119 1120 static int load_c8sectpfe_fw(struct c8sectpfei *fei) 1121 { 1122 const struct firmware *fw; 1123 int err; 1124 1125 dev_info(fei->dev, "Loading firmware: %s\n", FIRMWARE_MEMDMA); 1126 1127 err = request_firmware(&fw, FIRMWARE_MEMDMA, fei->dev); 1128 if (err) 1129 return err; 1130 1131 err = c8sectpfe_elf_sanity_check(fei, fw); 1132 if (err) { 1133 dev_err(fei->dev, "c8sectpfe_elf_sanity_check failed err=(%d)\n" 1134 , err); 1135 release_firmware(fw); 1136 return err; 1137 } 1138 1139 err = load_slim_core_fw(fw, fei); 1140 if (err) { 1141 dev_err(fei->dev, "load_slim_core_fw failed err=(%d)\n", err); 1142 return err; 1143 } 1144 1145 /* now the firmware is loaded configure the input blocks */ 1146 err = configure_channels(fei); 1147 if (err) { 1148 dev_err(fei->dev, "configure_channels failed err=(%d)\n", err); 1149 return err; 1150 } 1151 1152 /* 1153 * STBus target port can access IMEM and DMEM ports 1154 * without waiting for CPU 1155 */ 1156 writel(0x1, fei->io + DMA_PER_STBUS_SYNC); 1157 1158 dev_info(fei->dev, "Boot the memdma SLIM core\n"); 1159 writel(0x1, fei->io + DMA_CPU_RUN); 1160 1161 atomic_set(&fei->fw_loaded, 1); 1162 1163 return 0; 1164 } 1165 1166 static const struct of_device_id c8sectpfe_match[] = { 1167 { .compatible = "st,stih407-c8sectpfe" }, 1168 { /* sentinel */ }, 1169 }; 1170 MODULE_DEVICE_TABLE(of, c8sectpfe_match); 1171 1172 static struct platform_driver c8sectpfe_driver = { 1173 .driver = { 1174 .name = "c8sectpfe", 1175 .of_match_table = of_match_ptr(c8sectpfe_match), 1176 }, 1177 .probe = c8sectpfe_probe, 1178 .remove = c8sectpfe_remove, 1179 }; 1180 1181 module_platform_driver(c8sectpfe_driver); 1182 1183 MODULE_AUTHOR("Peter Bennett <peter.bennett@st.com>"); 1184 MODULE_AUTHOR("Peter Griffin <peter.griffin@linaro.org>"); 1185 MODULE_DESCRIPTION("C8SECTPFE STi DVB Driver"); 1186 MODULE_LICENSE("GPL"); 1187