1*43ecec16SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*43ecec16SMauro Carvalho Chehab /* 3*43ecec16SMauro Carvalho Chehab * Samsung S5P Multi Format Codec v 5.0 4*43ecec16SMauro Carvalho Chehab * 5*43ecec16SMauro Carvalho Chehab * This file contains definitions of enums and structs used by the codec 6*43ecec16SMauro Carvalho Chehab * driver. 7*43ecec16SMauro Carvalho Chehab * 8*43ecec16SMauro Carvalho Chehab * Copyright (C) 2011 Samsung Electronics Co., Ltd. 9*43ecec16SMauro Carvalho Chehab * Kamil Debski, <k.debski@samsung.com> 10*43ecec16SMauro Carvalho Chehab */ 11*43ecec16SMauro Carvalho Chehab 12*43ecec16SMauro Carvalho Chehab #ifndef S5P_MFC_COMMON_H_ 13*43ecec16SMauro Carvalho Chehab #define S5P_MFC_COMMON_H_ 14*43ecec16SMauro Carvalho Chehab 15*43ecec16SMauro Carvalho Chehab #include <linux/platform_device.h> 16*43ecec16SMauro Carvalho Chehab #include <linux/videodev2.h> 17*43ecec16SMauro Carvalho Chehab #include <media/v4l2-ctrls.h> 18*43ecec16SMauro Carvalho Chehab #include <media/v4l2-device.h> 19*43ecec16SMauro Carvalho Chehab #include <media/v4l2-ioctl.h> 20*43ecec16SMauro Carvalho Chehab #include <media/videobuf2-v4l2.h> 21*43ecec16SMauro Carvalho Chehab #include "regs-mfc.h" 22*43ecec16SMauro Carvalho Chehab #include "regs-mfc-v10.h" 23*43ecec16SMauro Carvalho Chehab 24*43ecec16SMauro Carvalho Chehab #define S5P_MFC_NAME "s5p-mfc" 25*43ecec16SMauro Carvalho Chehab 26*43ecec16SMauro Carvalho Chehab /* Definitions related to MFC memory */ 27*43ecec16SMauro Carvalho Chehab 28*43ecec16SMauro Carvalho Chehab /* Offset base used to differentiate between CAPTURE and OUTPUT 29*43ecec16SMauro Carvalho Chehab * while mmaping */ 30*43ecec16SMauro Carvalho Chehab #define DST_QUEUE_OFF_BASE (1 << 30) 31*43ecec16SMauro Carvalho Chehab 32*43ecec16SMauro Carvalho Chehab #define BANK_L_CTX 0 33*43ecec16SMauro Carvalho Chehab #define BANK_R_CTX 1 34*43ecec16SMauro Carvalho Chehab #define BANK_CTX_NUM 2 35*43ecec16SMauro Carvalho Chehab 36*43ecec16SMauro Carvalho Chehab #define MFC_BANK1_ALIGN_ORDER 13 37*43ecec16SMauro Carvalho Chehab #define MFC_BANK2_ALIGN_ORDER 13 38*43ecec16SMauro Carvalho Chehab #define MFC_BASE_ALIGN_ORDER 17 39*43ecec16SMauro Carvalho Chehab 40*43ecec16SMauro Carvalho Chehab #define MFC_FW_MAX_VERSIONS 2 41*43ecec16SMauro Carvalho Chehab 42*43ecec16SMauro Carvalho Chehab #include <media/videobuf2-dma-contig.h> 43*43ecec16SMauro Carvalho Chehab 44*43ecec16SMauro Carvalho Chehab /* MFC definitions */ 45*43ecec16SMauro Carvalho Chehab #define MFC_MAX_EXTRA_DPB 5 46*43ecec16SMauro Carvalho Chehab #define MFC_MAX_BUFFERS 32 47*43ecec16SMauro Carvalho Chehab #define MFC_NUM_CONTEXTS 4 48*43ecec16SMauro Carvalho Chehab /* Interrupt timeout */ 49*43ecec16SMauro Carvalho Chehab #define MFC_INT_TIMEOUT 2000 50*43ecec16SMauro Carvalho Chehab /* Busy wait timeout */ 51*43ecec16SMauro Carvalho Chehab #define MFC_BW_TIMEOUT 500 52*43ecec16SMauro Carvalho Chehab /* Watchdog interval */ 53*43ecec16SMauro Carvalho Chehab #define MFC_WATCHDOG_INTERVAL 1000 54*43ecec16SMauro Carvalho Chehab /* After how many executions watchdog should assume lock up */ 55*43ecec16SMauro Carvalho Chehab #define MFC_WATCHDOG_CNT 10 56*43ecec16SMauro Carvalho Chehab #define MFC_NO_INSTANCE_SET -1 57*43ecec16SMauro Carvalho Chehab #define MFC_ENC_CAP_PLANE_COUNT 1 58*43ecec16SMauro Carvalho Chehab #define MFC_ENC_OUT_PLANE_COUNT 2 59*43ecec16SMauro Carvalho Chehab #define STUFF_BYTE 4 60*43ecec16SMauro Carvalho Chehab #define MFC_MAX_CTRLS 128 61*43ecec16SMauro Carvalho Chehab 62*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_NONE -1 63*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_H264_DEC 0 64*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_H264_MVC_DEC 1 65*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_VC1_DEC 2 66*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_MPEG4_DEC 3 67*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_MPEG2_DEC 4 68*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_H263_DEC 5 69*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_VC1RCV_DEC 6 70*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_VP8_DEC 7 71*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_HEVC_DEC 17 72*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_VP9_DEC 18 73*43ecec16SMauro Carvalho Chehab 74*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_H264_ENC 20 75*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_H264_MVC_ENC 21 76*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_MPEG4_ENC 22 77*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_H263_ENC 23 78*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_VP8_ENC 24 79*43ecec16SMauro Carvalho Chehab #define S5P_MFC_CODEC_HEVC_ENC 26 80*43ecec16SMauro Carvalho Chehab 81*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_EMPTY 0 82*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 83*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2 84*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3 85*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4 86*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6 87*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_SLEEP_RET 7 88*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_WAKEUP_RET 8 89*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9 90*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10 91*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11 92*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_FW_STATUS_RET 12 93*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13 94*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14 95*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15 96*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16 97*43ecec16SMauro Carvalho Chehab #define S5P_MFC_R2H_CMD_ERR_RET 32 98*43ecec16SMauro Carvalho Chehab 99*43ecec16SMauro Carvalho Chehab #define MFC_MAX_CLOCKS 4 100*43ecec16SMauro Carvalho Chehab 101*43ecec16SMauro Carvalho Chehab #define mfc_read(dev, offset) readl(dev->regs_base + (offset)) 102*43ecec16SMauro Carvalho Chehab #define mfc_write(dev, data, offset) writel((data), dev->regs_base + \ 103*43ecec16SMauro Carvalho Chehab (offset)) 104*43ecec16SMauro Carvalho Chehab 105*43ecec16SMauro Carvalho Chehab /* 106*43ecec16SMauro Carvalho Chehab * enum s5p_mfc_fmt_type - type of the pixelformat 107*43ecec16SMauro Carvalho Chehab */ 108*43ecec16SMauro Carvalho Chehab enum s5p_mfc_fmt_type { 109*43ecec16SMauro Carvalho Chehab MFC_FMT_DEC, 110*43ecec16SMauro Carvalho Chehab MFC_FMT_ENC, 111*43ecec16SMauro Carvalho Chehab MFC_FMT_RAW, 112*43ecec16SMauro Carvalho Chehab }; 113*43ecec16SMauro Carvalho Chehab 114*43ecec16SMauro Carvalho Chehab /* 115*43ecec16SMauro Carvalho Chehab * enum s5p_mfc_inst_type - The type of an MFC instance. 116*43ecec16SMauro Carvalho Chehab */ 117*43ecec16SMauro Carvalho Chehab enum s5p_mfc_inst_type { 118*43ecec16SMauro Carvalho Chehab MFCINST_INVALID, 119*43ecec16SMauro Carvalho Chehab MFCINST_DECODER, 120*43ecec16SMauro Carvalho Chehab MFCINST_ENCODER, 121*43ecec16SMauro Carvalho Chehab }; 122*43ecec16SMauro Carvalho Chehab 123*43ecec16SMauro Carvalho Chehab /* 124*43ecec16SMauro Carvalho Chehab * enum s5p_mfc_inst_state - The state of an MFC instance. 125*43ecec16SMauro Carvalho Chehab */ 126*43ecec16SMauro Carvalho Chehab enum s5p_mfc_inst_state { 127*43ecec16SMauro Carvalho Chehab MFCINST_FREE = 0, 128*43ecec16SMauro Carvalho Chehab MFCINST_INIT = 100, 129*43ecec16SMauro Carvalho Chehab MFCINST_GOT_INST, 130*43ecec16SMauro Carvalho Chehab MFCINST_HEAD_PARSED, 131*43ecec16SMauro Carvalho Chehab MFCINST_HEAD_PRODUCED, 132*43ecec16SMauro Carvalho Chehab MFCINST_BUFS_SET, 133*43ecec16SMauro Carvalho Chehab MFCINST_RUNNING, 134*43ecec16SMauro Carvalho Chehab MFCINST_FINISHING, 135*43ecec16SMauro Carvalho Chehab MFCINST_FINISHED, 136*43ecec16SMauro Carvalho Chehab MFCINST_RETURN_INST, 137*43ecec16SMauro Carvalho Chehab MFCINST_ERROR, 138*43ecec16SMauro Carvalho Chehab MFCINST_ABORT, 139*43ecec16SMauro Carvalho Chehab MFCINST_FLUSH, 140*43ecec16SMauro Carvalho Chehab MFCINST_RES_CHANGE_INIT, 141*43ecec16SMauro Carvalho Chehab MFCINST_RES_CHANGE_FLUSH, 142*43ecec16SMauro Carvalho Chehab MFCINST_RES_CHANGE_END, 143*43ecec16SMauro Carvalho Chehab }; 144*43ecec16SMauro Carvalho Chehab 145*43ecec16SMauro Carvalho Chehab /* 146*43ecec16SMauro Carvalho Chehab * enum s5p_mfc_queue_state - The state of buffer queue. 147*43ecec16SMauro Carvalho Chehab */ 148*43ecec16SMauro Carvalho Chehab enum s5p_mfc_queue_state { 149*43ecec16SMauro Carvalho Chehab QUEUE_FREE, 150*43ecec16SMauro Carvalho Chehab QUEUE_BUFS_REQUESTED, 151*43ecec16SMauro Carvalho Chehab QUEUE_BUFS_QUERIED, 152*43ecec16SMauro Carvalho Chehab QUEUE_BUFS_MMAPED, 153*43ecec16SMauro Carvalho Chehab }; 154*43ecec16SMauro Carvalho Chehab 155*43ecec16SMauro Carvalho Chehab /* 156*43ecec16SMauro Carvalho Chehab * enum s5p_mfc_decode_arg - type of frame decoding 157*43ecec16SMauro Carvalho Chehab */ 158*43ecec16SMauro Carvalho Chehab enum s5p_mfc_decode_arg { 159*43ecec16SMauro Carvalho Chehab MFC_DEC_FRAME, 160*43ecec16SMauro Carvalho Chehab MFC_DEC_LAST_FRAME, 161*43ecec16SMauro Carvalho Chehab MFC_DEC_RES_CHANGE, 162*43ecec16SMauro Carvalho Chehab }; 163*43ecec16SMauro Carvalho Chehab 164*43ecec16SMauro Carvalho Chehab enum s5p_mfc_fw_ver { 165*43ecec16SMauro Carvalho Chehab MFC_FW_V1, 166*43ecec16SMauro Carvalho Chehab MFC_FW_V2, 167*43ecec16SMauro Carvalho Chehab }; 168*43ecec16SMauro Carvalho Chehab 169*43ecec16SMauro Carvalho Chehab #define MFC_BUF_FLAG_USED (1 << 0) 170*43ecec16SMauro Carvalho Chehab #define MFC_BUF_FLAG_EOS (1 << 1) 171*43ecec16SMauro Carvalho Chehab 172*43ecec16SMauro Carvalho Chehab struct s5p_mfc_ctx; 173*43ecec16SMauro Carvalho Chehab 174*43ecec16SMauro Carvalho Chehab /* 175*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_buf - MFC buffer 176*43ecec16SMauro Carvalho Chehab */ 177*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf { 178*43ecec16SMauro Carvalho Chehab struct vb2_v4l2_buffer *b; 179*43ecec16SMauro Carvalho Chehab struct list_head list; 180*43ecec16SMauro Carvalho Chehab union { 181*43ecec16SMauro Carvalho Chehab struct { 182*43ecec16SMauro Carvalho Chehab size_t luma; 183*43ecec16SMauro Carvalho Chehab size_t chroma; 184*43ecec16SMauro Carvalho Chehab } raw; 185*43ecec16SMauro Carvalho Chehab size_t stream; 186*43ecec16SMauro Carvalho Chehab } cookie; 187*43ecec16SMauro Carvalho Chehab int flags; 188*43ecec16SMauro Carvalho Chehab }; 189*43ecec16SMauro Carvalho Chehab 190*43ecec16SMauro Carvalho Chehab /* 191*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_pm - power management data structure 192*43ecec16SMauro Carvalho Chehab */ 193*43ecec16SMauro Carvalho Chehab struct s5p_mfc_pm { 194*43ecec16SMauro Carvalho Chehab struct clk *clock_gate; 195*43ecec16SMauro Carvalho Chehab const char * const *clk_names; 196*43ecec16SMauro Carvalho Chehab struct clk *clocks[MFC_MAX_CLOCKS]; 197*43ecec16SMauro Carvalho Chehab int num_clocks; 198*43ecec16SMauro Carvalho Chehab bool use_clock_gating; 199*43ecec16SMauro Carvalho Chehab 200*43ecec16SMauro Carvalho Chehab struct device *device; 201*43ecec16SMauro Carvalho Chehab }; 202*43ecec16SMauro Carvalho Chehab 203*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf_size_v5 { 204*43ecec16SMauro Carvalho Chehab unsigned int h264_ctx; 205*43ecec16SMauro Carvalho Chehab unsigned int non_h264_ctx; 206*43ecec16SMauro Carvalho Chehab unsigned int dsc; 207*43ecec16SMauro Carvalho Chehab unsigned int shm; 208*43ecec16SMauro Carvalho Chehab }; 209*43ecec16SMauro Carvalho Chehab 210*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf_size_v6 { 211*43ecec16SMauro Carvalho Chehab unsigned int dev_ctx; 212*43ecec16SMauro Carvalho Chehab unsigned int h264_dec_ctx; 213*43ecec16SMauro Carvalho Chehab unsigned int other_dec_ctx; 214*43ecec16SMauro Carvalho Chehab unsigned int h264_enc_ctx; 215*43ecec16SMauro Carvalho Chehab unsigned int hevc_enc_ctx; 216*43ecec16SMauro Carvalho Chehab unsigned int other_enc_ctx; 217*43ecec16SMauro Carvalho Chehab }; 218*43ecec16SMauro Carvalho Chehab 219*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf_size { 220*43ecec16SMauro Carvalho Chehab unsigned int fw; 221*43ecec16SMauro Carvalho Chehab unsigned int cpb; 222*43ecec16SMauro Carvalho Chehab void *priv; 223*43ecec16SMauro Carvalho Chehab }; 224*43ecec16SMauro Carvalho Chehab 225*43ecec16SMauro Carvalho Chehab struct s5p_mfc_variant { 226*43ecec16SMauro Carvalho Chehab unsigned int version; 227*43ecec16SMauro Carvalho Chehab unsigned int port_num; 228*43ecec16SMauro Carvalho Chehab u32 version_bit; 229*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf_size *buf_size; 230*43ecec16SMauro Carvalho Chehab char *fw_name[MFC_FW_MAX_VERSIONS]; 231*43ecec16SMauro Carvalho Chehab const char *clk_names[MFC_MAX_CLOCKS]; 232*43ecec16SMauro Carvalho Chehab int num_clocks; 233*43ecec16SMauro Carvalho Chehab bool use_clock_gating; 234*43ecec16SMauro Carvalho Chehab }; 235*43ecec16SMauro Carvalho Chehab 236*43ecec16SMauro Carvalho Chehab /** 237*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_priv_buf - represents internal used buffer 238*43ecec16SMauro Carvalho Chehab * @ofs: offset of each buffer, will be used for MFC 239*43ecec16SMauro Carvalho Chehab * @virt: kernel virtual address, only valid when the 240*43ecec16SMauro Carvalho Chehab * buffer accessed by driver 241*43ecec16SMauro Carvalho Chehab * @dma: DMA address, only valid when kernel DMA API used 242*43ecec16SMauro Carvalho Chehab * @size: size of the buffer 243*43ecec16SMauro Carvalho Chehab * @ctx: memory context (bank) used for this allocation 244*43ecec16SMauro Carvalho Chehab */ 245*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf { 246*43ecec16SMauro Carvalho Chehab unsigned long ofs; 247*43ecec16SMauro Carvalho Chehab void *virt; 248*43ecec16SMauro Carvalho Chehab dma_addr_t dma; 249*43ecec16SMauro Carvalho Chehab size_t size; 250*43ecec16SMauro Carvalho Chehab unsigned int ctx; 251*43ecec16SMauro Carvalho Chehab }; 252*43ecec16SMauro Carvalho Chehab 253*43ecec16SMauro Carvalho Chehab /** 254*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_dev - The struct containing driver internal parameters. 255*43ecec16SMauro Carvalho Chehab * 256*43ecec16SMauro Carvalho Chehab * @v4l2_dev: v4l2_device 257*43ecec16SMauro Carvalho Chehab * @vfd_dec: video device for decoding 258*43ecec16SMauro Carvalho Chehab * @vfd_enc: video device for encoding 259*43ecec16SMauro Carvalho Chehab * @plat_dev: platform device 260*43ecec16SMauro Carvalho Chehab * @mem_dev: child devices of the memory banks 261*43ecec16SMauro Carvalho Chehab * @regs_base: base address of the MFC hw registers 262*43ecec16SMauro Carvalho Chehab * @irq: irq resource 263*43ecec16SMauro Carvalho Chehab * @dec_ctrl_handler: control framework handler for decoding 264*43ecec16SMauro Carvalho Chehab * @enc_ctrl_handler: control framework handler for encoding 265*43ecec16SMauro Carvalho Chehab * @pm: power management control 266*43ecec16SMauro Carvalho Chehab * @variant: MFC hardware variant information 267*43ecec16SMauro Carvalho Chehab * @num_inst: counter of active MFC instances 268*43ecec16SMauro Carvalho Chehab * @irqlock: lock for operations on videobuf2 queues 269*43ecec16SMauro Carvalho Chehab * @condlock: lock for changing/checking if a context is ready to be 270*43ecec16SMauro Carvalho Chehab * processed 271*43ecec16SMauro Carvalho Chehab * @mfc_mutex: lock for video_device 272*43ecec16SMauro Carvalho Chehab * @int_cond: variable used by the waitqueue 273*43ecec16SMauro Carvalho Chehab * @int_type: type of last interrupt 274*43ecec16SMauro Carvalho Chehab * @int_err: error number for last interrupt 275*43ecec16SMauro Carvalho Chehab * @queue: waitqueue for waiting for completion of device commands 276*43ecec16SMauro Carvalho Chehab * @fw_buf: the firmware buffer data structure 277*43ecec16SMauro Carvalho Chehab * @mem_size: size of the firmware operation memory 278*43ecec16SMauro Carvalho Chehab * @mem_base: base DMA address of the firmware operation memory 279*43ecec16SMauro Carvalho Chehab * @mem_bitmap: bitmap for managing MFC internal buffer allocations 280*43ecec16SMauro Carvalho Chehab * @mem_virt: virtual address of the firmware operation memory 281*43ecec16SMauro Carvalho Chehab * @dma_base: address of the beginning of memory banks 282*43ecec16SMauro Carvalho Chehab * @hw_lock: used for hardware locking 283*43ecec16SMauro Carvalho Chehab * @ctx: array of driver contexts 284*43ecec16SMauro Carvalho Chehab * @curr_ctx: number of the currently running context 285*43ecec16SMauro Carvalho Chehab * @ctx_work_bits: used to mark which contexts are waiting for hardware 286*43ecec16SMauro Carvalho Chehab * @watchdog_cnt: counter for the watchdog 287*43ecec16SMauro Carvalho Chehab * @watchdog_timer: timer for the watchdog 288*43ecec16SMauro Carvalho Chehab * @watchdog_workqueue: workqueue for the watchdog 289*43ecec16SMauro Carvalho Chehab * @watchdog_work: worker for the watchdog 290*43ecec16SMauro Carvalho Chehab * @enter_suspend: flag set when entering suspend 291*43ecec16SMauro Carvalho Chehab * @ctx_buf: common context memory (MFCv6) 292*43ecec16SMauro Carvalho Chehab * @warn_start: hardware error code from which warnings start 293*43ecec16SMauro Carvalho Chehab * @mfc_ops: ops structure holding HW operation function pointers 294*43ecec16SMauro Carvalho Chehab * @mfc_cmds: cmd structure holding HW commands function pointers 295*43ecec16SMauro Carvalho Chehab * @mfc_regs: structure holding MFC registers 296*43ecec16SMauro Carvalho Chehab * @fw_ver: loaded firmware sub-version 297*43ecec16SMauro Carvalho Chehab * @fw_get_done: flag set when request_firmware() is complete and 298*43ecec16SMauro Carvalho Chehab * copied into fw_buf 299*43ecec16SMauro Carvalho Chehab * @risc_on: flag indicates RISC is on or off 300*43ecec16SMauro Carvalho Chehab * 301*43ecec16SMauro Carvalho Chehab */ 302*43ecec16SMauro Carvalho Chehab struct s5p_mfc_dev { 303*43ecec16SMauro Carvalho Chehab struct v4l2_device v4l2_dev; 304*43ecec16SMauro Carvalho Chehab struct video_device *vfd_dec; 305*43ecec16SMauro Carvalho Chehab struct video_device *vfd_enc; 306*43ecec16SMauro Carvalho Chehab struct platform_device *plat_dev; 307*43ecec16SMauro Carvalho Chehab struct device *mem_dev[BANK_CTX_NUM]; 308*43ecec16SMauro Carvalho Chehab void __iomem *regs_base; 309*43ecec16SMauro Carvalho Chehab int irq; 310*43ecec16SMauro Carvalho Chehab struct v4l2_ctrl_handler dec_ctrl_handler; 311*43ecec16SMauro Carvalho Chehab struct v4l2_ctrl_handler enc_ctrl_handler; 312*43ecec16SMauro Carvalho Chehab struct s5p_mfc_pm pm; 313*43ecec16SMauro Carvalho Chehab const struct s5p_mfc_variant *variant; 314*43ecec16SMauro Carvalho Chehab int num_inst; 315*43ecec16SMauro Carvalho Chehab spinlock_t irqlock; /* lock when operating on context */ 316*43ecec16SMauro Carvalho Chehab spinlock_t condlock; /* lock when changing/checking if a context is 317*43ecec16SMauro Carvalho Chehab ready to be processed */ 318*43ecec16SMauro Carvalho Chehab struct mutex mfc_mutex; /* video_device lock */ 319*43ecec16SMauro Carvalho Chehab int int_cond; 320*43ecec16SMauro Carvalho Chehab int int_type; 321*43ecec16SMauro Carvalho Chehab unsigned int int_err; 322*43ecec16SMauro Carvalho Chehab wait_queue_head_t queue; 323*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf fw_buf; 324*43ecec16SMauro Carvalho Chehab size_t mem_size; 325*43ecec16SMauro Carvalho Chehab dma_addr_t mem_base; 326*43ecec16SMauro Carvalho Chehab unsigned long *mem_bitmap; 327*43ecec16SMauro Carvalho Chehab void *mem_virt; 328*43ecec16SMauro Carvalho Chehab dma_addr_t dma_base[BANK_CTX_NUM]; 329*43ecec16SMauro Carvalho Chehab unsigned long hw_lock; 330*43ecec16SMauro Carvalho Chehab struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS]; 331*43ecec16SMauro Carvalho Chehab int curr_ctx; 332*43ecec16SMauro Carvalho Chehab unsigned long ctx_work_bits; 333*43ecec16SMauro Carvalho Chehab atomic_t watchdog_cnt; 334*43ecec16SMauro Carvalho Chehab struct timer_list watchdog_timer; 335*43ecec16SMauro Carvalho Chehab struct workqueue_struct *watchdog_workqueue; 336*43ecec16SMauro Carvalho Chehab struct work_struct watchdog_work; 337*43ecec16SMauro Carvalho Chehab unsigned long enter_suspend; 338*43ecec16SMauro Carvalho Chehab 339*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf ctx_buf; 340*43ecec16SMauro Carvalho Chehab int warn_start; 341*43ecec16SMauro Carvalho Chehab struct s5p_mfc_hw_ops *mfc_ops; 342*43ecec16SMauro Carvalho Chehab struct s5p_mfc_hw_cmds *mfc_cmds; 343*43ecec16SMauro Carvalho Chehab const struct s5p_mfc_regs *mfc_regs; 344*43ecec16SMauro Carvalho Chehab enum s5p_mfc_fw_ver fw_ver; 345*43ecec16SMauro Carvalho Chehab bool fw_get_done; 346*43ecec16SMauro Carvalho Chehab bool risc_on; /* indicates if RISC is on or off */ 347*43ecec16SMauro Carvalho Chehab }; 348*43ecec16SMauro Carvalho Chehab 349*43ecec16SMauro Carvalho Chehab /* 350*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_h264_enc_params - encoding parameters for h264 351*43ecec16SMauro Carvalho Chehab */ 352*43ecec16SMauro Carvalho Chehab struct s5p_mfc_h264_enc_params { 353*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_h264_profile profile; 354*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode; 355*43ecec16SMauro Carvalho Chehab s8 loop_filter_alpha; 356*43ecec16SMauro Carvalho Chehab s8 loop_filter_beta; 357*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_h264_entropy_mode entropy_mode; 358*43ecec16SMauro Carvalho Chehab u8 max_ref_pic; 359*43ecec16SMauro Carvalho Chehab u8 num_ref_pic_4p; 360*43ecec16SMauro Carvalho Chehab int _8x8_transform; 361*43ecec16SMauro Carvalho Chehab int rc_mb_dark; 362*43ecec16SMauro Carvalho Chehab int rc_mb_smooth; 363*43ecec16SMauro Carvalho Chehab int rc_mb_static; 364*43ecec16SMauro Carvalho Chehab int rc_mb_activity; 365*43ecec16SMauro Carvalho Chehab int vui_sar; 366*43ecec16SMauro Carvalho Chehab u8 vui_sar_idc; 367*43ecec16SMauro Carvalho Chehab u16 vui_ext_sar_width; 368*43ecec16SMauro Carvalho Chehab u16 vui_ext_sar_height; 369*43ecec16SMauro Carvalho Chehab int open_gop; 370*43ecec16SMauro Carvalho Chehab u16 open_gop_size; 371*43ecec16SMauro Carvalho Chehab u8 rc_frame_qp; 372*43ecec16SMauro Carvalho Chehab u8 rc_min_qp; 373*43ecec16SMauro Carvalho Chehab u8 rc_max_qp; 374*43ecec16SMauro Carvalho Chehab u8 rc_p_frame_qp; 375*43ecec16SMauro Carvalho Chehab u8 rc_b_frame_qp; 376*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_h264_level level_v4l2; 377*43ecec16SMauro Carvalho Chehab int level; 378*43ecec16SMauro Carvalho Chehab u16 cpb_size; 379*43ecec16SMauro Carvalho Chehab int interlace; 380*43ecec16SMauro Carvalho Chehab u8 hier_qp; 381*43ecec16SMauro Carvalho Chehab u8 hier_qp_type; 382*43ecec16SMauro Carvalho Chehab u8 hier_qp_layer; 383*43ecec16SMauro Carvalho Chehab u8 hier_qp_layer_qp[7]; 384*43ecec16SMauro Carvalho Chehab u8 sei_frame_packing; 385*43ecec16SMauro Carvalho Chehab u8 sei_fp_curr_frame_0; 386*43ecec16SMauro Carvalho Chehab u8 sei_fp_arrangement_type; 387*43ecec16SMauro Carvalho Chehab 388*43ecec16SMauro Carvalho Chehab u8 fmo; 389*43ecec16SMauro Carvalho Chehab u8 fmo_map_type; 390*43ecec16SMauro Carvalho Chehab u8 fmo_slice_grp; 391*43ecec16SMauro Carvalho Chehab u8 fmo_chg_dir; 392*43ecec16SMauro Carvalho Chehab u32 fmo_chg_rate; 393*43ecec16SMauro Carvalho Chehab u32 fmo_run_len[4]; 394*43ecec16SMauro Carvalho Chehab u8 aso; 395*43ecec16SMauro Carvalho Chehab u32 aso_slice_order[8]; 396*43ecec16SMauro Carvalho Chehab }; 397*43ecec16SMauro Carvalho Chehab 398*43ecec16SMauro Carvalho Chehab /* 399*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4 400*43ecec16SMauro Carvalho Chehab */ 401*43ecec16SMauro Carvalho Chehab struct s5p_mfc_mpeg4_enc_params { 402*43ecec16SMauro Carvalho Chehab /* MPEG4 Only */ 403*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_mpeg4_profile profile; 404*43ecec16SMauro Carvalho Chehab int quarter_pixel; 405*43ecec16SMauro Carvalho Chehab /* Common for MPEG4, H263 */ 406*43ecec16SMauro Carvalho Chehab u16 vop_time_res; 407*43ecec16SMauro Carvalho Chehab u16 vop_frm_delta; 408*43ecec16SMauro Carvalho Chehab u8 rc_frame_qp; 409*43ecec16SMauro Carvalho Chehab u8 rc_min_qp; 410*43ecec16SMauro Carvalho Chehab u8 rc_max_qp; 411*43ecec16SMauro Carvalho Chehab u8 rc_p_frame_qp; 412*43ecec16SMauro Carvalho Chehab u8 rc_b_frame_qp; 413*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_mpeg4_level level_v4l2; 414*43ecec16SMauro Carvalho Chehab int level; 415*43ecec16SMauro Carvalho Chehab }; 416*43ecec16SMauro Carvalho Chehab 417*43ecec16SMauro Carvalho Chehab /* 418*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8 419*43ecec16SMauro Carvalho Chehab */ 420*43ecec16SMauro Carvalho Chehab struct s5p_mfc_vp8_enc_params { 421*43ecec16SMauro Carvalho Chehab u8 imd_4x4; 422*43ecec16SMauro Carvalho Chehab enum v4l2_vp8_num_partitions num_partitions; 423*43ecec16SMauro Carvalho Chehab enum v4l2_vp8_num_ref_frames num_ref; 424*43ecec16SMauro Carvalho Chehab u8 filter_level; 425*43ecec16SMauro Carvalho Chehab u8 filter_sharpness; 426*43ecec16SMauro Carvalho Chehab u32 golden_frame_ref_period; 427*43ecec16SMauro Carvalho Chehab enum v4l2_vp8_golden_frame_sel golden_frame_sel; 428*43ecec16SMauro Carvalho Chehab u8 hier_layer; 429*43ecec16SMauro Carvalho Chehab u8 hier_layer_qp[3]; 430*43ecec16SMauro Carvalho Chehab u8 rc_min_qp; 431*43ecec16SMauro Carvalho Chehab u8 rc_max_qp; 432*43ecec16SMauro Carvalho Chehab u8 rc_frame_qp; 433*43ecec16SMauro Carvalho Chehab u8 rc_p_frame_qp; 434*43ecec16SMauro Carvalho Chehab u8 profile; 435*43ecec16SMauro Carvalho Chehab }; 436*43ecec16SMauro Carvalho Chehab 437*43ecec16SMauro Carvalho Chehab struct s5p_mfc_hevc_enc_params { 438*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_hevc_profile profile; 439*43ecec16SMauro Carvalho Chehab int level; 440*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_h264_level level_v4l2; 441*43ecec16SMauro Carvalho Chehab u8 tier; 442*43ecec16SMauro Carvalho Chehab u32 rc_framerate; 443*43ecec16SMauro Carvalho Chehab u8 rc_min_qp; 444*43ecec16SMauro Carvalho Chehab u8 rc_max_qp; 445*43ecec16SMauro Carvalho Chehab u8 rc_lcu_dark; 446*43ecec16SMauro Carvalho Chehab u8 rc_lcu_smooth; 447*43ecec16SMauro Carvalho Chehab u8 rc_lcu_static; 448*43ecec16SMauro Carvalho Chehab u8 rc_lcu_activity; 449*43ecec16SMauro Carvalho Chehab u8 rc_frame_qp; 450*43ecec16SMauro Carvalho Chehab u8 rc_p_frame_qp; 451*43ecec16SMauro Carvalho Chehab u8 rc_b_frame_qp; 452*43ecec16SMauro Carvalho Chehab u8 max_partition_depth; 453*43ecec16SMauro Carvalho Chehab u8 num_refs_for_p; 454*43ecec16SMauro Carvalho Chehab u8 refreshtype; 455*43ecec16SMauro Carvalho Chehab u16 refreshperiod; 456*43ecec16SMauro Carvalho Chehab s32 lf_beta_offset_div2; 457*43ecec16SMauro Carvalho Chehab s32 lf_tc_offset_div2; 458*43ecec16SMauro Carvalho Chehab u8 loopfilter; 459*43ecec16SMauro Carvalho Chehab u8 loopfilter_disable; 460*43ecec16SMauro Carvalho Chehab u8 loopfilter_across; 461*43ecec16SMauro Carvalho Chehab u8 nal_control_length_filed; 462*43ecec16SMauro Carvalho Chehab u8 nal_control_user_ref; 463*43ecec16SMauro Carvalho Chehab u8 nal_control_store_ref; 464*43ecec16SMauro Carvalho Chehab u8 const_intra_period_enable; 465*43ecec16SMauro Carvalho Chehab u8 lossless_cu_enable; 466*43ecec16SMauro Carvalho Chehab u8 wavefront_enable; 467*43ecec16SMauro Carvalho Chehab u8 enable_ltr; 468*43ecec16SMauro Carvalho Chehab u8 hier_qp_enable; 469*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type; 470*43ecec16SMauro Carvalho Chehab u8 num_hier_layer; 471*43ecec16SMauro Carvalho Chehab u8 hier_qp_layer[7]; 472*43ecec16SMauro Carvalho Chehab u32 hier_bit_layer[7]; 473*43ecec16SMauro Carvalho Chehab u8 sign_data_hiding; 474*43ecec16SMauro Carvalho Chehab u8 general_pb_enable; 475*43ecec16SMauro Carvalho Chehab u8 temporal_id_enable; 476*43ecec16SMauro Carvalho Chehab u8 strong_intra_smooth; 477*43ecec16SMauro Carvalho Chehab u8 intra_pu_split_disable; 478*43ecec16SMauro Carvalho Chehab u8 tmv_prediction_disable; 479*43ecec16SMauro Carvalho Chehab u8 max_num_merge_mv; 480*43ecec16SMauro Carvalho Chehab u8 eco_mode_enable; 481*43ecec16SMauro Carvalho Chehab u8 encoding_nostartcode_enable; 482*43ecec16SMauro Carvalho Chehab u8 size_of_length_field; 483*43ecec16SMauro Carvalho Chehab u8 prepend_sps_pps_to_idr; 484*43ecec16SMauro Carvalho Chehab }; 485*43ecec16SMauro Carvalho Chehab 486*43ecec16SMauro Carvalho Chehab /* 487*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_enc_params - general encoding parameters 488*43ecec16SMauro Carvalho Chehab */ 489*43ecec16SMauro Carvalho Chehab struct s5p_mfc_enc_params { 490*43ecec16SMauro Carvalho Chehab u16 width; 491*43ecec16SMauro Carvalho Chehab u16 height; 492*43ecec16SMauro Carvalho Chehab u32 mv_h_range; 493*43ecec16SMauro Carvalho Chehab u32 mv_v_range; 494*43ecec16SMauro Carvalho Chehab 495*43ecec16SMauro Carvalho Chehab u16 gop_size; 496*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_multi_slice_mode slice_mode; 497*43ecec16SMauro Carvalho Chehab u16 slice_mb; 498*43ecec16SMauro Carvalho Chehab u32 slice_bit; 499*43ecec16SMauro Carvalho Chehab u16 intra_refresh_mb; 500*43ecec16SMauro Carvalho Chehab int pad; 501*43ecec16SMauro Carvalho Chehab u8 pad_luma; 502*43ecec16SMauro Carvalho Chehab u8 pad_cb; 503*43ecec16SMauro Carvalho Chehab u8 pad_cr; 504*43ecec16SMauro Carvalho Chehab int rc_frame; 505*43ecec16SMauro Carvalho Chehab int rc_mb; 506*43ecec16SMauro Carvalho Chehab u32 rc_bitrate; 507*43ecec16SMauro Carvalho Chehab u16 rc_reaction_coeff; 508*43ecec16SMauro Carvalho Chehab u16 vbv_size; 509*43ecec16SMauro Carvalho Chehab u32 vbv_delay; 510*43ecec16SMauro Carvalho Chehab 511*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_header_mode seq_hdr_mode; 512*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode; 513*43ecec16SMauro Carvalho Chehab int fixed_target_bit; 514*43ecec16SMauro Carvalho Chehab 515*43ecec16SMauro Carvalho Chehab u8 num_b_frame; 516*43ecec16SMauro Carvalho Chehab u32 rc_framerate_num; 517*43ecec16SMauro Carvalho Chehab u32 rc_framerate_denom; 518*43ecec16SMauro Carvalho Chehab 519*43ecec16SMauro Carvalho Chehab struct { 520*43ecec16SMauro Carvalho Chehab struct s5p_mfc_h264_enc_params h264; 521*43ecec16SMauro Carvalho Chehab struct s5p_mfc_mpeg4_enc_params mpeg4; 522*43ecec16SMauro Carvalho Chehab struct s5p_mfc_vp8_enc_params vp8; 523*43ecec16SMauro Carvalho Chehab struct s5p_mfc_hevc_enc_params hevc; 524*43ecec16SMauro Carvalho Chehab } codec; 525*43ecec16SMauro Carvalho Chehab 526*43ecec16SMauro Carvalho Chehab }; 527*43ecec16SMauro Carvalho Chehab 528*43ecec16SMauro Carvalho Chehab /* 529*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_codec_ops - codec ops, used by encoding 530*43ecec16SMauro Carvalho Chehab */ 531*43ecec16SMauro Carvalho Chehab struct s5p_mfc_codec_ops { 532*43ecec16SMauro Carvalho Chehab /* initialization routines */ 533*43ecec16SMauro Carvalho Chehab int (*pre_seq_start) (struct s5p_mfc_ctx *ctx); 534*43ecec16SMauro Carvalho Chehab int (*post_seq_start) (struct s5p_mfc_ctx *ctx); 535*43ecec16SMauro Carvalho Chehab /* execution routines */ 536*43ecec16SMauro Carvalho Chehab int (*pre_frame_start) (struct s5p_mfc_ctx *ctx); 537*43ecec16SMauro Carvalho Chehab int (*post_frame_start) (struct s5p_mfc_ctx *ctx); 538*43ecec16SMauro Carvalho Chehab }; 539*43ecec16SMauro Carvalho Chehab 540*43ecec16SMauro Carvalho Chehab #define call_cop(c, op, args...) \ 541*43ecec16SMauro Carvalho Chehab (((c)->c_ops->op) ? \ 542*43ecec16SMauro Carvalho Chehab ((c)->c_ops->op(args)) : 0) 543*43ecec16SMauro Carvalho Chehab 544*43ecec16SMauro Carvalho Chehab /** 545*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_ctx - This struct contains the instance context 546*43ecec16SMauro Carvalho Chehab * 547*43ecec16SMauro Carvalho Chehab * @dev: pointer to the s5p_mfc_dev of the device 548*43ecec16SMauro Carvalho Chehab * @fh: struct v4l2_fh 549*43ecec16SMauro Carvalho Chehab * @num: number of the context that this structure describes 550*43ecec16SMauro Carvalho Chehab * @int_cond: variable used by the waitqueue 551*43ecec16SMauro Carvalho Chehab * @int_type: type of the last interrupt 552*43ecec16SMauro Carvalho Chehab * @int_err: error number received from MFC hw in the interrupt 553*43ecec16SMauro Carvalho Chehab * @queue: waitqueue that can be used to wait for this context to 554*43ecec16SMauro Carvalho Chehab * finish 555*43ecec16SMauro Carvalho Chehab * @src_fmt: source pixelformat information 556*43ecec16SMauro Carvalho Chehab * @dst_fmt: destination pixelformat information 557*43ecec16SMauro Carvalho Chehab * @vq_src: vb2 queue for source buffers 558*43ecec16SMauro Carvalho Chehab * @vq_dst: vb2 queue for destination buffers 559*43ecec16SMauro Carvalho Chehab * @src_queue: driver internal queue for source buffers 560*43ecec16SMauro Carvalho Chehab * @dst_queue: driver internal queue for destination buffers 561*43ecec16SMauro Carvalho Chehab * @src_queue_cnt: number of buffers queued on the source internal queue 562*43ecec16SMauro Carvalho Chehab * @dst_queue_cnt: number of buffers queued on the dest internal queue 563*43ecec16SMauro Carvalho Chehab * @type: type of the instance - decoder or encoder 564*43ecec16SMauro Carvalho Chehab * @state: state of the context 565*43ecec16SMauro Carvalho Chehab * @inst_no: number of hw instance associated with the context 566*43ecec16SMauro Carvalho Chehab * @img_width: width of the image that is decoded or encoded 567*43ecec16SMauro Carvalho Chehab * @img_height: height of the image that is decoded or encoded 568*43ecec16SMauro Carvalho Chehab * @buf_width: width of the buffer for processed image 569*43ecec16SMauro Carvalho Chehab * @buf_height: height of the buffer for processed image 570*43ecec16SMauro Carvalho Chehab * @luma_size: size of a luma plane 571*43ecec16SMauro Carvalho Chehab * @chroma_size: size of a chroma plane 572*43ecec16SMauro Carvalho Chehab * @mv_size: size of a motion vectors buffer 573*43ecec16SMauro Carvalho Chehab * @consumed_stream: number of bytes that have been used so far from the 574*43ecec16SMauro Carvalho Chehab * decoding buffer 575*43ecec16SMauro Carvalho Chehab * @dpb_flush_flag: flag used to indicate that a DPB buffers are being 576*43ecec16SMauro Carvalho Chehab * flushed 577*43ecec16SMauro Carvalho Chehab * @head_processed: flag mentioning whether the header data is processed 578*43ecec16SMauro Carvalho Chehab * completely or not 579*43ecec16SMauro Carvalho Chehab * @bank1: handle to memory allocated for temporary buffers from 580*43ecec16SMauro Carvalho Chehab * memory bank 1 581*43ecec16SMauro Carvalho Chehab * @bank2: handle to memory allocated for temporary buffers from 582*43ecec16SMauro Carvalho Chehab * memory bank 2 583*43ecec16SMauro Carvalho Chehab * @capture_state: state of the capture buffers queue 584*43ecec16SMauro Carvalho Chehab * @output_state: state of the output buffers queue 585*43ecec16SMauro Carvalho Chehab * @src_bufs: information on allocated source buffers 586*43ecec16SMauro Carvalho Chehab * @src_bufs_cnt: number of allocated source buffers 587*43ecec16SMauro Carvalho Chehab * @dst_bufs: information on allocated destination buffers 588*43ecec16SMauro Carvalho Chehab * @dst_bufs_cnt: number of allocated destination buffers 589*43ecec16SMauro Carvalho Chehab * @sequence: counter for the sequence number for v4l2 590*43ecec16SMauro Carvalho Chehab * @dec_dst_flag: flags for buffers queued in the hardware 591*43ecec16SMauro Carvalho Chehab * @dec_src_buf_size: size of the buffer for source buffers in decoding 592*43ecec16SMauro Carvalho Chehab * @codec_mode: number of codec mode used by MFC hw 593*43ecec16SMauro Carvalho Chehab * @slice_interface: slice interface flag 594*43ecec16SMauro Carvalho Chehab * @loop_filter_mpeg4: loop filter for MPEG4 flag 595*43ecec16SMauro Carvalho Chehab * @display_delay: value of the display delay for H264 596*43ecec16SMauro Carvalho Chehab * @display_delay_enable: display delay for H264 enable flag 597*43ecec16SMauro Carvalho Chehab * @after_packed_pb: flag used to track buffer when stream is in 598*43ecec16SMauro Carvalho Chehab * Packed PB format 599*43ecec16SMauro Carvalho Chehab * @sei_fp_parse: enable/disable parsing of frame packing SEI information 600*43ecec16SMauro Carvalho Chehab * @pb_count: count of the DPB buffers required by MFC hw 601*43ecec16SMauro Carvalho Chehab * @total_dpb_count: count of DPB buffers with additional buffers 602*43ecec16SMauro Carvalho Chehab * requested by the application 603*43ecec16SMauro Carvalho Chehab * @ctx: context buffer information 604*43ecec16SMauro Carvalho Chehab * @dsc: descriptor buffer information 605*43ecec16SMauro Carvalho Chehab * @shm: shared memory buffer information 606*43ecec16SMauro Carvalho Chehab * @mv_count: number of MV buffers allocated for decoding 607*43ecec16SMauro Carvalho Chehab * @enc_params: encoding parameters for MFC 608*43ecec16SMauro Carvalho Chehab * @enc_dst_buf_size: size of the buffers for encoder output 609*43ecec16SMauro Carvalho Chehab * @luma_dpb_size: dpb buffer size for luma 610*43ecec16SMauro Carvalho Chehab * @chroma_dpb_size: dpb buffer size for chroma 611*43ecec16SMauro Carvalho Chehab * @me_buffer_size: size of the motion estimation buffer 612*43ecec16SMauro Carvalho Chehab * @tmv_buffer_size: size of temporal predictor motion vector buffer 613*43ecec16SMauro Carvalho Chehab * @frame_type: used to force the type of the next encoded frame 614*43ecec16SMauro Carvalho Chehab * @ref_queue: list of the reference buffers for encoding 615*43ecec16SMauro Carvalho Chehab * @force_frame_type: encoder's frame type forcing control 616*43ecec16SMauro Carvalho Chehab * @ref_queue_cnt: number of the buffers in the reference list 617*43ecec16SMauro Carvalho Chehab * @slice_size: slice size 618*43ecec16SMauro Carvalho Chehab * @slice_mode: mode of dividing frames into slices 619*43ecec16SMauro Carvalho Chehab * @c_ops: ops for encoding 620*43ecec16SMauro Carvalho Chehab * @ctrls: array of controls, used when adding controls to the 621*43ecec16SMauro Carvalho Chehab * v4l2 control framework 622*43ecec16SMauro Carvalho Chehab * @ctrl_handler: handler for v4l2 framework 623*43ecec16SMauro Carvalho Chehab * @scratch_buf_size: scratch buffer size 624*43ecec16SMauro Carvalho Chehab */ 625*43ecec16SMauro Carvalho Chehab struct s5p_mfc_ctx { 626*43ecec16SMauro Carvalho Chehab struct s5p_mfc_dev *dev; 627*43ecec16SMauro Carvalho Chehab struct v4l2_fh fh; 628*43ecec16SMauro Carvalho Chehab 629*43ecec16SMauro Carvalho Chehab int num; 630*43ecec16SMauro Carvalho Chehab 631*43ecec16SMauro Carvalho Chehab int int_cond; 632*43ecec16SMauro Carvalho Chehab int int_type; 633*43ecec16SMauro Carvalho Chehab unsigned int int_err; 634*43ecec16SMauro Carvalho Chehab wait_queue_head_t queue; 635*43ecec16SMauro Carvalho Chehab 636*43ecec16SMauro Carvalho Chehab struct s5p_mfc_fmt *src_fmt; 637*43ecec16SMauro Carvalho Chehab struct s5p_mfc_fmt *dst_fmt; 638*43ecec16SMauro Carvalho Chehab 639*43ecec16SMauro Carvalho Chehab struct vb2_queue vq_src; 640*43ecec16SMauro Carvalho Chehab struct vb2_queue vq_dst; 641*43ecec16SMauro Carvalho Chehab 642*43ecec16SMauro Carvalho Chehab struct list_head src_queue; 643*43ecec16SMauro Carvalho Chehab struct list_head dst_queue; 644*43ecec16SMauro Carvalho Chehab 645*43ecec16SMauro Carvalho Chehab unsigned int src_queue_cnt; 646*43ecec16SMauro Carvalho Chehab unsigned int dst_queue_cnt; 647*43ecec16SMauro Carvalho Chehab 648*43ecec16SMauro Carvalho Chehab enum s5p_mfc_inst_type type; 649*43ecec16SMauro Carvalho Chehab enum s5p_mfc_inst_state state; 650*43ecec16SMauro Carvalho Chehab int inst_no; 651*43ecec16SMauro Carvalho Chehab 652*43ecec16SMauro Carvalho Chehab /* Image parameters */ 653*43ecec16SMauro Carvalho Chehab int img_width; 654*43ecec16SMauro Carvalho Chehab int img_height; 655*43ecec16SMauro Carvalho Chehab int buf_width; 656*43ecec16SMauro Carvalho Chehab int buf_height; 657*43ecec16SMauro Carvalho Chehab 658*43ecec16SMauro Carvalho Chehab int luma_size; 659*43ecec16SMauro Carvalho Chehab int chroma_size; 660*43ecec16SMauro Carvalho Chehab int mv_size; 661*43ecec16SMauro Carvalho Chehab 662*43ecec16SMauro Carvalho Chehab unsigned long consumed_stream; 663*43ecec16SMauro Carvalho Chehab 664*43ecec16SMauro Carvalho Chehab unsigned int dpb_flush_flag; 665*43ecec16SMauro Carvalho Chehab unsigned int head_processed; 666*43ecec16SMauro Carvalho Chehab 667*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf bank1; 668*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf bank2; 669*43ecec16SMauro Carvalho Chehab 670*43ecec16SMauro Carvalho Chehab enum s5p_mfc_queue_state capture_state; 671*43ecec16SMauro Carvalho Chehab enum s5p_mfc_queue_state output_state; 672*43ecec16SMauro Carvalho Chehab 673*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS]; 674*43ecec16SMauro Carvalho Chehab int src_bufs_cnt; 675*43ecec16SMauro Carvalho Chehab struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS]; 676*43ecec16SMauro Carvalho Chehab int dst_bufs_cnt; 677*43ecec16SMauro Carvalho Chehab 678*43ecec16SMauro Carvalho Chehab unsigned int sequence; 679*43ecec16SMauro Carvalho Chehab unsigned long dec_dst_flag; 680*43ecec16SMauro Carvalho Chehab size_t dec_src_buf_size; 681*43ecec16SMauro Carvalho Chehab 682*43ecec16SMauro Carvalho Chehab /* Control values */ 683*43ecec16SMauro Carvalho Chehab int codec_mode; 684*43ecec16SMauro Carvalho Chehab int slice_interface; 685*43ecec16SMauro Carvalho Chehab int loop_filter_mpeg4; 686*43ecec16SMauro Carvalho Chehab int display_delay; 687*43ecec16SMauro Carvalho Chehab int display_delay_enable; 688*43ecec16SMauro Carvalho Chehab int after_packed_pb; 689*43ecec16SMauro Carvalho Chehab int sei_fp_parse; 690*43ecec16SMauro Carvalho Chehab 691*43ecec16SMauro Carvalho Chehab int pb_count; 692*43ecec16SMauro Carvalho Chehab int total_dpb_count; 693*43ecec16SMauro Carvalho Chehab int mv_count; 694*43ecec16SMauro Carvalho Chehab /* Buffers */ 695*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf ctx; 696*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf dsc; 697*43ecec16SMauro Carvalho Chehab struct s5p_mfc_priv_buf shm; 698*43ecec16SMauro Carvalho Chehab 699*43ecec16SMauro Carvalho Chehab struct s5p_mfc_enc_params enc_params; 700*43ecec16SMauro Carvalho Chehab 701*43ecec16SMauro Carvalho Chehab size_t enc_dst_buf_size; 702*43ecec16SMauro Carvalho Chehab size_t luma_dpb_size; 703*43ecec16SMauro Carvalho Chehab size_t chroma_dpb_size; 704*43ecec16SMauro Carvalho Chehab size_t me_buffer_size; 705*43ecec16SMauro Carvalho Chehab size_t tmv_buffer_size; 706*43ecec16SMauro Carvalho Chehab 707*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type; 708*43ecec16SMauro Carvalho Chehab 709*43ecec16SMauro Carvalho Chehab struct list_head ref_queue; 710*43ecec16SMauro Carvalho Chehab unsigned int ref_queue_cnt; 711*43ecec16SMauro Carvalho Chehab 712*43ecec16SMauro Carvalho Chehab enum v4l2_mpeg_video_multi_slice_mode slice_mode; 713*43ecec16SMauro Carvalho Chehab union { 714*43ecec16SMauro Carvalho Chehab unsigned int mb; 715*43ecec16SMauro Carvalho Chehab unsigned int bits; 716*43ecec16SMauro Carvalho Chehab } slice_size; 717*43ecec16SMauro Carvalho Chehab 718*43ecec16SMauro Carvalho Chehab const struct s5p_mfc_codec_ops *c_ops; 719*43ecec16SMauro Carvalho Chehab 720*43ecec16SMauro Carvalho Chehab struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS]; 721*43ecec16SMauro Carvalho Chehab struct v4l2_ctrl_handler ctrl_handler; 722*43ecec16SMauro Carvalho Chehab size_t scratch_buf_size; 723*43ecec16SMauro Carvalho Chehab }; 724*43ecec16SMauro Carvalho Chehab 725*43ecec16SMauro Carvalho Chehab /* 726*43ecec16SMauro Carvalho Chehab * struct s5p_mfc_fmt - structure used to store information about pixelformats 727*43ecec16SMauro Carvalho Chehab * used by the MFC 728*43ecec16SMauro Carvalho Chehab */ 729*43ecec16SMauro Carvalho Chehab struct s5p_mfc_fmt { 730*43ecec16SMauro Carvalho Chehab u32 fourcc; 731*43ecec16SMauro Carvalho Chehab u32 codec_mode; 732*43ecec16SMauro Carvalho Chehab enum s5p_mfc_fmt_type type; 733*43ecec16SMauro Carvalho Chehab u32 num_planes; 734*43ecec16SMauro Carvalho Chehab u32 versions; 735*43ecec16SMauro Carvalho Chehab u32 flags; 736*43ecec16SMauro Carvalho Chehab }; 737*43ecec16SMauro Carvalho Chehab 738*43ecec16SMauro Carvalho Chehab /* 739*43ecec16SMauro Carvalho Chehab * struct mfc_control - structure used to store information about MFC controls 740*43ecec16SMauro Carvalho Chehab * it is used to initialize the control framework. 741*43ecec16SMauro Carvalho Chehab */ 742*43ecec16SMauro Carvalho Chehab struct mfc_control { 743*43ecec16SMauro Carvalho Chehab __u32 id; 744*43ecec16SMauro Carvalho Chehab enum v4l2_ctrl_type type; 745*43ecec16SMauro Carvalho Chehab __u8 name[32]; /* Whatever */ 746*43ecec16SMauro Carvalho Chehab __s32 minimum; /* Note signedness */ 747*43ecec16SMauro Carvalho Chehab __s32 maximum; 748*43ecec16SMauro Carvalho Chehab __s32 step; 749*43ecec16SMauro Carvalho Chehab __u32 menu_skip_mask; 750*43ecec16SMauro Carvalho Chehab __s32 default_value; 751*43ecec16SMauro Carvalho Chehab __u32 flags; 752*43ecec16SMauro Carvalho Chehab __u32 reserved[2]; 753*43ecec16SMauro Carvalho Chehab __u8 is_volatile; 754*43ecec16SMauro Carvalho Chehab }; 755*43ecec16SMauro Carvalho Chehab 756*43ecec16SMauro Carvalho Chehab /* Macro for making hardware specific calls */ 757*43ecec16SMauro Carvalho Chehab #define s5p_mfc_hw_call(f, op, args...) \ 758*43ecec16SMauro Carvalho Chehab ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV)) 759*43ecec16SMauro Carvalho Chehab 760*43ecec16SMauro Carvalho Chehab #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh) 761*43ecec16SMauro Carvalho Chehab #define ctrl_to_ctx(__ctrl) \ 762*43ecec16SMauro Carvalho Chehab container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler) 763*43ecec16SMauro Carvalho Chehab 764*43ecec16SMauro Carvalho Chehab void clear_work_bit(struct s5p_mfc_ctx *ctx); 765*43ecec16SMauro Carvalho Chehab void set_work_bit(struct s5p_mfc_ctx *ctx); 766*43ecec16SMauro Carvalho Chehab void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 767*43ecec16SMauro Carvalho Chehab void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx); 768*43ecec16SMauro Carvalho Chehab int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev); 769*43ecec16SMauro Carvalho Chehab void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); 770*43ecec16SMauro Carvalho Chehab 771*43ecec16SMauro Carvalho Chehab #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \ 772*43ecec16SMauro Carvalho Chehab (dev->variant->port_num ? 1 : 0) : 0) : 0) 773*43ecec16SMauro Carvalho Chehab #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0) 774*43ecec16SMauro Carvalho Chehab #define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0) 775*43ecec16SMauro Carvalho Chehab #define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0) 776*43ecec16SMauro Carvalho Chehab #define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0) 777*43ecec16SMauro Carvalho Chehab #define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0) 778*43ecec16SMauro Carvalho Chehab #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev)) 779*43ecec16SMauro Carvalho Chehab 780*43ecec16SMauro Carvalho Chehab #define MFC_V5_BIT BIT(0) 781*43ecec16SMauro Carvalho Chehab #define MFC_V6_BIT BIT(1) 782*43ecec16SMauro Carvalho Chehab #define MFC_V7_BIT BIT(2) 783*43ecec16SMauro Carvalho Chehab #define MFC_V8_BIT BIT(3) 784*43ecec16SMauro Carvalho Chehab #define MFC_V10_BIT BIT(5) 785*43ecec16SMauro Carvalho Chehab 786*43ecec16SMauro Carvalho Chehab #define MFC_V5PLUS_BITS (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \ 787*43ecec16SMauro Carvalho Chehab MFC_V8_BIT | MFC_V10_BIT) 788*43ecec16SMauro Carvalho Chehab #define MFC_V6PLUS_BITS (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \ 789*43ecec16SMauro Carvalho Chehab MFC_V10_BIT) 790*43ecec16SMauro Carvalho Chehab #define MFC_V7PLUS_BITS (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT) 791*43ecec16SMauro Carvalho Chehab 792*43ecec16SMauro Carvalho Chehab #endif /* S5P_MFC_COMMON_H_ */ 793