1*43ecec16SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0 */ 2*43ecec16SMauro Carvalho Chehab /* 3*43ecec16SMauro Carvalho Chehab * 4*43ecec16SMauro Carvalho Chehab * Copyright (c) 2017 Samsung Electronics Co., Ltd. 5*43ecec16SMauro Carvalho Chehab * http://www.samsung.com/ 6*43ecec16SMauro Carvalho Chehab * 7*43ecec16SMauro Carvalho Chehab * Register definition file for Samsung MFC V10.x Interface (FIMV) driver 8*43ecec16SMauro Carvalho Chehab * 9*43ecec16SMauro Carvalho Chehab */ 10*43ecec16SMauro Carvalho Chehab 11*43ecec16SMauro Carvalho Chehab #ifndef _REGS_MFC_V10_H 12*43ecec16SMauro Carvalho Chehab #define _REGS_MFC_V10_H 13*43ecec16SMauro Carvalho Chehab 14*43ecec16SMauro Carvalho Chehab #include <linux/sizes.h> 15*43ecec16SMauro Carvalho Chehab #include "regs-mfc-v8.h" 16*43ecec16SMauro Carvalho Chehab 17*43ecec16SMauro Carvalho Chehab /* MFCv10 register definitions*/ 18*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_MFC_CLOCK_OFF_V10 0x7120 19*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_MFC_STATE_V10 0x7124 20*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_STATIC_BUFFER_ADDR_V10 0xF570 21*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_D_STATIC_BUFFER_SIZE_V10 0xF574 22*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_NUM_T_LAYER_V10 0xFBAC 23*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10 0xFBB0 24*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER1_V10 0xFBB4 25*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER2_V10 0xFBB8 26*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER3_V10 0xFBBC 27*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER4_V10 0xFBC0 28*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER5_V10 0xFBC4 29*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_QP_LAYER6_V10 0xFBC8 30*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10 0xFD18 31*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER1_V10 0xFD1C 32*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER2_V10 0xFD20 33*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER3_V10 0xFD24 34*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER4_V10 0xFD28 35*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER5_V10 0xFD2C 36*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER6_V10 0xFD30 37*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HEVC_OPTIONS_V10 0xFDD4 38*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10 0xFDD8 39*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HEVC_CHROMA_QP_OFFSET_V10 0xFDDC 40*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10 0xFDE0 41*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10 0xFDE4 42*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_E_HEVC_NAL_CONTROL_V10 0xFDE8 43*43ecec16SMauro Carvalho Chehab 44*43ecec16SMauro Carvalho Chehab /* MFCv10 Context buffer sizes */ 45*43ecec16SMauro Carvalho Chehab #define MFC_CTX_BUF_SIZE_V10 (30 * SZ_1K) 46*43ecec16SMauro Carvalho Chehab #define MFC_H264_DEC_CTX_BUF_SIZE_V10 (2 * SZ_1M) 47*43ecec16SMauro Carvalho Chehab #define MFC_OTHER_DEC_CTX_BUF_SIZE_V10 (20 * SZ_1K) 48*43ecec16SMauro Carvalho Chehab #define MFC_H264_ENC_CTX_BUF_SIZE_V10 (100 * SZ_1K) 49*43ecec16SMauro Carvalho Chehab #define MFC_HEVC_ENC_CTX_BUF_SIZE_V10 (30 * SZ_1K) 50*43ecec16SMauro Carvalho Chehab #define MFC_OTHER_ENC_CTX_BUF_SIZE_V10 (15 * SZ_1K) 51*43ecec16SMauro Carvalho Chehab 52*43ecec16SMauro Carvalho Chehab /* MFCv10 variant defines */ 53*43ecec16SMauro Carvalho Chehab #define MAX_FW_SIZE_V10 (SZ_1M) 54*43ecec16SMauro Carvalho Chehab #define MAX_CPB_SIZE_V10 (3 * SZ_1M) 55*43ecec16SMauro Carvalho Chehab #define MFC_VERSION_V10 0xA0 56*43ecec16SMauro Carvalho Chehab #define MFC_NUM_PORTS_V10 1 57*43ecec16SMauro Carvalho Chehab 58*43ecec16SMauro Carvalho Chehab /* MFCv10 codec defines*/ 59*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_CODEC_HEVC_DEC 17 60*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_CODEC_VP9_DEC 18 61*43ecec16SMauro Carvalho Chehab #define S5P_FIMV_CODEC_HEVC_ENC 26 62*43ecec16SMauro Carvalho Chehab 63*43ecec16SMauro Carvalho Chehab /* Decoder buffer size for MFC v10 */ 64*43ecec16SMauro Carvalho Chehab #define DEC_VP9_STATIC_BUFFER_SIZE 20480 65*43ecec16SMauro Carvalho Chehab 66*43ecec16SMauro Carvalho Chehab /* Encoder buffer size for MFC v10.0 */ 67*43ecec16SMauro Carvalho Chehab #define ENC_V100_BASE_SIZE(x, y) \ 68*43ecec16SMauro Carvalho Chehab (((x + 3) * (y + 3) * 8) \ 69*43ecec16SMauro Carvalho Chehab + ((y * 64) + 1280) * DIV_ROUND_UP(x, 8)) 70*43ecec16SMauro Carvalho Chehab 71*43ecec16SMauro Carvalho Chehab #define ENC_V100_H264_ME_SIZE(x, y) \ 72*43ecec16SMauro Carvalho Chehab (ENC_V100_BASE_SIZE(x, y) \ 73*43ecec16SMauro Carvalho Chehab + (DIV_ROUND_UP(x * y, 64) * 32)) 74*43ecec16SMauro Carvalho Chehab 75*43ecec16SMauro Carvalho Chehab #define ENC_V100_MPEG4_ME_SIZE(x, y) \ 76*43ecec16SMauro Carvalho Chehab (ENC_V100_BASE_SIZE(x, y) \ 77*43ecec16SMauro Carvalho Chehab + (DIV_ROUND_UP(x * y, 128) * 16)) 78*43ecec16SMauro Carvalho Chehab 79*43ecec16SMauro Carvalho Chehab #define ENC_V100_VP8_ME_SIZE(x, y) \ 80*43ecec16SMauro Carvalho Chehab ENC_V100_BASE_SIZE(x, y) 81*43ecec16SMauro Carvalho Chehab 82*43ecec16SMauro Carvalho Chehab #define ENC_V100_HEVC_ME_SIZE(x, y) \ 83*43ecec16SMauro Carvalho Chehab (((x + 3) * (y + 3) * 32) \ 84*43ecec16SMauro Carvalho Chehab + ((y * 128) + 1280) * DIV_ROUND_UP(x, 4)) 85*43ecec16SMauro Carvalho Chehab 86*43ecec16SMauro Carvalho Chehab #endif /*_REGS_MFC_V10_H*/ 87*43ecec16SMauro Carvalho Chehab 88