1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver 4 * 5 * Copyright (C) 2013 Samsung Electronics Co., Ltd. 6 * 7 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com> 8 * Younghwan Joo <yhwan.joo@samsung.com> 9 */ 10 #ifndef FIMC_IS_REG_H_ 11 #define FIMC_IS_REG_H_ 12 13 /* WDT_ISP register */ 14 #define REG_WDT_ISP 0x00170000 15 16 /* MCUCTL registers base offset */ 17 #define MCUCTL_BASE 0x00180000 18 19 /* MCU Controller Register */ 20 #define MCUCTL_REG_MCUCTRL (MCUCTL_BASE + 0x00) 21 #define MCUCTRL_MSWRST (1 << 0) 22 23 /* Boot Base Offset Address Register */ 24 #define MCUCTL_REG_BBOAR (MCUCTL_BASE + 0x04) 25 26 /* Interrupt Generation Register 0 from Host CPU to VIC */ 27 #define MCUCTL_REG_INTGR0 (MCUCTL_BASE + 0x08) 28 /* __n = 0...9 */ 29 #define INTGR0_INTGC(__n) (1 << ((__n) + 16)) 30 /* __n = 0...5 */ 31 #define INTGR0_INTGD(__n) (1 << (__n)) 32 33 /* Interrupt Clear Register 0 from Host CPU to VIC */ 34 #define MCUCTL_REG_INTCR0 (MCUCTL_BASE + 0x0c) 35 /* __n = 0...9 */ 36 #define INTCR0_INTGC(__n) (1 << ((__n) + 16)) 37 /* __n = 0...5 */ 38 #define INTCR0_INTCD(__n) (1 << ((__n) + 16)) 39 40 /* Interrupt Mask Register 0 from Host CPU to VIC */ 41 #define MCUCTL_REG_INTMR0 (MCUCTL_BASE + 0x10) 42 /* __n = 0...9 */ 43 #define INTMR0_INTMC(__n) (1 << ((__n) + 16)) 44 /* __n = 0...5 */ 45 #define INTMR0_INTMD(__n) (1 << (__n)) 46 47 /* Interrupt Status Register 0 from Host CPU to VIC */ 48 #define MCUCTL_REG_INTSR0 (MCUCTL_BASE + 0x14) 49 /* __n (bit number) = 0...4 */ 50 #define INTSR0_GET_INTSD(x, __n) (((x) >> (__n)) & 0x1) 51 /* __n (bit number) = 0...9 */ 52 #define INTSR0_GET_INTSC(x, __n) (((x) >> ((__n) + 16)) & 0x1) 53 54 /* Interrupt Mask Status Register 0 from Host CPU to VIC */ 55 #define MCUCTL_REG_INTMSR0 (MCUCTL_BASE + 0x18) 56 /* __n (bit number) = 0...4 */ 57 #define INTMSR0_GET_INTMSD(x, __n) (((x) >> (__n)) & 0x1) 58 /* __n (bit number) = 0...9 */ 59 #define INTMSR0_GET_INTMSC(x, __n) (((x) >> ((__n) + 16)) & 0x1) 60 61 /* Interrupt Generation Register 1 from ISP CPU to Host IC */ 62 #define MCUCTL_REG_INTGR1 (MCUCTL_BASE + 0x1c) 63 /* __n = 0...9 */ 64 #define INTGR1_INTGC(__n) (1 << (__n)) 65 66 /* Interrupt Clear Register 1 from ISP CPU to Host IC */ 67 #define MCUCTL_REG_INTCR1 (MCUCTL_BASE + 0x20) 68 /* __n = 0...9 */ 69 #define INTCR1_INTCC(__n) (1 << (__n)) 70 71 /* Interrupt Mask Register 1 from ISP CPU to Host IC */ 72 #define MCUCTL_REG_INTMR1 (MCUCTL_BASE + 0x24) 73 /* __n = 0...9 */ 74 #define INTMR1_INTMC(__n) (1 << (__n)) 75 76 /* Interrupt Status Register 1 from ISP CPU to Host IC */ 77 #define MCUCTL_REG_INTSR1 (MCUCTL_BASE + 0x28) 78 /* Interrupt Mask Status Register 1 from ISP CPU to Host IC */ 79 #define MCUCTL_REG_INTMSR1 (MCUCTL_BASE + 0x2c) 80 81 /* Interrupt Clear Register 2 from ISP BLK's interrupts to Host IC */ 82 #define MCUCTL_REG_INTCR2 (MCUCTL_BASE + 0x30) 83 /* __n = 0...5 */ 84 #define INTCR2_INTCC(__n) (1 << ((__n) + 16)) 85 86 /* Interrupt Mask Register 2 from ISP BLK's interrupts to Host IC */ 87 #define MCUCTL_REG_INTMR2 (MCUCTL_BASE + 0x34) 88 /* __n = 0...25 */ 89 #define INTMR2_INTMCIS(__n) (1 << (__n)) 90 91 /* Interrupt Status Register 2 from ISP BLK's interrupts to Host IC */ 92 #define MCUCTL_REG_INTSR2 (MCUCTL_BASE + 0x38) 93 /* Interrupt Mask Status Register 2 from ISP BLK's interrupts to Host IC */ 94 #define MCUCTL_REG_INTMSR2 (MCUCTL_BASE + 0x3c) 95 96 /* General Purpose Output Control Register (0~17) */ 97 #define MCUCTL_REG_GPOCTLR (MCUCTL_BASE + 0x40) 98 /* __n = 0...17 */ 99 #define GPOCTLR_GPOG(__n) (1 << (__n)) 100 101 /* General Purpose Pad Output Enable Register (0~17) */ 102 #define MCUCTL_REG_GPOENCTLR (MCUCTL_BASE + 0x44) 103 /* __n = 0...17 */ 104 #define GPOENCTLR_GPOEN(__n) (1 << (__n)) 105 106 /* General Purpose Input Control Register (0~17) */ 107 #define MCUCTL_REG_GPICTLR (MCUCTL_BASE + 0x48) 108 109 /* Shared registers between ISP CPU and the host CPU - ISSRxx */ 110 111 /* ISSR(1): Command Host -> IS */ 112 /* ISSR(1): Sensor ID for Command, ISSR2...5 = Parameter 1...4 */ 113 114 /* ISSR(10): Reply IS -> Host */ 115 /* ISSR(11): Sensor ID for Reply, ISSR12...15 = Parameter 1...4 */ 116 117 /* ISSR(20): ISP_FRAME_DONE : SENSOR ID */ 118 /* ISSR(21): ISP_FRAME_DONE : PARAMETER 1 */ 119 120 /* ISSR(24): SCALERC_FRAME_DONE : SENSOR ID */ 121 /* ISSR(25): SCALERC_FRAME_DONE : PARAMETER 1 */ 122 123 /* ISSR(28): 3DNR_FRAME_DONE : SENSOR ID */ 124 /* ISSR(29): 3DNR_FRAME_DONE : PARAMETER 1 */ 125 126 /* ISSR(32): SCALERP_FRAME_DONE : SENSOR ID */ 127 /* ISSR(33): SCALERP_FRAME_DONE : PARAMETER 1 */ 128 129 /* __n = 0...63 */ 130 #define MCUCTL_REG_ISSR(__n) (MCUCTL_BASE + 0x80 + ((__n) * 4)) 131 132 /* PMU ISP register offsets */ 133 #define REG_CMU_RESET_ISP_SYS_PWR_REG 0x1174 134 #define REG_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13b8 135 #define REG_PMU_ISP_ARM_SYS 0x1050 136 #define REG_PMU_ISP_ARM_CONFIGURATION 0x2280 137 #define REG_PMU_ISP_ARM_STATUS 0x2284 138 #define REG_PMU_ISP_ARM_OPTION 0x2288 139 140 void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int bit); 141 void fimc_is_fw_clear_irq2(struct fimc_is *is); 142 int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num); 143 144 void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is); 145 int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is); 146 void fimc_is_hw_set_sensor_num(struct fimc_is *is); 147 void fimc_is_hw_set_isp_buf_mask(struct fimc_is *is, unsigned int mask); 148 void fimc_is_hw_stream_on(struct fimc_is *is); 149 void fimc_is_hw_stream_off(struct fimc_is *is); 150 int fimc_is_hw_set_param(struct fimc_is *is); 151 int fimc_is_hw_change_mode(struct fimc_is *is); 152 153 void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index); 154 void fimc_is_hw_get_setfile_addr(struct fimc_is *is); 155 void fimc_is_hw_load_setfile(struct fimc_is *is); 156 void fimc_is_hw_subip_power_off(struct fimc_is *is); 157 158 int fimc_is_itf_s_param(struct fimc_is *is, bool update); 159 int fimc_is_itf_mode_change(struct fimc_is *is); 160 161 #endif /* FIMC_IS_REG_H_ */ 162