1238c84f7SMauro Carvalho Chehab /* SPDX-License-Identifier: GPL-2.0-only */
2238c84f7SMauro Carvalho Chehab /*
3238c84f7SMauro Carvalho Chehab * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
4238c84f7SMauro Carvalho Chehab */
5238c84f7SMauro Carvalho Chehab
6238c84f7SMauro Carvalho Chehab #ifndef FIMC_CORE_H_
7238c84f7SMauro Carvalho Chehab #define FIMC_CORE_H_
8238c84f7SMauro Carvalho Chehab
9238c84f7SMauro Carvalho Chehab /*#define DEBUG*/
10238c84f7SMauro Carvalho Chehab
11238c84f7SMauro Carvalho Chehab #include <linux/platform_device.h>
12238c84f7SMauro Carvalho Chehab #include <linux/regmap.h>
13238c84f7SMauro Carvalho Chehab #include <linux/sched.h>
14238c84f7SMauro Carvalho Chehab #include <linux/spinlock.h>
15238c84f7SMauro Carvalho Chehab #include <linux/mfd/syscon.h>
16238c84f7SMauro Carvalho Chehab #include <linux/types.h>
17238c84f7SMauro Carvalho Chehab #include <linux/videodev2.h>
18238c84f7SMauro Carvalho Chehab #include <linux/io.h>
19238c84f7SMauro Carvalho Chehab #include <linux/sizes.h>
20238c84f7SMauro Carvalho Chehab
21238c84f7SMauro Carvalho Chehab #include <media/media-entity.h>
22238c84f7SMauro Carvalho Chehab #include <media/videobuf2-v4l2.h>
23238c84f7SMauro Carvalho Chehab #include <media/v4l2-ctrls.h>
24238c84f7SMauro Carvalho Chehab #include <media/v4l2-device.h>
25238c84f7SMauro Carvalho Chehab #include <media/v4l2-mem2mem.h>
26238c84f7SMauro Carvalho Chehab #include <media/v4l2-mediabus.h>
27238c84f7SMauro Carvalho Chehab #include <media/drv-intf/exynos-fimc.h>
28238c84f7SMauro Carvalho Chehab
29238c84f7SMauro Carvalho Chehab #define dbg(fmt, args...) \
30238c84f7SMauro Carvalho Chehab pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
31238c84f7SMauro Carvalho Chehab
32238c84f7SMauro Carvalho Chehab /* Time to wait for next frame VSYNC interrupt while stopping operation. */
33238c84f7SMauro Carvalho Chehab #define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
34238c84f7SMauro Carvalho Chehab #define MAX_FIMC_CLOCKS 2
35238c84f7SMauro Carvalho Chehab #define FIMC_DRIVER_NAME "exynos4-fimc"
36238c84f7SMauro Carvalho Chehab #define FIMC_MAX_DEVS 4
37238c84f7SMauro Carvalho Chehab #define FIMC_MAX_OUT_BUFS 4
38238c84f7SMauro Carvalho Chehab #define SCALER_MAX_HRATIO 64
39238c84f7SMauro Carvalho Chehab #define SCALER_MAX_VRATIO 64
40238c84f7SMauro Carvalho Chehab #define DMA_MIN_SIZE 8
41238c84f7SMauro Carvalho Chehab #define FIMC_CAMIF_MAX_HEIGHT 0x2000
42238c84f7SMauro Carvalho Chehab #define FIMC_MAX_JPEG_BUF_SIZE (10 * SZ_1M)
43238c84f7SMauro Carvalho Chehab #define FIMC_MAX_PLANES 3
44238c84f7SMauro Carvalho Chehab #define FIMC_PIX_LIMITS_MAX 4
45238c84f7SMauro Carvalho Chehab #define FIMC_DEF_MIN_SIZE 16
46238c84f7SMauro Carvalho Chehab #define FIMC_DEF_HEIGHT_ALIGN 2
47238c84f7SMauro Carvalho Chehab #define FIMC_DEF_HOR_OFFS_ALIGN 1
48238c84f7SMauro Carvalho Chehab #define FIMC_DEFAULT_WIDTH 640
49238c84f7SMauro Carvalho Chehab #define FIMC_DEFAULT_HEIGHT 480
50238c84f7SMauro Carvalho Chehab
51238c84f7SMauro Carvalho Chehab /* indices to the clocks array */
52238c84f7SMauro Carvalho Chehab enum {
53238c84f7SMauro Carvalho Chehab CLK_BUS,
54238c84f7SMauro Carvalho Chehab CLK_GATE,
55238c84f7SMauro Carvalho Chehab };
56238c84f7SMauro Carvalho Chehab
57238c84f7SMauro Carvalho Chehab enum fimc_dev_flags {
58238c84f7SMauro Carvalho Chehab ST_LPM,
59238c84f7SMauro Carvalho Chehab /* m2m node */
60238c84f7SMauro Carvalho Chehab ST_M2M_RUN,
61238c84f7SMauro Carvalho Chehab ST_M2M_PEND,
62238c84f7SMauro Carvalho Chehab ST_M2M_SUSPENDING,
63238c84f7SMauro Carvalho Chehab ST_M2M_SUSPENDED,
64238c84f7SMauro Carvalho Chehab /* capture node */
65238c84f7SMauro Carvalho Chehab ST_CAPT_PEND,
66238c84f7SMauro Carvalho Chehab ST_CAPT_RUN,
67238c84f7SMauro Carvalho Chehab ST_CAPT_STREAM,
68238c84f7SMauro Carvalho Chehab ST_CAPT_ISP_STREAM,
69238c84f7SMauro Carvalho Chehab ST_CAPT_SUSPENDED,
70238c84f7SMauro Carvalho Chehab ST_CAPT_SHUT,
71238c84f7SMauro Carvalho Chehab ST_CAPT_BUSY,
72238c84f7SMauro Carvalho Chehab ST_CAPT_APPLY_CFG,
73238c84f7SMauro Carvalho Chehab ST_CAPT_JPEG,
74238c84f7SMauro Carvalho Chehab };
75238c84f7SMauro Carvalho Chehab
76238c84f7SMauro Carvalho Chehab #define fimc_m2m_active(dev) test_bit(ST_M2M_RUN, &(dev)->state)
77238c84f7SMauro Carvalho Chehab #define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
78238c84f7SMauro Carvalho Chehab
79238c84f7SMauro Carvalho Chehab #define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
80238c84f7SMauro Carvalho Chehab #define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
81238c84f7SMauro Carvalho Chehab #define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
82238c84f7SMauro Carvalho Chehab
83238c84f7SMauro Carvalho Chehab enum fimc_datapath {
84238c84f7SMauro Carvalho Chehab FIMC_IO_NONE,
85238c84f7SMauro Carvalho Chehab FIMC_IO_CAMERA,
86238c84f7SMauro Carvalho Chehab FIMC_IO_DMA,
87238c84f7SMauro Carvalho Chehab FIMC_IO_LCDFIFO,
88238c84f7SMauro Carvalho Chehab FIMC_IO_WRITEBACK,
89238c84f7SMauro Carvalho Chehab FIMC_IO_ISP,
90238c84f7SMauro Carvalho Chehab };
91238c84f7SMauro Carvalho Chehab
92238c84f7SMauro Carvalho Chehab enum fimc_color_fmt {
93238c84f7SMauro Carvalho Chehab FIMC_FMT_RGB444 = 0x10,
94238c84f7SMauro Carvalho Chehab FIMC_FMT_RGB555,
95238c84f7SMauro Carvalho Chehab FIMC_FMT_RGB565,
96238c84f7SMauro Carvalho Chehab FIMC_FMT_RGB666,
97238c84f7SMauro Carvalho Chehab FIMC_FMT_RGB888,
98238c84f7SMauro Carvalho Chehab FIMC_FMT_RGB30_LOCAL,
99238c84f7SMauro Carvalho Chehab FIMC_FMT_YCBCR420 = 0x20,
100238c84f7SMauro Carvalho Chehab FIMC_FMT_YCBYCR422,
101238c84f7SMauro Carvalho Chehab FIMC_FMT_YCRYCB422,
102238c84f7SMauro Carvalho Chehab FIMC_FMT_CBYCRY422,
103238c84f7SMauro Carvalho Chehab FIMC_FMT_CRYCBY422,
104238c84f7SMauro Carvalho Chehab FIMC_FMT_YCBCR444_LOCAL,
105238c84f7SMauro Carvalho Chehab FIMC_FMT_RAW8 = 0x40,
106238c84f7SMauro Carvalho Chehab FIMC_FMT_RAW10,
107238c84f7SMauro Carvalho Chehab FIMC_FMT_RAW12,
108238c84f7SMauro Carvalho Chehab FIMC_FMT_JPEG = 0x80,
109238c84f7SMauro Carvalho Chehab FIMC_FMT_YUYV_JPEG = 0x100,
110238c84f7SMauro Carvalho Chehab };
111238c84f7SMauro Carvalho Chehab
112238c84f7SMauro Carvalho Chehab #define fimc_fmt_is_user_defined(x) (!!((x) & 0x180))
113238c84f7SMauro Carvalho Chehab #define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
114238c84f7SMauro Carvalho Chehab
115238c84f7SMauro Carvalho Chehab #define IS_M2M(__strt) ((__strt) == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE || \
116238c84f7SMauro Carvalho Chehab __strt == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
117238c84f7SMauro Carvalho Chehab
118238c84f7SMauro Carvalho Chehab /* The hardware context state. */
119238c84f7SMauro Carvalho Chehab #define FIMC_PARAMS (1 << 0)
120238c84f7SMauro Carvalho Chehab #define FIMC_COMPOSE (1 << 1)
121238c84f7SMauro Carvalho Chehab #define FIMC_CTX_M2M (1 << 16)
122238c84f7SMauro Carvalho Chehab #define FIMC_CTX_CAP (1 << 17)
123238c84f7SMauro Carvalho Chehab #define FIMC_CTX_SHUT (1 << 18)
124238c84f7SMauro Carvalho Chehab
125238c84f7SMauro Carvalho Chehab /* Image conversion flags */
126238c84f7SMauro Carvalho Chehab #define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
127238c84f7SMauro Carvalho Chehab #define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
128238c84f7SMauro Carvalho Chehab #define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
129238c84f7SMauro Carvalho Chehab #define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
130238c84f7SMauro Carvalho Chehab #define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
131238c84f7SMauro Carvalho Chehab #define FIMC_SCAN_MODE_INTERLACED (1 << 2)
132238c84f7SMauro Carvalho Chehab /*
133238c84f7SMauro Carvalho Chehab * YCbCr data dynamic range for RGB-YUV color conversion.
134238c84f7SMauro Carvalho Chehab * Y/Cb/Cr: (0 ~ 255) */
135238c84f7SMauro Carvalho Chehab #define FIMC_COLOR_RANGE_WIDE (0 << 3)
136238c84f7SMauro Carvalho Chehab /* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
137238c84f7SMauro Carvalho Chehab #define FIMC_COLOR_RANGE_NARROW (1 << 3)
138238c84f7SMauro Carvalho Chehab
139238c84f7SMauro Carvalho Chehab /**
140238c84f7SMauro Carvalho Chehab * struct fimc_dma_offset - pixel offset information for DMA
141238c84f7SMauro Carvalho Chehab * @y_h: y value horizontal offset
142238c84f7SMauro Carvalho Chehab * @y_v: y value vertical offset
143238c84f7SMauro Carvalho Chehab * @cb_h: cb value horizontal offset
144238c84f7SMauro Carvalho Chehab * @cb_v: cb value vertical offset
145238c84f7SMauro Carvalho Chehab * @cr_h: cr value horizontal offset
146238c84f7SMauro Carvalho Chehab * @cr_v: cr value vertical offset
147238c84f7SMauro Carvalho Chehab */
148238c84f7SMauro Carvalho Chehab struct fimc_dma_offset {
149238c84f7SMauro Carvalho Chehab int y_h;
150238c84f7SMauro Carvalho Chehab int y_v;
151238c84f7SMauro Carvalho Chehab int cb_h;
152238c84f7SMauro Carvalho Chehab int cb_v;
153238c84f7SMauro Carvalho Chehab int cr_h;
154238c84f7SMauro Carvalho Chehab int cr_v;
155238c84f7SMauro Carvalho Chehab };
156238c84f7SMauro Carvalho Chehab
157238c84f7SMauro Carvalho Chehab /**
158238c84f7SMauro Carvalho Chehab * struct fimc_effect - color effect information
159238c84f7SMauro Carvalho Chehab * @type: effect type
160238c84f7SMauro Carvalho Chehab * @pat_cb: cr value when type is "arbitrary"
161238c84f7SMauro Carvalho Chehab * @pat_cr: cr value when type is "arbitrary"
162238c84f7SMauro Carvalho Chehab */
163238c84f7SMauro Carvalho Chehab struct fimc_effect {
164238c84f7SMauro Carvalho Chehab u32 type;
165238c84f7SMauro Carvalho Chehab u8 pat_cb;
166238c84f7SMauro Carvalho Chehab u8 pat_cr;
167238c84f7SMauro Carvalho Chehab };
168238c84f7SMauro Carvalho Chehab
169238c84f7SMauro Carvalho Chehab /**
170238c84f7SMauro Carvalho Chehab * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
171238c84f7SMauro Carvalho Chehab * @scaleup_h: flag indicating scaling up horizontally
172238c84f7SMauro Carvalho Chehab * @scaleup_v: flag indicating scaling up vertically
173238c84f7SMauro Carvalho Chehab * @copy_mode: flag indicating transparent DMA transfer (no scaling
174238c84f7SMauro Carvalho Chehab * and color format conversion)
175238c84f7SMauro Carvalho Chehab * @enabled: flag indicating if the scaler is used
176238c84f7SMauro Carvalho Chehab * @hfactor: horizontal shift factor
177238c84f7SMauro Carvalho Chehab * @vfactor: vertical shift factor
178238c84f7SMauro Carvalho Chehab * @pre_hratio: horizontal ratio of the prescaler
179238c84f7SMauro Carvalho Chehab * @pre_vratio: vertical ratio of the prescaler
180238c84f7SMauro Carvalho Chehab * @pre_dst_width: the prescaler's destination width
181238c84f7SMauro Carvalho Chehab * @pre_dst_height: the prescaler's destination height
182238c84f7SMauro Carvalho Chehab * @main_hratio: the main scaler's horizontal ratio
183238c84f7SMauro Carvalho Chehab * @main_vratio: the main scaler's vertical ratio
184238c84f7SMauro Carvalho Chehab * @real_width: source pixel (width - offset)
185238c84f7SMauro Carvalho Chehab * @real_height: source pixel (height - offset)
186238c84f7SMauro Carvalho Chehab */
187238c84f7SMauro Carvalho Chehab struct fimc_scaler {
188238c84f7SMauro Carvalho Chehab unsigned int scaleup_h:1;
189238c84f7SMauro Carvalho Chehab unsigned int scaleup_v:1;
190238c84f7SMauro Carvalho Chehab unsigned int copy_mode:1;
191238c84f7SMauro Carvalho Chehab unsigned int enabled:1;
192238c84f7SMauro Carvalho Chehab u32 hfactor;
193238c84f7SMauro Carvalho Chehab u32 vfactor;
194238c84f7SMauro Carvalho Chehab u32 pre_hratio;
195238c84f7SMauro Carvalho Chehab u32 pre_vratio;
196238c84f7SMauro Carvalho Chehab u32 pre_dst_width;
197238c84f7SMauro Carvalho Chehab u32 pre_dst_height;
198238c84f7SMauro Carvalho Chehab u32 main_hratio;
199238c84f7SMauro Carvalho Chehab u32 main_vratio;
200238c84f7SMauro Carvalho Chehab u32 real_width;
201238c84f7SMauro Carvalho Chehab u32 real_height;
202238c84f7SMauro Carvalho Chehab };
203238c84f7SMauro Carvalho Chehab
204238c84f7SMauro Carvalho Chehab /**
205238c84f7SMauro Carvalho Chehab * struct fimc_addr - the FIMC address set for DMA
206238c84f7SMauro Carvalho Chehab * @y: luminance plane address
207238c84f7SMauro Carvalho Chehab * @cb: Cb plane address
208238c84f7SMauro Carvalho Chehab * @cr: Cr plane address
209238c84f7SMauro Carvalho Chehab */
210238c84f7SMauro Carvalho Chehab struct fimc_addr {
211238c84f7SMauro Carvalho Chehab u32 y;
212238c84f7SMauro Carvalho Chehab u32 cb;
213238c84f7SMauro Carvalho Chehab u32 cr;
214238c84f7SMauro Carvalho Chehab };
215238c84f7SMauro Carvalho Chehab
216238c84f7SMauro Carvalho Chehab /**
217238c84f7SMauro Carvalho Chehab * struct fimc_vid_buffer - the driver's video buffer
218*f068a6ceSHans Verkuil * @vb: v4l vb2 buffer
219238c84f7SMauro Carvalho Chehab * @list: linked list structure for buffer queue
220238c84f7SMauro Carvalho Chehab * @addr: precalculated DMA address set
221238c84f7SMauro Carvalho Chehab * @index: buffer index for the output DMA engine
222238c84f7SMauro Carvalho Chehab */
223238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer {
224238c84f7SMauro Carvalho Chehab struct vb2_v4l2_buffer vb;
225238c84f7SMauro Carvalho Chehab struct list_head list;
226238c84f7SMauro Carvalho Chehab struct fimc_addr addr;
227238c84f7SMauro Carvalho Chehab int index;
228238c84f7SMauro Carvalho Chehab };
229238c84f7SMauro Carvalho Chehab
230238c84f7SMauro Carvalho Chehab /**
231238c84f7SMauro Carvalho Chehab * struct fimc_frame - source/target frame properties
232238c84f7SMauro Carvalho Chehab * @f_width: image full width (virtual screen size)
233238c84f7SMauro Carvalho Chehab * @f_height: image full height (virtual screen size)
234238c84f7SMauro Carvalho Chehab * @o_width: original image width as set by S_FMT
235238c84f7SMauro Carvalho Chehab * @o_height: original image height as set by S_FMT
236238c84f7SMauro Carvalho Chehab * @offs_h: image horizontal pixel offset
237238c84f7SMauro Carvalho Chehab * @offs_v: image vertical pixel offset
238238c84f7SMauro Carvalho Chehab * @width: image pixel width
239238c84f7SMauro Carvalho Chehab * @height: image pixel weight
240238c84f7SMauro Carvalho Chehab * @payload: image size in bytes (w x h x bpp)
241238c84f7SMauro Carvalho Chehab * @bytesperline: bytesperline value for each plane
242238c84f7SMauro Carvalho Chehab * @addr: image frame buffer DMA addresses
243238c84f7SMauro Carvalho Chehab * @dma_offset: DMA offset in bytes
244238c84f7SMauro Carvalho Chehab * @fmt: fimc color format pointer
245238c84f7SMauro Carvalho Chehab * @alpha: alpha value
246238c84f7SMauro Carvalho Chehab */
247238c84f7SMauro Carvalho Chehab struct fimc_frame {
248238c84f7SMauro Carvalho Chehab u32 f_width;
249238c84f7SMauro Carvalho Chehab u32 f_height;
250238c84f7SMauro Carvalho Chehab u32 o_width;
251238c84f7SMauro Carvalho Chehab u32 o_height;
252238c84f7SMauro Carvalho Chehab u32 offs_h;
253238c84f7SMauro Carvalho Chehab u32 offs_v;
254238c84f7SMauro Carvalho Chehab u32 width;
255238c84f7SMauro Carvalho Chehab u32 height;
256238c84f7SMauro Carvalho Chehab unsigned int payload[VIDEO_MAX_PLANES];
257238c84f7SMauro Carvalho Chehab unsigned int bytesperline[VIDEO_MAX_PLANES];
258238c84f7SMauro Carvalho Chehab struct fimc_addr addr;
259238c84f7SMauro Carvalho Chehab struct fimc_dma_offset dma_offset;
260238c84f7SMauro Carvalho Chehab struct fimc_fmt *fmt;
261238c84f7SMauro Carvalho Chehab u8 alpha;
262238c84f7SMauro Carvalho Chehab };
263238c84f7SMauro Carvalho Chehab
264238c84f7SMauro Carvalho Chehab /**
265238c84f7SMauro Carvalho Chehab * struct fimc_m2m_device - v4l2 memory-to-memory device data
266238c84f7SMauro Carvalho Chehab * @vfd: the video device node for v4l2 m2m mode
267238c84f7SMauro Carvalho Chehab * @m2m_dev: v4l2 memory-to-memory device data
268238c84f7SMauro Carvalho Chehab * @ctx: hardware context data
269238c84f7SMauro Carvalho Chehab * @refcnt: the reference counter
270238c84f7SMauro Carvalho Chehab */
271238c84f7SMauro Carvalho Chehab struct fimc_m2m_device {
272238c84f7SMauro Carvalho Chehab struct video_device vfd;
273238c84f7SMauro Carvalho Chehab struct v4l2_m2m_dev *m2m_dev;
274238c84f7SMauro Carvalho Chehab struct fimc_ctx *ctx;
275238c84f7SMauro Carvalho Chehab int refcnt;
276238c84f7SMauro Carvalho Chehab };
277238c84f7SMauro Carvalho Chehab
278238c84f7SMauro Carvalho Chehab #define FIMC_SD_PAD_SINK_CAM 0
279238c84f7SMauro Carvalho Chehab #define FIMC_SD_PAD_SINK_FIFO 1
280238c84f7SMauro Carvalho Chehab #define FIMC_SD_PAD_SOURCE 2
281238c84f7SMauro Carvalho Chehab #define FIMC_SD_PADS_NUM 3
282238c84f7SMauro Carvalho Chehab
283238c84f7SMauro Carvalho Chehab /**
284238c84f7SMauro Carvalho Chehab * struct fimc_vid_cap - camera capture device information
285238c84f7SMauro Carvalho Chehab * @ctx: hardware context data
286238c84f7SMauro Carvalho Chehab * @subdev: subdev exposing the FIMC processing block
287238c84f7SMauro Carvalho Chehab * @ve: exynos video device entity structure
288238c84f7SMauro Carvalho Chehab * @vd_pad: fimc video capture node pad
289238c84f7SMauro Carvalho Chehab * @sd_pads: fimc video processing block pads
290238c84f7SMauro Carvalho Chehab * @ci_fmt: image format at the FIMC camera input (and the scaler output)
291238c84f7SMauro Carvalho Chehab * @wb_fmt: image format at the FIMC ISP Writeback input
292238c84f7SMauro Carvalho Chehab * @source_config: external image source related configuration structure
293238c84f7SMauro Carvalho Chehab * @pending_buf_q: the pending buffer queue head
294238c84f7SMauro Carvalho Chehab * @active_buf_q: the queue head of buffers scheduled in hardware
295238c84f7SMauro Carvalho Chehab * @vbq: the capture am video buffer queue
296238c84f7SMauro Carvalho Chehab * @active_buf_cnt: number of video buffers scheduled in hardware
297238c84f7SMauro Carvalho Chehab * @buf_index: index for managing the output DMA buffers
298238c84f7SMauro Carvalho Chehab * @frame_count: the frame counter for statistics
299238c84f7SMauro Carvalho Chehab * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
300238c84f7SMauro Carvalho Chehab * @streaming: is streaming in progress?
301238c84f7SMauro Carvalho Chehab * @input: capture input type, grp_id of the attached subdev
302238c84f7SMauro Carvalho Chehab * @user_subdev_api: true if subdevs are not configured by the host driver
303238c84f7SMauro Carvalho Chehab */
304238c84f7SMauro Carvalho Chehab struct fimc_vid_cap {
305238c84f7SMauro Carvalho Chehab struct fimc_ctx *ctx;
306238c84f7SMauro Carvalho Chehab struct v4l2_subdev subdev;
307238c84f7SMauro Carvalho Chehab struct exynos_video_entity ve;
308238c84f7SMauro Carvalho Chehab struct media_pad vd_pad;
309238c84f7SMauro Carvalho Chehab struct media_pad sd_pads[FIMC_SD_PADS_NUM];
310238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt ci_fmt;
311238c84f7SMauro Carvalho Chehab struct v4l2_mbus_framefmt wb_fmt;
312238c84f7SMauro Carvalho Chehab struct fimc_source_info source_config;
313238c84f7SMauro Carvalho Chehab struct list_head pending_buf_q;
314238c84f7SMauro Carvalho Chehab struct list_head active_buf_q;
315238c84f7SMauro Carvalho Chehab struct vb2_queue vbq;
316238c84f7SMauro Carvalho Chehab int active_buf_cnt;
317238c84f7SMauro Carvalho Chehab int buf_index;
318238c84f7SMauro Carvalho Chehab unsigned int frame_count;
319238c84f7SMauro Carvalho Chehab unsigned int reqbufs_count;
320238c84f7SMauro Carvalho Chehab bool streaming;
321238c84f7SMauro Carvalho Chehab u32 input;
322238c84f7SMauro Carvalho Chehab bool user_subdev_api;
323238c84f7SMauro Carvalho Chehab };
324238c84f7SMauro Carvalho Chehab
325238c84f7SMauro Carvalho Chehab /**
326238c84f7SMauro Carvalho Chehab * struct fimc_pix_limit - image pixel size limits in various IP configurations
327238c84f7SMauro Carvalho Chehab *
328238c84f7SMauro Carvalho Chehab * @scaler_en_w: max input pixel width when the scaler is enabled
329238c84f7SMauro Carvalho Chehab * @scaler_dis_w: max input pixel width when the scaler is disabled
330238c84f7SMauro Carvalho Chehab * @in_rot_en_h: max input width with the input rotator is on
331238c84f7SMauro Carvalho Chehab * @in_rot_dis_w: max input width with the input rotator is off
332238c84f7SMauro Carvalho Chehab * @out_rot_en_w: max output width with the output rotator on
333238c84f7SMauro Carvalho Chehab * @out_rot_dis_w: max output width with the output rotator off
334238c84f7SMauro Carvalho Chehab */
335238c84f7SMauro Carvalho Chehab struct fimc_pix_limit {
336238c84f7SMauro Carvalho Chehab u16 scaler_en_w;
337238c84f7SMauro Carvalho Chehab u16 scaler_dis_w;
338238c84f7SMauro Carvalho Chehab u16 in_rot_en_h;
339238c84f7SMauro Carvalho Chehab u16 in_rot_dis_w;
340238c84f7SMauro Carvalho Chehab u16 out_rot_en_w;
341238c84f7SMauro Carvalho Chehab u16 out_rot_dis_w;
342238c84f7SMauro Carvalho Chehab };
343238c84f7SMauro Carvalho Chehab
344238c84f7SMauro Carvalho Chehab /**
345238c84f7SMauro Carvalho Chehab * struct fimc_variant - FIMC device variant information
346238c84f7SMauro Carvalho Chehab * @has_inp_rot: set if has input rotator
347238c84f7SMauro Carvalho Chehab * @has_out_rot: set if has output rotator
348238c84f7SMauro Carvalho Chehab * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
349238c84f7SMauro Carvalho Chehab * are present in this IP revision
350238c84f7SMauro Carvalho Chehab * @has_cam_if: set if this instance has a camera input interface
351238c84f7SMauro Carvalho Chehab * @has_isp_wb: set if this instance has ISP writeback input
352238c84f7SMauro Carvalho Chehab * @pix_limit: pixel size constraints for the scaler
353238c84f7SMauro Carvalho Chehab * @min_inp_pixsize: minimum input pixel size
354238c84f7SMauro Carvalho Chehab * @min_out_pixsize: minimum output pixel size
355238c84f7SMauro Carvalho Chehab * @hor_offs_align: horizontal pixel offset alignment
356238c84f7SMauro Carvalho Chehab * @min_vsize_align: minimum vertical pixel size alignment
357238c84f7SMauro Carvalho Chehab */
358238c84f7SMauro Carvalho Chehab struct fimc_variant {
359238c84f7SMauro Carvalho Chehab unsigned int has_inp_rot:1;
360238c84f7SMauro Carvalho Chehab unsigned int has_out_rot:1;
361238c84f7SMauro Carvalho Chehab unsigned int has_mainscaler_ext:1;
362238c84f7SMauro Carvalho Chehab unsigned int has_cam_if:1;
363238c84f7SMauro Carvalho Chehab unsigned int has_isp_wb:1;
364238c84f7SMauro Carvalho Chehab const struct fimc_pix_limit *pix_limit;
365238c84f7SMauro Carvalho Chehab u16 min_inp_pixsize;
366238c84f7SMauro Carvalho Chehab u16 min_out_pixsize;
367238c84f7SMauro Carvalho Chehab u16 hor_offs_align;
368238c84f7SMauro Carvalho Chehab u16 min_vsize_align;
369238c84f7SMauro Carvalho Chehab };
370238c84f7SMauro Carvalho Chehab
371238c84f7SMauro Carvalho Chehab /**
372238c84f7SMauro Carvalho Chehab * struct fimc_drvdata - per device type driver data
373238c84f7SMauro Carvalho Chehab * @variant: variant information for this device
374238c84f7SMauro Carvalho Chehab * @num_entities: number of fimc instances available in a SoC
375238c84f7SMauro Carvalho Chehab * @lclk_frequency: local bus clock frequency
376238c84f7SMauro Carvalho Chehab * @cistatus2: 1 if the FIMC IPs have CISTATUS2 register
377238c84f7SMauro Carvalho Chehab * @dma_pix_hoff: the horizontal DMA offset unit: 1 - pixels, 0 - bytes
378238c84f7SMauro Carvalho Chehab * @alpha_color: 1 if alpha color component is supported
379238c84f7SMauro Carvalho Chehab * @out_buf_count: maximum number of output DMA buffers supported
380238c84f7SMauro Carvalho Chehab */
381238c84f7SMauro Carvalho Chehab struct fimc_drvdata {
382238c84f7SMauro Carvalho Chehab const struct fimc_variant *variant[FIMC_MAX_DEVS];
383238c84f7SMauro Carvalho Chehab int num_entities;
384238c84f7SMauro Carvalho Chehab unsigned long lclk_frequency;
385238c84f7SMauro Carvalho Chehab /* Fields common to all FIMC IP instances */
386238c84f7SMauro Carvalho Chehab u8 cistatus2;
387238c84f7SMauro Carvalho Chehab u8 dma_pix_hoff;
388238c84f7SMauro Carvalho Chehab u8 alpha_color;
389238c84f7SMauro Carvalho Chehab u8 out_buf_count;
390238c84f7SMauro Carvalho Chehab };
391238c84f7SMauro Carvalho Chehab
392238c84f7SMauro Carvalho Chehab #define fimc_get_drvdata(_pdev) \
393238c84f7SMauro Carvalho Chehab ((struct fimc_drvdata *) platform_get_device_id(_pdev)->driver_data)
394238c84f7SMauro Carvalho Chehab
395238c84f7SMauro Carvalho Chehab struct fimc_ctx;
396238c84f7SMauro Carvalho Chehab
397238c84f7SMauro Carvalho Chehab /**
398238c84f7SMauro Carvalho Chehab * struct fimc_dev - abstraction for FIMC entity
399238c84f7SMauro Carvalho Chehab * @slock: the spinlock protecting this data structure
400238c84f7SMauro Carvalho Chehab * @lock: the mutex protecting this data structure
401238c84f7SMauro Carvalho Chehab * @pdev: pointer to the FIMC platform device
402238c84f7SMauro Carvalho Chehab * @pdata: pointer to the device platform data
403238c84f7SMauro Carvalho Chehab * @sysreg: pointer to the SYSREG regmap
404238c84f7SMauro Carvalho Chehab * @variant: the IP variant information
405238c84f7SMauro Carvalho Chehab * @drv_data: driver data
406238c84f7SMauro Carvalho Chehab * @id: FIMC device index (0..FIMC_MAX_DEVS)
407238c84f7SMauro Carvalho Chehab * @clock: clocks required for FIMC operation
408238c84f7SMauro Carvalho Chehab * @regs: the mapped hardware registers
409238c84f7SMauro Carvalho Chehab * @irq_queue: interrupt handler waitqueue
410238c84f7SMauro Carvalho Chehab * @v4l2_dev: root v4l2_device
411238c84f7SMauro Carvalho Chehab * @m2m: memory-to-memory V4L2 device information
412238c84f7SMauro Carvalho Chehab * @vid_cap: camera capture device information
413238c84f7SMauro Carvalho Chehab * @state: flags used to synchronize m2m and capture mode operation
414238c84f7SMauro Carvalho Chehab */
415238c84f7SMauro Carvalho Chehab struct fimc_dev {
416238c84f7SMauro Carvalho Chehab spinlock_t slock;
417238c84f7SMauro Carvalho Chehab struct mutex lock;
418238c84f7SMauro Carvalho Chehab struct platform_device *pdev;
419238c84f7SMauro Carvalho Chehab struct s5p_platform_fimc *pdata;
420238c84f7SMauro Carvalho Chehab struct regmap *sysreg;
421238c84f7SMauro Carvalho Chehab const struct fimc_variant *variant;
422238c84f7SMauro Carvalho Chehab const struct fimc_drvdata *drv_data;
423238c84f7SMauro Carvalho Chehab int id;
424238c84f7SMauro Carvalho Chehab struct clk *clock[MAX_FIMC_CLOCKS];
425238c84f7SMauro Carvalho Chehab void __iomem *regs;
426238c84f7SMauro Carvalho Chehab wait_queue_head_t irq_queue;
427238c84f7SMauro Carvalho Chehab struct v4l2_device *v4l2_dev;
428238c84f7SMauro Carvalho Chehab struct fimc_m2m_device m2m;
429238c84f7SMauro Carvalho Chehab struct fimc_vid_cap vid_cap;
430238c84f7SMauro Carvalho Chehab unsigned long state;
431238c84f7SMauro Carvalho Chehab };
432238c84f7SMauro Carvalho Chehab
433238c84f7SMauro Carvalho Chehab /**
434238c84f7SMauro Carvalho Chehab * struct fimc_ctrls - v4l2 controls structure
435238c84f7SMauro Carvalho Chehab * @handler: the control handler
436238c84f7SMauro Carvalho Chehab * @colorfx: image effect control
437238c84f7SMauro Carvalho Chehab * @colorfx_cbcr: Cb/Cr coefficients control
438238c84f7SMauro Carvalho Chehab * @rotate: image rotation control
439238c84f7SMauro Carvalho Chehab * @hflip: horizontal flip control
440238c84f7SMauro Carvalho Chehab * @vflip: vertical flip control
441238c84f7SMauro Carvalho Chehab * @alpha: RGB alpha control
442238c84f7SMauro Carvalho Chehab * @ready: true if @handler is initialized
443238c84f7SMauro Carvalho Chehab */
444238c84f7SMauro Carvalho Chehab struct fimc_ctrls {
445238c84f7SMauro Carvalho Chehab struct v4l2_ctrl_handler handler;
446238c84f7SMauro Carvalho Chehab struct {
447238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *colorfx;
448238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *colorfx_cbcr;
449238c84f7SMauro Carvalho Chehab };
450238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *rotate;
451238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *hflip;
452238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *vflip;
453238c84f7SMauro Carvalho Chehab struct v4l2_ctrl *alpha;
454238c84f7SMauro Carvalho Chehab bool ready;
455238c84f7SMauro Carvalho Chehab };
456238c84f7SMauro Carvalho Chehab
457238c84f7SMauro Carvalho Chehab /**
458238c84f7SMauro Carvalho Chehab * struct fimc_ctx - the device context data
459238c84f7SMauro Carvalho Chehab * @s_frame: source frame properties
460238c84f7SMauro Carvalho Chehab * @d_frame: destination frame properties
461238c84f7SMauro Carvalho Chehab * @out_order_1p: output 1-plane YCBCR order
462238c84f7SMauro Carvalho Chehab * @out_order_2p: output 2-plane YCBCR order
463238c84f7SMauro Carvalho Chehab * @in_order_1p: input 1-plane YCBCR order
464238c84f7SMauro Carvalho Chehab * @in_order_2p: input 2-plane YCBCR order
465238c84f7SMauro Carvalho Chehab * @in_path: input mode (DMA or camera)
466238c84f7SMauro Carvalho Chehab * @out_path: output mode (DMA or FIFO)
467238c84f7SMauro Carvalho Chehab * @scaler: image scaler properties
468238c84f7SMauro Carvalho Chehab * @effect: image effect
469238c84f7SMauro Carvalho Chehab * @rotation: image clockwise rotation in degrees
470238c84f7SMauro Carvalho Chehab * @hflip: indicates image horizontal flip if set
471238c84f7SMauro Carvalho Chehab * @vflip: indicates image vertical flip if set
472238c84f7SMauro Carvalho Chehab * @flags: additional flags for image conversion
473238c84f7SMauro Carvalho Chehab * @state: flags to keep track of user configuration
474238c84f7SMauro Carvalho Chehab * @fimc_dev: the FIMC device this context applies to
475238c84f7SMauro Carvalho Chehab * @fh: v4l2 file handle
476238c84f7SMauro Carvalho Chehab * @ctrls: v4l2 controls structure
477238c84f7SMauro Carvalho Chehab */
478238c84f7SMauro Carvalho Chehab struct fimc_ctx {
479238c84f7SMauro Carvalho Chehab struct fimc_frame s_frame;
480238c84f7SMauro Carvalho Chehab struct fimc_frame d_frame;
481238c84f7SMauro Carvalho Chehab u32 out_order_1p;
482238c84f7SMauro Carvalho Chehab u32 out_order_2p;
483238c84f7SMauro Carvalho Chehab u32 in_order_1p;
484238c84f7SMauro Carvalho Chehab u32 in_order_2p;
485238c84f7SMauro Carvalho Chehab enum fimc_datapath in_path;
486238c84f7SMauro Carvalho Chehab enum fimc_datapath out_path;
487238c84f7SMauro Carvalho Chehab struct fimc_scaler scaler;
488238c84f7SMauro Carvalho Chehab struct fimc_effect effect;
489238c84f7SMauro Carvalho Chehab int rotation;
490238c84f7SMauro Carvalho Chehab unsigned int hflip:1;
491238c84f7SMauro Carvalho Chehab unsigned int vflip:1;
492238c84f7SMauro Carvalho Chehab u32 flags;
493238c84f7SMauro Carvalho Chehab u32 state;
494238c84f7SMauro Carvalho Chehab struct fimc_dev *fimc_dev;
495238c84f7SMauro Carvalho Chehab struct v4l2_fh fh;
496238c84f7SMauro Carvalho Chehab struct fimc_ctrls ctrls;
497238c84f7SMauro Carvalho Chehab };
498238c84f7SMauro Carvalho Chehab
499238c84f7SMauro Carvalho Chehab #define fh_to_ctx(__fh) container_of(__fh, struct fimc_ctx, fh)
500238c84f7SMauro Carvalho Chehab
set_frame_bounds(struct fimc_frame * f,u32 width,u32 height)501238c84f7SMauro Carvalho Chehab static inline void set_frame_bounds(struct fimc_frame *f, u32 width, u32 height)
502238c84f7SMauro Carvalho Chehab {
503238c84f7SMauro Carvalho Chehab f->o_width = width;
504238c84f7SMauro Carvalho Chehab f->o_height = height;
505238c84f7SMauro Carvalho Chehab f->f_width = width;
506238c84f7SMauro Carvalho Chehab f->f_height = height;
507238c84f7SMauro Carvalho Chehab }
508238c84f7SMauro Carvalho Chehab
set_frame_crop(struct fimc_frame * f,u32 left,u32 top,u32 width,u32 height)509238c84f7SMauro Carvalho Chehab static inline void set_frame_crop(struct fimc_frame *f,
510238c84f7SMauro Carvalho Chehab u32 left, u32 top, u32 width, u32 height)
511238c84f7SMauro Carvalho Chehab {
512238c84f7SMauro Carvalho Chehab f->offs_h = left;
513238c84f7SMauro Carvalho Chehab f->offs_v = top;
514238c84f7SMauro Carvalho Chehab f->width = width;
515238c84f7SMauro Carvalho Chehab f->height = height;
516238c84f7SMauro Carvalho Chehab }
517238c84f7SMauro Carvalho Chehab
fimc_get_format_depth(struct fimc_fmt * ff)518238c84f7SMauro Carvalho Chehab static inline u32 fimc_get_format_depth(struct fimc_fmt *ff)
519238c84f7SMauro Carvalho Chehab {
520238c84f7SMauro Carvalho Chehab u32 i, depth = 0;
521238c84f7SMauro Carvalho Chehab
522238c84f7SMauro Carvalho Chehab if (ff != NULL)
523238c84f7SMauro Carvalho Chehab for (i = 0; i < ff->colplanes; i++)
524238c84f7SMauro Carvalho Chehab depth += ff->depth[i];
525238c84f7SMauro Carvalho Chehab return depth;
526238c84f7SMauro Carvalho Chehab }
527238c84f7SMauro Carvalho Chehab
fimc_capture_active(struct fimc_dev * fimc)528238c84f7SMauro Carvalho Chehab static inline bool fimc_capture_active(struct fimc_dev *fimc)
529238c84f7SMauro Carvalho Chehab {
530238c84f7SMauro Carvalho Chehab unsigned long flags;
531238c84f7SMauro Carvalho Chehab bool ret;
532238c84f7SMauro Carvalho Chehab
533238c84f7SMauro Carvalho Chehab spin_lock_irqsave(&fimc->slock, flags);
534238c84f7SMauro Carvalho Chehab ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
535238c84f7SMauro Carvalho Chehab fimc->state & (1 << ST_CAPT_PEND));
536238c84f7SMauro Carvalho Chehab spin_unlock_irqrestore(&fimc->slock, flags);
537238c84f7SMauro Carvalho Chehab return ret;
538238c84f7SMauro Carvalho Chehab }
539238c84f7SMauro Carvalho Chehab
fimc_ctx_state_set(u32 state,struct fimc_ctx * ctx)540238c84f7SMauro Carvalho Chehab static inline void fimc_ctx_state_set(u32 state, struct fimc_ctx *ctx)
541238c84f7SMauro Carvalho Chehab {
542238c84f7SMauro Carvalho Chehab unsigned long flags;
543238c84f7SMauro Carvalho Chehab
544238c84f7SMauro Carvalho Chehab spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
545238c84f7SMauro Carvalho Chehab ctx->state |= state;
546238c84f7SMauro Carvalho Chehab spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
547238c84f7SMauro Carvalho Chehab }
548238c84f7SMauro Carvalho Chehab
fimc_ctx_state_is_set(u32 mask,struct fimc_ctx * ctx)549238c84f7SMauro Carvalho Chehab static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
550238c84f7SMauro Carvalho Chehab {
551238c84f7SMauro Carvalho Chehab unsigned long flags;
552238c84f7SMauro Carvalho Chehab bool ret;
553238c84f7SMauro Carvalho Chehab
554238c84f7SMauro Carvalho Chehab spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
555238c84f7SMauro Carvalho Chehab ret = (ctx->state & mask) == mask;
556238c84f7SMauro Carvalho Chehab spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
557238c84f7SMauro Carvalho Chehab return ret;
558238c84f7SMauro Carvalho Chehab }
559238c84f7SMauro Carvalho Chehab
tiled_fmt(struct fimc_fmt * fmt)560238c84f7SMauro Carvalho Chehab static inline int tiled_fmt(struct fimc_fmt *fmt)
561238c84f7SMauro Carvalho Chehab {
562238c84f7SMauro Carvalho Chehab return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
563238c84f7SMauro Carvalho Chehab }
564238c84f7SMauro Carvalho Chehab
fimc_jpeg_fourcc(u32 pixelformat)565238c84f7SMauro Carvalho Chehab static inline bool fimc_jpeg_fourcc(u32 pixelformat)
566238c84f7SMauro Carvalho Chehab {
567238c84f7SMauro Carvalho Chehab return (pixelformat == V4L2_PIX_FMT_JPEG ||
568238c84f7SMauro Carvalho Chehab pixelformat == V4L2_PIX_FMT_S5C_UYVY_JPG);
569238c84f7SMauro Carvalho Chehab }
570238c84f7SMauro Carvalho Chehab
fimc_user_defined_mbus_fmt(u32 code)571238c84f7SMauro Carvalho Chehab static inline bool fimc_user_defined_mbus_fmt(u32 code)
572238c84f7SMauro Carvalho Chehab {
573238c84f7SMauro Carvalho Chehab return (code == MEDIA_BUS_FMT_JPEG_1X8 ||
574238c84f7SMauro Carvalho Chehab code == MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8);
575238c84f7SMauro Carvalho Chehab }
576238c84f7SMauro Carvalho Chehab
577238c84f7SMauro Carvalho Chehab /* Return the alpha component bit mask */
fimc_get_alpha_mask(struct fimc_fmt * fmt)578238c84f7SMauro Carvalho Chehab static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
579238c84f7SMauro Carvalho Chehab {
580238c84f7SMauro Carvalho Chehab switch (fmt->color) {
581238c84f7SMauro Carvalho Chehab case FIMC_FMT_RGB444: return 0x0f;
582238c84f7SMauro Carvalho Chehab case FIMC_FMT_RGB555: return 0x01;
583238c84f7SMauro Carvalho Chehab case FIMC_FMT_RGB888: return 0xff;
584238c84f7SMauro Carvalho Chehab default: return 0;
585238c84f7SMauro Carvalho Chehab };
586238c84f7SMauro Carvalho Chehab }
587238c84f7SMauro Carvalho Chehab
ctx_get_frame(struct fimc_ctx * ctx,enum v4l2_buf_type type)588238c84f7SMauro Carvalho Chehab static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
589238c84f7SMauro Carvalho Chehab enum v4l2_buf_type type)
590238c84f7SMauro Carvalho Chehab {
591238c84f7SMauro Carvalho Chehab struct fimc_frame *frame;
592238c84f7SMauro Carvalho Chehab
593238c84f7SMauro Carvalho Chehab if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE ||
594238c84f7SMauro Carvalho Chehab type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
595238c84f7SMauro Carvalho Chehab if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
596238c84f7SMauro Carvalho Chehab frame = &ctx->s_frame;
597238c84f7SMauro Carvalho Chehab else
598238c84f7SMauro Carvalho Chehab return ERR_PTR(-EINVAL);
599238c84f7SMauro Carvalho Chehab } else if (type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
600238c84f7SMauro Carvalho Chehab type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
601238c84f7SMauro Carvalho Chehab frame = &ctx->d_frame;
602238c84f7SMauro Carvalho Chehab } else {
603238c84f7SMauro Carvalho Chehab v4l2_err(ctx->fimc_dev->v4l2_dev,
604238c84f7SMauro Carvalho Chehab "Wrong buffer/video queue type (%d)\n", type);
605238c84f7SMauro Carvalho Chehab return ERR_PTR(-EINVAL);
606238c84f7SMauro Carvalho Chehab }
607238c84f7SMauro Carvalho Chehab
608238c84f7SMauro Carvalho Chehab return frame;
609238c84f7SMauro Carvalho Chehab }
610238c84f7SMauro Carvalho Chehab
611238c84f7SMauro Carvalho Chehab /* -----------------------------------------------------*/
612238c84f7SMauro Carvalho Chehab /* fimc-core.c */
613238c84f7SMauro Carvalho Chehab int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
614238c84f7SMauro Carvalho Chehab struct v4l2_fmtdesc *f);
615238c84f7SMauro Carvalho Chehab int fimc_ctrls_create(struct fimc_ctx *ctx);
616238c84f7SMauro Carvalho Chehab void fimc_ctrls_delete(struct fimc_ctx *ctx);
617238c84f7SMauro Carvalho Chehab void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active);
618238c84f7SMauro Carvalho Chehab void fimc_alpha_ctrl_update(struct fimc_ctx *ctx);
619238c84f7SMauro Carvalho Chehab void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f);
620238c84f7SMauro Carvalho Chehab void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
621238c84f7SMauro Carvalho Chehab struct v4l2_pix_format_mplane *pix);
622238c84f7SMauro Carvalho Chehab struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
623238c84f7SMauro Carvalho Chehab unsigned int mask, int index);
624238c84f7SMauro Carvalho Chehab struct fimc_fmt *fimc_get_format(unsigned int index);
625238c84f7SMauro Carvalho Chehab
626238c84f7SMauro Carvalho Chehab int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
627238c84f7SMauro Carvalho Chehab int dw, int dh, int rotation);
628238c84f7SMauro Carvalho Chehab int fimc_set_scaler_info(struct fimc_ctx *ctx);
629238c84f7SMauro Carvalho Chehab int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
630238c84f7SMauro Carvalho Chehab int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
631238c84f7SMauro Carvalho Chehab struct fimc_frame *frame, struct fimc_addr *addr);
632238c84f7SMauro Carvalho Chehab void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f);
633238c84f7SMauro Carvalho Chehab void fimc_set_yuv_order(struct fimc_ctx *ctx);
634238c84f7SMauro Carvalho Chehab void fimc_capture_irq_handler(struct fimc_dev *fimc, int deq_buf);
635238c84f7SMauro Carvalho Chehab
636238c84f7SMauro Carvalho Chehab int fimc_register_m2m_device(struct fimc_dev *fimc,
637238c84f7SMauro Carvalho Chehab struct v4l2_device *v4l2_dev);
638238c84f7SMauro Carvalho Chehab void fimc_unregister_m2m_device(struct fimc_dev *fimc);
639238c84f7SMauro Carvalho Chehab int fimc_register_driver(void);
640238c84f7SMauro Carvalho Chehab void fimc_unregister_driver(void);
641238c84f7SMauro Carvalho Chehab
642238c84f7SMauro Carvalho Chehab #ifdef CONFIG_MFD_SYSCON
fimc_get_sysreg_regmap(struct device_node * node)643238c84f7SMauro Carvalho Chehab static inline struct regmap * fimc_get_sysreg_regmap(struct device_node *node)
644238c84f7SMauro Carvalho Chehab {
645238c84f7SMauro Carvalho Chehab return syscon_regmap_lookup_by_phandle(node, "samsung,sysreg");
646238c84f7SMauro Carvalho Chehab }
647238c84f7SMauro Carvalho Chehab #else
648238c84f7SMauro Carvalho Chehab #define fimc_get_sysreg_regmap(node) (NULL)
649238c84f7SMauro Carvalho Chehab #endif
650238c84f7SMauro Carvalho Chehab
651238c84f7SMauro Carvalho Chehab /* -----------------------------------------------------*/
652238c84f7SMauro Carvalho Chehab /* fimc-m2m.c */
653238c84f7SMauro Carvalho Chehab void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state);
654238c84f7SMauro Carvalho Chehab
655238c84f7SMauro Carvalho Chehab /* -----------------------------------------------------*/
656238c84f7SMauro Carvalho Chehab /* fimc-capture.c */
657238c84f7SMauro Carvalho Chehab int fimc_initialize_capture_subdev(struct fimc_dev *fimc);
658238c84f7SMauro Carvalho Chehab void fimc_unregister_capture_subdev(struct fimc_dev *fimc);
659238c84f7SMauro Carvalho Chehab int fimc_capture_ctrls_create(struct fimc_dev *fimc);
660238c84f7SMauro Carvalho Chehab void fimc_sensor_notify(struct v4l2_subdev *sd, unsigned int notification,
661238c84f7SMauro Carvalho Chehab void *arg);
662238c84f7SMauro Carvalho Chehab int fimc_capture_suspend(struct fimc_dev *fimc);
663238c84f7SMauro Carvalho Chehab int fimc_capture_resume(struct fimc_dev *fimc);
664238c84f7SMauro Carvalho Chehab
665238c84f7SMauro Carvalho Chehab /*
666238c84f7SMauro Carvalho Chehab * Buffer list manipulation functions. Must be called with fimc.slock held.
667238c84f7SMauro Carvalho Chehab */
668238c84f7SMauro Carvalho Chehab
669238c84f7SMauro Carvalho Chehab /**
670238c84f7SMauro Carvalho Chehab * fimc_active_queue_add - add buffer to the capture active buffers queue
671238c84f7SMauro Carvalho Chehab * @vid_cap: camera capture device information
672238c84f7SMauro Carvalho Chehab * @buf: buffer to add to the active buffers list
673238c84f7SMauro Carvalho Chehab */
fimc_active_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)674238c84f7SMauro Carvalho Chehab static inline void fimc_active_queue_add(struct fimc_vid_cap *vid_cap,
675238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer *buf)
676238c84f7SMauro Carvalho Chehab {
677238c84f7SMauro Carvalho Chehab list_add_tail(&buf->list, &vid_cap->active_buf_q);
678238c84f7SMauro Carvalho Chehab vid_cap->active_buf_cnt++;
679238c84f7SMauro Carvalho Chehab }
680238c84f7SMauro Carvalho Chehab
681238c84f7SMauro Carvalho Chehab /**
682238c84f7SMauro Carvalho Chehab * fimc_active_queue_pop - pop buffer from the capture active buffers queue
683238c84f7SMauro Carvalho Chehab * @vid_cap: camera capture device information
684238c84f7SMauro Carvalho Chehab *
685238c84f7SMauro Carvalho Chehab * The caller must assure the active_buf_q list is not empty.
686238c84f7SMauro Carvalho Chehab */
fimc_active_queue_pop(struct fimc_vid_cap * vid_cap)687238c84f7SMauro Carvalho Chehab static inline struct fimc_vid_buffer *fimc_active_queue_pop(
688238c84f7SMauro Carvalho Chehab struct fimc_vid_cap *vid_cap)
689238c84f7SMauro Carvalho Chehab {
690238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer *buf;
691238c84f7SMauro Carvalho Chehab buf = list_entry(vid_cap->active_buf_q.next,
692238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer, list);
693238c84f7SMauro Carvalho Chehab list_del(&buf->list);
694238c84f7SMauro Carvalho Chehab vid_cap->active_buf_cnt--;
695238c84f7SMauro Carvalho Chehab return buf;
696238c84f7SMauro Carvalho Chehab }
697238c84f7SMauro Carvalho Chehab
698238c84f7SMauro Carvalho Chehab /**
699238c84f7SMauro Carvalho Chehab * fimc_pending_queue_add - add buffer to the capture pending buffers queue
700238c84f7SMauro Carvalho Chehab * @vid_cap: camera capture device information
701238c84f7SMauro Carvalho Chehab * @buf: buffer to add to the pending buffers list
702238c84f7SMauro Carvalho Chehab */
fimc_pending_queue_add(struct fimc_vid_cap * vid_cap,struct fimc_vid_buffer * buf)703238c84f7SMauro Carvalho Chehab static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
704238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer *buf)
705238c84f7SMauro Carvalho Chehab {
706238c84f7SMauro Carvalho Chehab list_add_tail(&buf->list, &vid_cap->pending_buf_q);
707238c84f7SMauro Carvalho Chehab }
708238c84f7SMauro Carvalho Chehab
709238c84f7SMauro Carvalho Chehab /**
710238c84f7SMauro Carvalho Chehab * fimc_pending_queue_pop - pop buffer from the capture pending buffers queue
711238c84f7SMauro Carvalho Chehab * @vid_cap: camera capture device information
712238c84f7SMauro Carvalho Chehab *
713238c84f7SMauro Carvalho Chehab * The caller must assure the pending_buf_q list is not empty.
714238c84f7SMauro Carvalho Chehab */
fimc_pending_queue_pop(struct fimc_vid_cap * vid_cap)715238c84f7SMauro Carvalho Chehab static inline struct fimc_vid_buffer *fimc_pending_queue_pop(
716238c84f7SMauro Carvalho Chehab struct fimc_vid_cap *vid_cap)
717238c84f7SMauro Carvalho Chehab {
718238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer *buf;
719238c84f7SMauro Carvalho Chehab buf = list_entry(vid_cap->pending_buf_q.next,
720238c84f7SMauro Carvalho Chehab struct fimc_vid_buffer, list);
721238c84f7SMauro Carvalho Chehab list_del(&buf->list);
722238c84f7SMauro Carvalho Chehab return buf;
723238c84f7SMauro Carvalho Chehab }
724238c84f7SMauro Carvalho Chehab
725238c84f7SMauro Carvalho Chehab #endif /* FIMC_CORE_H_ */
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