1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - ISP Subdevice 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/iopoll.h> 12 #include <linux/phy/phy.h> 13 #include <linux/phy/phy-mipi-dphy.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/videodev2.h> 16 #include <linux/vmalloc.h> 17 #include <media/v4l2-event.h> 18 19 #include "rkisp1-common.h" 20 21 #define RKISP1_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10 22 #define RKISP1_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8 23 24 #define RKISP1_ISP_DEV_NAME RKISP1_DRIVER_NAME "_isp" 25 26 /* 27 * NOTE: MIPI controller and input MUX are also configured in this file. 28 * This is because ISP Subdev describes not only ISP submodule (input size, 29 * format, output size, format), but also a virtual route device. 30 */ 31 32 /* 33 * There are many variables named with format/frame in below code, 34 * please see here for their meaning. 35 * Cropping in the sink pad defines the image region from the sensor. 36 * Cropping in the source pad defines the region for the Image Stabilizer (IS) 37 * 38 * Cropping regions of ISP 39 * 40 * +---------------------------------------------------------+ 41 * | Sensor image | 42 * | +---------------------------------------------------+ | 43 * | | CIF_ISP_ACQ (for black level) | | 44 * | | sink pad format | | 45 * | | +--------------------------------------------+ | | 46 * | | | CIF_ISP_OUT | | | 47 * | | | sink pad crop | | | 48 * | | | +---------------------------------+ | | | 49 * | | | | CIF_ISP_IS | | | | 50 * | | | | source pad crop and format | | | | 51 * | | | +---------------------------------+ | | | 52 * | | +--------------------------------------------+ | | 53 * | +---------------------------------------------------+ | 54 * +---------------------------------------------------------+ 55 */ 56 57 static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = { 58 { 59 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 60 .pixel_enc = V4L2_PIXEL_ENC_YUV, 61 .direction = RKISP1_ISP_SD_SRC, 62 }, { 63 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, 64 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 65 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 66 .bayer_pat = RKISP1_RAW_RGGB, 67 .bus_width = 10, 68 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 69 }, { 70 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, 71 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 72 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 73 .bayer_pat = RKISP1_RAW_BGGR, 74 .bus_width = 10, 75 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 76 }, { 77 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, 78 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 79 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 80 .bayer_pat = RKISP1_RAW_GBRG, 81 .bus_width = 10, 82 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 83 }, { 84 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, 85 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 86 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW10, 87 .bayer_pat = RKISP1_RAW_GRBG, 88 .bus_width = 10, 89 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 90 }, { 91 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, 92 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 93 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 94 .bayer_pat = RKISP1_RAW_RGGB, 95 .bus_width = 12, 96 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 97 }, { 98 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, 99 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 100 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 101 .bayer_pat = RKISP1_RAW_BGGR, 102 .bus_width = 12, 103 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 104 }, { 105 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, 106 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 107 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 108 .bayer_pat = RKISP1_RAW_GBRG, 109 .bus_width = 12, 110 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 111 }, { 112 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, 113 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 114 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW12, 115 .bayer_pat = RKISP1_RAW_GRBG, 116 .bus_width = 12, 117 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 118 }, { 119 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, 120 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 121 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 122 .bayer_pat = RKISP1_RAW_RGGB, 123 .bus_width = 8, 124 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 125 }, { 126 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 127 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 128 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 129 .bayer_pat = RKISP1_RAW_BGGR, 130 .bus_width = 8, 131 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 132 }, { 133 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, 134 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 135 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 136 .bayer_pat = RKISP1_RAW_GBRG, 137 .bus_width = 8, 138 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 139 }, { 140 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, 141 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 142 .mipi_dt = RKISP1_CIF_CSI2_DT_RAW8, 143 .bayer_pat = RKISP1_RAW_GRBG, 144 .bus_width = 8, 145 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 146 }, { 147 .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, 148 .pixel_enc = V4L2_PIXEL_ENC_YUV, 149 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 150 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR, 151 .bus_width = 16, 152 .direction = RKISP1_ISP_SD_SINK, 153 }, { 154 .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16, 155 .pixel_enc = V4L2_PIXEL_ENC_YUV, 156 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 157 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB, 158 .bus_width = 16, 159 .direction = RKISP1_ISP_SD_SINK, 160 }, { 161 .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, 162 .pixel_enc = V4L2_PIXEL_ENC_YUV, 163 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 164 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY, 165 .bus_width = 16, 166 .direction = RKISP1_ISP_SD_SINK, 167 }, { 168 .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, 169 .pixel_enc = V4L2_PIXEL_ENC_YUV, 170 .mipi_dt = RKISP1_CIF_CSI2_DT_YUV422_8b, 171 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY, 172 .bus_width = 16, 173 .direction = RKISP1_ISP_SD_SINK, 174 }, 175 }; 176 177 /* ---------------------------------------------------------------------------- 178 * Helpers 179 */ 180 181 const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code) 182 { 183 unsigned int i; 184 185 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) { 186 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i]; 187 188 if (fmt->mbus_code == mbus_code) 189 return fmt; 190 } 191 192 return NULL; 193 } 194 195 static struct v4l2_subdev *rkisp1_get_remote_sensor(struct v4l2_subdev *sd) 196 { 197 struct media_pad *local, *remote; 198 struct media_entity *sensor_me; 199 200 local = &sd->entity.pads[RKISP1_ISP_PAD_SINK_VIDEO]; 201 remote = media_entity_remote_pad(local); 202 if (!remote) 203 return NULL; 204 205 sensor_me = remote->entity; 206 return media_entity_to_v4l2_subdev(sensor_me); 207 } 208 209 static struct v4l2_mbus_framefmt * 210 rkisp1_isp_get_pad_fmt(struct rkisp1_isp *isp, 211 struct v4l2_subdev_state *sd_state, 212 unsigned int pad, u32 which) 213 { 214 struct v4l2_subdev_state state = { 215 .pads = isp->pad_cfg 216 }; 217 if (which == V4L2_SUBDEV_FORMAT_TRY) 218 return v4l2_subdev_get_try_format(&isp->sd, sd_state, pad); 219 else 220 return v4l2_subdev_get_try_format(&isp->sd, &state, pad); 221 } 222 223 static struct v4l2_rect * 224 rkisp1_isp_get_pad_crop(struct rkisp1_isp *isp, 225 struct v4l2_subdev_state *sd_state, 226 unsigned int pad, u32 which) 227 { 228 struct v4l2_subdev_state state = { 229 .pads = isp->pad_cfg 230 }; 231 if (which == V4L2_SUBDEV_FORMAT_TRY) 232 return v4l2_subdev_get_try_crop(&isp->sd, sd_state, pad); 233 else 234 return v4l2_subdev_get_try_crop(&isp->sd, &state, pad); 235 } 236 237 /* ---------------------------------------------------------------------------- 238 * Camera Interface registers configurations 239 */ 240 241 /* 242 * Image Stabilization. 243 * This should only be called when configuring CIF 244 * or at the frame end interrupt 245 */ 246 static void rkisp1_config_ism(struct rkisp1_device *rkisp1) 247 { 248 struct v4l2_rect *src_crop = 249 rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL, 250 RKISP1_ISP_PAD_SOURCE_VIDEO, 251 V4L2_SUBDEV_FORMAT_ACTIVE); 252 u32 val; 253 254 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_RECENTER); 255 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DX); 256 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DY); 257 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_DISPLACE); 258 rkisp1_write(rkisp1, src_crop->left, RKISP1_CIF_ISP_IS_H_OFFS); 259 rkisp1_write(rkisp1, src_crop->top, RKISP1_CIF_ISP_IS_V_OFFS); 260 rkisp1_write(rkisp1, src_crop->width, RKISP1_CIF_ISP_IS_H_SIZE); 261 rkisp1_write(rkisp1, src_crop->height, RKISP1_CIF_ISP_IS_V_SIZE); 262 263 /* IS(Image Stabilization) is always on, working as output crop */ 264 rkisp1_write(rkisp1, 1, RKISP1_CIF_ISP_IS_CTRL); 265 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 266 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD; 267 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL); 268 } 269 270 /* 271 * configure ISP blocks with input format, size...... 272 */ 273 static int rkisp1_config_isp(struct rkisp1_device *rkisp1) 274 { 275 u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0; 276 const struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt; 277 struct rkisp1_sensor_async *sensor; 278 struct v4l2_mbus_framefmt *sink_frm; 279 struct v4l2_rect *sink_crop; 280 281 sensor = rkisp1->active_sensor; 282 sink_fmt = rkisp1->isp.sink_fmt; 283 src_fmt = rkisp1->isp.src_fmt; 284 sink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL, 285 RKISP1_ISP_PAD_SINK_VIDEO, 286 V4L2_SUBDEV_FORMAT_ACTIVE); 287 sink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL, 288 RKISP1_ISP_PAD_SINK_VIDEO, 289 V4L2_SUBDEV_FORMAT_ACTIVE); 290 291 if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) { 292 acq_mult = 1; 293 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) { 294 if (sensor->mbus_type == V4L2_MBUS_BT656) 295 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656; 296 else 297 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT; 298 } else { 299 rkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc), 300 RKISP1_CIF_ISP_DEMOSAIC); 301 302 if (sensor->mbus_type == V4L2_MBUS_BT656) 303 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656; 304 else 305 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601; 306 } 307 } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) { 308 acq_mult = 2; 309 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) { 310 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601; 311 } else { 312 if (sensor->mbus_type == V4L2_MBUS_BT656) 313 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656; 314 else 315 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601; 316 } 317 318 irq_mask |= RKISP1_CIF_ISP_DATA_LOSS; 319 } 320 321 /* Set up input acquisition properties */ 322 if (sensor->mbus_type == V4L2_MBUS_BT656 || 323 sensor->mbus_type == V4L2_MBUS_PARALLEL) { 324 if (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 325 signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE; 326 } 327 328 if (sensor->mbus_type == V4L2_MBUS_PARALLEL) { 329 if (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) 330 signal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW; 331 332 if (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 333 signal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW; 334 } 335 336 rkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL); 337 rkisp1_write(rkisp1, signal | sink_fmt->yuv_seq | 338 RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) | 339 RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL, 340 RKISP1_CIF_ISP_ACQ_PROP); 341 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES); 342 343 /* Acquisition Size */ 344 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS); 345 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS); 346 rkisp1_write(rkisp1, 347 acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE); 348 rkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE); 349 350 /* ISP Out Area */ 351 rkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS); 352 rkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS); 353 rkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE); 354 rkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE); 355 356 irq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START | 357 RKISP1_CIF_ISP_PIC_SIZE_ERROR; 358 rkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC); 359 360 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) { 361 rkisp1_params_disable(&rkisp1->params); 362 } else { 363 struct v4l2_mbus_framefmt *src_frm; 364 365 src_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL, 366 RKISP1_ISP_PAD_SINK_VIDEO, 367 V4L2_SUBDEV_FORMAT_ACTIVE); 368 rkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat, 369 src_frm->quantization); 370 } 371 372 return 0; 373 } 374 375 static int rkisp1_config_dvp(struct rkisp1_device *rkisp1) 376 { 377 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt; 378 u32 val, input_sel; 379 380 switch (sink_fmt->bus_width) { 381 case 8: 382 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO; 383 break; 384 case 10: 385 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO; 386 break; 387 case 12: 388 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B; 389 break; 390 default: 391 dev_err(rkisp1->dev, "Invalid bus width\n"); 392 return -EINVAL; 393 } 394 395 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP); 396 rkisp1_write(rkisp1, val | input_sel, RKISP1_CIF_ISP_ACQ_PROP); 397 398 return 0; 399 } 400 401 static int rkisp1_config_mipi(struct rkisp1_device *rkisp1) 402 { 403 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt; 404 unsigned int lanes = rkisp1->active_sensor->lanes; 405 u32 mipi_ctrl; 406 407 if (lanes < 1 || lanes > 4) 408 return -EINVAL; 409 410 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | 411 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | 412 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP | 413 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA; 414 415 rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL); 416 417 /* V12 could also use a newer csi2-host, but we don't want that yet */ 418 if (rkisp1->media_dev.hw_revision == RKISP1_V12) 419 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0); 420 421 /* Configure Data Type and Virtual Channel */ 422 rkisp1_write(rkisp1, 423 RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) | 424 RKISP1_CIF_MIPI_DATA_SEL_VC(0), 425 RKISP1_CIF_MIPI_IMG_DATA_SEL); 426 427 /* Clear MIPI interrupts */ 428 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR); 429 /* 430 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for 431 * isp bus may be dead when switch isp. 432 */ 433 rkisp1_write(rkisp1, 434 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI | 435 RKISP1_CIF_MIPI_ERR_DPHY | 436 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | 437 RKISP1_CIF_MIPI_ADD_DATA_OVFLW, 438 RKISP1_CIF_MIPI_IMSC); 439 440 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n" 441 " MIPI_IMG_DATA_SEL 0x%08x\n" 442 " MIPI_STATUS 0x%08x\n" 443 " MIPI_IMSC 0x%08x\n", 444 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL), 445 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL), 446 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS), 447 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC)); 448 449 return 0; 450 } 451 452 /* Configure MUX */ 453 static int rkisp1_config_path(struct rkisp1_device *rkisp1) 454 { 455 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor; 456 u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL); 457 int ret = 0; 458 459 if (sensor->mbus_type == V4L2_MBUS_BT656 || 460 sensor->mbus_type == V4L2_MBUS_PARALLEL) { 461 ret = rkisp1_config_dvp(rkisp1); 462 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL; 463 } else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) { 464 ret = rkisp1_config_mipi(rkisp1); 465 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI; 466 } 467 468 rkisp1_write(rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 469 470 return ret; 471 } 472 473 /* Hardware configure Entry */ 474 static int rkisp1_config_cif(struct rkisp1_device *rkisp1) 475 { 476 u32 cif_id; 477 int ret; 478 479 cif_id = rkisp1_read(rkisp1, RKISP1_CIF_VI_ID); 480 dev_dbg(rkisp1->dev, "CIF_ID 0x%08x\n", cif_id); 481 482 ret = rkisp1_config_isp(rkisp1); 483 if (ret) 484 return ret; 485 ret = rkisp1_config_path(rkisp1); 486 if (ret) 487 return ret; 488 rkisp1_config_ism(rkisp1); 489 490 return 0; 491 } 492 493 static void rkisp1_isp_stop(struct rkisp1_device *rkisp1) 494 { 495 u32 val; 496 497 /* 498 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) -> 499 * Stop ISP(isp) ->wait for ISP isp off 500 */ 501 /* stop and clear MI, MIPI, and ISP interrupts */ 502 rkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC); 503 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR); 504 505 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC); 506 rkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR); 507 508 rkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC); 509 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR); 510 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 511 rkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA), 512 RKISP1_CIF_MIPI_CTRL); 513 /* stop ISP */ 514 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 515 val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE | 516 RKISP1_CIF_ISP_CTRL_ISP_ENABLE); 517 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL); 518 519 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 520 rkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD, 521 RKISP1_CIF_ISP_CTRL); 522 523 readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS, 524 val, val & RKISP1_CIF_ISP_OFF, 20, 100); 525 rkisp1_write(rkisp1, 526 RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST, 527 RKISP1_CIF_IRCL); 528 rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL); 529 } 530 531 static void rkisp1_config_clk(struct rkisp1_device *rkisp1) 532 { 533 u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK | 534 RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK | 535 RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK | 536 RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK | 537 RKISP1_CIF_ICCL_DCROP_CLK; 538 539 rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL); 540 541 /* ensure sp and mp can run at the same time in V12 */ 542 if (rkisp1->media_dev.hw_revision == RKISP1_V12) { 543 val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP | 544 RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 | 545 RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD | 546 RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE; 547 rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12); 548 } 549 } 550 551 static void rkisp1_isp_start(struct rkisp1_device *rkisp1) 552 { 553 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor; 554 u32 val; 555 556 rkisp1_config_clk(rkisp1); 557 558 /* Activate MIPI */ 559 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) { 560 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 561 rkisp1_write(rkisp1, val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA, 562 RKISP1_CIF_MIPI_CTRL); 563 } 564 /* Activate ISP */ 565 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 566 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD | 567 RKISP1_CIF_ISP_CTRL_ISP_ENABLE | 568 RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE; 569 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL); 570 571 /* 572 * CIF spec says to wait for sufficient time after enabling 573 * the MIPI interface and before starting the sensor output. 574 */ 575 usleep_range(1000, 1200); 576 } 577 578 /* ---------------------------------------------------------------------------- 579 * Subdev pad operations 580 */ 581 582 static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd, 583 struct v4l2_subdev_state *sd_state, 584 struct v4l2_subdev_mbus_code_enum *code) 585 { 586 unsigned int i, dir; 587 int pos = 0; 588 589 if (code->pad == RKISP1_ISP_PAD_SINK_VIDEO) { 590 dir = RKISP1_ISP_SD_SINK; 591 } else if (code->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) { 592 dir = RKISP1_ISP_SD_SRC; 593 } else { 594 if (code->index > 0) 595 return -EINVAL; 596 code->code = MEDIA_BUS_FMT_METADATA_FIXED; 597 return 0; 598 } 599 600 if (code->index >= ARRAY_SIZE(rkisp1_isp_formats)) 601 return -EINVAL; 602 603 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) { 604 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i]; 605 606 if (fmt->direction & dir) 607 pos++; 608 609 if (code->index == pos - 1) { 610 code->code = fmt->mbus_code; 611 if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV && 612 dir == RKISP1_ISP_SD_SRC) 613 code->flags = 614 V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION; 615 return 0; 616 } 617 } 618 619 return -EINVAL; 620 } 621 622 static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd, 623 struct v4l2_subdev_state *sd_state, 624 struct v4l2_subdev_frame_size_enum *fse) 625 { 626 const struct rkisp1_isp_mbus_info *mbus_info; 627 628 if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS || 629 fse->pad == RKISP1_ISP_PAD_SOURCE_STATS) 630 return -ENOTTY; 631 632 if (fse->index > 0) 633 return -EINVAL; 634 635 mbus_info = rkisp1_isp_mbus_info_get(fse->code); 636 if (!mbus_info) 637 return -EINVAL; 638 639 if (!(mbus_info->direction & RKISP1_ISP_SD_SINK) && 640 fse->pad == RKISP1_ISP_PAD_SINK_VIDEO) 641 return -EINVAL; 642 643 if (!(mbus_info->direction & RKISP1_ISP_SD_SRC) && 644 fse->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) 645 return -EINVAL; 646 647 fse->min_width = RKISP1_ISP_MIN_WIDTH; 648 fse->max_width = RKISP1_ISP_MAX_WIDTH; 649 fse->min_height = RKISP1_ISP_MIN_HEIGHT; 650 fse->max_height = RKISP1_ISP_MAX_HEIGHT; 651 652 return 0; 653 } 654 655 static int rkisp1_isp_init_config(struct v4l2_subdev *sd, 656 struct v4l2_subdev_state *sd_state) 657 { 658 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 659 struct v4l2_rect *sink_crop, *src_crop; 660 661 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state, 662 RKISP1_ISP_PAD_SINK_VIDEO); 663 sink_fmt->width = RKISP1_DEFAULT_WIDTH; 664 sink_fmt->height = RKISP1_DEFAULT_HEIGHT; 665 sink_fmt->field = V4L2_FIELD_NONE; 666 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT; 667 668 sink_crop = v4l2_subdev_get_try_crop(sd, sd_state, 669 RKISP1_ISP_PAD_SINK_VIDEO); 670 sink_crop->width = RKISP1_DEFAULT_WIDTH; 671 sink_crop->height = RKISP1_DEFAULT_HEIGHT; 672 sink_crop->left = 0; 673 sink_crop->top = 0; 674 675 src_fmt = v4l2_subdev_get_try_format(sd, sd_state, 676 RKISP1_ISP_PAD_SOURCE_VIDEO); 677 *src_fmt = *sink_fmt; 678 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT; 679 680 src_crop = v4l2_subdev_get_try_crop(sd, sd_state, 681 RKISP1_ISP_PAD_SOURCE_VIDEO); 682 *src_crop = *sink_crop; 683 684 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state, 685 RKISP1_ISP_PAD_SINK_PARAMS); 686 src_fmt = v4l2_subdev_get_try_format(sd, sd_state, 687 RKISP1_ISP_PAD_SOURCE_STATS); 688 sink_fmt->width = 0; 689 sink_fmt->height = 0; 690 sink_fmt->field = V4L2_FIELD_NONE; 691 sink_fmt->code = MEDIA_BUS_FMT_METADATA_FIXED; 692 *src_fmt = *sink_fmt; 693 694 return 0; 695 } 696 697 static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp, 698 struct v4l2_subdev_state *sd_state, 699 struct v4l2_mbus_framefmt *format, 700 unsigned int which) 701 { 702 const struct rkisp1_isp_mbus_info *mbus_info; 703 struct v4l2_mbus_framefmt *src_fmt; 704 const struct v4l2_rect *src_crop; 705 706 src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 707 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 708 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 709 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 710 711 src_fmt->code = format->code; 712 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code); 713 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) { 714 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT; 715 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code); 716 } 717 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) 718 isp->src_fmt = mbus_info; 719 src_fmt->width = src_crop->width; 720 src_fmt->height = src_crop->height; 721 722 /* 723 * The CSC API is used to allow userspace to force full 724 * quantization on YUV formats. 725 */ 726 if (format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC && 727 format->quantization == V4L2_QUANTIZATION_FULL_RANGE && 728 mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV) 729 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 730 else if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV) 731 src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE; 732 else 733 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 734 735 *format = *src_fmt; 736 } 737 738 static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp, 739 struct v4l2_subdev_state *sd_state, 740 struct v4l2_rect *r, unsigned int which) 741 { 742 struct v4l2_mbus_framefmt *src_fmt; 743 const struct v4l2_rect *sink_crop; 744 struct v4l2_rect *src_crop; 745 746 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 747 RKISP1_ISP_PAD_SOURCE_VIDEO, 748 which); 749 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 750 RKISP1_ISP_PAD_SINK_VIDEO, 751 which); 752 753 src_crop->left = ALIGN(r->left, 2); 754 src_crop->width = ALIGN(r->width, 2); 755 src_crop->top = r->top; 756 src_crop->height = r->height; 757 rkisp1_sd_adjust_crop_rect(src_crop, sink_crop); 758 759 *r = *src_crop; 760 761 /* Propagate to out format */ 762 src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 763 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 764 rkisp1_isp_set_src_fmt(isp, sd_state, src_fmt, which); 765 } 766 767 static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp, 768 struct v4l2_subdev_state *sd_state, 769 struct v4l2_rect *r, unsigned int which) 770 { 771 struct v4l2_rect *sink_crop, *src_crop; 772 struct v4l2_mbus_framefmt *sink_fmt; 773 774 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 775 RKISP1_ISP_PAD_SINK_VIDEO, 776 which); 777 sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 778 RKISP1_ISP_PAD_SINK_VIDEO, 779 which); 780 781 sink_crop->left = ALIGN(r->left, 2); 782 sink_crop->width = ALIGN(r->width, 2); 783 sink_crop->top = r->top; 784 sink_crop->height = r->height; 785 rkisp1_sd_adjust_crop(sink_crop, sink_fmt); 786 787 *r = *sink_crop; 788 789 /* Propagate to out crop */ 790 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 791 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 792 rkisp1_isp_set_src_crop(isp, sd_state, src_crop, which); 793 } 794 795 static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp, 796 struct v4l2_subdev_state *sd_state, 797 struct v4l2_mbus_framefmt *format, 798 unsigned int which) 799 { 800 const struct rkisp1_isp_mbus_info *mbus_info; 801 struct v4l2_mbus_framefmt *sink_fmt; 802 struct v4l2_rect *sink_crop; 803 804 sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 805 RKISP1_ISP_PAD_SINK_VIDEO, 806 which); 807 sink_fmt->code = format->code; 808 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code); 809 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) { 810 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT; 811 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code); 812 } 813 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) 814 isp->sink_fmt = mbus_info; 815 816 sink_fmt->width = clamp_t(u32, format->width, 817 RKISP1_ISP_MIN_WIDTH, 818 RKISP1_ISP_MAX_WIDTH); 819 sink_fmt->height = clamp_t(u32, format->height, 820 RKISP1_ISP_MIN_HEIGHT, 821 RKISP1_ISP_MAX_HEIGHT); 822 823 *format = *sink_fmt; 824 825 /* Propagate to in crop */ 826 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 827 RKISP1_ISP_PAD_SINK_VIDEO, 828 which); 829 rkisp1_isp_set_sink_crop(isp, sd_state, sink_crop, which); 830 } 831 832 static int rkisp1_isp_get_fmt(struct v4l2_subdev *sd, 833 struct v4l2_subdev_state *sd_state, 834 struct v4l2_subdev_format *fmt) 835 { 836 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 837 838 mutex_lock(&isp->ops_lock); 839 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad, 840 fmt->which); 841 mutex_unlock(&isp->ops_lock); 842 return 0; 843 } 844 845 static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd, 846 struct v4l2_subdev_state *sd_state, 847 struct v4l2_subdev_format *fmt) 848 { 849 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 850 851 mutex_lock(&isp->ops_lock); 852 if (fmt->pad == RKISP1_ISP_PAD_SINK_VIDEO) 853 rkisp1_isp_set_sink_fmt(isp, sd_state, &fmt->format, 854 fmt->which); 855 else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) 856 rkisp1_isp_set_src_fmt(isp, sd_state, &fmt->format, 857 fmt->which); 858 else 859 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad, 860 fmt->which); 861 862 mutex_unlock(&isp->ops_lock); 863 return 0; 864 } 865 866 static int rkisp1_isp_get_selection(struct v4l2_subdev *sd, 867 struct v4l2_subdev_state *sd_state, 868 struct v4l2_subdev_selection *sel) 869 { 870 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 871 int ret = 0; 872 873 if (sel->pad != RKISP1_ISP_PAD_SOURCE_VIDEO && 874 sel->pad != RKISP1_ISP_PAD_SINK_VIDEO) 875 return -EINVAL; 876 877 mutex_lock(&isp->ops_lock); 878 switch (sel->target) { 879 case V4L2_SEL_TGT_CROP_BOUNDS: 880 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) { 881 struct v4l2_mbus_framefmt *fmt; 882 883 fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, sel->pad, 884 sel->which); 885 sel->r.height = fmt->height; 886 sel->r.width = fmt->width; 887 sel->r.left = 0; 888 sel->r.top = 0; 889 } else { 890 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state, 891 RKISP1_ISP_PAD_SINK_VIDEO, 892 sel->which); 893 } 894 break; 895 case V4L2_SEL_TGT_CROP: 896 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state, sel->pad, 897 sel->which); 898 break; 899 default: 900 ret = -EINVAL; 901 } 902 mutex_unlock(&isp->ops_lock); 903 return ret; 904 } 905 906 static int rkisp1_isp_set_selection(struct v4l2_subdev *sd, 907 struct v4l2_subdev_state *sd_state, 908 struct v4l2_subdev_selection *sel) 909 { 910 struct rkisp1_device *rkisp1 = 911 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev); 912 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 913 int ret = 0; 914 915 if (sel->target != V4L2_SEL_TGT_CROP) 916 return -EINVAL; 917 918 dev_dbg(rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, 919 sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height); 920 mutex_lock(&isp->ops_lock); 921 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) 922 rkisp1_isp_set_sink_crop(isp, sd_state, &sel->r, sel->which); 923 else if (sel->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) 924 rkisp1_isp_set_src_crop(isp, sd_state, &sel->r, sel->which); 925 else 926 ret = -EINVAL; 927 928 mutex_unlock(&isp->ops_lock); 929 return ret; 930 } 931 932 static int rkisp1_subdev_link_validate(struct media_link *link) 933 { 934 if (link->sink->index == RKISP1_ISP_PAD_SINK_PARAMS) 935 return 0; 936 937 return v4l2_subdev_link_validate(link); 938 } 939 940 static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = { 941 .enum_mbus_code = rkisp1_isp_enum_mbus_code, 942 .enum_frame_size = rkisp1_isp_enum_frame_size, 943 .get_selection = rkisp1_isp_get_selection, 944 .set_selection = rkisp1_isp_set_selection, 945 .init_cfg = rkisp1_isp_init_config, 946 .get_fmt = rkisp1_isp_get_fmt, 947 .set_fmt = rkisp1_isp_set_fmt, 948 .link_validate = v4l2_subdev_link_validate_default, 949 }; 950 951 /* ---------------------------------------------------------------------------- 952 * Stream operations 953 */ 954 955 static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp, 956 struct rkisp1_sensor_async *sensor) 957 { 958 struct rkisp1_device *rkisp1 = 959 container_of(isp->sd.v4l2_dev, struct rkisp1_device, v4l2_dev); 960 union phy_configure_opts opts; 961 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; 962 s64 pixel_clock; 963 964 if (!sensor->pixel_rate_ctrl) { 965 dev_warn(rkisp1->dev, "No pixel rate control in sensor subdev\n"); 966 return -EPIPE; 967 } 968 969 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl); 970 if (!pixel_clock) { 971 dev_err(rkisp1->dev, "Invalid pixel rate value\n"); 972 return -EINVAL; 973 } 974 975 phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width, 976 sensor->lanes, cfg); 977 phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY); 978 phy_configure(sensor->dphy, &opts); 979 phy_power_on(sensor->dphy); 980 981 return 0; 982 } 983 984 static void rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async *sensor) 985 { 986 phy_power_off(sensor->dphy); 987 } 988 989 static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable) 990 { 991 struct rkisp1_device *rkisp1 = 992 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev); 993 struct rkisp1_isp *isp = &rkisp1->isp; 994 struct v4l2_subdev *sensor_sd; 995 int ret = 0; 996 997 if (!enable) { 998 rkisp1_isp_stop(rkisp1); 999 rkisp1_mipi_csi2_stop(rkisp1->active_sensor); 1000 return 0; 1001 } 1002 1003 sensor_sd = rkisp1_get_remote_sensor(sd); 1004 if (!sensor_sd) { 1005 dev_warn(rkisp1->dev, "No link between isp and sensor\n"); 1006 return -ENODEV; 1007 } 1008 1009 rkisp1->active_sensor = container_of(sensor_sd->asd, 1010 struct rkisp1_sensor_async, asd); 1011 1012 if (rkisp1->active_sensor->mbus_type != V4L2_MBUS_CSI2_DPHY) 1013 return -EINVAL; 1014 1015 rkisp1->isp.frame_sequence = -1; 1016 mutex_lock(&isp->ops_lock); 1017 ret = rkisp1_config_cif(rkisp1); 1018 if (ret) 1019 goto mutex_unlock; 1020 1021 ret = rkisp1_mipi_csi2_start(&rkisp1->isp, rkisp1->active_sensor); 1022 if (ret) 1023 goto mutex_unlock; 1024 1025 rkisp1_isp_start(rkisp1); 1026 1027 mutex_unlock: 1028 mutex_unlock(&isp->ops_lock); 1029 return ret; 1030 } 1031 1032 static int rkisp1_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1033 struct v4l2_event_subscription *sub) 1034 { 1035 if (sub->type != V4L2_EVENT_FRAME_SYNC) 1036 return -EINVAL; 1037 1038 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */ 1039 if (sub->id != 0) 1040 return -EINVAL; 1041 1042 return v4l2_event_subscribe(fh, sub, 0, NULL); 1043 } 1044 1045 static const struct media_entity_operations rkisp1_isp_media_ops = { 1046 .link_validate = rkisp1_subdev_link_validate, 1047 }; 1048 1049 static const struct v4l2_subdev_video_ops rkisp1_isp_video_ops = { 1050 .s_stream = rkisp1_isp_s_stream, 1051 }; 1052 1053 static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = { 1054 .subscribe_event = rkisp1_isp_subs_evt, 1055 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1056 }; 1057 1058 static const struct v4l2_subdev_ops rkisp1_isp_ops = { 1059 .core = &rkisp1_isp_core_ops, 1060 .video = &rkisp1_isp_video_ops, 1061 .pad = &rkisp1_isp_pad_ops, 1062 }; 1063 1064 int rkisp1_isp_register(struct rkisp1_device *rkisp1) 1065 { 1066 struct v4l2_subdev_state state = { 1067 .pads = rkisp1->isp.pad_cfg 1068 }; 1069 struct rkisp1_isp *isp = &rkisp1->isp; 1070 struct media_pad *pads = isp->pads; 1071 struct v4l2_subdev *sd = &isp->sd; 1072 int ret; 1073 1074 v4l2_subdev_init(sd, &rkisp1_isp_ops); 1075 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1076 sd->entity.ops = &rkisp1_isp_media_ops; 1077 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 1078 sd->owner = THIS_MODULE; 1079 strscpy(sd->name, RKISP1_ISP_DEV_NAME, sizeof(sd->name)); 1080 1081 pads[RKISP1_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK | 1082 MEDIA_PAD_FL_MUST_CONNECT; 1083 pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK; 1084 pads[RKISP1_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE; 1085 pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE; 1086 1087 isp->sink_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SINK_PAD_FMT); 1088 isp->src_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SRC_PAD_FMT); 1089 1090 mutex_init(&isp->ops_lock); 1091 ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, pads); 1092 if (ret) 1093 return ret; 1094 1095 ret = v4l2_device_register_subdev(&rkisp1->v4l2_dev, sd); 1096 if (ret) { 1097 dev_err(rkisp1->dev, "Failed to register isp subdev\n"); 1098 goto err_cleanup_media_entity; 1099 } 1100 1101 rkisp1_isp_init_config(sd, &state); 1102 return 0; 1103 1104 err_cleanup_media_entity: 1105 media_entity_cleanup(&sd->entity); 1106 1107 return ret; 1108 } 1109 1110 void rkisp1_isp_unregister(struct rkisp1_device *rkisp1) 1111 { 1112 struct v4l2_subdev *sd = &rkisp1->isp.sd; 1113 1114 v4l2_device_unregister_subdev(sd); 1115 media_entity_cleanup(&sd->entity); 1116 } 1117 1118 /* ---------------------------------------------------------------------------- 1119 * Interrupt handlers 1120 */ 1121 1122 irqreturn_t rkisp1_mipi_isr(int irq, void *ctx) 1123 { 1124 struct device *dev = ctx; 1125 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 1126 u32 val, status; 1127 1128 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS); 1129 if (!status) 1130 return IRQ_NONE; 1131 1132 rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR); 1133 1134 /* 1135 * Disable DPHY errctrl interrupt, because this dphy 1136 * erctrl signal is asserted until the next changes 1137 * of line state. This time is may be too long and cpu 1138 * is hold in this interrupt. 1139 */ 1140 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) { 1141 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 1142 rkisp1_write(rkisp1, val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f), 1143 RKISP1_CIF_MIPI_IMSC); 1144 rkisp1->isp.is_dphy_errctrl_disabled = true; 1145 } 1146 1147 /* 1148 * Enable DPHY errctrl interrupt again, if mipi have receive 1149 * the whole frame without any error. 1150 */ 1151 if (status == RKISP1_CIF_MIPI_FRAME_END) { 1152 /* 1153 * Enable DPHY errctrl interrupt again, if mipi have receive 1154 * the whole frame without any error. 1155 */ 1156 if (rkisp1->isp.is_dphy_errctrl_disabled) { 1157 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 1158 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f); 1159 rkisp1_write(rkisp1, val, RKISP1_CIF_MIPI_IMSC); 1160 rkisp1->isp.is_dphy_errctrl_disabled = false; 1161 } 1162 } else { 1163 rkisp1->debug.mipi_error++; 1164 } 1165 1166 return IRQ_HANDLED; 1167 } 1168 1169 static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp) 1170 { 1171 struct v4l2_event event = { 1172 .type = V4L2_EVENT_FRAME_SYNC, 1173 }; 1174 event.u.frame_sync.frame_sequence = isp->frame_sequence; 1175 1176 v4l2_event_queue(isp->sd.devnode, &event); 1177 } 1178 1179 irqreturn_t rkisp1_isp_isr(int irq, void *ctx) 1180 { 1181 struct device *dev = ctx; 1182 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 1183 u32 status, isp_err; 1184 1185 status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS); 1186 if (!status) 1187 return IRQ_NONE; 1188 1189 rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR); 1190 1191 /* Vertical sync signal, starting generating new frame */ 1192 if (status & RKISP1_CIF_ISP_V_START) { 1193 rkisp1->isp.frame_sequence++; 1194 rkisp1_isp_queue_event_sof(&rkisp1->isp); 1195 if (status & RKISP1_CIF_ISP_FRAME) { 1196 WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n"); 1197 rkisp1->debug.irq_delay++; 1198 } 1199 } 1200 if (status & RKISP1_CIF_ISP_PIC_SIZE_ERROR) { 1201 /* Clear pic_size_error */ 1202 isp_err = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ERR); 1203 if (isp_err & RKISP1_CIF_ISP_ERR_INFORM_SIZE) 1204 rkisp1->debug.inform_size_error++; 1205 if (isp_err & RKISP1_CIF_ISP_ERR_IS_SIZE) 1206 rkisp1->debug.img_stabilization_size_error++; 1207 if (isp_err & RKISP1_CIF_ISP_ERR_OUTFORM_SIZE) 1208 rkisp1->debug.outform_size_error++; 1209 rkisp1_write(rkisp1, isp_err, RKISP1_CIF_ISP_ERR_CLR); 1210 } else if (status & RKISP1_CIF_ISP_DATA_LOSS) { 1211 /* keep track of data_loss in debugfs */ 1212 rkisp1->debug.data_loss++; 1213 } 1214 1215 if (status & RKISP1_CIF_ISP_FRAME) { 1216 u32 isp_ris; 1217 1218 /* New frame from the sensor received */ 1219 isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS); 1220 if (isp_ris & RKISP1_STATS_MEAS_MASK) 1221 rkisp1_stats_isr(&rkisp1->stats, isp_ris); 1222 /* 1223 * Then update changed configs. Some of them involve 1224 * lot of register writes. Do those only one per frame. 1225 * Do the updates in the order of the processing flow. 1226 */ 1227 rkisp1_params_isr(rkisp1); 1228 } 1229 1230 return IRQ_HANDLED; 1231 } 1232