1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - ISP Subdevice 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/iopoll.h> 12 #include <linux/phy/phy.h> 13 #include <linux/phy/phy-mipi-dphy.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/videodev2.h> 16 #include <linux/vmalloc.h> 17 18 #include <media/mipi-csi2.h> 19 #include <media/v4l2-event.h> 20 21 #include "rkisp1-common.h" 22 23 #define RKISP1_DEF_SINK_PAD_FMT MEDIA_BUS_FMT_SRGGB10_1X10 24 #define RKISP1_DEF_SRC_PAD_FMT MEDIA_BUS_FMT_YUYV8_2X8 25 26 #define RKISP1_ISP_DEV_NAME RKISP1_DRIVER_NAME "_isp" 27 28 /* 29 * NOTE: MIPI controller and input MUX are also configured in this file. 30 * This is because ISP Subdev describes not only ISP submodule (input size, 31 * format, output size, format), but also a virtual route device. 32 */ 33 34 /* 35 * There are many variables named with format/frame in below code, 36 * please see here for their meaning. 37 * Cropping in the sink pad defines the image region from the sensor. 38 * Cropping in the source pad defines the region for the Image Stabilizer (IS) 39 * 40 * Cropping regions of ISP 41 * 42 * +---------------------------------------------------------+ 43 * | Sensor image | 44 * | +---------------------------------------------------+ | 45 * | | CIF_ISP_ACQ (for black level) | | 46 * | | sink pad format | | 47 * | | +--------------------------------------------+ | | 48 * | | | CIF_ISP_OUT | | | 49 * | | | sink pad crop | | | 50 * | | | +---------------------------------+ | | | 51 * | | | | CIF_ISP_IS | | | | 52 * | | | | source pad crop and format | | | | 53 * | | | +---------------------------------+ | | | 54 * | | +--------------------------------------------+ | | 55 * | +---------------------------------------------------+ | 56 * +---------------------------------------------------------+ 57 */ 58 59 static const struct rkisp1_isp_mbus_info rkisp1_isp_formats[] = { 60 { 61 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8, 62 .pixel_enc = V4L2_PIXEL_ENC_YUV, 63 .direction = RKISP1_ISP_SD_SRC, 64 }, { 65 .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, 66 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 67 .mipi_dt = MIPI_CSI2_DT_RAW10, 68 .bayer_pat = RKISP1_RAW_RGGB, 69 .bus_width = 10, 70 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 71 }, { 72 .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, 73 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 74 .mipi_dt = MIPI_CSI2_DT_RAW10, 75 .bayer_pat = RKISP1_RAW_BGGR, 76 .bus_width = 10, 77 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 78 }, { 79 .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, 80 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 81 .mipi_dt = MIPI_CSI2_DT_RAW10, 82 .bayer_pat = RKISP1_RAW_GBRG, 83 .bus_width = 10, 84 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 85 }, { 86 .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, 87 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 88 .mipi_dt = MIPI_CSI2_DT_RAW10, 89 .bayer_pat = RKISP1_RAW_GRBG, 90 .bus_width = 10, 91 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 92 }, { 93 .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, 94 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 95 .mipi_dt = MIPI_CSI2_DT_RAW12, 96 .bayer_pat = RKISP1_RAW_RGGB, 97 .bus_width = 12, 98 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 99 }, { 100 .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, 101 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 102 .mipi_dt = MIPI_CSI2_DT_RAW12, 103 .bayer_pat = RKISP1_RAW_BGGR, 104 .bus_width = 12, 105 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 106 }, { 107 .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, 108 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 109 .mipi_dt = MIPI_CSI2_DT_RAW12, 110 .bayer_pat = RKISP1_RAW_GBRG, 111 .bus_width = 12, 112 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 113 }, { 114 .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, 115 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 116 .mipi_dt = MIPI_CSI2_DT_RAW12, 117 .bayer_pat = RKISP1_RAW_GRBG, 118 .bus_width = 12, 119 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 120 }, { 121 .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, 122 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 123 .mipi_dt = MIPI_CSI2_DT_RAW8, 124 .bayer_pat = RKISP1_RAW_RGGB, 125 .bus_width = 8, 126 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 127 }, { 128 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, 129 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 130 .mipi_dt = MIPI_CSI2_DT_RAW8, 131 .bayer_pat = RKISP1_RAW_BGGR, 132 .bus_width = 8, 133 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 134 }, { 135 .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, 136 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 137 .mipi_dt = MIPI_CSI2_DT_RAW8, 138 .bayer_pat = RKISP1_RAW_GBRG, 139 .bus_width = 8, 140 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 141 }, { 142 .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, 143 .pixel_enc = V4L2_PIXEL_ENC_BAYER, 144 .mipi_dt = MIPI_CSI2_DT_RAW8, 145 .bayer_pat = RKISP1_RAW_GRBG, 146 .bus_width = 8, 147 .direction = RKISP1_ISP_SD_SINK | RKISP1_ISP_SD_SRC, 148 }, { 149 .mbus_code = MEDIA_BUS_FMT_YUYV8_1X16, 150 .pixel_enc = V4L2_PIXEL_ENC_YUV, 151 .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 152 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCBYCR, 153 .bus_width = 16, 154 .direction = RKISP1_ISP_SD_SINK, 155 }, { 156 .mbus_code = MEDIA_BUS_FMT_YVYU8_1X16, 157 .pixel_enc = V4L2_PIXEL_ENC_YUV, 158 .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 159 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_YCRYCB, 160 .bus_width = 16, 161 .direction = RKISP1_ISP_SD_SINK, 162 }, { 163 .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, 164 .pixel_enc = V4L2_PIXEL_ENC_YUV, 165 .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 166 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CBYCRY, 167 .bus_width = 16, 168 .direction = RKISP1_ISP_SD_SINK, 169 }, { 170 .mbus_code = MEDIA_BUS_FMT_VYUY8_1X16, 171 .pixel_enc = V4L2_PIXEL_ENC_YUV, 172 .mipi_dt = MIPI_CSI2_DT_YUV422_8B, 173 .yuv_seq = RKISP1_CIF_ISP_ACQ_PROP_CRYCBY, 174 .bus_width = 16, 175 .direction = RKISP1_ISP_SD_SINK, 176 }, 177 }; 178 179 /* ---------------------------------------------------------------------------- 180 * Helpers 181 */ 182 183 const struct rkisp1_isp_mbus_info *rkisp1_isp_mbus_info_get(u32 mbus_code) 184 { 185 unsigned int i; 186 187 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) { 188 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i]; 189 190 if (fmt->mbus_code == mbus_code) 191 return fmt; 192 } 193 194 return NULL; 195 } 196 197 static struct v4l2_subdev *rkisp1_get_remote_sensor(struct v4l2_subdev *sd) 198 { 199 struct media_pad *local, *remote; 200 struct media_entity *sensor_me; 201 202 local = &sd->entity.pads[RKISP1_ISP_PAD_SINK_VIDEO]; 203 remote = media_entity_remote_pad(local); 204 if (!remote) 205 return NULL; 206 207 sensor_me = remote->entity; 208 return media_entity_to_v4l2_subdev(sensor_me); 209 } 210 211 static struct v4l2_mbus_framefmt * 212 rkisp1_isp_get_pad_fmt(struct rkisp1_isp *isp, 213 struct v4l2_subdev_state *sd_state, 214 unsigned int pad, u32 which) 215 { 216 struct v4l2_subdev_state state = { 217 .pads = isp->pad_cfg 218 }; 219 if (which == V4L2_SUBDEV_FORMAT_TRY) 220 return v4l2_subdev_get_try_format(&isp->sd, sd_state, pad); 221 else 222 return v4l2_subdev_get_try_format(&isp->sd, &state, pad); 223 } 224 225 static struct v4l2_rect * 226 rkisp1_isp_get_pad_crop(struct rkisp1_isp *isp, 227 struct v4l2_subdev_state *sd_state, 228 unsigned int pad, u32 which) 229 { 230 struct v4l2_subdev_state state = { 231 .pads = isp->pad_cfg 232 }; 233 if (which == V4L2_SUBDEV_FORMAT_TRY) 234 return v4l2_subdev_get_try_crop(&isp->sd, sd_state, pad); 235 else 236 return v4l2_subdev_get_try_crop(&isp->sd, &state, pad); 237 } 238 239 /* ---------------------------------------------------------------------------- 240 * Camera Interface registers configurations 241 */ 242 243 /* 244 * Image Stabilization. 245 * This should only be called when configuring CIF 246 * or at the frame end interrupt 247 */ 248 static void rkisp1_config_ism(struct rkisp1_device *rkisp1) 249 { 250 struct v4l2_rect *src_crop = 251 rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL, 252 RKISP1_ISP_PAD_SOURCE_VIDEO, 253 V4L2_SUBDEV_FORMAT_ACTIVE); 254 u32 val; 255 256 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_RECENTER); 257 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DX); 258 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_MAX_DY); 259 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IS_DISPLACE); 260 rkisp1_write(rkisp1, src_crop->left, RKISP1_CIF_ISP_IS_H_OFFS); 261 rkisp1_write(rkisp1, src_crop->top, RKISP1_CIF_ISP_IS_V_OFFS); 262 rkisp1_write(rkisp1, src_crop->width, RKISP1_CIF_ISP_IS_H_SIZE); 263 rkisp1_write(rkisp1, src_crop->height, RKISP1_CIF_ISP_IS_V_SIZE); 264 265 /* IS(Image Stabilization) is always on, working as output crop */ 266 rkisp1_write(rkisp1, 1, RKISP1_CIF_ISP_IS_CTRL); 267 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 268 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD; 269 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL); 270 } 271 272 /* 273 * configure ISP blocks with input format, size...... 274 */ 275 static int rkisp1_config_isp(struct rkisp1_device *rkisp1) 276 { 277 u32 isp_ctrl = 0, irq_mask = 0, acq_mult = 0, signal = 0; 278 const struct rkisp1_isp_mbus_info *src_fmt, *sink_fmt; 279 struct rkisp1_sensor_async *sensor; 280 struct v4l2_mbus_framefmt *sink_frm; 281 struct v4l2_rect *sink_crop; 282 283 sensor = rkisp1->active_sensor; 284 sink_fmt = rkisp1->isp.sink_fmt; 285 src_fmt = rkisp1->isp.src_fmt; 286 sink_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL, 287 RKISP1_ISP_PAD_SINK_VIDEO, 288 V4L2_SUBDEV_FORMAT_ACTIVE); 289 sink_crop = rkisp1_isp_get_pad_crop(&rkisp1->isp, NULL, 290 RKISP1_ISP_PAD_SINK_VIDEO, 291 V4L2_SUBDEV_FORMAT_ACTIVE); 292 293 if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) { 294 acq_mult = 1; 295 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) { 296 if (sensor->mbus_type == V4L2_MBUS_BT656) 297 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT_ITU656; 298 else 299 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_RAW_PICT; 300 } else { 301 rkisp1_write(rkisp1, RKISP1_CIF_ISP_DEMOSAIC_TH(0xc), 302 RKISP1_CIF_ISP_DEMOSAIC); 303 304 if (sensor->mbus_type == V4L2_MBUS_BT656) 305 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU656; 306 else 307 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_BAYER_ITU601; 308 } 309 } else if (sink_fmt->pixel_enc == V4L2_PIXEL_ENC_YUV) { 310 acq_mult = 2; 311 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) { 312 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601; 313 } else { 314 if (sensor->mbus_type == V4L2_MBUS_BT656) 315 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU656; 316 else 317 isp_ctrl = RKISP1_CIF_ISP_CTRL_ISP_MODE_ITU601; 318 } 319 320 irq_mask |= RKISP1_CIF_ISP_DATA_LOSS; 321 } 322 323 /* Set up input acquisition properties */ 324 if (sensor->mbus_type == V4L2_MBUS_BT656 || 325 sensor->mbus_type == V4L2_MBUS_PARALLEL) { 326 if (sensor->mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) 327 signal = RKISP1_CIF_ISP_ACQ_PROP_POS_EDGE; 328 } 329 330 if (sensor->mbus_type == V4L2_MBUS_PARALLEL) { 331 if (sensor->mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW) 332 signal |= RKISP1_CIF_ISP_ACQ_PROP_VSYNC_LOW; 333 334 if (sensor->mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) 335 signal |= RKISP1_CIF_ISP_ACQ_PROP_HSYNC_LOW; 336 } 337 338 rkisp1_write(rkisp1, isp_ctrl, RKISP1_CIF_ISP_CTRL); 339 rkisp1_write(rkisp1, signal | sink_fmt->yuv_seq | 340 RKISP1_CIF_ISP_ACQ_PROP_BAYER_PAT(sink_fmt->bayer_pat) | 341 RKISP1_CIF_ISP_ACQ_PROP_FIELD_SEL_ALL, 342 RKISP1_CIF_ISP_ACQ_PROP); 343 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_NR_FRAMES); 344 345 /* Acquisition Size */ 346 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_H_OFFS); 347 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_ACQ_V_OFFS); 348 rkisp1_write(rkisp1, 349 acq_mult * sink_frm->width, RKISP1_CIF_ISP_ACQ_H_SIZE); 350 rkisp1_write(rkisp1, sink_frm->height, RKISP1_CIF_ISP_ACQ_V_SIZE); 351 352 /* ISP Out Area */ 353 rkisp1_write(rkisp1, sink_crop->left, RKISP1_CIF_ISP_OUT_H_OFFS); 354 rkisp1_write(rkisp1, sink_crop->top, RKISP1_CIF_ISP_OUT_V_OFFS); 355 rkisp1_write(rkisp1, sink_crop->width, RKISP1_CIF_ISP_OUT_H_SIZE); 356 rkisp1_write(rkisp1, sink_crop->height, RKISP1_CIF_ISP_OUT_V_SIZE); 357 358 irq_mask |= RKISP1_CIF_ISP_FRAME | RKISP1_CIF_ISP_V_START | 359 RKISP1_CIF_ISP_PIC_SIZE_ERROR; 360 rkisp1_write(rkisp1, irq_mask, RKISP1_CIF_ISP_IMSC); 361 362 if (src_fmt->pixel_enc == V4L2_PIXEL_ENC_BAYER) { 363 rkisp1_params_disable(&rkisp1->params); 364 } else { 365 struct v4l2_mbus_framefmt *src_frm; 366 367 src_frm = rkisp1_isp_get_pad_fmt(&rkisp1->isp, NULL, 368 RKISP1_ISP_PAD_SINK_VIDEO, 369 V4L2_SUBDEV_FORMAT_ACTIVE); 370 rkisp1_params_configure(&rkisp1->params, sink_fmt->bayer_pat, 371 src_frm->quantization); 372 } 373 374 return 0; 375 } 376 377 static int rkisp1_config_dvp(struct rkisp1_device *rkisp1) 378 { 379 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt; 380 u32 val, input_sel; 381 382 switch (sink_fmt->bus_width) { 383 case 8: 384 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_8B_ZERO; 385 break; 386 case 10: 387 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_10B_ZERO; 388 break; 389 case 12: 390 input_sel = RKISP1_CIF_ISP_ACQ_PROP_IN_SEL_12B; 391 break; 392 default: 393 dev_err(rkisp1->dev, "Invalid bus width\n"); 394 return -EINVAL; 395 } 396 397 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ACQ_PROP); 398 rkisp1_write(rkisp1, val | input_sel, RKISP1_CIF_ISP_ACQ_PROP); 399 400 return 0; 401 } 402 403 static int rkisp1_config_mipi(struct rkisp1_device *rkisp1) 404 { 405 const struct rkisp1_isp_mbus_info *sink_fmt = rkisp1->isp.sink_fmt; 406 unsigned int lanes = rkisp1->active_sensor->lanes; 407 u32 mipi_ctrl; 408 409 if (lanes < 1 || lanes > 4) 410 return -EINVAL; 411 412 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | 413 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | 414 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP | 415 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA; 416 417 rkisp1_write(rkisp1, mipi_ctrl, RKISP1_CIF_MIPI_CTRL); 418 419 /* V12 could also use a newer csi2-host, but we don't want that yet */ 420 if (rkisp1->media_dev.hw_revision == RKISP1_V12) 421 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_CSI0_CTRL0); 422 423 /* Configure Data Type and Virtual Channel */ 424 rkisp1_write(rkisp1, 425 RKISP1_CIF_MIPI_DATA_SEL_DT(sink_fmt->mipi_dt) | 426 RKISP1_CIF_MIPI_DATA_SEL_VC(0), 427 RKISP1_CIF_MIPI_IMG_DATA_SEL); 428 429 /* Clear MIPI interrupts */ 430 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR); 431 /* 432 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for 433 * isp bus may be dead when switch isp. 434 */ 435 rkisp1_write(rkisp1, 436 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI | 437 RKISP1_CIF_MIPI_ERR_DPHY | 438 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | 439 RKISP1_CIF_MIPI_ADD_DATA_OVFLW, 440 RKISP1_CIF_MIPI_IMSC); 441 442 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n" 443 " MIPI_IMG_DATA_SEL 0x%08x\n" 444 " MIPI_STATUS 0x%08x\n" 445 " MIPI_IMSC 0x%08x\n", 446 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL), 447 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL), 448 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS), 449 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC)); 450 451 return 0; 452 } 453 454 /* Configure MUX */ 455 static int rkisp1_config_path(struct rkisp1_device *rkisp1) 456 { 457 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor; 458 u32 dpcl = rkisp1_read(rkisp1, RKISP1_CIF_VI_DPCL); 459 int ret = 0; 460 461 if (sensor->mbus_type == V4L2_MBUS_BT656 || 462 sensor->mbus_type == V4L2_MBUS_PARALLEL) { 463 ret = rkisp1_config_dvp(rkisp1); 464 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_PARALLEL; 465 } else if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) { 466 ret = rkisp1_config_mipi(rkisp1); 467 dpcl |= RKISP1_CIF_VI_DPCL_IF_SEL_MIPI; 468 } 469 470 rkisp1_write(rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 471 472 return ret; 473 } 474 475 /* Hardware configure Entry */ 476 static int rkisp1_config_cif(struct rkisp1_device *rkisp1) 477 { 478 u32 cif_id; 479 int ret; 480 481 cif_id = rkisp1_read(rkisp1, RKISP1_CIF_VI_ID); 482 dev_dbg(rkisp1->dev, "CIF_ID 0x%08x\n", cif_id); 483 484 ret = rkisp1_config_isp(rkisp1); 485 if (ret) 486 return ret; 487 ret = rkisp1_config_path(rkisp1); 488 if (ret) 489 return ret; 490 rkisp1_config_ism(rkisp1); 491 492 return 0; 493 } 494 495 static void rkisp1_isp_stop(struct rkisp1_device *rkisp1) 496 { 497 u32 val; 498 499 /* 500 * ISP(mi) stop in mi frame end -> Stop ISP(mipi) -> 501 * Stop ISP(isp) ->wait for ISP isp off 502 */ 503 /* stop and clear MI, MIPI, and ISP interrupts */ 504 rkisp1_write(rkisp1, 0, RKISP1_CIF_MIPI_IMSC); 505 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MIPI_ICR); 506 507 rkisp1_write(rkisp1, 0, RKISP1_CIF_ISP_IMSC); 508 rkisp1_write(rkisp1, ~0, RKISP1_CIF_ISP_ICR); 509 510 rkisp1_write(rkisp1, 0, RKISP1_CIF_MI_IMSC); 511 rkisp1_write(rkisp1, ~0, RKISP1_CIF_MI_ICR); 512 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 513 rkisp1_write(rkisp1, val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA), 514 RKISP1_CIF_MIPI_CTRL); 515 /* stop ISP */ 516 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 517 val &= ~(RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE | 518 RKISP1_CIF_ISP_CTRL_ISP_ENABLE); 519 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL); 520 521 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 522 rkisp1_write(rkisp1, val | RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD, 523 RKISP1_CIF_ISP_CTRL); 524 525 readx_poll_timeout(readl, rkisp1->base_addr + RKISP1_CIF_ISP_RIS, 526 val, val & RKISP1_CIF_ISP_OFF, 20, 100); 527 rkisp1_write(rkisp1, 528 RKISP1_CIF_IRCL_MIPI_SW_RST | RKISP1_CIF_IRCL_ISP_SW_RST, 529 RKISP1_CIF_IRCL); 530 rkisp1_write(rkisp1, 0x0, RKISP1_CIF_IRCL); 531 } 532 533 static void rkisp1_config_clk(struct rkisp1_device *rkisp1) 534 { 535 u32 val = RKISP1_CIF_ICCL_ISP_CLK | RKISP1_CIF_ICCL_CP_CLK | 536 RKISP1_CIF_ICCL_MRSZ_CLK | RKISP1_CIF_ICCL_SRSZ_CLK | 537 RKISP1_CIF_ICCL_JPEG_CLK | RKISP1_CIF_ICCL_MI_CLK | 538 RKISP1_CIF_ICCL_IE_CLK | RKISP1_CIF_ICCL_MIPI_CLK | 539 RKISP1_CIF_ICCL_DCROP_CLK; 540 541 rkisp1_write(rkisp1, val, RKISP1_CIF_ICCL); 542 543 /* ensure sp and mp can run at the same time in V12 */ 544 if (rkisp1->media_dev.hw_revision == RKISP1_V12) { 545 val = RKISP1_CIF_CLK_CTRL_MI_Y12 | RKISP1_CIF_CLK_CTRL_MI_SP | 546 RKISP1_CIF_CLK_CTRL_MI_RAW0 | RKISP1_CIF_CLK_CTRL_MI_RAW1 | 547 RKISP1_CIF_CLK_CTRL_MI_READ | RKISP1_CIF_CLK_CTRL_MI_RAWRD | 548 RKISP1_CIF_CLK_CTRL_CP | RKISP1_CIF_CLK_CTRL_IE; 549 rkisp1_write(rkisp1, val, RKISP1_CIF_VI_ISP_CLK_CTRL_V12); 550 } 551 } 552 553 static void rkisp1_isp_start(struct rkisp1_device *rkisp1) 554 { 555 struct rkisp1_sensor_async *sensor = rkisp1->active_sensor; 556 u32 val; 557 558 rkisp1_config_clk(rkisp1); 559 560 /* Activate MIPI */ 561 if (sensor->mbus_type == V4L2_MBUS_CSI2_DPHY) { 562 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 563 rkisp1_write(rkisp1, val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA, 564 RKISP1_CIF_MIPI_CTRL); 565 } 566 /* Activate ISP */ 567 val = rkisp1_read(rkisp1, RKISP1_CIF_ISP_CTRL); 568 val |= RKISP1_CIF_ISP_CTRL_ISP_CFG_UPD | 569 RKISP1_CIF_ISP_CTRL_ISP_ENABLE | 570 RKISP1_CIF_ISP_CTRL_ISP_INFORM_ENABLE; 571 rkisp1_write(rkisp1, val, RKISP1_CIF_ISP_CTRL); 572 573 /* 574 * CIF spec says to wait for sufficient time after enabling 575 * the MIPI interface and before starting the sensor output. 576 */ 577 usleep_range(1000, 1200); 578 } 579 580 /* ---------------------------------------------------------------------------- 581 * Subdev pad operations 582 */ 583 584 static int rkisp1_isp_enum_mbus_code(struct v4l2_subdev *sd, 585 struct v4l2_subdev_state *sd_state, 586 struct v4l2_subdev_mbus_code_enum *code) 587 { 588 unsigned int i, dir; 589 int pos = 0; 590 591 if (code->pad == RKISP1_ISP_PAD_SINK_VIDEO) { 592 dir = RKISP1_ISP_SD_SINK; 593 } else if (code->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) { 594 dir = RKISP1_ISP_SD_SRC; 595 } else { 596 if (code->index > 0) 597 return -EINVAL; 598 code->code = MEDIA_BUS_FMT_METADATA_FIXED; 599 return 0; 600 } 601 602 if (code->index >= ARRAY_SIZE(rkisp1_isp_formats)) 603 return -EINVAL; 604 605 for (i = 0; i < ARRAY_SIZE(rkisp1_isp_formats); i++) { 606 const struct rkisp1_isp_mbus_info *fmt = &rkisp1_isp_formats[i]; 607 608 if (fmt->direction & dir) 609 pos++; 610 611 if (code->index == pos - 1) { 612 code->code = fmt->mbus_code; 613 if (fmt->pixel_enc == V4L2_PIXEL_ENC_YUV && 614 dir == RKISP1_ISP_SD_SRC) 615 code->flags = 616 V4L2_SUBDEV_MBUS_CODE_CSC_QUANTIZATION; 617 return 0; 618 } 619 } 620 621 return -EINVAL; 622 } 623 624 static int rkisp1_isp_enum_frame_size(struct v4l2_subdev *sd, 625 struct v4l2_subdev_state *sd_state, 626 struct v4l2_subdev_frame_size_enum *fse) 627 { 628 const struct rkisp1_isp_mbus_info *mbus_info; 629 630 if (fse->pad == RKISP1_ISP_PAD_SINK_PARAMS || 631 fse->pad == RKISP1_ISP_PAD_SOURCE_STATS) 632 return -ENOTTY; 633 634 if (fse->index > 0) 635 return -EINVAL; 636 637 mbus_info = rkisp1_isp_mbus_info_get(fse->code); 638 if (!mbus_info) 639 return -EINVAL; 640 641 if (!(mbus_info->direction & RKISP1_ISP_SD_SINK) && 642 fse->pad == RKISP1_ISP_PAD_SINK_VIDEO) 643 return -EINVAL; 644 645 if (!(mbus_info->direction & RKISP1_ISP_SD_SRC) && 646 fse->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) 647 return -EINVAL; 648 649 fse->min_width = RKISP1_ISP_MIN_WIDTH; 650 fse->max_width = RKISP1_ISP_MAX_WIDTH; 651 fse->min_height = RKISP1_ISP_MIN_HEIGHT; 652 fse->max_height = RKISP1_ISP_MAX_HEIGHT; 653 654 return 0; 655 } 656 657 static int rkisp1_isp_init_config(struct v4l2_subdev *sd, 658 struct v4l2_subdev_state *sd_state) 659 { 660 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 661 struct v4l2_rect *sink_crop, *src_crop; 662 663 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state, 664 RKISP1_ISP_PAD_SINK_VIDEO); 665 sink_fmt->width = RKISP1_DEFAULT_WIDTH; 666 sink_fmt->height = RKISP1_DEFAULT_HEIGHT; 667 sink_fmt->field = V4L2_FIELD_NONE; 668 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT; 669 670 sink_crop = v4l2_subdev_get_try_crop(sd, sd_state, 671 RKISP1_ISP_PAD_SINK_VIDEO); 672 sink_crop->width = RKISP1_DEFAULT_WIDTH; 673 sink_crop->height = RKISP1_DEFAULT_HEIGHT; 674 sink_crop->left = 0; 675 sink_crop->top = 0; 676 677 src_fmt = v4l2_subdev_get_try_format(sd, sd_state, 678 RKISP1_ISP_PAD_SOURCE_VIDEO); 679 *src_fmt = *sink_fmt; 680 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT; 681 682 src_crop = v4l2_subdev_get_try_crop(sd, sd_state, 683 RKISP1_ISP_PAD_SOURCE_VIDEO); 684 *src_crop = *sink_crop; 685 686 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state, 687 RKISP1_ISP_PAD_SINK_PARAMS); 688 src_fmt = v4l2_subdev_get_try_format(sd, sd_state, 689 RKISP1_ISP_PAD_SOURCE_STATS); 690 sink_fmt->width = 0; 691 sink_fmt->height = 0; 692 sink_fmt->field = V4L2_FIELD_NONE; 693 sink_fmt->code = MEDIA_BUS_FMT_METADATA_FIXED; 694 *src_fmt = *sink_fmt; 695 696 return 0; 697 } 698 699 static void rkisp1_isp_set_src_fmt(struct rkisp1_isp *isp, 700 struct v4l2_subdev_state *sd_state, 701 struct v4l2_mbus_framefmt *format, 702 unsigned int which) 703 { 704 const struct rkisp1_isp_mbus_info *mbus_info; 705 struct v4l2_mbus_framefmt *src_fmt; 706 const struct v4l2_rect *src_crop; 707 708 src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 709 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 710 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 711 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 712 713 src_fmt->code = format->code; 714 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code); 715 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SRC)) { 716 src_fmt->code = RKISP1_DEF_SRC_PAD_FMT; 717 mbus_info = rkisp1_isp_mbus_info_get(src_fmt->code); 718 } 719 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) 720 isp->src_fmt = mbus_info; 721 src_fmt->width = src_crop->width; 722 src_fmt->height = src_crop->height; 723 724 /* 725 * The CSC API is used to allow userspace to force full 726 * quantization on YUV formats. 727 */ 728 if (format->flags & V4L2_MBUS_FRAMEFMT_SET_CSC && 729 format->quantization == V4L2_QUANTIZATION_FULL_RANGE && 730 mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV) 731 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 732 else if (mbus_info->pixel_enc == V4L2_PIXEL_ENC_YUV) 733 src_fmt->quantization = V4L2_QUANTIZATION_LIM_RANGE; 734 else 735 src_fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE; 736 737 *format = *src_fmt; 738 } 739 740 static void rkisp1_isp_set_src_crop(struct rkisp1_isp *isp, 741 struct v4l2_subdev_state *sd_state, 742 struct v4l2_rect *r, unsigned int which) 743 { 744 struct v4l2_mbus_framefmt *src_fmt; 745 const struct v4l2_rect *sink_crop; 746 struct v4l2_rect *src_crop; 747 748 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 749 RKISP1_ISP_PAD_SOURCE_VIDEO, 750 which); 751 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 752 RKISP1_ISP_PAD_SINK_VIDEO, 753 which); 754 755 src_crop->left = ALIGN(r->left, 2); 756 src_crop->width = ALIGN(r->width, 2); 757 src_crop->top = r->top; 758 src_crop->height = r->height; 759 rkisp1_sd_adjust_crop_rect(src_crop, sink_crop); 760 761 *r = *src_crop; 762 763 /* Propagate to out format */ 764 src_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 765 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 766 rkisp1_isp_set_src_fmt(isp, sd_state, src_fmt, which); 767 } 768 769 static void rkisp1_isp_set_sink_crop(struct rkisp1_isp *isp, 770 struct v4l2_subdev_state *sd_state, 771 struct v4l2_rect *r, unsigned int which) 772 { 773 struct v4l2_rect *sink_crop, *src_crop; 774 struct v4l2_mbus_framefmt *sink_fmt; 775 776 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 777 RKISP1_ISP_PAD_SINK_VIDEO, 778 which); 779 sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 780 RKISP1_ISP_PAD_SINK_VIDEO, 781 which); 782 783 sink_crop->left = ALIGN(r->left, 2); 784 sink_crop->width = ALIGN(r->width, 2); 785 sink_crop->top = r->top; 786 sink_crop->height = r->height; 787 rkisp1_sd_adjust_crop(sink_crop, sink_fmt); 788 789 *r = *sink_crop; 790 791 /* Propagate to out crop */ 792 src_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 793 RKISP1_ISP_PAD_SOURCE_VIDEO, which); 794 rkisp1_isp_set_src_crop(isp, sd_state, src_crop, which); 795 } 796 797 static void rkisp1_isp_set_sink_fmt(struct rkisp1_isp *isp, 798 struct v4l2_subdev_state *sd_state, 799 struct v4l2_mbus_framefmt *format, 800 unsigned int which) 801 { 802 const struct rkisp1_isp_mbus_info *mbus_info; 803 struct v4l2_mbus_framefmt *sink_fmt; 804 struct v4l2_rect *sink_crop; 805 806 sink_fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, 807 RKISP1_ISP_PAD_SINK_VIDEO, 808 which); 809 sink_fmt->code = format->code; 810 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code); 811 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) { 812 sink_fmt->code = RKISP1_DEF_SINK_PAD_FMT; 813 mbus_info = rkisp1_isp_mbus_info_get(sink_fmt->code); 814 } 815 if (which == V4L2_SUBDEV_FORMAT_ACTIVE) 816 isp->sink_fmt = mbus_info; 817 818 sink_fmt->width = clamp_t(u32, format->width, 819 RKISP1_ISP_MIN_WIDTH, 820 RKISP1_ISP_MAX_WIDTH); 821 sink_fmt->height = clamp_t(u32, format->height, 822 RKISP1_ISP_MIN_HEIGHT, 823 RKISP1_ISP_MAX_HEIGHT); 824 825 *format = *sink_fmt; 826 827 /* Propagate to in crop */ 828 sink_crop = rkisp1_isp_get_pad_crop(isp, sd_state, 829 RKISP1_ISP_PAD_SINK_VIDEO, 830 which); 831 rkisp1_isp_set_sink_crop(isp, sd_state, sink_crop, which); 832 } 833 834 static int rkisp1_isp_get_fmt(struct v4l2_subdev *sd, 835 struct v4l2_subdev_state *sd_state, 836 struct v4l2_subdev_format *fmt) 837 { 838 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 839 840 mutex_lock(&isp->ops_lock); 841 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad, 842 fmt->which); 843 mutex_unlock(&isp->ops_lock); 844 return 0; 845 } 846 847 static int rkisp1_isp_set_fmt(struct v4l2_subdev *sd, 848 struct v4l2_subdev_state *sd_state, 849 struct v4l2_subdev_format *fmt) 850 { 851 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 852 853 mutex_lock(&isp->ops_lock); 854 if (fmt->pad == RKISP1_ISP_PAD_SINK_VIDEO) 855 rkisp1_isp_set_sink_fmt(isp, sd_state, &fmt->format, 856 fmt->which); 857 else if (fmt->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) 858 rkisp1_isp_set_src_fmt(isp, sd_state, &fmt->format, 859 fmt->which); 860 else 861 fmt->format = *rkisp1_isp_get_pad_fmt(isp, sd_state, fmt->pad, 862 fmt->which); 863 864 mutex_unlock(&isp->ops_lock); 865 return 0; 866 } 867 868 static int rkisp1_isp_get_selection(struct v4l2_subdev *sd, 869 struct v4l2_subdev_state *sd_state, 870 struct v4l2_subdev_selection *sel) 871 { 872 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 873 int ret = 0; 874 875 if (sel->pad != RKISP1_ISP_PAD_SOURCE_VIDEO && 876 sel->pad != RKISP1_ISP_PAD_SINK_VIDEO) 877 return -EINVAL; 878 879 mutex_lock(&isp->ops_lock); 880 switch (sel->target) { 881 case V4L2_SEL_TGT_CROP_BOUNDS: 882 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) { 883 struct v4l2_mbus_framefmt *fmt; 884 885 fmt = rkisp1_isp_get_pad_fmt(isp, sd_state, sel->pad, 886 sel->which); 887 sel->r.height = fmt->height; 888 sel->r.width = fmt->width; 889 sel->r.left = 0; 890 sel->r.top = 0; 891 } else { 892 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state, 893 RKISP1_ISP_PAD_SINK_VIDEO, 894 sel->which); 895 } 896 break; 897 case V4L2_SEL_TGT_CROP: 898 sel->r = *rkisp1_isp_get_pad_crop(isp, sd_state, sel->pad, 899 sel->which); 900 break; 901 default: 902 ret = -EINVAL; 903 } 904 mutex_unlock(&isp->ops_lock); 905 return ret; 906 } 907 908 static int rkisp1_isp_set_selection(struct v4l2_subdev *sd, 909 struct v4l2_subdev_state *sd_state, 910 struct v4l2_subdev_selection *sel) 911 { 912 struct rkisp1_device *rkisp1 = 913 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev); 914 struct rkisp1_isp *isp = container_of(sd, struct rkisp1_isp, sd); 915 int ret = 0; 916 917 if (sel->target != V4L2_SEL_TGT_CROP) 918 return -EINVAL; 919 920 dev_dbg(rkisp1->dev, "%s: pad: %d sel(%d,%d)/%dx%d\n", __func__, 921 sel->pad, sel->r.left, sel->r.top, sel->r.width, sel->r.height); 922 mutex_lock(&isp->ops_lock); 923 if (sel->pad == RKISP1_ISP_PAD_SINK_VIDEO) 924 rkisp1_isp_set_sink_crop(isp, sd_state, &sel->r, sel->which); 925 else if (sel->pad == RKISP1_ISP_PAD_SOURCE_VIDEO) 926 rkisp1_isp_set_src_crop(isp, sd_state, &sel->r, sel->which); 927 else 928 ret = -EINVAL; 929 930 mutex_unlock(&isp->ops_lock); 931 return ret; 932 } 933 934 static int rkisp1_subdev_link_validate(struct media_link *link) 935 { 936 if (link->sink->index == RKISP1_ISP_PAD_SINK_PARAMS) 937 return 0; 938 939 return v4l2_subdev_link_validate(link); 940 } 941 942 static const struct v4l2_subdev_pad_ops rkisp1_isp_pad_ops = { 943 .enum_mbus_code = rkisp1_isp_enum_mbus_code, 944 .enum_frame_size = rkisp1_isp_enum_frame_size, 945 .get_selection = rkisp1_isp_get_selection, 946 .set_selection = rkisp1_isp_set_selection, 947 .init_cfg = rkisp1_isp_init_config, 948 .get_fmt = rkisp1_isp_get_fmt, 949 .set_fmt = rkisp1_isp_set_fmt, 950 .link_validate = v4l2_subdev_link_validate_default, 951 }; 952 953 /* ---------------------------------------------------------------------------- 954 * Stream operations 955 */ 956 957 static int rkisp1_mipi_csi2_start(struct rkisp1_isp *isp, 958 struct rkisp1_sensor_async *sensor) 959 { 960 struct rkisp1_device *rkisp1 = 961 container_of(isp->sd.v4l2_dev, struct rkisp1_device, v4l2_dev); 962 union phy_configure_opts opts; 963 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; 964 s64 pixel_clock; 965 966 if (!sensor->pixel_rate_ctrl) { 967 dev_warn(rkisp1->dev, "No pixel rate control in sensor subdev\n"); 968 return -EPIPE; 969 } 970 971 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl); 972 if (!pixel_clock) { 973 dev_err(rkisp1->dev, "Invalid pixel rate value\n"); 974 return -EINVAL; 975 } 976 977 phy_mipi_dphy_get_default_config(pixel_clock, isp->sink_fmt->bus_width, 978 sensor->lanes, cfg); 979 phy_set_mode(sensor->dphy, PHY_MODE_MIPI_DPHY); 980 phy_configure(sensor->dphy, &opts); 981 phy_power_on(sensor->dphy); 982 983 return 0; 984 } 985 986 static void rkisp1_mipi_csi2_stop(struct rkisp1_sensor_async *sensor) 987 { 988 phy_power_off(sensor->dphy); 989 } 990 991 static int rkisp1_isp_s_stream(struct v4l2_subdev *sd, int enable) 992 { 993 struct rkisp1_device *rkisp1 = 994 container_of(sd->v4l2_dev, struct rkisp1_device, v4l2_dev); 995 struct rkisp1_isp *isp = &rkisp1->isp; 996 struct v4l2_subdev *sensor_sd; 997 int ret = 0; 998 999 if (!enable) { 1000 rkisp1_isp_stop(rkisp1); 1001 rkisp1_mipi_csi2_stop(rkisp1->active_sensor); 1002 return 0; 1003 } 1004 1005 sensor_sd = rkisp1_get_remote_sensor(sd); 1006 if (!sensor_sd) { 1007 dev_warn(rkisp1->dev, "No link between isp and sensor\n"); 1008 return -ENODEV; 1009 } 1010 1011 rkisp1->active_sensor = container_of(sensor_sd->asd, 1012 struct rkisp1_sensor_async, asd); 1013 1014 if (rkisp1->active_sensor->mbus_type != V4L2_MBUS_CSI2_DPHY) 1015 return -EINVAL; 1016 1017 rkisp1->isp.frame_sequence = -1; 1018 mutex_lock(&isp->ops_lock); 1019 ret = rkisp1_config_cif(rkisp1); 1020 if (ret) 1021 goto mutex_unlock; 1022 1023 ret = rkisp1_mipi_csi2_start(&rkisp1->isp, rkisp1->active_sensor); 1024 if (ret) 1025 goto mutex_unlock; 1026 1027 rkisp1_isp_start(rkisp1); 1028 1029 mutex_unlock: 1030 mutex_unlock(&isp->ops_lock); 1031 return ret; 1032 } 1033 1034 static int rkisp1_isp_subs_evt(struct v4l2_subdev *sd, struct v4l2_fh *fh, 1035 struct v4l2_event_subscription *sub) 1036 { 1037 if (sub->type != V4L2_EVENT_FRAME_SYNC) 1038 return -EINVAL; 1039 1040 /* V4L2_EVENT_FRAME_SYNC doesn't require an id, so zero should be set */ 1041 if (sub->id != 0) 1042 return -EINVAL; 1043 1044 return v4l2_event_subscribe(fh, sub, 0, NULL); 1045 } 1046 1047 static const struct media_entity_operations rkisp1_isp_media_ops = { 1048 .link_validate = rkisp1_subdev_link_validate, 1049 }; 1050 1051 static const struct v4l2_subdev_video_ops rkisp1_isp_video_ops = { 1052 .s_stream = rkisp1_isp_s_stream, 1053 }; 1054 1055 static const struct v4l2_subdev_core_ops rkisp1_isp_core_ops = { 1056 .subscribe_event = rkisp1_isp_subs_evt, 1057 .unsubscribe_event = v4l2_event_subdev_unsubscribe, 1058 }; 1059 1060 static const struct v4l2_subdev_ops rkisp1_isp_ops = { 1061 .core = &rkisp1_isp_core_ops, 1062 .video = &rkisp1_isp_video_ops, 1063 .pad = &rkisp1_isp_pad_ops, 1064 }; 1065 1066 int rkisp1_isp_register(struct rkisp1_device *rkisp1) 1067 { 1068 struct v4l2_subdev_state state = { 1069 .pads = rkisp1->isp.pad_cfg 1070 }; 1071 struct rkisp1_isp *isp = &rkisp1->isp; 1072 struct media_pad *pads = isp->pads; 1073 struct v4l2_subdev *sd = &isp->sd; 1074 int ret; 1075 1076 v4l2_subdev_init(sd, &rkisp1_isp_ops); 1077 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS; 1078 sd->entity.ops = &rkisp1_isp_media_ops; 1079 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 1080 sd->owner = THIS_MODULE; 1081 strscpy(sd->name, RKISP1_ISP_DEV_NAME, sizeof(sd->name)); 1082 1083 pads[RKISP1_ISP_PAD_SINK_VIDEO].flags = MEDIA_PAD_FL_SINK | 1084 MEDIA_PAD_FL_MUST_CONNECT; 1085 pads[RKISP1_ISP_PAD_SINK_PARAMS].flags = MEDIA_PAD_FL_SINK; 1086 pads[RKISP1_ISP_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE; 1087 pads[RKISP1_ISP_PAD_SOURCE_STATS].flags = MEDIA_PAD_FL_SOURCE; 1088 1089 isp->sink_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SINK_PAD_FMT); 1090 isp->src_fmt = rkisp1_isp_mbus_info_get(RKISP1_DEF_SRC_PAD_FMT); 1091 1092 mutex_init(&isp->ops_lock); 1093 ret = media_entity_pads_init(&sd->entity, RKISP1_ISP_PAD_MAX, pads); 1094 if (ret) 1095 return ret; 1096 1097 ret = v4l2_device_register_subdev(&rkisp1->v4l2_dev, sd); 1098 if (ret) { 1099 dev_err(rkisp1->dev, "Failed to register isp subdev\n"); 1100 goto err_cleanup_media_entity; 1101 } 1102 1103 rkisp1_isp_init_config(sd, &state); 1104 return 0; 1105 1106 err_cleanup_media_entity: 1107 media_entity_cleanup(&sd->entity); 1108 1109 return ret; 1110 } 1111 1112 void rkisp1_isp_unregister(struct rkisp1_device *rkisp1) 1113 { 1114 struct v4l2_subdev *sd = &rkisp1->isp.sd; 1115 1116 v4l2_device_unregister_subdev(sd); 1117 media_entity_cleanup(&sd->entity); 1118 } 1119 1120 /* ---------------------------------------------------------------------------- 1121 * Interrupt handlers 1122 */ 1123 1124 irqreturn_t rkisp1_mipi_isr(int irq, void *ctx) 1125 { 1126 struct device *dev = ctx; 1127 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 1128 u32 val, status; 1129 1130 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS); 1131 if (!status) 1132 return IRQ_NONE; 1133 1134 rkisp1_write(rkisp1, status, RKISP1_CIF_MIPI_ICR); 1135 1136 /* 1137 * Disable DPHY errctrl interrupt, because this dphy 1138 * erctrl signal is asserted until the next changes 1139 * of line state. This time is may be too long and cpu 1140 * is hold in this interrupt. 1141 */ 1142 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) { 1143 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 1144 rkisp1_write(rkisp1, val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f), 1145 RKISP1_CIF_MIPI_IMSC); 1146 rkisp1->isp.is_dphy_errctrl_disabled = true; 1147 } 1148 1149 /* 1150 * Enable DPHY errctrl interrupt again, if mipi have receive 1151 * the whole frame without any error. 1152 */ 1153 if (status == RKISP1_CIF_MIPI_FRAME_END) { 1154 /* 1155 * Enable DPHY errctrl interrupt again, if mipi have receive 1156 * the whole frame without any error. 1157 */ 1158 if (rkisp1->isp.is_dphy_errctrl_disabled) { 1159 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 1160 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f); 1161 rkisp1_write(rkisp1, val, RKISP1_CIF_MIPI_IMSC); 1162 rkisp1->isp.is_dphy_errctrl_disabled = false; 1163 } 1164 } else { 1165 rkisp1->debug.mipi_error++; 1166 } 1167 1168 return IRQ_HANDLED; 1169 } 1170 1171 static void rkisp1_isp_queue_event_sof(struct rkisp1_isp *isp) 1172 { 1173 struct v4l2_event event = { 1174 .type = V4L2_EVENT_FRAME_SYNC, 1175 }; 1176 event.u.frame_sync.frame_sequence = isp->frame_sequence; 1177 1178 v4l2_event_queue(isp->sd.devnode, &event); 1179 } 1180 1181 irqreturn_t rkisp1_isp_isr(int irq, void *ctx) 1182 { 1183 struct device *dev = ctx; 1184 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 1185 u32 status, isp_err; 1186 1187 status = rkisp1_read(rkisp1, RKISP1_CIF_ISP_MIS); 1188 if (!status) 1189 return IRQ_NONE; 1190 1191 rkisp1_write(rkisp1, status, RKISP1_CIF_ISP_ICR); 1192 1193 /* Vertical sync signal, starting generating new frame */ 1194 if (status & RKISP1_CIF_ISP_V_START) { 1195 rkisp1->isp.frame_sequence++; 1196 rkisp1_isp_queue_event_sof(&rkisp1->isp); 1197 if (status & RKISP1_CIF_ISP_FRAME) { 1198 WARN_ONCE(1, "irq delay is too long, buffers might not be in sync\n"); 1199 rkisp1->debug.irq_delay++; 1200 } 1201 } 1202 if (status & RKISP1_CIF_ISP_PIC_SIZE_ERROR) { 1203 /* Clear pic_size_error */ 1204 isp_err = rkisp1_read(rkisp1, RKISP1_CIF_ISP_ERR); 1205 if (isp_err & RKISP1_CIF_ISP_ERR_INFORM_SIZE) 1206 rkisp1->debug.inform_size_error++; 1207 if (isp_err & RKISP1_CIF_ISP_ERR_IS_SIZE) 1208 rkisp1->debug.img_stabilization_size_error++; 1209 if (isp_err & RKISP1_CIF_ISP_ERR_OUTFORM_SIZE) 1210 rkisp1->debug.outform_size_error++; 1211 rkisp1_write(rkisp1, isp_err, RKISP1_CIF_ISP_ERR_CLR); 1212 } else if (status & RKISP1_CIF_ISP_DATA_LOSS) { 1213 /* keep track of data_loss in debugfs */ 1214 rkisp1->debug.data_loss++; 1215 } 1216 1217 if (status & RKISP1_CIF_ISP_FRAME) { 1218 u32 isp_ris; 1219 1220 /* New frame from the sensor received */ 1221 isp_ris = rkisp1_read(rkisp1, RKISP1_CIF_ISP_RIS); 1222 if (isp_ris & RKISP1_STATS_MEAS_MASK) 1223 rkisp1_stats_isr(&rkisp1->stats, isp_ris); 1224 /* 1225 * Then update changed configs. Some of them involve 1226 * lot of register writes. Do those only one per frame. 1227 * Do the updates in the order of the processing flow. 1228 */ 1229 rkisp1_params_isr(rkisp1); 1230 } 1231 1232 return IRQ_HANDLED; 1233 } 1234