1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Rockchip ISP1 Driver - CSI-2 Receiver
4  *
5  * Copyright (C) 2019 Collabora, Ltd.
6  * Copyright (C) 2022 Ideas on Board
7  *
8  * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd.
9  * Copyright (C) 2017 Rockchip Electronics Co., Ltd.
10  */
11 
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/lockdep.h>
15 #include <linux/phy/phy.h>
16 #include <linux/phy/phy-mipi-dphy.h>
17 
18 #include <media/v4l2-ctrls.h>
19 #include <media/v4l2-fwnode.h>
20 
21 #include "rkisp1-common.h"
22 #include "rkisp1-csi.h"
23 
24 #define RKISP1_CSI_DEV_NAME	RKISP1_DRIVER_NAME "_csi"
25 
26 #define RKISP1_CSI_DEF_FMT	MEDIA_BUS_FMT_SRGGB10_1X10
27 
28 static inline struct rkisp1_csi *to_rkisp1_csi(struct v4l2_subdev *sd)
29 {
30 	return container_of(sd, struct rkisp1_csi, sd);
31 }
32 
33 static struct v4l2_mbus_framefmt *
34 rkisp1_csi_get_pad_fmt(struct rkisp1_csi *csi,
35 		       struct v4l2_subdev_state *sd_state,
36 		       unsigned int pad, u32 which)
37 {
38 	struct v4l2_subdev_state state = {
39 		.pads = csi->pad_cfg
40 	};
41 
42 	lockdep_assert_held(&csi->lock);
43 
44 	if (which == V4L2_SUBDEV_FORMAT_TRY)
45 		return v4l2_subdev_get_try_format(&csi->sd, sd_state, pad);
46 	else
47 		return v4l2_subdev_get_try_format(&csi->sd, &state, pad);
48 }
49 
50 int rkisp1_csi_link_sensor(struct rkisp1_device *rkisp1, struct v4l2_subdev *sd,
51 			   struct rkisp1_sensor_async *s_asd,
52 			   unsigned int source_pad)
53 {
54 	struct rkisp1_csi *csi = &rkisp1->csi;
55 	int ret;
56 
57 	s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler,
58 						V4L2_CID_PIXEL_RATE);
59 	if (!s_asd->pixel_rate_ctrl) {
60 		dev_err(rkisp1->dev, "No pixel rate control in subdev %s\n",
61 			sd->name);
62 		return -EINVAL;
63 	}
64 
65 	/* Create the link from the sensor to the CSI receiver. */
66 	ret = media_create_pad_link(&sd->entity, source_pad,
67 				    &csi->sd.entity, RKISP1_CSI_PAD_SINK,
68 				    !s_asd->index ? MEDIA_LNK_FL_ENABLED : 0);
69 	if (ret) {
70 		dev_err(csi->rkisp1->dev, "failed to link src pad of %s\n",
71 			sd->name);
72 		return ret;
73 	}
74 
75 	return 0;
76 }
77 
78 static int rkisp1_csi_config(struct rkisp1_csi *csi,
79 			     const struct rkisp1_sensor_async *sensor)
80 {
81 	struct rkisp1_device *rkisp1 = csi->rkisp1;
82 	unsigned int lanes = sensor->lanes;
83 	u32 mipi_ctrl;
84 
85 	if (lanes < 1 || lanes > 4)
86 		return -EINVAL;
87 
88 	mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) |
89 		    RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) |
90 		    RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP |
91 		    RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA;
92 
93 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, mipi_ctrl);
94 
95 	/* V12 could also use a newer csi2-host, but we don't want that yet */
96 	if (rkisp1->info->isp_ver == RKISP1_V12)
97 		rkisp1_write(rkisp1, RKISP1_CIF_ISP_CSI0_CTRL0, 0);
98 
99 	/* Configure Data Type and Virtual Channel */
100 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL,
101 		     RKISP1_CIF_MIPI_DATA_SEL_DT(csi->sink_fmt->mipi_dt) |
102 		     RKISP1_CIF_MIPI_DATA_SEL_VC(0));
103 
104 	/* Clear MIPI interrupts */
105 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);
106 
107 	/*
108 	 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for
109 	 * isp bus may be dead when switch isp.
110 	 */
111 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC,
112 		     RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI |
113 		     RKISP1_CIF_MIPI_ERR_DPHY |
114 		     RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) |
115 		     RKISP1_CIF_MIPI_ADD_DATA_OVFLW);
116 
117 	dev_dbg(rkisp1->dev, "\n  MIPI_CTRL 0x%08x\n"
118 		"  MIPI_IMG_DATA_SEL 0x%08x\n"
119 		"  MIPI_STATUS 0x%08x\n"
120 		"  MIPI_IMSC 0x%08x\n",
121 		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL),
122 		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL),
123 		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS),
124 		rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC));
125 
126 	return 0;
127 }
128 
129 static void rkisp1_csi_enable(struct rkisp1_csi *csi)
130 {
131 	struct rkisp1_device *rkisp1 = csi->rkisp1;
132 	u32 val;
133 
134 	val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
135 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
136 		     val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA);
137 }
138 
139 static void rkisp1_csi_disable(struct rkisp1_csi *csi)
140 {
141 	struct rkisp1_device *rkisp1 = csi->rkisp1;
142 	u32 val;
143 
144 	/* Mask and clear interrupts. */
145 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0);
146 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0);
147 
148 	val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL);
149 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL,
150 		     val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA));
151 }
152 
153 static int rkisp1_csi_start(struct rkisp1_csi *csi,
154 			    const struct rkisp1_sensor_async *sensor)
155 {
156 	struct rkisp1_device *rkisp1 = csi->rkisp1;
157 	union phy_configure_opts opts;
158 	struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy;
159 	s64 pixel_clock;
160 	int ret;
161 
162 	ret = rkisp1_csi_config(csi, sensor);
163 	if (ret)
164 		return ret;
165 
166 	pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl);
167 	if (!pixel_clock) {
168 		dev_err(rkisp1->dev, "Invalid pixel rate value\n");
169 		return -EINVAL;
170 	}
171 
172 	phy_mipi_dphy_get_default_config(pixel_clock, csi->sink_fmt->bus_width,
173 					 sensor->lanes, cfg);
174 	phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY);
175 	phy_configure(csi->dphy, &opts);
176 	phy_power_on(csi->dphy);
177 
178 	rkisp1_csi_enable(csi);
179 
180 	/*
181 	 * CIF spec says to wait for sufficient time after enabling
182 	 * the MIPI interface and before starting the sensor output.
183 	 */
184 	usleep_range(1000, 1200);
185 
186 	return 0;
187 }
188 
189 static void rkisp1_csi_stop(struct rkisp1_csi *csi)
190 {
191 	rkisp1_csi_disable(csi);
192 
193 	phy_power_off(csi->dphy);
194 }
195 
196 irqreturn_t rkisp1_csi_isr(int irq, void *ctx)
197 {
198 	struct device *dev = ctx;
199 	struct rkisp1_device *rkisp1 = dev_get_drvdata(dev);
200 	u32 val, status;
201 
202 	status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS);
203 	if (!status)
204 		return IRQ_NONE;
205 
206 	rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, status);
207 
208 	/*
209 	 * Disable DPHY errctrl interrupt, because this dphy
210 	 * erctrl signal is asserted until the next changes
211 	 * of line state. This time is may be too long and cpu
212 	 * is hold in this interrupt.
213 	 */
214 	if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) {
215 		val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
216 		rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC,
217 			     val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f));
218 		rkisp1->csi.is_dphy_errctrl_disabled = true;
219 	}
220 
221 	/*
222 	 * Enable DPHY errctrl interrupt again, if mipi have receive
223 	 * the whole frame without any error.
224 	 */
225 	if (status == RKISP1_CIF_MIPI_FRAME_END) {
226 		/*
227 		 * Enable DPHY errctrl interrupt again, if mipi have receive
228 		 * the whole frame without any error.
229 		 */
230 		if (rkisp1->csi.is_dphy_errctrl_disabled) {
231 			val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC);
232 			val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f);
233 			rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, val);
234 			rkisp1->csi.is_dphy_errctrl_disabled = false;
235 		}
236 	} else {
237 		rkisp1->debug.mipi_error++;
238 	}
239 
240 	return IRQ_HANDLED;
241 }
242 
243 /* ----------------------------------------------------------------------------
244  * Subdev pad operations
245  */
246 
247 static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd,
248 				     struct v4l2_subdev_state *sd_state,
249 				     struct v4l2_subdev_mbus_code_enum *code)
250 {
251 	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
252 	unsigned int i;
253 	int pos = 0;
254 
255 	if (code->pad == RKISP1_CSI_PAD_SRC) {
256 		const struct v4l2_mbus_framefmt *sink_fmt;
257 
258 		if (code->index)
259 			return -EINVAL;
260 
261 		mutex_lock(&csi->lock);
262 
263 		sink_fmt = rkisp1_csi_get_pad_fmt(csi, sd_state,
264 						  RKISP1_CSI_PAD_SINK,
265 						  code->which);
266 		code->code = sink_fmt->code;
267 
268 		mutex_unlock(&csi->lock);
269 
270 		return 0;
271 	}
272 
273 	for (i = 0; ; i++) {
274 		const struct rkisp1_mbus_info *fmt =
275 			rkisp1_mbus_info_get_by_index(i);
276 
277 		if (!fmt)
278 			return -EINVAL;
279 
280 		if (!(fmt->direction & RKISP1_ISP_SD_SINK))
281 			continue;
282 
283 		if (code->index == pos) {
284 			code->code = fmt->mbus_code;
285 			return 0;
286 		}
287 
288 		pos++;
289 	}
290 
291 	return -EINVAL;
292 }
293 
294 static int rkisp1_csi_init_config(struct v4l2_subdev *sd,
295 				  struct v4l2_subdev_state *sd_state)
296 {
297 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
298 
299 	sink_fmt = v4l2_subdev_get_try_format(sd, sd_state,
300 					      RKISP1_CSI_PAD_SINK);
301 	src_fmt = v4l2_subdev_get_try_format(sd, sd_state,
302 					     RKISP1_CSI_PAD_SRC);
303 
304 	sink_fmt->width = RKISP1_DEFAULT_WIDTH;
305 	sink_fmt->height = RKISP1_DEFAULT_HEIGHT;
306 	sink_fmt->field = V4L2_FIELD_NONE;
307 	sink_fmt->code = RKISP1_CSI_DEF_FMT;
308 
309 	*src_fmt = *sink_fmt;
310 
311 	return 0;
312 }
313 
314 static int rkisp1_csi_get_fmt(struct v4l2_subdev *sd,
315 			      struct v4l2_subdev_state *sd_state,
316 			      struct v4l2_subdev_format *fmt)
317 {
318 	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
319 
320 	mutex_lock(&csi->lock);
321 	fmt->format = *rkisp1_csi_get_pad_fmt(csi, sd_state, fmt->pad,
322 					      fmt->which);
323 	mutex_unlock(&csi->lock);
324 
325 	return 0;
326 }
327 
328 static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd,
329 			      struct v4l2_subdev_state *sd_state,
330 			      struct v4l2_subdev_format *fmt)
331 {
332 	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
333 	const struct rkisp1_mbus_info *mbus_info;
334 	struct v4l2_mbus_framefmt *sink_fmt, *src_fmt;
335 
336 	/* The format on the source pad always matches the sink pad. */
337 	if (fmt->pad == RKISP1_CSI_PAD_SRC)
338 		return rkisp1_csi_get_fmt(sd, sd_state, fmt);
339 
340 	mutex_lock(&csi->lock);
341 
342 	sink_fmt = rkisp1_csi_get_pad_fmt(csi, sd_state, RKISP1_CSI_PAD_SINK,
343 					  fmt->which);
344 
345 	sink_fmt->code = fmt->format.code;
346 
347 	mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code);
348 	if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) {
349 		sink_fmt->code = RKISP1_CSI_DEF_FMT;
350 		mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code);
351 	}
352 
353 	sink_fmt->width = clamp_t(u32, fmt->format.width,
354 				  RKISP1_ISP_MIN_WIDTH,
355 				  RKISP1_ISP_MAX_WIDTH);
356 	sink_fmt->height = clamp_t(u32, fmt->format.height,
357 				   RKISP1_ISP_MIN_HEIGHT,
358 				   RKISP1_ISP_MAX_HEIGHT);
359 
360 	fmt->format = *sink_fmt;
361 
362 	if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
363 		csi->sink_fmt = mbus_info;
364 
365 	/* Propagate the format to the source pad. */
366 	src_fmt = rkisp1_csi_get_pad_fmt(csi, sd_state, RKISP1_CSI_PAD_SRC,
367 					 fmt->which);
368 	*src_fmt = *sink_fmt;
369 
370 	mutex_unlock(&csi->lock);
371 
372 	return 0;
373 }
374 
375 /* ----------------------------------------------------------------------------
376  * Subdev video operations
377  */
378 
379 static int rkisp1_csi_s_stream(struct v4l2_subdev *sd, int enable)
380 {
381 	struct rkisp1_csi *csi = to_rkisp1_csi(sd);
382 	struct rkisp1_device *rkisp1 = csi->rkisp1;
383 	struct rkisp1_sensor_async *source_asd;
384 	struct media_pad *source_pad;
385 	struct v4l2_subdev *source;
386 	int ret;
387 
388 	if (!enable) {
389 		v4l2_subdev_call(csi->source, video, s_stream, false);
390 
391 		rkisp1_csi_stop(csi);
392 
393 		return 0;
394 	}
395 
396 	source_pad = media_entity_remote_source_pad_unique(&sd->entity);
397 	if (IS_ERR(source_pad)) {
398 		dev_dbg(rkisp1->dev, "Failed to get source for CSI: %ld\n",
399 			PTR_ERR(source_pad));
400 		return -EPIPE;
401 	}
402 
403 	source = media_entity_to_v4l2_subdev(source_pad->entity);
404 	if (!source) {
405 		/* This should really not happen, so is not worth a message. */
406 		return -EPIPE;
407 	}
408 
409 	source_asd = container_of(source->asd, struct rkisp1_sensor_async, asd);
410 	if (source_asd->mbus_type != V4L2_MBUS_CSI2_DPHY)
411 		return -EINVAL;
412 
413 	mutex_lock(&csi->lock);
414 	ret = rkisp1_csi_start(csi, source_asd);
415 	mutex_unlock(&csi->lock);
416 	if (ret)
417 		return ret;
418 
419 	ret = v4l2_subdev_call(source, video, s_stream, true);
420 	if (ret) {
421 		rkisp1_csi_stop(csi);
422 		return ret;
423 	}
424 
425 	csi->source = source;
426 
427 	return 0;
428 }
429 
430 /* ----------------------------------------------------------------------------
431  * Registration
432  */
433 
434 static const struct media_entity_operations rkisp1_csi_media_ops = {
435 	.link_validate = v4l2_subdev_link_validate,
436 };
437 
438 static const struct v4l2_subdev_video_ops rkisp1_csi_video_ops = {
439 	.s_stream = rkisp1_csi_s_stream,
440 };
441 
442 static const struct v4l2_subdev_pad_ops rkisp1_csi_pad_ops = {
443 	.enum_mbus_code = rkisp1_csi_enum_mbus_code,
444 	.init_cfg = rkisp1_csi_init_config,
445 	.get_fmt = rkisp1_csi_get_fmt,
446 	.set_fmt = rkisp1_csi_set_fmt,
447 };
448 
449 static const struct v4l2_subdev_ops rkisp1_csi_ops = {
450 	.video = &rkisp1_csi_video_ops,
451 	.pad = &rkisp1_csi_pad_ops,
452 };
453 
454 int rkisp1_csi_register(struct rkisp1_device *rkisp1)
455 {
456 	struct rkisp1_csi *csi = &rkisp1->csi;
457 	struct v4l2_subdev_state state = {};
458 	struct media_pad *pads;
459 	struct v4l2_subdev *sd;
460 	int ret;
461 
462 	csi->rkisp1 = rkisp1;
463 	mutex_init(&csi->lock);
464 
465 	sd = &csi->sd;
466 	v4l2_subdev_init(sd, &rkisp1_csi_ops);
467 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
468 	sd->entity.ops = &rkisp1_csi_media_ops;
469 	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
470 	sd->owner = THIS_MODULE;
471 	strscpy(sd->name, RKISP1_CSI_DEV_NAME, sizeof(sd->name));
472 
473 	pads = csi->pads;
474 	pads[RKISP1_CSI_PAD_SINK].flags = MEDIA_PAD_FL_SINK |
475 					  MEDIA_PAD_FL_MUST_CONNECT;
476 	pads[RKISP1_CSI_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE |
477 					 MEDIA_PAD_FL_MUST_CONNECT;
478 
479 	csi->sink_fmt = rkisp1_mbus_info_get_by_code(RKISP1_CSI_DEF_FMT);
480 
481 	ret = media_entity_pads_init(&sd->entity, RKISP1_CSI_PAD_NUM, pads);
482 	if (ret)
483 		goto error;
484 
485 	state.pads = csi->pad_cfg;
486 	rkisp1_csi_init_config(sd, &state);
487 
488 	ret = v4l2_device_register_subdev(&csi->rkisp1->v4l2_dev, sd);
489 	if (ret) {
490 		dev_err(sd->dev, "Failed to register csi receiver subdev\n");
491 		goto error;
492 	}
493 
494 	return 0;
495 
496 error:
497 	media_entity_cleanup(&sd->entity);
498 	mutex_destroy(&csi->lock);
499 	csi->rkisp1 = NULL;
500 	return ret;
501 }
502 
503 void rkisp1_csi_unregister(struct rkisp1_device *rkisp1)
504 {
505 	struct rkisp1_csi *csi = &rkisp1->csi;
506 
507 	if (!csi->rkisp1)
508 		return;
509 
510 	v4l2_device_unregister_subdev(&csi->sd);
511 	media_entity_cleanup(&csi->sd.entity);
512 	mutex_destroy(&csi->lock);
513 }
514 
515 int rkisp1_csi_init(struct rkisp1_device *rkisp1)
516 {
517 	struct rkisp1_csi *csi = &rkisp1->csi;
518 
519 	csi->rkisp1 = rkisp1;
520 
521 	csi->dphy = devm_phy_get(rkisp1->dev, "dphy");
522 	if (IS_ERR(csi->dphy))
523 		return dev_err_probe(rkisp1->dev, PTR_ERR(csi->dphy),
524 				     "Couldn't get the MIPI D-PHY\n");
525 
526 	phy_init(csi->dphy);
527 
528 	return 0;
529 }
530 
531 void rkisp1_csi_cleanup(struct rkisp1_device *rkisp1)
532 {
533 	struct rkisp1_csi *csi = &rkisp1->csi;
534 
535 	phy_exit(csi->dphy);
536 }
537