1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - CSI-2 Receiver 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * Copyright (C) 2022 Ideas on Board 7 * 8 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 9 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/lockdep.h> 15 #include <linux/phy/phy.h> 16 #include <linux/phy/phy-mipi-dphy.h> 17 18 #include <media/v4l2-ctrls.h> 19 #include <media/v4l2-fwnode.h> 20 21 #include "rkisp1-common.h" 22 #include "rkisp1-csi.h" 23 24 #define RKISP1_CSI_DEV_NAME RKISP1_DRIVER_NAME "_csi" 25 26 #define RKISP1_CSI_DEF_FMT MEDIA_BUS_FMT_SRGGB10_1X10 27 28 static inline struct rkisp1_csi *to_rkisp1_csi(struct v4l2_subdev *sd) 29 { 30 return container_of(sd, struct rkisp1_csi, sd); 31 } 32 33 static struct v4l2_mbus_framefmt * 34 rkisp1_csi_get_pad_fmt(struct rkisp1_csi *csi, 35 struct v4l2_subdev_state *sd_state, 36 unsigned int pad, u32 which) 37 { 38 struct v4l2_subdev_state state = { 39 .pads = csi->pad_cfg 40 }; 41 42 lockdep_assert_held(&csi->lock); 43 44 if (which == V4L2_SUBDEV_FORMAT_TRY) 45 return v4l2_subdev_get_try_format(&csi->sd, sd_state, pad); 46 else 47 return v4l2_subdev_get_try_format(&csi->sd, &state, pad); 48 } 49 50 int rkisp1_csi_link_sensor(struct rkisp1_device *rkisp1, struct v4l2_subdev *sd, 51 struct rkisp1_sensor_async *s_asd, 52 unsigned int source_pad) 53 { 54 struct rkisp1_csi *csi = &rkisp1->csi; 55 int ret; 56 57 s_asd->pixel_rate_ctrl = v4l2_ctrl_find(sd->ctrl_handler, 58 V4L2_CID_PIXEL_RATE); 59 if (!s_asd->pixel_rate_ctrl) { 60 dev_err(rkisp1->dev, "No pixel rate control in subdev %s\n", 61 sd->name); 62 return -EINVAL; 63 } 64 65 /* Create the link from the sensor to the CSI receiver. */ 66 ret = media_create_pad_link(&sd->entity, source_pad, 67 &csi->sd.entity, RKISP1_CSI_PAD_SINK, 68 !s_asd->index ? MEDIA_LNK_FL_ENABLED : 0); 69 if (ret) { 70 dev_err(csi->rkisp1->dev, "failed to link src pad of %s\n", 71 sd->name); 72 return ret; 73 } 74 75 return 0; 76 } 77 78 static int rkisp1_csi_config(struct rkisp1_csi *csi, 79 const struct rkisp1_sensor_async *sensor) 80 { 81 struct rkisp1_device *rkisp1 = csi->rkisp1; 82 unsigned int lanes = sensor->lanes; 83 u32 mipi_ctrl; 84 85 if (lanes < 1 || lanes > 4) 86 return -EINVAL; 87 88 mipi_ctrl = RKISP1_CIF_MIPI_CTRL_NUM_LANES(lanes - 1) | 89 RKISP1_CIF_MIPI_CTRL_SHUTDOWNLANES(0xf) | 90 RKISP1_CIF_MIPI_CTRL_ERR_SOT_SYNC_HS_SKIP | 91 RKISP1_CIF_MIPI_CTRL_CLOCKLANE_ENA; 92 93 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, mipi_ctrl); 94 95 /* V12 could also use a newer csi2-host, but we don't want that yet */ 96 if (rkisp1->info->isp_ver == RKISP1_V12) 97 rkisp1_write(rkisp1, RKISP1_CIF_ISP_CSI0_CTRL0, 0); 98 99 /* Configure Data Type and Virtual Channel */ 100 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL, 101 RKISP1_CIF_MIPI_DATA_SEL_DT(csi->sink_fmt->mipi_dt) | 102 RKISP1_CIF_MIPI_DATA_SEL_VC(0)); 103 104 /* Clear MIPI interrupts */ 105 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0); 106 107 /* 108 * Disable RKISP1_CIF_MIPI_ERR_DPHY interrupt here temporary for 109 * isp bus may be dead when switch isp. 110 */ 111 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 112 RKISP1_CIF_MIPI_FRAME_END | RKISP1_CIF_MIPI_ERR_CSI | 113 RKISP1_CIF_MIPI_ERR_DPHY | 114 RKISP1_CIF_MIPI_SYNC_FIFO_OVFLW(0x03) | 115 RKISP1_CIF_MIPI_ADD_DATA_OVFLW); 116 117 dev_dbg(rkisp1->dev, "\n MIPI_CTRL 0x%08x\n" 118 " MIPI_IMG_DATA_SEL 0x%08x\n" 119 " MIPI_STATUS 0x%08x\n" 120 " MIPI_IMSC 0x%08x\n", 121 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL), 122 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMG_DATA_SEL), 123 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_STATUS), 124 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC)); 125 126 return 0; 127 } 128 129 static void rkisp1_csi_enable(struct rkisp1_csi *csi) 130 { 131 struct rkisp1_device *rkisp1 = csi->rkisp1; 132 u32 val; 133 134 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 135 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, 136 val | RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA); 137 } 138 139 static void rkisp1_csi_disable(struct rkisp1_csi *csi) 140 { 141 struct rkisp1_device *rkisp1 = csi->rkisp1; 142 u32 val; 143 144 /* Mask MIPI interrupts. */ 145 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 0); 146 147 /* Flush posted writes */ 148 rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 149 150 /* 151 * Wait until the IRQ handler has ended. The IRQ handler may get called 152 * even after this, but it will return immediately as the MIPI 153 * interrupts have been masked. 154 */ 155 synchronize_irq(rkisp1->irqs[RKISP1_IRQ_MIPI]); 156 157 /* Clear MIPI interrupt status */ 158 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, ~0); 159 160 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_CTRL); 161 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_CTRL, 162 val & (~RKISP1_CIF_MIPI_CTRL_OUTPUT_ENA)); 163 } 164 165 static int rkisp1_csi_start(struct rkisp1_csi *csi, 166 const struct rkisp1_sensor_async *sensor) 167 { 168 struct rkisp1_device *rkisp1 = csi->rkisp1; 169 union phy_configure_opts opts; 170 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; 171 s64 pixel_clock; 172 int ret; 173 174 ret = rkisp1_csi_config(csi, sensor); 175 if (ret) 176 return ret; 177 178 pixel_clock = v4l2_ctrl_g_ctrl_int64(sensor->pixel_rate_ctrl); 179 if (!pixel_clock) { 180 dev_err(rkisp1->dev, "Invalid pixel rate value\n"); 181 return -EINVAL; 182 } 183 184 phy_mipi_dphy_get_default_config(pixel_clock, csi->sink_fmt->bus_width, 185 sensor->lanes, cfg); 186 phy_set_mode(csi->dphy, PHY_MODE_MIPI_DPHY); 187 phy_configure(csi->dphy, &opts); 188 phy_power_on(csi->dphy); 189 190 rkisp1_csi_enable(csi); 191 192 /* 193 * CIF spec says to wait for sufficient time after enabling 194 * the MIPI interface and before starting the sensor output. 195 */ 196 usleep_range(1000, 1200); 197 198 return 0; 199 } 200 201 static void rkisp1_csi_stop(struct rkisp1_csi *csi) 202 { 203 rkisp1_csi_disable(csi); 204 205 phy_power_off(csi->dphy); 206 } 207 208 irqreturn_t rkisp1_csi_isr(int irq, void *ctx) 209 { 210 struct device *dev = ctx; 211 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 212 u32 val, status; 213 214 status = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_MIS); 215 if (!status) 216 return IRQ_NONE; 217 218 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_ICR, status); 219 220 /* 221 * Disable DPHY errctrl interrupt, because this dphy 222 * erctrl signal is asserted until the next changes 223 * of line state. This time is may be too long and cpu 224 * is hold in this interrupt. 225 */ 226 if (status & RKISP1_CIF_MIPI_ERR_CTRL(0x0f)) { 227 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 228 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, 229 val & ~RKISP1_CIF_MIPI_ERR_CTRL(0x0f)); 230 rkisp1->csi.is_dphy_errctrl_disabled = true; 231 } 232 233 /* 234 * Enable DPHY errctrl interrupt again, if mipi have receive 235 * the whole frame without any error. 236 */ 237 if (status == RKISP1_CIF_MIPI_FRAME_END) { 238 /* 239 * Enable DPHY errctrl interrupt again, if mipi have receive 240 * the whole frame without any error. 241 */ 242 if (rkisp1->csi.is_dphy_errctrl_disabled) { 243 val = rkisp1_read(rkisp1, RKISP1_CIF_MIPI_IMSC); 244 val |= RKISP1_CIF_MIPI_ERR_CTRL(0x0f); 245 rkisp1_write(rkisp1, RKISP1_CIF_MIPI_IMSC, val); 246 rkisp1->csi.is_dphy_errctrl_disabled = false; 247 } 248 } else { 249 rkisp1->debug.mipi_error++; 250 } 251 252 return IRQ_HANDLED; 253 } 254 255 /* ---------------------------------------------------------------------------- 256 * Subdev pad operations 257 */ 258 259 static int rkisp1_csi_enum_mbus_code(struct v4l2_subdev *sd, 260 struct v4l2_subdev_state *sd_state, 261 struct v4l2_subdev_mbus_code_enum *code) 262 { 263 struct rkisp1_csi *csi = to_rkisp1_csi(sd); 264 unsigned int i; 265 int pos = 0; 266 267 if (code->pad == RKISP1_CSI_PAD_SRC) { 268 const struct v4l2_mbus_framefmt *sink_fmt; 269 270 if (code->index) 271 return -EINVAL; 272 273 mutex_lock(&csi->lock); 274 275 sink_fmt = rkisp1_csi_get_pad_fmt(csi, sd_state, 276 RKISP1_CSI_PAD_SINK, 277 code->which); 278 code->code = sink_fmt->code; 279 280 mutex_unlock(&csi->lock); 281 282 return 0; 283 } 284 285 for (i = 0; ; i++) { 286 const struct rkisp1_mbus_info *fmt = 287 rkisp1_mbus_info_get_by_index(i); 288 289 if (!fmt) 290 return -EINVAL; 291 292 if (!(fmt->direction & RKISP1_ISP_SD_SINK)) 293 continue; 294 295 if (code->index == pos) { 296 code->code = fmt->mbus_code; 297 return 0; 298 } 299 300 pos++; 301 } 302 303 return -EINVAL; 304 } 305 306 static int rkisp1_csi_init_config(struct v4l2_subdev *sd, 307 struct v4l2_subdev_state *sd_state) 308 { 309 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 310 311 sink_fmt = v4l2_subdev_get_try_format(sd, sd_state, 312 RKISP1_CSI_PAD_SINK); 313 src_fmt = v4l2_subdev_get_try_format(sd, sd_state, 314 RKISP1_CSI_PAD_SRC); 315 316 sink_fmt->width = RKISP1_DEFAULT_WIDTH; 317 sink_fmt->height = RKISP1_DEFAULT_HEIGHT; 318 sink_fmt->field = V4L2_FIELD_NONE; 319 sink_fmt->code = RKISP1_CSI_DEF_FMT; 320 321 *src_fmt = *sink_fmt; 322 323 return 0; 324 } 325 326 static int rkisp1_csi_get_fmt(struct v4l2_subdev *sd, 327 struct v4l2_subdev_state *sd_state, 328 struct v4l2_subdev_format *fmt) 329 { 330 struct rkisp1_csi *csi = to_rkisp1_csi(sd); 331 332 mutex_lock(&csi->lock); 333 fmt->format = *rkisp1_csi_get_pad_fmt(csi, sd_state, fmt->pad, 334 fmt->which); 335 mutex_unlock(&csi->lock); 336 337 return 0; 338 } 339 340 static int rkisp1_csi_set_fmt(struct v4l2_subdev *sd, 341 struct v4l2_subdev_state *sd_state, 342 struct v4l2_subdev_format *fmt) 343 { 344 struct rkisp1_csi *csi = to_rkisp1_csi(sd); 345 const struct rkisp1_mbus_info *mbus_info; 346 struct v4l2_mbus_framefmt *sink_fmt, *src_fmt; 347 348 /* The format on the source pad always matches the sink pad. */ 349 if (fmt->pad == RKISP1_CSI_PAD_SRC) 350 return rkisp1_csi_get_fmt(sd, sd_state, fmt); 351 352 mutex_lock(&csi->lock); 353 354 sink_fmt = rkisp1_csi_get_pad_fmt(csi, sd_state, RKISP1_CSI_PAD_SINK, 355 fmt->which); 356 357 sink_fmt->code = fmt->format.code; 358 359 mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code); 360 if (!mbus_info || !(mbus_info->direction & RKISP1_ISP_SD_SINK)) { 361 sink_fmt->code = RKISP1_CSI_DEF_FMT; 362 mbus_info = rkisp1_mbus_info_get_by_code(sink_fmt->code); 363 } 364 365 sink_fmt->width = clamp_t(u32, fmt->format.width, 366 RKISP1_ISP_MIN_WIDTH, 367 RKISP1_ISP_MAX_WIDTH); 368 sink_fmt->height = clamp_t(u32, fmt->format.height, 369 RKISP1_ISP_MIN_HEIGHT, 370 RKISP1_ISP_MAX_HEIGHT); 371 372 fmt->format = *sink_fmt; 373 374 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE) 375 csi->sink_fmt = mbus_info; 376 377 /* Propagate the format to the source pad. */ 378 src_fmt = rkisp1_csi_get_pad_fmt(csi, sd_state, RKISP1_CSI_PAD_SRC, 379 fmt->which); 380 *src_fmt = *sink_fmt; 381 382 mutex_unlock(&csi->lock); 383 384 return 0; 385 } 386 387 /* ---------------------------------------------------------------------------- 388 * Subdev video operations 389 */ 390 391 static int rkisp1_csi_s_stream(struct v4l2_subdev *sd, int enable) 392 { 393 struct rkisp1_csi *csi = to_rkisp1_csi(sd); 394 struct rkisp1_device *rkisp1 = csi->rkisp1; 395 struct rkisp1_sensor_async *source_asd; 396 struct v4l2_async_connection *asc; 397 struct media_pad *source_pad; 398 struct v4l2_subdev *source; 399 int ret; 400 401 if (!enable) { 402 v4l2_subdev_call(csi->source, video, s_stream, false); 403 404 rkisp1_csi_stop(csi); 405 406 return 0; 407 } 408 409 source_pad = media_entity_remote_source_pad_unique(&sd->entity); 410 if (IS_ERR(source_pad)) { 411 dev_dbg(rkisp1->dev, "Failed to get source for CSI: %ld\n", 412 PTR_ERR(source_pad)); 413 return -EPIPE; 414 } 415 416 source = media_entity_to_v4l2_subdev(source_pad->entity); 417 if (!source) { 418 /* This should really not happen, so is not worth a message. */ 419 return -EPIPE; 420 } 421 422 asc = v4l2_async_connection_unique(source); 423 if (!asc) 424 return -EPIPE; 425 426 source_asd = container_of(asc, struct rkisp1_sensor_async, asd); 427 if (source_asd->mbus_type != V4L2_MBUS_CSI2_DPHY) 428 return -EINVAL; 429 430 mutex_lock(&csi->lock); 431 ret = rkisp1_csi_start(csi, source_asd); 432 mutex_unlock(&csi->lock); 433 if (ret) 434 return ret; 435 436 ret = v4l2_subdev_call(source, video, s_stream, true); 437 if (ret) { 438 rkisp1_csi_stop(csi); 439 return ret; 440 } 441 442 csi->source = source; 443 444 return 0; 445 } 446 447 /* ---------------------------------------------------------------------------- 448 * Registration 449 */ 450 451 static const struct media_entity_operations rkisp1_csi_media_ops = { 452 .link_validate = v4l2_subdev_link_validate, 453 }; 454 455 static const struct v4l2_subdev_video_ops rkisp1_csi_video_ops = { 456 .s_stream = rkisp1_csi_s_stream, 457 }; 458 459 static const struct v4l2_subdev_pad_ops rkisp1_csi_pad_ops = { 460 .enum_mbus_code = rkisp1_csi_enum_mbus_code, 461 .init_cfg = rkisp1_csi_init_config, 462 .get_fmt = rkisp1_csi_get_fmt, 463 .set_fmt = rkisp1_csi_set_fmt, 464 }; 465 466 static const struct v4l2_subdev_ops rkisp1_csi_ops = { 467 .video = &rkisp1_csi_video_ops, 468 .pad = &rkisp1_csi_pad_ops, 469 }; 470 471 int rkisp1_csi_register(struct rkisp1_device *rkisp1) 472 { 473 struct rkisp1_csi *csi = &rkisp1->csi; 474 struct v4l2_subdev_state state = {}; 475 struct media_pad *pads; 476 struct v4l2_subdev *sd; 477 int ret; 478 479 csi->rkisp1 = rkisp1; 480 mutex_init(&csi->lock); 481 482 sd = &csi->sd; 483 v4l2_subdev_init(sd, &rkisp1_csi_ops); 484 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 485 sd->entity.ops = &rkisp1_csi_media_ops; 486 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 487 sd->owner = THIS_MODULE; 488 strscpy(sd->name, RKISP1_CSI_DEV_NAME, sizeof(sd->name)); 489 490 pads = csi->pads; 491 pads[RKISP1_CSI_PAD_SINK].flags = MEDIA_PAD_FL_SINK | 492 MEDIA_PAD_FL_MUST_CONNECT; 493 pads[RKISP1_CSI_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE | 494 MEDIA_PAD_FL_MUST_CONNECT; 495 496 csi->sink_fmt = rkisp1_mbus_info_get_by_code(RKISP1_CSI_DEF_FMT); 497 498 ret = media_entity_pads_init(&sd->entity, RKISP1_CSI_PAD_NUM, pads); 499 if (ret) 500 goto error; 501 502 state.pads = csi->pad_cfg; 503 rkisp1_csi_init_config(sd, &state); 504 505 ret = v4l2_device_register_subdev(&csi->rkisp1->v4l2_dev, sd); 506 if (ret) { 507 dev_err(sd->dev, "Failed to register csi receiver subdev\n"); 508 goto error; 509 } 510 511 return 0; 512 513 error: 514 media_entity_cleanup(&sd->entity); 515 mutex_destroy(&csi->lock); 516 csi->rkisp1 = NULL; 517 return ret; 518 } 519 520 void rkisp1_csi_unregister(struct rkisp1_device *rkisp1) 521 { 522 struct rkisp1_csi *csi = &rkisp1->csi; 523 524 if (!csi->rkisp1) 525 return; 526 527 v4l2_device_unregister_subdev(&csi->sd); 528 media_entity_cleanup(&csi->sd.entity); 529 mutex_destroy(&csi->lock); 530 } 531 532 int rkisp1_csi_init(struct rkisp1_device *rkisp1) 533 { 534 struct rkisp1_csi *csi = &rkisp1->csi; 535 536 csi->rkisp1 = rkisp1; 537 538 csi->dphy = devm_phy_get(rkisp1->dev, "dphy"); 539 if (IS_ERR(csi->dphy)) 540 return dev_err_probe(rkisp1->dev, PTR_ERR(csi->dphy), 541 "Couldn't get the MIPI D-PHY\n"); 542 543 phy_init(csi->dphy); 544 545 return 0; 546 } 547 548 void rkisp1_csi_cleanup(struct rkisp1_device *rkisp1) 549 { 550 struct rkisp1_csi *csi = &rkisp1->csi; 551 552 phy_exit(csi->dphy); 553 } 554