1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - V4l capture device 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/pm_runtime.h> 13 #include <media/v4l2-common.h> 14 #include <media/v4l2-event.h> 15 #include <media/v4l2-fh.h> 16 #include <media/v4l2-ioctl.h> 17 #include <media/v4l2-mc.h> 18 #include <media/v4l2-subdev.h> 19 #include <media/videobuf2-dma-contig.h> 20 21 #include "rkisp1-common.h" 22 23 /* 24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath. 25 * 26 * differences between selfpath and mainpath 27 * available mp sink input: isp 28 * available sp sink input : isp, dma(TODO) 29 * available mp sink pad fmts: yuv422, raw 30 * available sp sink pad fmts: yuv422, yuv420...... 31 * available mp source fmts: yuv, raw, jpeg(TODO) 32 * available sp source fmts: yuv, rgb 33 */ 34 35 #define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath" 36 #define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath" 37 38 #define RKISP1_MIN_BUFFERS_NEEDED 3 39 40 enum rkisp1_plane { 41 RKISP1_PLANE_Y = 0, 42 RKISP1_PLANE_CB = 1, 43 RKISP1_PLANE_CR = 2 44 }; 45 46 /* 47 * @fourcc: pixel format 48 * @fmt_type: helper filed for pixel format 49 * @uv_swap: if cb cr swapped, for yuv 50 * @write_format: defines how YCbCr self picture data is written to memory 51 * @output_format: defines sp output format 52 * @mbus: the mbus code on the src resizer pad that matches the pixel format 53 */ 54 struct rkisp1_capture_fmt_cfg { 55 u32 fourcc; 56 u8 uv_swap; 57 u32 write_format; 58 u32 output_format; 59 u32 mbus; 60 }; 61 62 struct rkisp1_capture_ops { 63 void (*config)(struct rkisp1_capture *cap); 64 void (*stop)(struct rkisp1_capture *cap); 65 void (*enable)(struct rkisp1_capture *cap); 66 void (*disable)(struct rkisp1_capture *cap); 67 void (*set_data_path)(struct rkisp1_capture *cap); 68 bool (*is_stopped)(struct rkisp1_capture *cap); 69 }; 70 71 struct rkisp1_capture_config { 72 const struct rkisp1_capture_fmt_cfg *fmts; 73 int fmt_size; 74 struct { 75 u32 y_size_init; 76 u32 cb_size_init; 77 u32 cr_size_init; 78 u32 y_base_ad_init; 79 u32 cb_base_ad_init; 80 u32 cr_base_ad_init; 81 u32 y_offs_cnt_init; 82 u32 cb_offs_cnt_init; 83 u32 cr_offs_cnt_init; 84 } mi; 85 }; 86 87 /* 88 * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus' 89 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 90 */ 91 static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { 92 /* yuv422 */ 93 { 94 .fourcc = V4L2_PIX_FMT_YUYV, 95 .uv_swap = 0, 96 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, 97 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 98 }, { 99 .fourcc = V4L2_PIX_FMT_YUV422P, 100 .uv_swap = 0, 101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 102 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 103 }, { 104 .fourcc = V4L2_PIX_FMT_NV16, 105 .uv_swap = 0, 106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 107 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 108 }, { 109 .fourcc = V4L2_PIX_FMT_NV61, 110 .uv_swap = 1, 111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 112 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 113 }, { 114 .fourcc = V4L2_PIX_FMT_YVU422M, 115 .uv_swap = 1, 116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 117 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 118 }, 119 /* yuv400 */ 120 { 121 .fourcc = V4L2_PIX_FMT_GREY, 122 .uv_swap = 0, 123 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 124 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 125 }, 126 /* yuv420 */ 127 { 128 .fourcc = V4L2_PIX_FMT_NV21, 129 .uv_swap = 1, 130 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 131 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 132 }, { 133 .fourcc = V4L2_PIX_FMT_NV12, 134 .uv_swap = 0, 135 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 136 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 137 }, { 138 .fourcc = V4L2_PIX_FMT_NV21M, 139 .uv_swap = 1, 140 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 141 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 142 }, { 143 .fourcc = V4L2_PIX_FMT_NV12M, 144 .uv_swap = 0, 145 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 146 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 147 }, { 148 .fourcc = V4L2_PIX_FMT_YUV420, 149 .uv_swap = 0, 150 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 151 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 152 }, { 153 .fourcc = V4L2_PIX_FMT_YVU420, 154 .uv_swap = 1, 155 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 156 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 157 }, 158 /* raw */ 159 { 160 .fourcc = V4L2_PIX_FMT_SRGGB8, 161 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 162 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8, 163 }, { 164 .fourcc = V4L2_PIX_FMT_SGRBG8, 165 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 166 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8, 167 }, { 168 .fourcc = V4L2_PIX_FMT_SGBRG8, 169 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 170 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8, 171 }, { 172 .fourcc = V4L2_PIX_FMT_SBGGR8, 173 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 174 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8, 175 }, { 176 .fourcc = V4L2_PIX_FMT_SRGGB10, 177 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 178 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10, 179 }, { 180 .fourcc = V4L2_PIX_FMT_SGRBG10, 181 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 182 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10, 183 }, { 184 .fourcc = V4L2_PIX_FMT_SGBRG10, 185 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 186 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10, 187 }, { 188 .fourcc = V4L2_PIX_FMT_SBGGR10, 189 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 190 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10, 191 }, { 192 .fourcc = V4L2_PIX_FMT_SRGGB12, 193 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 194 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12, 195 }, { 196 .fourcc = V4L2_PIX_FMT_SGRBG12, 197 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 198 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12, 199 }, { 200 .fourcc = V4L2_PIX_FMT_SGBRG12, 201 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 202 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12, 203 }, { 204 .fourcc = V4L2_PIX_FMT_SBGGR12, 205 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 206 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12, 207 }, 208 }; 209 210 /* 211 * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus' 212 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 213 */ 214 static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = { 215 /* yuv422 */ 216 { 217 .fourcc = V4L2_PIX_FMT_YUYV, 218 .uv_swap = 0, 219 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT, 220 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 221 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 222 }, { 223 .fourcc = V4L2_PIX_FMT_YUV422P, 224 .uv_swap = 0, 225 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 226 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 227 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 228 }, { 229 .fourcc = V4L2_PIX_FMT_NV16, 230 .uv_swap = 0, 231 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 232 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 233 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 234 }, { 235 .fourcc = V4L2_PIX_FMT_NV61, 236 .uv_swap = 1, 237 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 238 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 239 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 240 }, { 241 .fourcc = V4L2_PIX_FMT_YVU422M, 242 .uv_swap = 1, 243 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 244 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 245 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 246 }, 247 /* yuv400 */ 248 { 249 .fourcc = V4L2_PIX_FMT_GREY, 250 .uv_swap = 0, 251 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 252 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV400, 253 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 254 }, 255 /* rgb */ 256 { 257 .fourcc = V4L2_PIX_FMT_XBGR32, 258 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 259 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888, 260 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 261 }, { 262 .fourcc = V4L2_PIX_FMT_RGB565, 263 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 264 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565, 265 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 266 }, 267 /* yuv420 */ 268 { 269 .fourcc = V4L2_PIX_FMT_NV21, 270 .uv_swap = 1, 271 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 272 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 273 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 274 }, { 275 .fourcc = V4L2_PIX_FMT_NV12, 276 .uv_swap = 0, 277 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 278 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 279 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 280 }, { 281 .fourcc = V4L2_PIX_FMT_NV21M, 282 .uv_swap = 1, 283 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 284 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 285 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 286 }, { 287 .fourcc = V4L2_PIX_FMT_NV12M, 288 .uv_swap = 0, 289 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 290 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 291 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 292 }, { 293 .fourcc = V4L2_PIX_FMT_YUV420, 294 .uv_swap = 0, 295 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 296 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 297 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 298 }, { 299 .fourcc = V4L2_PIX_FMT_YVU420, 300 .uv_swap = 1, 301 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 302 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 303 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 304 }, 305 }; 306 307 static const struct rkisp1_capture_config rkisp1_capture_config_mp = { 308 .fmts = rkisp1_mp_fmts, 309 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts), 310 .mi = { 311 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT, 312 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT, 313 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT, 314 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT, 315 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT, 316 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT, 317 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT, 318 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT, 319 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT, 320 }, 321 }; 322 323 static const struct rkisp1_capture_config rkisp1_capture_config_sp = { 324 .fmts = rkisp1_sp_fmts, 325 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts), 326 .mi = { 327 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT, 328 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT, 329 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT, 330 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT, 331 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT, 332 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT, 333 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT, 334 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT, 335 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT, 336 }, 337 }; 338 339 static inline struct rkisp1_vdev_node * 340 rkisp1_vdev_to_node(struct video_device *vdev) 341 { 342 return container_of(vdev, struct rkisp1_vdev_node, vdev); 343 } 344 345 int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap, 346 struct v4l2_subdev_mbus_code_enum *code) 347 { 348 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts; 349 /* 350 * initialize curr_mbus to non existing mbus code 0 to ensure it is 351 * different from fmts[0].mbus 352 */ 353 u32 curr_mbus = 0; 354 int i, n = 0; 355 356 for (i = 0; i < cap->config->fmt_size; i++) { 357 if (fmts[i].mbus == curr_mbus) 358 continue; 359 360 curr_mbus = fmts[i].mbus; 361 if (n++ == code->index) { 362 code->code = curr_mbus; 363 return 0; 364 } 365 } 366 return -EINVAL; 367 } 368 369 /* ---------------------------------------------------------------------------- 370 * Stream operations for self-picture path (sp) and main-picture path (mp) 371 */ 372 373 static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap) 374 { 375 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 376 377 mi_ctrl &= ~GENMASK(17, 16); 378 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64; 379 380 mi_ctrl &= ~GENMASK(19, 18); 381 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64; 382 383 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN | 384 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN; 385 386 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 387 } 388 389 static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm, 390 unsigned int component) 391 { 392 /* 393 * If packed format, then plane_fmt[0].sizeimage is the sum of all 394 * components, so we need to calculate just the size of Y component. 395 * See rkisp1_fill_pixfmt(). 396 */ 397 if (!component && pixm->num_planes == 1) 398 return pixm->plane_fmt[0].bytesperline * pixm->height; 399 return pixm->plane_fmt[component].sizeimage; 400 } 401 402 static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap) 403 { 404 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC); 405 406 mi_imsc |= RKISP1_CIF_MI_FRAME(cap); 407 rkisp1_write(cap->rkisp1, mi_imsc, RKISP1_CIF_MI_IMSC); 408 } 409 410 static void rkisp1_mp_config(struct rkisp1_capture *cap) 411 { 412 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 413 struct rkisp1_device *rkisp1 = cap->rkisp1; 414 u32 reg; 415 416 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 417 cap->config->mi.y_size_init); 418 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 419 cap->config->mi.cb_size_init); 420 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR), 421 cap->config->mi.cr_size_init); 422 423 rkisp1_irq_frame_end_enable(cap); 424 425 /* set uv swapping for semiplanar formats */ 426 if (cap->pix.info->comp_planes == 2) { 427 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 428 if (cap->pix.cfg->uv_swap) 429 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 430 else 431 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 432 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 433 } 434 435 rkisp1_mi_config_ctrl(cap); 436 437 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 438 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK; 439 reg |= cap->pix.cfg->write_format; 440 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL); 441 442 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 443 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE; 444 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL); 445 } 446 447 static void rkisp1_sp_config(struct rkisp1_capture *cap) 448 { 449 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 450 struct rkisp1_device *rkisp1 = cap->rkisp1; 451 u32 mi_ctrl, reg; 452 453 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 454 cap->config->mi.y_size_init); 455 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 456 cap->config->mi.cb_size_init); 457 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR), 458 cap->config->mi.cr_size_init); 459 460 rkisp1_write(rkisp1, pixm->width, RKISP1_CIF_MI_SP_Y_PIC_WIDTH); 461 rkisp1_write(rkisp1, pixm->height, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT); 462 rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH); 463 464 rkisp1_irq_frame_end_enable(cap); 465 466 /* set uv swapping for semiplanar formats */ 467 if (cap->pix.info->comp_planes == 2) { 468 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 469 if (cap->pix.cfg->uv_swap) 470 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 471 else 472 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 473 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 474 } 475 476 rkisp1_mi_config_ctrl(cap); 477 478 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 479 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK; 480 mi_ctrl |= cap->pix.cfg->write_format | 481 RKISP1_MI_CTRL_SP_INPUT_YUV422 | 482 cap->pix.cfg->output_format | 483 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE; 484 rkisp1_write(rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 485 } 486 487 static void rkisp1_mp_disable(struct rkisp1_capture *cap) 488 { 489 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 490 491 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE | 492 RKISP1_CIF_MI_CTRL_RAW_ENABLE); 493 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 494 } 495 496 static void rkisp1_sp_disable(struct rkisp1_capture *cap) 497 { 498 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 499 500 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE; 501 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 502 } 503 504 static void rkisp1_mp_enable(struct rkisp1_capture *cap) 505 { 506 u32 mi_ctrl; 507 508 rkisp1_mp_disable(cap); 509 510 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 511 if (v4l2_is_format_bayer(cap->pix.info)) 512 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE; 513 /* YUV */ 514 else 515 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE; 516 517 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 518 } 519 520 static void rkisp1_sp_enable(struct rkisp1_capture *cap) 521 { 522 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 523 524 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE; 525 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 526 } 527 528 static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap) 529 { 530 if (!cap->is_streaming) 531 return; 532 rkisp1_write(cap->rkisp1, 533 RKISP1_CIF_MI_FRAME(cap), RKISP1_CIF_MI_ICR); 534 cap->ops->disable(cap); 535 } 536 537 static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap) 538 { 539 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED | 540 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED; 541 542 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en); 543 } 544 545 static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap) 546 { 547 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & 548 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED); 549 } 550 551 static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap) 552 { 553 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 554 555 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP | 556 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI; 557 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 558 } 559 560 static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap) 561 { 562 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 563 564 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP; 565 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 566 } 567 568 static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = { 569 .config = rkisp1_mp_config, 570 .enable = rkisp1_mp_enable, 571 .disable = rkisp1_mp_disable, 572 .stop = rkisp1_mp_sp_stop, 573 .set_data_path = rkisp1_mp_set_data_path, 574 .is_stopped = rkisp1_mp_is_stopped, 575 }; 576 577 static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = { 578 .config = rkisp1_sp_config, 579 .enable = rkisp1_sp_enable, 580 .disable = rkisp1_sp_disable, 581 .stop = rkisp1_mp_sp_stop, 582 .set_data_path = rkisp1_sp_set_data_path, 583 .is_stopped = rkisp1_sp_is_stopped, 584 }; 585 586 /* ---------------------------------------------------------------------------- 587 * Frame buffer operations 588 */ 589 590 static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap) 591 { 592 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 593 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy; 594 595 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 596 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 597 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 598 599 /* The driver never access vaddr, no mapping is required */ 600 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev, 601 dummy_buf->size, 602 &dummy_buf->dma_addr, 603 GFP_KERNEL, 604 DMA_ATTR_NO_KERNEL_MAPPING); 605 if (!dummy_buf->vaddr) 606 return -ENOMEM; 607 608 return 0; 609 } 610 611 static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap) 612 { 613 dma_free_attrs(cap->rkisp1->dev, 614 cap->buf.dummy.size, cap->buf.dummy.vaddr, 615 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING); 616 } 617 618 static void rkisp1_set_next_buf(struct rkisp1_capture *cap) 619 { 620 cap->buf.curr = cap->buf.next; 621 cap->buf.next = NULL; 622 623 if (!list_empty(&cap->buf.queue)) { 624 u32 *buff_addr; 625 626 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue); 627 list_del(&cap->buf.next->queue); 628 629 buff_addr = cap->buf.next->buff_addr; 630 631 rkisp1_write(cap->rkisp1, 632 buff_addr[RKISP1_PLANE_Y], 633 cap->config->mi.y_base_ad_init); 634 rkisp1_write(cap->rkisp1, 635 buff_addr[RKISP1_PLANE_CB], 636 cap->config->mi.cb_base_ad_init); 637 rkisp1_write(cap->rkisp1, 638 buff_addr[RKISP1_PLANE_CR], 639 cap->config->mi.cr_base_ad_init); 640 } else { 641 /* 642 * Use the dummy space allocated by dma_alloc_coherent to 643 * throw data if there is no available buffer. 644 */ 645 rkisp1_write(cap->rkisp1, 646 cap->buf.dummy.dma_addr, 647 cap->config->mi.y_base_ad_init); 648 rkisp1_write(cap->rkisp1, 649 cap->buf.dummy.dma_addr, 650 cap->config->mi.cb_base_ad_init); 651 rkisp1_write(cap->rkisp1, 652 cap->buf.dummy.dma_addr, 653 cap->config->mi.cr_base_ad_init); 654 } 655 656 /* Set plane offsets */ 657 rkisp1_write(cap->rkisp1, 0, cap->config->mi.y_offs_cnt_init); 658 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cb_offs_cnt_init); 659 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cr_offs_cnt_init); 660 } 661 662 /* 663 * This function is called when a frame end comes. The next frame 664 * is processing and we should set up buffer for next-next frame, 665 * otherwise it will overflow. 666 */ 667 static void rkisp1_handle_buffer(struct rkisp1_capture *cap) 668 { 669 struct rkisp1_isp *isp = &cap->rkisp1->isp; 670 struct rkisp1_buffer *curr_buf; 671 672 spin_lock(&cap->buf.lock); 673 curr_buf = cap->buf.curr; 674 675 if (curr_buf) { 676 curr_buf->vb.sequence = isp->frame_sequence; 677 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns(); 678 curr_buf->vb.field = V4L2_FIELD_NONE; 679 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 680 } else { 681 cap->rkisp1->debug.frame_drop[cap->id]++; 682 } 683 684 rkisp1_set_next_buf(cap); 685 spin_unlock(&cap->buf.lock); 686 } 687 688 void rkisp1_capture_isr(struct rkisp1_device *rkisp1) 689 { 690 unsigned int i; 691 u32 status; 692 693 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS); 694 rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR); 695 696 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) { 697 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 698 699 if (!(status & RKISP1_CIF_MI_FRAME(cap))) 700 continue; 701 if (!cap->is_stopping) { 702 rkisp1_handle_buffer(cap); 703 continue; 704 } 705 /* 706 * Make sure stream is actually stopped, whose state 707 * can be read from the shadow register, before 708 * wake_up() thread which would immediately free all 709 * frame buffers. stop() takes effect at the next 710 * frame end that sync the configurations to shadow 711 * regs. 712 */ 713 if (!cap->ops->is_stopped(cap)) { 714 cap->ops->stop(cap); 715 continue; 716 } 717 cap->is_stopping = false; 718 cap->is_streaming = false; 719 wake_up(&cap->done); 720 } 721 } 722 723 /* ---------------------------------------------------------------------------- 724 * Vb2 operations 725 */ 726 727 static int rkisp1_vb2_queue_setup(struct vb2_queue *queue, 728 unsigned int *num_buffers, 729 unsigned int *num_planes, 730 unsigned int sizes[], 731 struct device *alloc_devs[]) 732 { 733 struct rkisp1_capture *cap = queue->drv_priv; 734 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 735 unsigned int i; 736 737 if (*num_planes) { 738 if (*num_planes != pixm->num_planes) 739 return -EINVAL; 740 741 for (i = 0; i < pixm->num_planes; i++) 742 if (sizes[i] < pixm->plane_fmt[i].sizeimage) 743 return -EINVAL; 744 } else { 745 *num_planes = pixm->num_planes; 746 for (i = 0; i < pixm->num_planes; i++) 747 sizes[i] = pixm->plane_fmt[i].sizeimage; 748 } 749 750 return 0; 751 } 752 753 static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb) 754 { 755 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 756 struct rkisp1_buffer *ispbuf = 757 container_of(vbuf, struct rkisp1_buffer, vb); 758 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 759 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 760 unsigned int i; 761 762 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr)); 763 for (i = 0; i < pixm->num_planes; i++) 764 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); 765 766 /* Convert to non-MPLANE */ 767 if (pixm->num_planes == 1) { 768 ispbuf->buff_addr[RKISP1_PLANE_CB] = 769 ispbuf->buff_addr[RKISP1_PLANE_Y] + 770 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y); 771 ispbuf->buff_addr[RKISP1_PLANE_CR] = 772 ispbuf->buff_addr[RKISP1_PLANE_CB] + 773 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB); 774 } 775 776 /* 777 * uv swap can be supported for planar formats by switching 778 * the address of cb and cr 779 */ 780 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap) 781 swap(ispbuf->buff_addr[RKISP1_PLANE_CR], 782 ispbuf->buff_addr[RKISP1_PLANE_CB]); 783 784 spin_lock_irq(&cap->buf.lock); 785 list_add_tail(&ispbuf->queue, &cap->buf.queue); 786 spin_unlock_irq(&cap->buf.lock); 787 } 788 789 static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb) 790 { 791 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 792 unsigned int i; 793 794 for (i = 0; i < cap->pix.fmt.num_planes; i++) { 795 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage; 796 797 if (vb2_plane_size(vb, i) < size) { 798 dev_err(cap->rkisp1->dev, 799 "User buffer too small (%ld < %ld)\n", 800 vb2_plane_size(vb, i), size); 801 return -EINVAL; 802 } 803 vb2_set_plane_payload(vb, i, size); 804 } 805 806 return 0; 807 } 808 809 static void rkisp1_return_all_buffers(struct rkisp1_capture *cap, 810 enum vb2_buffer_state state) 811 { 812 struct rkisp1_buffer *buf; 813 814 spin_lock_irq(&cap->buf.lock); 815 if (cap->buf.curr) { 816 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state); 817 cap->buf.curr = NULL; 818 } 819 if (cap->buf.next) { 820 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state); 821 cap->buf.next = NULL; 822 } 823 while (!list_empty(&cap->buf.queue)) { 824 buf = list_first_entry(&cap->buf.queue, 825 struct rkisp1_buffer, queue); 826 list_del(&buf->queue); 827 vb2_buffer_done(&buf->vb.vb2_buf, state); 828 } 829 spin_unlock_irq(&cap->buf.lock); 830 } 831 832 /* 833 * Most registers inside the rockchip ISP1 have shadow register since 834 * they must not be changed while processing a frame. 835 * Usually, each sub-module updates its shadow register after 836 * processing the last pixel of a frame. 837 */ 838 static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) 839 { 840 struct rkisp1_device *rkisp1 = cap->rkisp1; 841 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1]; 842 843 cap->ops->set_data_path(cap); 844 cap->ops->config(cap); 845 846 /* Setup a buffer for the next frame */ 847 spin_lock_irq(&cap->buf.lock); 848 rkisp1_set_next_buf(cap); 849 cap->ops->enable(cap); 850 /* It's safe to configure ACTIVE and SHADOW registers for the 851 * first stream. While when the second is starting, do NOT 852 * force update because it also updates the first one. 853 * 854 * The latter case would drop one more buffer(that is 2) since 855 * there's no buffer in a shadow register when the second FE received. 856 * This's also required because the second FE maybe corrupt 857 * especially when run at 120fps. 858 */ 859 if (!other->is_streaming) { 860 /* force cfg update */ 861 rkisp1_write(rkisp1, 862 RKISP1_CIF_MI_INIT_SOFT_UPD, RKISP1_CIF_MI_INIT); 863 rkisp1_set_next_buf(cap); 864 } 865 spin_unlock_irq(&cap->buf.lock); 866 cap->is_streaming = true; 867 } 868 869 static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap) 870 { 871 int ret; 872 873 /* Stream should stop in interrupt. If it doesn't, stop it by force. */ 874 cap->is_stopping = true; 875 ret = wait_event_timeout(cap->done, 876 !cap->is_streaming, 877 msecs_to_jiffies(1000)); 878 if (!ret) { 879 cap->rkisp1->debug.stop_timeout[cap->id]++; 880 cap->ops->stop(cap); 881 cap->is_stopping = false; 882 cap->is_streaming = false; 883 } 884 } 885 886 /* 887 * rkisp1_pipeline_stream_disable - disable nodes in the pipeline 888 * 889 * Call s_stream(false) in the reverse order from 890 * rkisp1_pipeline_stream_enable() and disable the DMA engine. 891 * Should be called before media_pipeline_stop() 892 */ 893 static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap) 894 __must_hold(&cap->rkisp1->stream_lock) 895 { 896 struct rkisp1_device *rkisp1 = cap->rkisp1; 897 898 rkisp1_cap_stream_disable(cap); 899 900 /* 901 * If the other capture is streaming, isp and sensor nodes shouldn't 902 * be disabled, skip them. 903 */ 904 if (rkisp1->pipe.streaming_count < 2) { 905 v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream, 906 false); 907 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 908 } 909 910 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 911 false); 912 } 913 914 /* 915 * rkisp1_pipeline_stream_enable - enable nodes in the pipeline 916 * 917 * Enable the DMA Engine and call s_stream(true) through the pipeline. 918 * Should be called after media_pipeline_start() 919 */ 920 static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap) 921 __must_hold(&cap->rkisp1->stream_lock) 922 { 923 struct rkisp1_device *rkisp1 = cap->rkisp1; 924 int ret; 925 926 rkisp1_cap_stream_enable(cap); 927 928 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, 929 s_stream, true); 930 if (ret) 931 goto err_disable_cap; 932 933 /* 934 * If the other capture is streaming, isp and sensor nodes are already 935 * enabled, skip them. 936 */ 937 if (rkisp1->pipe.streaming_count > 1) 938 return 0; 939 940 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true); 941 if (ret) 942 goto err_disable_rsz; 943 944 ret = v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream, 945 true); 946 if (ret) 947 goto err_disable_isp; 948 949 return 0; 950 951 err_disable_isp: 952 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 953 err_disable_rsz: 954 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 955 false); 956 err_disable_cap: 957 rkisp1_cap_stream_disable(cap); 958 959 return ret; 960 } 961 962 static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue) 963 { 964 struct rkisp1_capture *cap = queue->drv_priv; 965 struct rkisp1_vdev_node *node = &cap->vnode; 966 struct rkisp1_device *rkisp1 = cap->rkisp1; 967 int ret; 968 969 mutex_lock(&cap->rkisp1->stream_lock); 970 971 rkisp1_pipeline_stream_disable(cap); 972 973 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR); 974 975 v4l2_pipeline_pm_put(&node->vdev.entity); 976 ret = pm_runtime_put(rkisp1->dev); 977 if (ret < 0) 978 dev_err(rkisp1->dev, "power down failed error:%d\n", ret); 979 980 rkisp1_dummy_buf_destroy(cap); 981 982 media_pipeline_stop(&node->vdev.entity); 983 984 mutex_unlock(&cap->rkisp1->stream_lock); 985 } 986 987 static int 988 rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count) 989 { 990 struct rkisp1_capture *cap = queue->drv_priv; 991 struct media_entity *entity = &cap->vnode.vdev.entity; 992 int ret; 993 994 mutex_lock(&cap->rkisp1->stream_lock); 995 996 ret = media_pipeline_start(entity, &cap->rkisp1->pipe); 997 if (ret) { 998 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret); 999 goto err_ret_buffers; 1000 } 1001 1002 ret = rkisp1_dummy_buf_create(cap); 1003 if (ret) 1004 goto err_pipeline_stop; 1005 1006 ret = pm_runtime_resume_and_get(cap->rkisp1->dev); 1007 if (ret < 0) { 1008 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret); 1009 goto err_destroy_dummy; 1010 } 1011 ret = v4l2_pipeline_pm_get(entity); 1012 if (ret) { 1013 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret); 1014 goto err_pipe_pm_put; 1015 } 1016 1017 ret = rkisp1_pipeline_stream_enable(cap); 1018 if (ret) 1019 goto err_v4l2_pm_put; 1020 1021 mutex_unlock(&cap->rkisp1->stream_lock); 1022 1023 return 0; 1024 1025 err_v4l2_pm_put: 1026 v4l2_pipeline_pm_put(entity); 1027 err_pipe_pm_put: 1028 pm_runtime_put(cap->rkisp1->dev); 1029 err_destroy_dummy: 1030 rkisp1_dummy_buf_destroy(cap); 1031 err_pipeline_stop: 1032 media_pipeline_stop(entity); 1033 err_ret_buffers: 1034 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED); 1035 mutex_unlock(&cap->rkisp1->stream_lock); 1036 1037 return ret; 1038 } 1039 1040 static const struct vb2_ops rkisp1_vb2_ops = { 1041 .queue_setup = rkisp1_vb2_queue_setup, 1042 .buf_queue = rkisp1_vb2_buf_queue, 1043 .buf_prepare = rkisp1_vb2_buf_prepare, 1044 .wait_prepare = vb2_ops_wait_prepare, 1045 .wait_finish = vb2_ops_wait_finish, 1046 .stop_streaming = rkisp1_vb2_stop_streaming, 1047 .start_streaming = rkisp1_vb2_start_streaming, 1048 }; 1049 1050 /* ---------------------------------------------------------------------------- 1051 * IOCTLs operations 1052 */ 1053 1054 static const struct v4l2_format_info * 1055 rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm, 1056 enum rkisp1_stream_id id) 1057 { 1058 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0]; 1059 const struct v4l2_format_info *info; 1060 unsigned int i; 1061 u32 stride; 1062 1063 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt)); 1064 info = v4l2_format_info(pixm->pixelformat); 1065 pixm->num_planes = info->mem_planes; 1066 stride = info->bpp[0] * pixm->width; 1067 /* Self path supports custom stride but Main path doesn't */ 1068 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride) 1069 plane_y->bytesperline = stride; 1070 plane_y->sizeimage = plane_y->bytesperline * pixm->height; 1071 1072 /* normalize stride to pixels per line */ 1073 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]); 1074 1075 for (i = 1; i < info->comp_planes; i++) { 1076 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i]; 1077 1078 /* bytesperline for other components derive from Y component */ 1079 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) * 1080 info->bpp[i]; 1081 plane->sizeimage = plane->bytesperline * 1082 DIV_ROUND_UP(pixm->height, info->vdiv); 1083 } 1084 1085 /* 1086 * If pixfmt is packed, then plane_fmt[0] should contain the total size 1087 * considering all components. plane_fmt[i] for i > 0 should be ignored 1088 * by userspace as mem_planes == 1, but we are keeping information there 1089 * for convenience. 1090 */ 1091 if (info->mem_planes == 1) 1092 for (i = 1; i < info->comp_planes; i++) 1093 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage; 1094 1095 return info; 1096 } 1097 1098 static const struct rkisp1_capture_fmt_cfg * 1099 rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt) 1100 { 1101 unsigned int i; 1102 1103 for (i = 0; i < cap->config->fmt_size; i++) { 1104 if (cap->config->fmts[i].fourcc == pixelfmt) 1105 return &cap->config->fmts[i]; 1106 } 1107 return NULL; 1108 } 1109 1110 static void rkisp1_try_fmt(const struct rkisp1_capture *cap, 1111 struct v4l2_pix_format_mplane *pixm, 1112 const struct rkisp1_capture_fmt_cfg **fmt_cfg, 1113 const struct v4l2_format_info **fmt_info) 1114 { 1115 const struct rkisp1_capture_config *config = cap->config; 1116 const struct rkisp1_capture_fmt_cfg *fmt; 1117 const struct v4l2_format_info *info; 1118 const unsigned int max_widths[] = { RKISP1_RSZ_MP_SRC_MAX_WIDTH, 1119 RKISP1_RSZ_SP_SRC_MAX_WIDTH }; 1120 const unsigned int max_heights[] = { RKISP1_RSZ_MP_SRC_MAX_HEIGHT, 1121 RKISP1_RSZ_SP_SRC_MAX_HEIGHT}; 1122 1123 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat); 1124 if (!fmt) { 1125 fmt = config->fmts; 1126 pixm->pixelformat = fmt->fourcc; 1127 } 1128 1129 pixm->width = clamp_t(u32, pixm->width, 1130 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]); 1131 pixm->height = clamp_t(u32, pixm->height, 1132 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]); 1133 1134 pixm->field = V4L2_FIELD_NONE; 1135 pixm->colorspace = V4L2_COLORSPACE_DEFAULT; 1136 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1137 pixm->quantization = V4L2_QUANTIZATION_DEFAULT; 1138 1139 info = rkisp1_fill_pixfmt(pixm, cap->id); 1140 1141 if (fmt_cfg) 1142 *fmt_cfg = fmt; 1143 if (fmt_info) 1144 *fmt_info = info; 1145 } 1146 1147 static void rkisp1_set_fmt(struct rkisp1_capture *cap, 1148 struct v4l2_pix_format_mplane *pixm) 1149 { 1150 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info); 1151 cap->pix.fmt = *pixm; 1152 1153 /* SP supports custom stride in number of pixels of the Y plane */ 1154 if (cap->id == RKISP1_SELFPATH) 1155 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline / 1156 cap->pix.info->bpp[0]; 1157 } 1158 1159 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh, 1160 struct v4l2_format *f) 1161 { 1162 struct rkisp1_capture *cap = video_drvdata(file); 1163 1164 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL); 1165 1166 return 0; 1167 } 1168 1169 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv, 1170 struct v4l2_fmtdesc *f) 1171 { 1172 struct rkisp1_capture *cap = video_drvdata(file); 1173 const struct rkisp1_capture_fmt_cfg *fmt = NULL; 1174 unsigned int i, n = 0; 1175 1176 if (!f->mbus_code) { 1177 if (f->index >= cap->config->fmt_size) 1178 return -EINVAL; 1179 1180 fmt = &cap->config->fmts[f->index]; 1181 f->pixelformat = fmt->fourcc; 1182 return 0; 1183 } 1184 1185 for (i = 0; i < cap->config->fmt_size; i++) { 1186 if (cap->config->fmts[i].mbus != f->mbus_code) 1187 continue; 1188 1189 if (n++ == f->index) { 1190 f->pixelformat = cap->config->fmts[i].fourcc; 1191 return 0; 1192 } 1193 } 1194 return -EINVAL; 1195 } 1196 1197 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file, 1198 void *priv, struct v4l2_format *f) 1199 { 1200 struct rkisp1_capture *cap = video_drvdata(file); 1201 struct rkisp1_vdev_node *node = 1202 rkisp1_vdev_to_node(&cap->vnode.vdev); 1203 1204 if (vb2_is_busy(&node->buf_queue)) 1205 return -EBUSY; 1206 1207 rkisp1_set_fmt(cap, &f->fmt.pix_mp); 1208 1209 return 0; 1210 } 1211 1212 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh, 1213 struct v4l2_format *f) 1214 { 1215 struct rkisp1_capture *cap = video_drvdata(file); 1216 1217 f->fmt.pix_mp = cap->pix.fmt; 1218 1219 return 0; 1220 } 1221 1222 static int 1223 rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 1224 { 1225 struct rkisp1_capture *cap_dev = video_drvdata(file); 1226 struct rkisp1_device *rkisp1 = cap_dev->rkisp1; 1227 1228 strscpy(cap->driver, rkisp1->dev->driver->name, sizeof(cap->driver)); 1229 strscpy(cap->card, rkisp1->dev->driver->name, sizeof(cap->card)); 1230 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info)); 1231 1232 return 0; 1233 } 1234 1235 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = { 1236 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1237 .vidioc_querybuf = vb2_ioctl_querybuf, 1238 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1239 .vidioc_qbuf = vb2_ioctl_qbuf, 1240 .vidioc_expbuf = vb2_ioctl_expbuf, 1241 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1242 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1243 .vidioc_streamon = vb2_ioctl_streamon, 1244 .vidioc_streamoff = vb2_ioctl_streamoff, 1245 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane, 1246 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane, 1247 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane, 1248 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane, 1249 .vidioc_querycap = rkisp1_querycap, 1250 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1251 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1252 }; 1253 1254 static int rkisp1_capture_link_validate(struct media_link *link) 1255 { 1256 struct video_device *vdev = 1257 media_entity_to_video_device(link->sink->entity); 1258 struct v4l2_subdev *sd = 1259 media_entity_to_v4l2_subdev(link->source->entity); 1260 struct rkisp1_capture *cap = video_get_drvdata(vdev); 1261 const struct rkisp1_capture_fmt_cfg *fmt = 1262 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat); 1263 struct v4l2_subdev_format sd_fmt; 1264 int ret; 1265 1266 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 1267 sd_fmt.pad = link->source->index; 1268 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt); 1269 if (ret) 1270 return ret; 1271 1272 if (sd_fmt.format.height != cap->pix.fmt.height || 1273 sd_fmt.format.width != cap->pix.fmt.width || 1274 sd_fmt.format.code != fmt->mbus) 1275 return -EPIPE; 1276 1277 return 0; 1278 } 1279 1280 /* ---------------------------------------------------------------------------- 1281 * core functions 1282 */ 1283 1284 static const struct media_entity_operations rkisp1_media_ops = { 1285 .link_validate = rkisp1_capture_link_validate, 1286 }; 1287 1288 static const struct v4l2_file_operations rkisp1_fops = { 1289 .open = v4l2_fh_open, 1290 .release = vb2_fop_release, 1291 .unlocked_ioctl = video_ioctl2, 1292 .poll = vb2_fop_poll, 1293 .mmap = vb2_fop_mmap, 1294 }; 1295 1296 static void rkisp1_unregister_capture(struct rkisp1_capture *cap) 1297 { 1298 media_entity_cleanup(&cap->vnode.vdev.entity); 1299 vb2_video_unregister_device(&cap->vnode.vdev); 1300 } 1301 1302 void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1) 1303 { 1304 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH]; 1305 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH]; 1306 1307 rkisp1_unregister_capture(mp); 1308 rkisp1_unregister_capture(sp); 1309 } 1310 1311 static int rkisp1_register_capture(struct rkisp1_capture *cap) 1312 { 1313 const char * const dev_names[] = {RKISP1_MP_DEV_NAME, 1314 RKISP1_SP_DEV_NAME}; 1315 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev; 1316 struct video_device *vdev = &cap->vnode.vdev; 1317 struct rkisp1_vdev_node *node; 1318 struct vb2_queue *q; 1319 int ret; 1320 1321 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name)); 1322 node = rkisp1_vdev_to_node(vdev); 1323 mutex_init(&node->vlock); 1324 1325 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops; 1326 vdev->release = video_device_release_empty; 1327 vdev->fops = &rkisp1_fops; 1328 vdev->minor = -1; 1329 vdev->v4l2_dev = v4l2_dev; 1330 vdev->lock = &node->vlock; 1331 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1332 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; 1333 vdev->entity.ops = &rkisp1_media_ops; 1334 video_set_drvdata(vdev, cap); 1335 vdev->vfl_dir = VFL_DIR_RX; 1336 node->pad.flags = MEDIA_PAD_FL_SINK; 1337 1338 q = &node->buf_queue; 1339 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1340 q->io_modes = VB2_MMAP | VB2_DMABUF; 1341 q->drv_priv = cap; 1342 q->ops = &rkisp1_vb2_ops; 1343 q->mem_ops = &vb2_dma_contig_memops; 1344 q->buf_struct_size = sizeof(struct rkisp1_buffer); 1345 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED; 1346 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1347 q->lock = &node->vlock; 1348 q->dev = cap->rkisp1->dev; 1349 ret = vb2_queue_init(q); 1350 if (ret) { 1351 dev_err(cap->rkisp1->dev, 1352 "vb2 queue init failed (err=%d)\n", ret); 1353 return ret; 1354 } 1355 1356 vdev->queue = q; 1357 1358 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1359 if (ret) { 1360 dev_err(cap->rkisp1->dev, 1361 "failed to register %s, ret=%d\n", vdev->name, ret); 1362 return ret; 1363 } 1364 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name, 1365 vdev->num); 1366 1367 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); 1368 if (ret) { 1369 video_unregister_device(vdev); 1370 return ret; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static void 1377 rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id) 1378 { 1379 struct rkisp1_capture *cap = &rkisp1->capture_devs[id]; 1380 struct v4l2_pix_format_mplane pixm; 1381 1382 memset(cap, 0, sizeof(*cap)); 1383 cap->id = id; 1384 cap->rkisp1 = rkisp1; 1385 1386 INIT_LIST_HEAD(&cap->buf.queue); 1387 init_waitqueue_head(&cap->done); 1388 spin_lock_init(&cap->buf.lock); 1389 if (cap->id == RKISP1_SELFPATH) { 1390 cap->ops = &rkisp1_capture_ops_sp; 1391 cap->config = &rkisp1_capture_config_sp; 1392 } else { 1393 cap->ops = &rkisp1_capture_ops_mp; 1394 cap->config = &rkisp1_capture_config_mp; 1395 } 1396 1397 cap->is_streaming = false; 1398 1399 memset(&pixm, 0, sizeof(pixm)); 1400 pixm.pixelformat = V4L2_PIX_FMT_YUYV; 1401 pixm.width = RKISP1_DEFAULT_WIDTH; 1402 pixm.height = RKISP1_DEFAULT_HEIGHT; 1403 rkisp1_set_fmt(cap, &pixm); 1404 } 1405 1406 int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1) 1407 { 1408 struct rkisp1_capture *cap; 1409 unsigned int i, j; 1410 int ret; 1411 1412 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) { 1413 rkisp1_capture_init(rkisp1, i); 1414 cap = &rkisp1->capture_devs[i]; 1415 cap->rkisp1 = rkisp1; 1416 ret = rkisp1_register_capture(cap); 1417 if (ret) 1418 goto err_unreg_capture_devs; 1419 } 1420 1421 return 0; 1422 1423 err_unreg_capture_devs: 1424 for (j = 0; j < i; j++) { 1425 cap = &rkisp1->capture_devs[j]; 1426 rkisp1_unregister_capture(cap); 1427 } 1428 1429 return ret; 1430 } 1431