1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - V4l capture device 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/pm_runtime.h> 13 #include <media/v4l2-common.h> 14 #include <media/v4l2-event.h> 15 #include <media/v4l2-fh.h> 16 #include <media/v4l2-ioctl.h> 17 #include <media/v4l2-mc.h> 18 #include <media/v4l2-subdev.h> 19 #include <media/videobuf2-dma-contig.h> 20 21 #include "rkisp1-common.h" 22 23 /* 24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath. 25 * 26 * differences between selfpath and mainpath 27 * available mp sink input: isp 28 * available sp sink input : isp, dma(TODO) 29 * available mp sink pad fmts: yuv422, raw 30 * available sp sink pad fmts: yuv422, yuv420...... 31 * available mp source fmts: yuv, raw, jpeg(TODO) 32 * available sp source fmts: yuv, rgb 33 */ 34 35 #define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath" 36 #define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath" 37 38 #define RKISP1_MIN_BUFFERS_NEEDED 3 39 40 enum rkisp1_plane { 41 RKISP1_PLANE_Y = 0, 42 RKISP1_PLANE_CB = 1, 43 RKISP1_PLANE_CR = 2 44 }; 45 46 /* 47 * @fourcc: pixel format 48 * @fmt_type: helper filed for pixel format 49 * @uv_swap: if cb cr swapped, for yuv 50 * @write_format: defines how YCbCr self picture data is written to memory 51 * @output_format: defines sp output format 52 * @mbus: the mbus code on the src resizer pad that matches the pixel format 53 */ 54 struct rkisp1_capture_fmt_cfg { 55 u32 fourcc; 56 u8 uv_swap; 57 u32 write_format; 58 u32 output_format; 59 u32 mbus; 60 }; 61 62 struct rkisp1_capture_ops { 63 void (*config)(struct rkisp1_capture *cap); 64 void (*stop)(struct rkisp1_capture *cap); 65 void (*enable)(struct rkisp1_capture *cap); 66 void (*disable)(struct rkisp1_capture *cap); 67 void (*set_data_path)(struct rkisp1_capture *cap); 68 bool (*is_stopped)(struct rkisp1_capture *cap); 69 }; 70 71 struct rkisp1_capture_config { 72 const struct rkisp1_capture_fmt_cfg *fmts; 73 int fmt_size; 74 struct { 75 u32 y_size_init; 76 u32 cb_size_init; 77 u32 cr_size_init; 78 u32 y_base_ad_init; 79 u32 cb_base_ad_init; 80 u32 cr_base_ad_init; 81 u32 y_offs_cnt_init; 82 u32 cb_offs_cnt_init; 83 u32 cr_offs_cnt_init; 84 } mi; 85 }; 86 87 /* 88 * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus' 89 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 90 */ 91 static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { 92 /* yuv422 */ 93 { 94 .fourcc = V4L2_PIX_FMT_YUYV, 95 .uv_swap = 0, 96 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, 97 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 98 }, { 99 .fourcc = V4L2_PIX_FMT_YUV422P, 100 .uv_swap = 0, 101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 102 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 103 }, { 104 .fourcc = V4L2_PIX_FMT_NV16, 105 .uv_swap = 0, 106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 107 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 108 }, { 109 .fourcc = V4L2_PIX_FMT_NV61, 110 .uv_swap = 1, 111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 112 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 113 }, { 114 .fourcc = V4L2_PIX_FMT_YVU422M, 115 .uv_swap = 1, 116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 117 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 118 }, 119 /* yuv400 */ 120 { 121 .fourcc = V4L2_PIX_FMT_GREY, 122 .uv_swap = 0, 123 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 124 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 125 }, 126 /* yuv420 */ 127 { 128 .fourcc = V4L2_PIX_FMT_NV21, 129 .uv_swap = 1, 130 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 131 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 132 }, { 133 .fourcc = V4L2_PIX_FMT_NV12, 134 .uv_swap = 0, 135 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 136 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 137 }, { 138 .fourcc = V4L2_PIX_FMT_NV21M, 139 .uv_swap = 1, 140 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 141 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 142 }, { 143 .fourcc = V4L2_PIX_FMT_NV12M, 144 .uv_swap = 0, 145 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 146 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 147 }, { 148 .fourcc = V4L2_PIX_FMT_YUV420, 149 .uv_swap = 0, 150 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 151 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 152 }, { 153 .fourcc = V4L2_PIX_FMT_YVU420, 154 .uv_swap = 1, 155 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 156 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 157 }, 158 /* raw */ 159 { 160 .fourcc = V4L2_PIX_FMT_SRGGB8, 161 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 162 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8, 163 }, { 164 .fourcc = V4L2_PIX_FMT_SGRBG8, 165 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 166 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8, 167 }, { 168 .fourcc = V4L2_PIX_FMT_SGBRG8, 169 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 170 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8, 171 }, { 172 .fourcc = V4L2_PIX_FMT_SBGGR8, 173 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 174 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8, 175 }, { 176 .fourcc = V4L2_PIX_FMT_SRGGB10, 177 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 178 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10, 179 }, { 180 .fourcc = V4L2_PIX_FMT_SGRBG10, 181 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 182 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10, 183 }, { 184 .fourcc = V4L2_PIX_FMT_SGBRG10, 185 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 186 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10, 187 }, { 188 .fourcc = V4L2_PIX_FMT_SBGGR10, 189 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 190 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10, 191 }, { 192 .fourcc = V4L2_PIX_FMT_SRGGB12, 193 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 194 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12, 195 }, { 196 .fourcc = V4L2_PIX_FMT_SGRBG12, 197 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 198 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12, 199 }, { 200 .fourcc = V4L2_PIX_FMT_SGBRG12, 201 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 202 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12, 203 }, { 204 .fourcc = V4L2_PIX_FMT_SBGGR12, 205 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 206 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12, 207 }, 208 }; 209 210 /* 211 * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus' 212 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 213 */ 214 static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = { 215 /* yuv422 */ 216 { 217 .fourcc = V4L2_PIX_FMT_YUYV, 218 .uv_swap = 0, 219 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT, 220 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 221 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 222 }, { 223 .fourcc = V4L2_PIX_FMT_YUV422P, 224 .uv_swap = 0, 225 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 226 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 227 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 228 }, { 229 .fourcc = V4L2_PIX_FMT_NV16, 230 .uv_swap = 0, 231 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 232 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 233 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 234 }, { 235 .fourcc = V4L2_PIX_FMT_NV61, 236 .uv_swap = 1, 237 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 238 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 239 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 240 }, { 241 .fourcc = V4L2_PIX_FMT_YVU422M, 242 .uv_swap = 1, 243 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 244 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 245 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 246 }, 247 /* yuv400 */ 248 { 249 .fourcc = V4L2_PIX_FMT_GREY, 250 .uv_swap = 0, 251 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 252 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV400, 253 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 254 }, 255 /* rgb */ 256 { 257 .fourcc = V4L2_PIX_FMT_XBGR32, 258 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 259 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888, 260 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 261 }, { 262 .fourcc = V4L2_PIX_FMT_RGB565, 263 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 264 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565, 265 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 266 }, 267 /* yuv420 */ 268 { 269 .fourcc = V4L2_PIX_FMT_NV21, 270 .uv_swap = 1, 271 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 272 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 273 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 274 }, { 275 .fourcc = V4L2_PIX_FMT_NV12, 276 .uv_swap = 0, 277 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 278 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 279 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 280 }, { 281 .fourcc = V4L2_PIX_FMT_NV21M, 282 .uv_swap = 1, 283 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 284 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 285 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 286 }, { 287 .fourcc = V4L2_PIX_FMT_NV12M, 288 .uv_swap = 0, 289 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 290 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 291 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 292 }, { 293 .fourcc = V4L2_PIX_FMT_YUV420, 294 .uv_swap = 0, 295 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 296 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 297 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 298 }, { 299 .fourcc = V4L2_PIX_FMT_YVU420, 300 .uv_swap = 1, 301 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 302 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 303 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 304 }, 305 }; 306 307 static const struct rkisp1_capture_config rkisp1_capture_config_mp = { 308 .fmts = rkisp1_mp_fmts, 309 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts), 310 .mi = { 311 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT, 312 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT, 313 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT, 314 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT, 315 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT, 316 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT, 317 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT, 318 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT, 319 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT, 320 }, 321 }; 322 323 static const struct rkisp1_capture_config rkisp1_capture_config_sp = { 324 .fmts = rkisp1_sp_fmts, 325 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts), 326 .mi = { 327 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT, 328 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT, 329 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT, 330 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT, 331 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT, 332 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT, 333 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT, 334 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT, 335 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT, 336 }, 337 }; 338 339 static inline struct rkisp1_vdev_node * 340 rkisp1_vdev_to_node(struct video_device *vdev) 341 { 342 return container_of(vdev, struct rkisp1_vdev_node, vdev); 343 } 344 345 int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap, 346 struct v4l2_subdev_mbus_code_enum *code) 347 { 348 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts; 349 /* 350 * initialize curr_mbus to non existing mbus code 0 to ensure it is 351 * different from fmts[0].mbus 352 */ 353 u32 curr_mbus = 0; 354 int i, n = 0; 355 356 for (i = 0; i < cap->config->fmt_size; i++) { 357 if (fmts[i].mbus == curr_mbus) 358 continue; 359 360 curr_mbus = fmts[i].mbus; 361 if (n++ == code->index) { 362 code->code = curr_mbus; 363 return 0; 364 } 365 } 366 return -EINVAL; 367 } 368 369 /* ---------------------------------------------------------------------------- 370 * Stream operations for self-picture path (sp) and main-picture path (mp) 371 */ 372 373 static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap) 374 { 375 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 376 377 mi_ctrl &= ~GENMASK(17, 16); 378 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64; 379 380 mi_ctrl &= ~GENMASK(19, 18); 381 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64; 382 383 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN | 384 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN; 385 386 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 387 } 388 389 static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm, 390 unsigned int component) 391 { 392 /* 393 * If packed format, then plane_fmt[0].sizeimage is the sum of all 394 * components, so we need to calculate just the size of Y component. 395 * See rkisp1_fill_pixfmt(). 396 */ 397 if (!component && pixm->num_planes == 1) 398 return pixm->plane_fmt[0].bytesperline * pixm->height; 399 return pixm->plane_fmt[component].sizeimage; 400 } 401 402 static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap) 403 { 404 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC); 405 406 mi_imsc |= RKISP1_CIF_MI_FRAME(cap); 407 rkisp1_write(cap->rkisp1, mi_imsc, RKISP1_CIF_MI_IMSC); 408 } 409 410 static void rkisp1_mp_config(struct rkisp1_capture *cap) 411 { 412 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 413 struct rkisp1_device *rkisp1 = cap->rkisp1; 414 u32 reg; 415 416 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 417 cap->config->mi.y_size_init); 418 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 419 cap->config->mi.cb_size_init); 420 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR), 421 cap->config->mi.cr_size_init); 422 423 rkisp1_irq_frame_end_enable(cap); 424 425 /* set uv swapping for semiplanar formats */ 426 if (cap->pix.info->comp_planes == 2) { 427 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 428 if (cap->pix.cfg->uv_swap) 429 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 430 else 431 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 432 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 433 } 434 435 rkisp1_mi_config_ctrl(cap); 436 437 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 438 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK; 439 reg |= cap->pix.cfg->write_format; 440 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL); 441 442 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 443 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE; 444 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL); 445 } 446 447 static void rkisp1_sp_config(struct rkisp1_capture *cap) 448 { 449 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 450 struct rkisp1_device *rkisp1 = cap->rkisp1; 451 u32 mi_ctrl, reg; 452 453 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 454 cap->config->mi.y_size_init); 455 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 456 cap->config->mi.cb_size_init); 457 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR), 458 cap->config->mi.cr_size_init); 459 460 rkisp1_write(rkisp1, pixm->width, RKISP1_CIF_MI_SP_Y_PIC_WIDTH); 461 rkisp1_write(rkisp1, pixm->height, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT); 462 rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH); 463 464 rkisp1_irq_frame_end_enable(cap); 465 466 /* set uv swapping for semiplanar formats */ 467 if (cap->pix.info->comp_planes == 2) { 468 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 469 if (cap->pix.cfg->uv_swap) 470 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 471 else 472 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 473 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 474 } 475 476 rkisp1_mi_config_ctrl(cap); 477 478 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 479 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK; 480 mi_ctrl |= cap->pix.cfg->write_format | 481 RKISP1_MI_CTRL_SP_INPUT_YUV422 | 482 cap->pix.cfg->output_format | 483 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE; 484 rkisp1_write(rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 485 } 486 487 static void rkisp1_mp_disable(struct rkisp1_capture *cap) 488 { 489 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 490 491 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE | 492 RKISP1_CIF_MI_CTRL_RAW_ENABLE); 493 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 494 } 495 496 static void rkisp1_sp_disable(struct rkisp1_capture *cap) 497 { 498 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 499 500 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE; 501 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 502 } 503 504 static void rkisp1_mp_enable(struct rkisp1_capture *cap) 505 { 506 u32 mi_ctrl; 507 508 rkisp1_mp_disable(cap); 509 510 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 511 if (v4l2_is_format_bayer(cap->pix.info)) 512 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE; 513 /* YUV */ 514 else 515 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE; 516 517 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 518 } 519 520 static void rkisp1_sp_enable(struct rkisp1_capture *cap) 521 { 522 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 523 524 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE; 525 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 526 } 527 528 static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap) 529 { 530 if (!cap->is_streaming) 531 return; 532 rkisp1_write(cap->rkisp1, 533 RKISP1_CIF_MI_FRAME(cap), RKISP1_CIF_MI_ICR); 534 cap->ops->disable(cap); 535 } 536 537 static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap) 538 { 539 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED | 540 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED; 541 542 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en); 543 } 544 545 static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap) 546 { 547 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & 548 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED); 549 } 550 551 static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap) 552 { 553 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 554 555 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP | 556 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI; 557 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 558 } 559 560 static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap) 561 { 562 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 563 564 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP; 565 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 566 } 567 568 static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = { 569 .config = rkisp1_mp_config, 570 .enable = rkisp1_mp_enable, 571 .disable = rkisp1_mp_disable, 572 .stop = rkisp1_mp_sp_stop, 573 .set_data_path = rkisp1_mp_set_data_path, 574 .is_stopped = rkisp1_mp_is_stopped, 575 }; 576 577 static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = { 578 .config = rkisp1_sp_config, 579 .enable = rkisp1_sp_enable, 580 .disable = rkisp1_sp_disable, 581 .stop = rkisp1_mp_sp_stop, 582 .set_data_path = rkisp1_sp_set_data_path, 583 .is_stopped = rkisp1_sp_is_stopped, 584 }; 585 586 /* ---------------------------------------------------------------------------- 587 * Frame buffer operations 588 */ 589 590 static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap) 591 { 592 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 593 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy; 594 595 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 596 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 597 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 598 599 /* The driver never access vaddr, no mapping is required */ 600 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev, 601 dummy_buf->size, 602 &dummy_buf->dma_addr, 603 GFP_KERNEL, 604 DMA_ATTR_NO_KERNEL_MAPPING); 605 if (!dummy_buf->vaddr) 606 return -ENOMEM; 607 608 return 0; 609 } 610 611 static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap) 612 { 613 dma_free_attrs(cap->rkisp1->dev, 614 cap->buf.dummy.size, cap->buf.dummy.vaddr, 615 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING); 616 } 617 618 static void rkisp1_set_next_buf(struct rkisp1_capture *cap) 619 { 620 cap->buf.curr = cap->buf.next; 621 cap->buf.next = NULL; 622 623 if (!list_empty(&cap->buf.queue)) { 624 u32 *buff_addr; 625 626 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue); 627 list_del(&cap->buf.next->queue); 628 629 buff_addr = cap->buf.next->buff_addr; 630 631 rkisp1_write(cap->rkisp1, 632 buff_addr[RKISP1_PLANE_Y], 633 cap->config->mi.y_base_ad_init); 634 rkisp1_write(cap->rkisp1, 635 buff_addr[RKISP1_PLANE_CB], 636 cap->config->mi.cb_base_ad_init); 637 rkisp1_write(cap->rkisp1, 638 buff_addr[RKISP1_PLANE_CR], 639 cap->config->mi.cr_base_ad_init); 640 } else { 641 /* 642 * Use the dummy space allocated by dma_alloc_coherent to 643 * throw data if there is no available buffer. 644 */ 645 rkisp1_write(cap->rkisp1, 646 cap->buf.dummy.dma_addr, 647 cap->config->mi.y_base_ad_init); 648 rkisp1_write(cap->rkisp1, 649 cap->buf.dummy.dma_addr, 650 cap->config->mi.cb_base_ad_init); 651 rkisp1_write(cap->rkisp1, 652 cap->buf.dummy.dma_addr, 653 cap->config->mi.cr_base_ad_init); 654 } 655 656 /* Set plane offsets */ 657 rkisp1_write(cap->rkisp1, 0, cap->config->mi.y_offs_cnt_init); 658 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cb_offs_cnt_init); 659 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cr_offs_cnt_init); 660 } 661 662 /* 663 * This function is called when a frame end comes. The next frame 664 * is processing and we should set up buffer for next-next frame, 665 * otherwise it will overflow. 666 */ 667 static void rkisp1_handle_buffer(struct rkisp1_capture *cap) 668 { 669 struct rkisp1_isp *isp = &cap->rkisp1->isp; 670 struct rkisp1_buffer *curr_buf; 671 672 spin_lock(&cap->buf.lock); 673 curr_buf = cap->buf.curr; 674 675 if (curr_buf) { 676 curr_buf->vb.sequence = isp->frame_sequence; 677 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns(); 678 curr_buf->vb.field = V4L2_FIELD_NONE; 679 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 680 } else { 681 cap->rkisp1->debug.frame_drop[cap->id]++; 682 } 683 684 rkisp1_set_next_buf(cap); 685 spin_unlock(&cap->buf.lock); 686 } 687 688 irqreturn_t rkisp1_capture_isr(int irq, void *ctx) 689 { 690 struct device *dev = ctx; 691 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 692 unsigned int i; 693 u32 status; 694 695 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS); 696 if (!status) 697 return IRQ_NONE; 698 699 rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR); 700 701 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) { 702 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 703 704 if (!(status & RKISP1_CIF_MI_FRAME(cap))) 705 continue; 706 if (!cap->is_stopping) { 707 rkisp1_handle_buffer(cap); 708 continue; 709 } 710 /* 711 * Make sure stream is actually stopped, whose state 712 * can be read from the shadow register, before 713 * wake_up() thread which would immediately free all 714 * frame buffers. stop() takes effect at the next 715 * frame end that sync the configurations to shadow 716 * regs. 717 */ 718 if (!cap->ops->is_stopped(cap)) { 719 cap->ops->stop(cap); 720 continue; 721 } 722 cap->is_stopping = false; 723 cap->is_streaming = false; 724 wake_up(&cap->done); 725 } 726 727 return IRQ_HANDLED; 728 } 729 730 /* ---------------------------------------------------------------------------- 731 * Vb2 operations 732 */ 733 734 static int rkisp1_vb2_queue_setup(struct vb2_queue *queue, 735 unsigned int *num_buffers, 736 unsigned int *num_planes, 737 unsigned int sizes[], 738 struct device *alloc_devs[]) 739 { 740 struct rkisp1_capture *cap = queue->drv_priv; 741 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 742 unsigned int i; 743 744 if (*num_planes) { 745 if (*num_planes != pixm->num_planes) 746 return -EINVAL; 747 748 for (i = 0; i < pixm->num_planes; i++) 749 if (sizes[i] < pixm->plane_fmt[i].sizeimage) 750 return -EINVAL; 751 } else { 752 *num_planes = pixm->num_planes; 753 for (i = 0; i < pixm->num_planes; i++) 754 sizes[i] = pixm->plane_fmt[i].sizeimage; 755 } 756 757 return 0; 758 } 759 760 static int rkisp1_vb2_buf_init(struct vb2_buffer *vb) 761 { 762 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 763 struct rkisp1_buffer *ispbuf = 764 container_of(vbuf, struct rkisp1_buffer, vb); 765 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 766 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 767 unsigned int i; 768 769 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr)); 770 for (i = 0; i < pixm->num_planes; i++) 771 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); 772 773 /* Convert to non-MPLANE */ 774 if (pixm->num_planes == 1) { 775 ispbuf->buff_addr[RKISP1_PLANE_CB] = 776 ispbuf->buff_addr[RKISP1_PLANE_Y] + 777 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y); 778 ispbuf->buff_addr[RKISP1_PLANE_CR] = 779 ispbuf->buff_addr[RKISP1_PLANE_CB] + 780 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB); 781 } 782 783 /* 784 * uv swap can be supported for planar formats by switching 785 * the address of cb and cr 786 */ 787 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap) 788 swap(ispbuf->buff_addr[RKISP1_PLANE_CR], 789 ispbuf->buff_addr[RKISP1_PLANE_CB]); 790 return 0; 791 } 792 793 static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb) 794 { 795 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 796 struct rkisp1_buffer *ispbuf = 797 container_of(vbuf, struct rkisp1_buffer, vb); 798 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 799 800 spin_lock_irq(&cap->buf.lock); 801 list_add_tail(&ispbuf->queue, &cap->buf.queue); 802 spin_unlock_irq(&cap->buf.lock); 803 } 804 805 static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb) 806 { 807 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 808 unsigned int i; 809 810 for (i = 0; i < cap->pix.fmt.num_planes; i++) { 811 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage; 812 813 if (vb2_plane_size(vb, i) < size) { 814 dev_err(cap->rkisp1->dev, 815 "User buffer too small (%ld < %ld)\n", 816 vb2_plane_size(vb, i), size); 817 return -EINVAL; 818 } 819 vb2_set_plane_payload(vb, i, size); 820 } 821 822 return 0; 823 } 824 825 static void rkisp1_return_all_buffers(struct rkisp1_capture *cap, 826 enum vb2_buffer_state state) 827 { 828 struct rkisp1_buffer *buf; 829 830 spin_lock_irq(&cap->buf.lock); 831 if (cap->buf.curr) { 832 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state); 833 cap->buf.curr = NULL; 834 } 835 if (cap->buf.next) { 836 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state); 837 cap->buf.next = NULL; 838 } 839 while (!list_empty(&cap->buf.queue)) { 840 buf = list_first_entry(&cap->buf.queue, 841 struct rkisp1_buffer, queue); 842 list_del(&buf->queue); 843 vb2_buffer_done(&buf->vb.vb2_buf, state); 844 } 845 spin_unlock_irq(&cap->buf.lock); 846 } 847 848 /* 849 * Most registers inside the rockchip ISP1 have shadow register since 850 * they must not be changed while processing a frame. 851 * Usually, each sub-module updates its shadow register after 852 * processing the last pixel of a frame. 853 */ 854 static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) 855 { 856 struct rkisp1_device *rkisp1 = cap->rkisp1; 857 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1]; 858 859 cap->ops->set_data_path(cap); 860 cap->ops->config(cap); 861 862 /* Setup a buffer for the next frame */ 863 spin_lock_irq(&cap->buf.lock); 864 rkisp1_set_next_buf(cap); 865 cap->ops->enable(cap); 866 /* It's safe to configure ACTIVE and SHADOW registers for the 867 * first stream. While when the second is starting, do NOT 868 * force update because it also updates the first one. 869 * 870 * The latter case would drop one more buffer(that is 2) since 871 * there's no buffer in a shadow register when the second FE received. 872 * This's also required because the second FE maybe corrupt 873 * especially when run at 120fps. 874 */ 875 if (!other->is_streaming) { 876 /* force cfg update */ 877 rkisp1_write(rkisp1, 878 RKISP1_CIF_MI_INIT_SOFT_UPD, RKISP1_CIF_MI_INIT); 879 rkisp1_set_next_buf(cap); 880 } 881 spin_unlock_irq(&cap->buf.lock); 882 cap->is_streaming = true; 883 } 884 885 static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap) 886 { 887 int ret; 888 889 /* Stream should stop in interrupt. If it doesn't, stop it by force. */ 890 cap->is_stopping = true; 891 ret = wait_event_timeout(cap->done, 892 !cap->is_streaming, 893 msecs_to_jiffies(1000)); 894 if (!ret) { 895 cap->rkisp1->debug.stop_timeout[cap->id]++; 896 cap->ops->stop(cap); 897 cap->is_stopping = false; 898 cap->is_streaming = false; 899 } 900 } 901 902 /* 903 * rkisp1_pipeline_stream_disable - disable nodes in the pipeline 904 * 905 * Call s_stream(false) in the reverse order from 906 * rkisp1_pipeline_stream_enable() and disable the DMA engine. 907 * Should be called before media_pipeline_stop() 908 */ 909 static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap) 910 __must_hold(&cap->rkisp1->stream_lock) 911 { 912 struct rkisp1_device *rkisp1 = cap->rkisp1; 913 914 rkisp1_cap_stream_disable(cap); 915 916 /* 917 * If the other capture is streaming, isp and sensor nodes shouldn't 918 * be disabled, skip them. 919 */ 920 if (rkisp1->pipe.streaming_count < 2) { 921 v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream, 922 false); 923 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 924 } 925 926 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 927 false); 928 } 929 930 /* 931 * rkisp1_pipeline_stream_enable - enable nodes in the pipeline 932 * 933 * Enable the DMA Engine and call s_stream(true) through the pipeline. 934 * Should be called after media_pipeline_start() 935 */ 936 static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap) 937 __must_hold(&cap->rkisp1->stream_lock) 938 { 939 struct rkisp1_device *rkisp1 = cap->rkisp1; 940 int ret; 941 942 rkisp1_cap_stream_enable(cap); 943 944 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, 945 s_stream, true); 946 if (ret) 947 goto err_disable_cap; 948 949 /* 950 * If the other capture is streaming, isp and sensor nodes are already 951 * enabled, skip them. 952 */ 953 if (rkisp1->pipe.streaming_count > 1) 954 return 0; 955 956 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true); 957 if (ret) 958 goto err_disable_rsz; 959 960 ret = v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream, 961 true); 962 if (ret) 963 goto err_disable_isp; 964 965 return 0; 966 967 err_disable_isp: 968 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 969 err_disable_rsz: 970 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 971 false); 972 err_disable_cap: 973 rkisp1_cap_stream_disable(cap); 974 975 return ret; 976 } 977 978 static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue) 979 { 980 struct rkisp1_capture *cap = queue->drv_priv; 981 struct rkisp1_vdev_node *node = &cap->vnode; 982 struct rkisp1_device *rkisp1 = cap->rkisp1; 983 int ret; 984 985 mutex_lock(&cap->rkisp1->stream_lock); 986 987 rkisp1_pipeline_stream_disable(cap); 988 989 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR); 990 991 v4l2_pipeline_pm_put(&node->vdev.entity); 992 ret = pm_runtime_put(rkisp1->dev); 993 if (ret < 0) 994 dev_err(rkisp1->dev, "power down failed error:%d\n", ret); 995 996 rkisp1_dummy_buf_destroy(cap); 997 998 media_pipeline_stop(&node->vdev.entity); 999 1000 mutex_unlock(&cap->rkisp1->stream_lock); 1001 } 1002 1003 static int 1004 rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count) 1005 { 1006 struct rkisp1_capture *cap = queue->drv_priv; 1007 struct media_entity *entity = &cap->vnode.vdev.entity; 1008 int ret; 1009 1010 mutex_lock(&cap->rkisp1->stream_lock); 1011 1012 ret = media_pipeline_start(entity, &cap->rkisp1->pipe); 1013 if (ret) { 1014 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret); 1015 goto err_ret_buffers; 1016 } 1017 1018 ret = rkisp1_dummy_buf_create(cap); 1019 if (ret) 1020 goto err_pipeline_stop; 1021 1022 ret = pm_runtime_resume_and_get(cap->rkisp1->dev); 1023 if (ret < 0) { 1024 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret); 1025 goto err_destroy_dummy; 1026 } 1027 ret = v4l2_pipeline_pm_get(entity); 1028 if (ret) { 1029 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret); 1030 goto err_pipe_pm_put; 1031 } 1032 1033 ret = rkisp1_pipeline_stream_enable(cap); 1034 if (ret) 1035 goto err_v4l2_pm_put; 1036 1037 mutex_unlock(&cap->rkisp1->stream_lock); 1038 1039 return 0; 1040 1041 err_v4l2_pm_put: 1042 v4l2_pipeline_pm_put(entity); 1043 err_pipe_pm_put: 1044 pm_runtime_put(cap->rkisp1->dev); 1045 err_destroy_dummy: 1046 rkisp1_dummy_buf_destroy(cap); 1047 err_pipeline_stop: 1048 media_pipeline_stop(entity); 1049 err_ret_buffers: 1050 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED); 1051 mutex_unlock(&cap->rkisp1->stream_lock); 1052 1053 return ret; 1054 } 1055 1056 static const struct vb2_ops rkisp1_vb2_ops = { 1057 .queue_setup = rkisp1_vb2_queue_setup, 1058 .buf_init = rkisp1_vb2_buf_init, 1059 .buf_queue = rkisp1_vb2_buf_queue, 1060 .buf_prepare = rkisp1_vb2_buf_prepare, 1061 .wait_prepare = vb2_ops_wait_prepare, 1062 .wait_finish = vb2_ops_wait_finish, 1063 .stop_streaming = rkisp1_vb2_stop_streaming, 1064 .start_streaming = rkisp1_vb2_start_streaming, 1065 }; 1066 1067 /* ---------------------------------------------------------------------------- 1068 * IOCTLs operations 1069 */ 1070 1071 static const struct v4l2_format_info * 1072 rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm, 1073 enum rkisp1_stream_id id) 1074 { 1075 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0]; 1076 const struct v4l2_format_info *info; 1077 unsigned int i; 1078 u32 stride; 1079 1080 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt)); 1081 info = v4l2_format_info(pixm->pixelformat); 1082 pixm->num_planes = info->mem_planes; 1083 stride = info->bpp[0] * pixm->width; 1084 /* Self path supports custom stride but Main path doesn't */ 1085 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride) 1086 plane_y->bytesperline = stride; 1087 plane_y->sizeimage = plane_y->bytesperline * pixm->height; 1088 1089 /* normalize stride to pixels per line */ 1090 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]); 1091 1092 for (i = 1; i < info->comp_planes; i++) { 1093 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i]; 1094 1095 /* bytesperline for other components derive from Y component */ 1096 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) * 1097 info->bpp[i]; 1098 plane->sizeimage = plane->bytesperline * 1099 DIV_ROUND_UP(pixm->height, info->vdiv); 1100 } 1101 1102 /* 1103 * If pixfmt is packed, then plane_fmt[0] should contain the total size 1104 * considering all components. plane_fmt[i] for i > 0 should be ignored 1105 * by userspace as mem_planes == 1, but we are keeping information there 1106 * for convenience. 1107 */ 1108 if (info->mem_planes == 1) 1109 for (i = 1; i < info->comp_planes; i++) 1110 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage; 1111 1112 return info; 1113 } 1114 1115 static const struct rkisp1_capture_fmt_cfg * 1116 rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt) 1117 { 1118 unsigned int i; 1119 1120 for (i = 0; i < cap->config->fmt_size; i++) { 1121 if (cap->config->fmts[i].fourcc == pixelfmt) 1122 return &cap->config->fmts[i]; 1123 } 1124 return NULL; 1125 } 1126 1127 static void rkisp1_try_fmt(const struct rkisp1_capture *cap, 1128 struct v4l2_pix_format_mplane *pixm, 1129 const struct rkisp1_capture_fmt_cfg **fmt_cfg, 1130 const struct v4l2_format_info **fmt_info) 1131 { 1132 const struct rkisp1_capture_config *config = cap->config; 1133 const struct rkisp1_capture_fmt_cfg *fmt; 1134 const struct v4l2_format_info *info; 1135 const unsigned int max_widths[] = { RKISP1_RSZ_MP_SRC_MAX_WIDTH, 1136 RKISP1_RSZ_SP_SRC_MAX_WIDTH }; 1137 const unsigned int max_heights[] = { RKISP1_RSZ_MP_SRC_MAX_HEIGHT, 1138 RKISP1_RSZ_SP_SRC_MAX_HEIGHT}; 1139 1140 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat); 1141 if (!fmt) { 1142 fmt = config->fmts; 1143 pixm->pixelformat = fmt->fourcc; 1144 } 1145 1146 pixm->width = clamp_t(u32, pixm->width, 1147 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]); 1148 pixm->height = clamp_t(u32, pixm->height, 1149 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]); 1150 1151 pixm->field = V4L2_FIELD_NONE; 1152 pixm->colorspace = V4L2_COLORSPACE_DEFAULT; 1153 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1154 pixm->quantization = V4L2_QUANTIZATION_DEFAULT; 1155 1156 info = rkisp1_fill_pixfmt(pixm, cap->id); 1157 1158 if (fmt_cfg) 1159 *fmt_cfg = fmt; 1160 if (fmt_info) 1161 *fmt_info = info; 1162 } 1163 1164 static void rkisp1_set_fmt(struct rkisp1_capture *cap, 1165 struct v4l2_pix_format_mplane *pixm) 1166 { 1167 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info); 1168 cap->pix.fmt = *pixm; 1169 1170 /* SP supports custom stride in number of pixels of the Y plane */ 1171 if (cap->id == RKISP1_SELFPATH) 1172 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline / 1173 cap->pix.info->bpp[0]; 1174 } 1175 1176 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh, 1177 struct v4l2_format *f) 1178 { 1179 struct rkisp1_capture *cap = video_drvdata(file); 1180 1181 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL); 1182 1183 return 0; 1184 } 1185 1186 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv, 1187 struct v4l2_fmtdesc *f) 1188 { 1189 struct rkisp1_capture *cap = video_drvdata(file); 1190 const struct rkisp1_capture_fmt_cfg *fmt = NULL; 1191 unsigned int i, n = 0; 1192 1193 if (!f->mbus_code) { 1194 if (f->index >= cap->config->fmt_size) 1195 return -EINVAL; 1196 1197 fmt = &cap->config->fmts[f->index]; 1198 f->pixelformat = fmt->fourcc; 1199 return 0; 1200 } 1201 1202 for (i = 0; i < cap->config->fmt_size; i++) { 1203 if (cap->config->fmts[i].mbus != f->mbus_code) 1204 continue; 1205 1206 if (n++ == f->index) { 1207 f->pixelformat = cap->config->fmts[i].fourcc; 1208 return 0; 1209 } 1210 } 1211 return -EINVAL; 1212 } 1213 1214 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file, 1215 void *priv, struct v4l2_format *f) 1216 { 1217 struct rkisp1_capture *cap = video_drvdata(file); 1218 struct rkisp1_vdev_node *node = 1219 rkisp1_vdev_to_node(&cap->vnode.vdev); 1220 1221 if (vb2_is_busy(&node->buf_queue)) 1222 return -EBUSY; 1223 1224 rkisp1_set_fmt(cap, &f->fmt.pix_mp); 1225 1226 return 0; 1227 } 1228 1229 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh, 1230 struct v4l2_format *f) 1231 { 1232 struct rkisp1_capture *cap = video_drvdata(file); 1233 1234 f->fmt.pix_mp = cap->pix.fmt; 1235 1236 return 0; 1237 } 1238 1239 static int 1240 rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 1241 { 1242 struct rkisp1_capture *cap_dev = video_drvdata(file); 1243 struct rkisp1_device *rkisp1 = cap_dev->rkisp1; 1244 1245 strscpy(cap->driver, rkisp1->dev->driver->name, sizeof(cap->driver)); 1246 strscpy(cap->card, rkisp1->dev->driver->name, sizeof(cap->card)); 1247 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info)); 1248 1249 return 0; 1250 } 1251 1252 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = { 1253 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1254 .vidioc_querybuf = vb2_ioctl_querybuf, 1255 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1256 .vidioc_qbuf = vb2_ioctl_qbuf, 1257 .vidioc_expbuf = vb2_ioctl_expbuf, 1258 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1259 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1260 .vidioc_streamon = vb2_ioctl_streamon, 1261 .vidioc_streamoff = vb2_ioctl_streamoff, 1262 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane, 1263 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane, 1264 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane, 1265 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane, 1266 .vidioc_querycap = rkisp1_querycap, 1267 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1268 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1269 }; 1270 1271 static int rkisp1_capture_link_validate(struct media_link *link) 1272 { 1273 struct video_device *vdev = 1274 media_entity_to_video_device(link->sink->entity); 1275 struct v4l2_subdev *sd = 1276 media_entity_to_v4l2_subdev(link->source->entity); 1277 struct rkisp1_capture *cap = video_get_drvdata(vdev); 1278 const struct rkisp1_capture_fmt_cfg *fmt = 1279 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat); 1280 struct v4l2_subdev_format sd_fmt; 1281 int ret; 1282 1283 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 1284 sd_fmt.pad = link->source->index; 1285 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt); 1286 if (ret) 1287 return ret; 1288 1289 if (sd_fmt.format.height != cap->pix.fmt.height || 1290 sd_fmt.format.width != cap->pix.fmt.width || 1291 sd_fmt.format.code != fmt->mbus) 1292 return -EPIPE; 1293 1294 return 0; 1295 } 1296 1297 /* ---------------------------------------------------------------------------- 1298 * core functions 1299 */ 1300 1301 static const struct media_entity_operations rkisp1_media_ops = { 1302 .link_validate = rkisp1_capture_link_validate, 1303 }; 1304 1305 static const struct v4l2_file_operations rkisp1_fops = { 1306 .open = v4l2_fh_open, 1307 .release = vb2_fop_release, 1308 .unlocked_ioctl = video_ioctl2, 1309 .poll = vb2_fop_poll, 1310 .mmap = vb2_fop_mmap, 1311 }; 1312 1313 static void rkisp1_unregister_capture(struct rkisp1_capture *cap) 1314 { 1315 media_entity_cleanup(&cap->vnode.vdev.entity); 1316 vb2_video_unregister_device(&cap->vnode.vdev); 1317 } 1318 1319 void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1) 1320 { 1321 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH]; 1322 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH]; 1323 1324 rkisp1_unregister_capture(mp); 1325 rkisp1_unregister_capture(sp); 1326 } 1327 1328 static int rkisp1_register_capture(struct rkisp1_capture *cap) 1329 { 1330 const char * const dev_names[] = {RKISP1_MP_DEV_NAME, 1331 RKISP1_SP_DEV_NAME}; 1332 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev; 1333 struct video_device *vdev = &cap->vnode.vdev; 1334 struct rkisp1_vdev_node *node; 1335 struct vb2_queue *q; 1336 int ret; 1337 1338 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name)); 1339 node = rkisp1_vdev_to_node(vdev); 1340 mutex_init(&node->vlock); 1341 1342 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops; 1343 vdev->release = video_device_release_empty; 1344 vdev->fops = &rkisp1_fops; 1345 vdev->minor = -1; 1346 vdev->v4l2_dev = v4l2_dev; 1347 vdev->lock = &node->vlock; 1348 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1349 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; 1350 vdev->entity.ops = &rkisp1_media_ops; 1351 video_set_drvdata(vdev, cap); 1352 vdev->vfl_dir = VFL_DIR_RX; 1353 node->pad.flags = MEDIA_PAD_FL_SINK; 1354 1355 q = &node->buf_queue; 1356 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1357 q->io_modes = VB2_MMAP | VB2_DMABUF; 1358 q->drv_priv = cap; 1359 q->ops = &rkisp1_vb2_ops; 1360 q->mem_ops = &vb2_dma_contig_memops; 1361 q->buf_struct_size = sizeof(struct rkisp1_buffer); 1362 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED; 1363 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1364 q->lock = &node->vlock; 1365 q->dev = cap->rkisp1->dev; 1366 ret = vb2_queue_init(q); 1367 if (ret) { 1368 dev_err(cap->rkisp1->dev, 1369 "vb2 queue init failed (err=%d)\n", ret); 1370 return ret; 1371 } 1372 1373 vdev->queue = q; 1374 1375 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1376 if (ret) { 1377 dev_err(cap->rkisp1->dev, 1378 "failed to register %s, ret=%d\n", vdev->name, ret); 1379 return ret; 1380 } 1381 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name, 1382 vdev->num); 1383 1384 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); 1385 if (ret) { 1386 video_unregister_device(vdev); 1387 return ret; 1388 } 1389 1390 return 0; 1391 } 1392 1393 static void 1394 rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id) 1395 { 1396 struct rkisp1_capture *cap = &rkisp1->capture_devs[id]; 1397 struct v4l2_pix_format_mplane pixm; 1398 1399 memset(cap, 0, sizeof(*cap)); 1400 cap->id = id; 1401 cap->rkisp1 = rkisp1; 1402 1403 INIT_LIST_HEAD(&cap->buf.queue); 1404 init_waitqueue_head(&cap->done); 1405 spin_lock_init(&cap->buf.lock); 1406 if (cap->id == RKISP1_SELFPATH) { 1407 cap->ops = &rkisp1_capture_ops_sp; 1408 cap->config = &rkisp1_capture_config_sp; 1409 } else { 1410 cap->ops = &rkisp1_capture_ops_mp; 1411 cap->config = &rkisp1_capture_config_mp; 1412 } 1413 1414 cap->is_streaming = false; 1415 1416 memset(&pixm, 0, sizeof(pixm)); 1417 pixm.pixelformat = V4L2_PIX_FMT_YUYV; 1418 pixm.width = RKISP1_DEFAULT_WIDTH; 1419 pixm.height = RKISP1_DEFAULT_HEIGHT; 1420 rkisp1_set_fmt(cap, &pixm); 1421 } 1422 1423 int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1) 1424 { 1425 struct rkisp1_capture *cap; 1426 unsigned int i, j; 1427 int ret; 1428 1429 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) { 1430 rkisp1_capture_init(rkisp1, i); 1431 cap = &rkisp1->capture_devs[i]; 1432 cap->rkisp1 = rkisp1; 1433 ret = rkisp1_register_capture(cap); 1434 if (ret) 1435 goto err_unreg_capture_devs; 1436 } 1437 1438 return 0; 1439 1440 err_unreg_capture_devs: 1441 for (j = 0; j < i; j++) { 1442 cap = &rkisp1->capture_devs[j]; 1443 rkisp1_unregister_capture(cap); 1444 } 1445 1446 return ret; 1447 } 1448