1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 3 * Rockchip ISP1 Driver - V4l capture device 4 * 5 * Copyright (C) 2019 Collabora, Ltd. 6 * 7 * Based on Rockchip ISP1 driver by Rockchip Electronics Co., Ltd. 8 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 9 */ 10 11 #include <linux/delay.h> 12 #include <linux/pm_runtime.h> 13 #include <media/v4l2-common.h> 14 #include <media/v4l2-event.h> 15 #include <media/v4l2-fh.h> 16 #include <media/v4l2-ioctl.h> 17 #include <media/v4l2-mc.h> 18 #include <media/v4l2-subdev.h> 19 #include <media/videobuf2-dma-contig.h> 20 21 #include "rkisp1-common.h" 22 23 /* 24 * NOTE: There are two capture video devices in rkisp1, selfpath and mainpath. 25 * 26 * differences between selfpath and mainpath 27 * available mp sink input: isp 28 * available sp sink input : isp, dma(TODO) 29 * available mp sink pad fmts: yuv422, raw 30 * available sp sink pad fmts: yuv422, yuv420...... 31 * available mp source fmts: yuv, raw, jpeg(TODO) 32 * available sp source fmts: yuv, rgb 33 */ 34 35 #define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath" 36 #define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath" 37 38 #define RKISP1_MIN_BUFFERS_NEEDED 3 39 40 enum rkisp1_plane { 41 RKISP1_PLANE_Y = 0, 42 RKISP1_PLANE_CB = 1, 43 RKISP1_PLANE_CR = 2 44 }; 45 46 /* 47 * @fourcc: pixel format 48 * @fmt_type: helper filed for pixel format 49 * @uv_swap: if cb cr swapped, for yuv 50 * @write_format: defines how YCbCr self picture data is written to memory 51 * @output_format: defines sp output format 52 * @mbus: the mbus code on the src resizer pad that matches the pixel format 53 */ 54 struct rkisp1_capture_fmt_cfg { 55 u32 fourcc; 56 u8 uv_swap; 57 u32 write_format; 58 u32 output_format; 59 u32 mbus; 60 }; 61 62 struct rkisp1_capture_ops { 63 void (*config)(struct rkisp1_capture *cap); 64 void (*stop)(struct rkisp1_capture *cap); 65 void (*enable)(struct rkisp1_capture *cap); 66 void (*disable)(struct rkisp1_capture *cap); 67 void (*set_data_path)(struct rkisp1_capture *cap); 68 bool (*is_stopped)(struct rkisp1_capture *cap); 69 }; 70 71 struct rkisp1_capture_config { 72 const struct rkisp1_capture_fmt_cfg *fmts; 73 int fmt_size; 74 struct { 75 u32 y_size_init; 76 u32 cb_size_init; 77 u32 cr_size_init; 78 u32 y_base_ad_init; 79 u32 cb_base_ad_init; 80 u32 cr_base_ad_init; 81 u32 y_offs_cnt_init; 82 u32 cb_offs_cnt_init; 83 u32 cr_offs_cnt_init; 84 } mi; 85 }; 86 87 /* 88 * The supported pixel formats for mainpath. NOTE, pixel formats with identical 'mbus' 89 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 90 */ 91 static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = { 92 /* yuv422 */ 93 { 94 .fourcc = V4L2_PIX_FMT_YUYV, 95 .uv_swap = 0, 96 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT, 97 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 98 }, { 99 .fourcc = V4L2_PIX_FMT_YUV422P, 100 .uv_swap = 0, 101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 102 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 103 }, { 104 .fourcc = V4L2_PIX_FMT_NV16, 105 .uv_swap = 0, 106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 107 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 108 }, { 109 .fourcc = V4L2_PIX_FMT_NV61, 110 .uv_swap = 1, 111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 112 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 113 }, { 114 .fourcc = V4L2_PIX_FMT_YVU422M, 115 .uv_swap = 1, 116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 117 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 118 }, 119 /* yuv400 */ 120 { 121 .fourcc = V4L2_PIX_FMT_GREY, 122 .uv_swap = 0, 123 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 124 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 125 }, 126 /* yuv420 */ 127 { 128 .fourcc = V4L2_PIX_FMT_NV21, 129 .uv_swap = 1, 130 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 131 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 132 }, { 133 .fourcc = V4L2_PIX_FMT_NV12, 134 .uv_swap = 0, 135 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 136 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 137 }, { 138 .fourcc = V4L2_PIX_FMT_NV21M, 139 .uv_swap = 1, 140 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 141 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 142 }, { 143 .fourcc = V4L2_PIX_FMT_NV12M, 144 .uv_swap = 0, 145 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA, 146 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 147 }, { 148 .fourcc = V4L2_PIX_FMT_YUV420, 149 .uv_swap = 0, 150 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 151 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 152 }, { 153 .fourcc = V4L2_PIX_FMT_YVU420, 154 .uv_swap = 1, 155 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 156 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 157 }, 158 /* raw */ 159 { 160 .fourcc = V4L2_PIX_FMT_SRGGB8, 161 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 162 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8, 163 }, { 164 .fourcc = V4L2_PIX_FMT_SGRBG8, 165 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 166 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8, 167 }, { 168 .fourcc = V4L2_PIX_FMT_SGBRG8, 169 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 170 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8, 171 }, { 172 .fourcc = V4L2_PIX_FMT_SBGGR8, 173 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8, 174 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8, 175 }, { 176 .fourcc = V4L2_PIX_FMT_SRGGB10, 177 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 178 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10, 179 }, { 180 .fourcc = V4L2_PIX_FMT_SGRBG10, 181 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 182 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10, 183 }, { 184 .fourcc = V4L2_PIX_FMT_SGBRG10, 185 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 186 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10, 187 }, { 188 .fourcc = V4L2_PIX_FMT_SBGGR10, 189 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 190 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10, 191 }, { 192 .fourcc = V4L2_PIX_FMT_SRGGB12, 193 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 194 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12, 195 }, { 196 .fourcc = V4L2_PIX_FMT_SGRBG12, 197 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 198 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12, 199 }, { 200 .fourcc = V4L2_PIX_FMT_SGBRG12, 201 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 202 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12, 203 }, { 204 .fourcc = V4L2_PIX_FMT_SBGGR12, 205 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12, 206 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12, 207 }, 208 }; 209 210 /* 211 * The supported pixel formats for selfpath. NOTE, pixel formats with identical 'mbus' 212 * are grouped together. This is assumed and used by the function rkisp1_cap_enum_mbus_codes 213 */ 214 static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = { 215 /* yuv422 */ 216 { 217 .fourcc = V4L2_PIX_FMT_YUYV, 218 .uv_swap = 0, 219 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT, 220 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 221 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 222 }, { 223 .fourcc = V4L2_PIX_FMT_YUV422P, 224 .uv_swap = 0, 225 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 226 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 227 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 228 }, { 229 .fourcc = V4L2_PIX_FMT_NV16, 230 .uv_swap = 0, 231 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 232 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 233 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 234 }, { 235 .fourcc = V4L2_PIX_FMT_NV61, 236 .uv_swap = 1, 237 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 238 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 239 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 240 }, { 241 .fourcc = V4L2_PIX_FMT_YVU422M, 242 .uv_swap = 1, 243 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 244 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 245 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 246 }, 247 /* yuv400 */ 248 { 249 .fourcc = V4L2_PIX_FMT_GREY, 250 .uv_swap = 0, 251 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 252 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422, 253 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 254 }, 255 /* rgb */ 256 { 257 .fourcc = V4L2_PIX_FMT_XBGR32, 258 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 259 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888, 260 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 261 }, { 262 .fourcc = V4L2_PIX_FMT_RGB565, 263 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 264 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565, 265 .mbus = MEDIA_BUS_FMT_YUYV8_2X8, 266 }, 267 /* yuv420 */ 268 { 269 .fourcc = V4L2_PIX_FMT_NV21, 270 .uv_swap = 1, 271 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 272 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 273 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 274 }, { 275 .fourcc = V4L2_PIX_FMT_NV12, 276 .uv_swap = 0, 277 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 278 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 279 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 280 }, { 281 .fourcc = V4L2_PIX_FMT_NV21M, 282 .uv_swap = 1, 283 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 284 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 285 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 286 }, { 287 .fourcc = V4L2_PIX_FMT_NV12M, 288 .uv_swap = 0, 289 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA, 290 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 291 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 292 }, { 293 .fourcc = V4L2_PIX_FMT_YUV420, 294 .uv_swap = 0, 295 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 296 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 297 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 298 }, { 299 .fourcc = V4L2_PIX_FMT_YVU420, 300 .uv_swap = 1, 301 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA, 302 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420, 303 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8, 304 }, 305 }; 306 307 static const struct rkisp1_capture_config rkisp1_capture_config_mp = { 308 .fmts = rkisp1_mp_fmts, 309 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts), 310 .mi = { 311 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT, 312 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT, 313 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT, 314 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT, 315 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT, 316 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT, 317 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT, 318 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT, 319 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT, 320 }, 321 }; 322 323 static const struct rkisp1_capture_config rkisp1_capture_config_sp = { 324 .fmts = rkisp1_sp_fmts, 325 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts), 326 .mi = { 327 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT, 328 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT, 329 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT, 330 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT, 331 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT, 332 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT, 333 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT, 334 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT, 335 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT, 336 }, 337 }; 338 339 static inline struct rkisp1_vdev_node * 340 rkisp1_vdev_to_node(struct video_device *vdev) 341 { 342 return container_of(vdev, struct rkisp1_vdev_node, vdev); 343 } 344 345 int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap, 346 struct v4l2_subdev_mbus_code_enum *code) 347 { 348 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts; 349 /* 350 * initialize curr_mbus to non existing mbus code 0 to ensure it is 351 * different from fmts[0].mbus 352 */ 353 u32 curr_mbus = 0; 354 int i, n = 0; 355 356 for (i = 0; i < cap->config->fmt_size; i++) { 357 if (fmts[i].mbus == curr_mbus) 358 continue; 359 360 curr_mbus = fmts[i].mbus; 361 if (n++ == code->index) { 362 code->code = curr_mbus; 363 return 0; 364 } 365 } 366 return -EINVAL; 367 } 368 369 /* ---------------------------------------------------------------------------- 370 * Stream operations for self-picture path (sp) and main-picture path (mp) 371 */ 372 373 static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap) 374 { 375 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 376 377 mi_ctrl &= ~GENMASK(17, 16); 378 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64; 379 380 mi_ctrl &= ~GENMASK(19, 18); 381 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64; 382 383 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN | 384 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN; 385 386 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 387 } 388 389 static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm, 390 unsigned int component) 391 { 392 /* 393 * If packed format, then plane_fmt[0].sizeimage is the sum of all 394 * components, so we need to calculate just the size of Y component. 395 * See rkisp1_fill_pixfmt(). 396 */ 397 if (!component && pixm->num_planes == 1) 398 return pixm->plane_fmt[0].bytesperline * pixm->height; 399 return pixm->plane_fmt[component].sizeimage; 400 } 401 402 static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap) 403 { 404 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC); 405 406 mi_imsc |= RKISP1_CIF_MI_FRAME(cap); 407 rkisp1_write(cap->rkisp1, mi_imsc, RKISP1_CIF_MI_IMSC); 408 } 409 410 static void rkisp1_mp_config(struct rkisp1_capture *cap) 411 { 412 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 413 struct rkisp1_device *rkisp1 = cap->rkisp1; 414 u32 reg; 415 416 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 417 cap->config->mi.y_size_init); 418 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 419 cap->config->mi.cb_size_init); 420 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR), 421 cap->config->mi.cr_size_init); 422 423 rkisp1_irq_frame_end_enable(cap); 424 425 /* set uv swapping for semiplanar formats */ 426 if (cap->pix.info->comp_planes == 2) { 427 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 428 if (cap->pix.cfg->uv_swap) 429 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 430 else 431 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP; 432 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 433 } 434 435 rkisp1_mi_config_ctrl(cap); 436 437 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 438 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK; 439 reg |= cap->pix.cfg->write_format; 440 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL); 441 442 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 443 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE; 444 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL); 445 } 446 447 static void rkisp1_sp_config(struct rkisp1_capture *cap) 448 { 449 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 450 struct rkisp1_device *rkisp1 = cap->rkisp1; 451 u32 mi_ctrl, reg; 452 453 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 454 cap->config->mi.y_size_init); 455 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 456 cap->config->mi.cb_size_init); 457 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR), 458 cap->config->mi.cr_size_init); 459 460 rkisp1_write(rkisp1, pixm->width, RKISP1_CIF_MI_SP_Y_PIC_WIDTH); 461 rkisp1_write(rkisp1, pixm->height, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT); 462 rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH); 463 464 rkisp1_irq_frame_end_enable(cap); 465 466 /* set uv swapping for semiplanar formats */ 467 if (cap->pix.info->comp_planes == 2) { 468 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 469 if (cap->pix.cfg->uv_swap) 470 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 471 else 472 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP; 473 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL); 474 } 475 476 rkisp1_mi_config_ctrl(cap); 477 478 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL); 479 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK; 480 mi_ctrl |= cap->pix.cfg->write_format | 481 RKISP1_MI_CTRL_SP_INPUT_YUV422 | 482 cap->pix.cfg->output_format | 483 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE; 484 rkisp1_write(rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 485 } 486 487 static void rkisp1_mp_disable(struct rkisp1_capture *cap) 488 { 489 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 490 491 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE | 492 RKISP1_CIF_MI_CTRL_RAW_ENABLE); 493 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 494 } 495 496 static void rkisp1_sp_disable(struct rkisp1_capture *cap) 497 { 498 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 499 500 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE; 501 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 502 } 503 504 static void rkisp1_mp_enable(struct rkisp1_capture *cap) 505 { 506 u32 mi_ctrl; 507 508 rkisp1_mp_disable(cap); 509 510 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 511 if (v4l2_is_format_bayer(cap->pix.info)) 512 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE; 513 /* YUV */ 514 else 515 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE; 516 517 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 518 } 519 520 static void rkisp1_sp_enable(struct rkisp1_capture *cap) 521 { 522 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL); 523 524 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE; 525 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL); 526 } 527 528 static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap) 529 { 530 if (!cap->is_streaming) 531 return; 532 rkisp1_write(cap->rkisp1, 533 RKISP1_CIF_MI_FRAME(cap), RKISP1_CIF_MI_ICR); 534 cap->ops->disable(cap); 535 } 536 537 static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap) 538 { 539 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED | 540 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED; 541 542 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en); 543 } 544 545 static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap) 546 { 547 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & 548 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED); 549 } 550 551 static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap) 552 { 553 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 554 555 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP | 556 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI; 557 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 558 } 559 560 static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap) 561 { 562 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL); 563 564 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP; 565 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL); 566 } 567 568 static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = { 569 .config = rkisp1_mp_config, 570 .enable = rkisp1_mp_enable, 571 .disable = rkisp1_mp_disable, 572 .stop = rkisp1_mp_sp_stop, 573 .set_data_path = rkisp1_mp_set_data_path, 574 .is_stopped = rkisp1_mp_is_stopped, 575 }; 576 577 static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = { 578 .config = rkisp1_sp_config, 579 .enable = rkisp1_sp_enable, 580 .disable = rkisp1_sp_disable, 581 .stop = rkisp1_mp_sp_stop, 582 .set_data_path = rkisp1_sp_set_data_path, 583 .is_stopped = rkisp1_sp_is_stopped, 584 }; 585 586 /* ---------------------------------------------------------------------------- 587 * Frame buffer operations 588 */ 589 590 static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap) 591 { 592 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 593 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy; 594 595 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y), 596 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB), 597 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR)); 598 599 /* The driver never access vaddr, no mapping is required */ 600 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev, 601 dummy_buf->size, 602 &dummy_buf->dma_addr, 603 GFP_KERNEL, 604 DMA_ATTR_NO_KERNEL_MAPPING); 605 if (!dummy_buf->vaddr) 606 return -ENOMEM; 607 608 return 0; 609 } 610 611 static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap) 612 { 613 dma_free_attrs(cap->rkisp1->dev, 614 cap->buf.dummy.size, cap->buf.dummy.vaddr, 615 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING); 616 } 617 618 static void rkisp1_set_next_buf(struct rkisp1_capture *cap) 619 { 620 cap->buf.curr = cap->buf.next; 621 cap->buf.next = NULL; 622 623 if (!list_empty(&cap->buf.queue)) { 624 u32 *buff_addr; 625 626 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue); 627 list_del(&cap->buf.next->queue); 628 629 buff_addr = cap->buf.next->buff_addr; 630 631 rkisp1_write(cap->rkisp1, 632 buff_addr[RKISP1_PLANE_Y], 633 cap->config->mi.y_base_ad_init); 634 /* 635 * In order to support grey format we capture 636 * YUV422 planar format from the camera and 637 * set the U and V planes to the dummy buffer 638 */ 639 if (cap->pix.cfg->fourcc == V4L2_PIX_FMT_GREY) { 640 rkisp1_write(cap->rkisp1, 641 cap->buf.dummy.dma_addr, 642 cap->config->mi.cb_base_ad_init); 643 rkisp1_write(cap->rkisp1, 644 cap->buf.dummy.dma_addr, 645 cap->config->mi.cr_base_ad_init); 646 } else { 647 rkisp1_write(cap->rkisp1, 648 buff_addr[RKISP1_PLANE_CB], 649 cap->config->mi.cb_base_ad_init); 650 rkisp1_write(cap->rkisp1, 651 buff_addr[RKISP1_PLANE_CR], 652 cap->config->mi.cr_base_ad_init); 653 } 654 } else { 655 /* 656 * Use the dummy space allocated by dma_alloc_coherent to 657 * throw data if there is no available buffer. 658 */ 659 rkisp1_write(cap->rkisp1, 660 cap->buf.dummy.dma_addr, 661 cap->config->mi.y_base_ad_init); 662 rkisp1_write(cap->rkisp1, 663 cap->buf.dummy.dma_addr, 664 cap->config->mi.cb_base_ad_init); 665 rkisp1_write(cap->rkisp1, 666 cap->buf.dummy.dma_addr, 667 cap->config->mi.cr_base_ad_init); 668 } 669 670 /* Set plane offsets */ 671 rkisp1_write(cap->rkisp1, 0, cap->config->mi.y_offs_cnt_init); 672 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cb_offs_cnt_init); 673 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cr_offs_cnt_init); 674 } 675 676 /* 677 * This function is called when a frame end comes. The next frame 678 * is processing and we should set up buffer for next-next frame, 679 * otherwise it will overflow. 680 */ 681 static void rkisp1_handle_buffer(struct rkisp1_capture *cap) 682 { 683 struct rkisp1_isp *isp = &cap->rkisp1->isp; 684 struct rkisp1_buffer *curr_buf; 685 686 spin_lock(&cap->buf.lock); 687 curr_buf = cap->buf.curr; 688 689 if (curr_buf) { 690 curr_buf->vb.sequence = isp->frame_sequence; 691 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns(); 692 curr_buf->vb.field = V4L2_FIELD_NONE; 693 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE); 694 } else { 695 cap->rkisp1->debug.frame_drop[cap->id]++; 696 } 697 698 rkisp1_set_next_buf(cap); 699 spin_unlock(&cap->buf.lock); 700 } 701 702 irqreturn_t rkisp1_capture_isr(int irq, void *ctx) 703 { 704 struct device *dev = ctx; 705 struct rkisp1_device *rkisp1 = dev_get_drvdata(dev); 706 unsigned int i; 707 u32 status; 708 709 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS); 710 if (!status) 711 return IRQ_NONE; 712 713 rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR); 714 715 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) { 716 struct rkisp1_capture *cap = &rkisp1->capture_devs[i]; 717 718 if (!(status & RKISP1_CIF_MI_FRAME(cap))) 719 continue; 720 if (!cap->is_stopping) { 721 rkisp1_handle_buffer(cap); 722 continue; 723 } 724 /* 725 * Make sure stream is actually stopped, whose state 726 * can be read from the shadow register, before 727 * wake_up() thread which would immediately free all 728 * frame buffers. stop() takes effect at the next 729 * frame end that sync the configurations to shadow 730 * regs. 731 */ 732 if (!cap->ops->is_stopped(cap)) { 733 cap->ops->stop(cap); 734 continue; 735 } 736 cap->is_stopping = false; 737 cap->is_streaming = false; 738 wake_up(&cap->done); 739 } 740 741 return IRQ_HANDLED; 742 } 743 744 /* ---------------------------------------------------------------------------- 745 * Vb2 operations 746 */ 747 748 static int rkisp1_vb2_queue_setup(struct vb2_queue *queue, 749 unsigned int *num_buffers, 750 unsigned int *num_planes, 751 unsigned int sizes[], 752 struct device *alloc_devs[]) 753 { 754 struct rkisp1_capture *cap = queue->drv_priv; 755 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 756 unsigned int i; 757 758 if (*num_planes) { 759 if (*num_planes != pixm->num_planes) 760 return -EINVAL; 761 762 for (i = 0; i < pixm->num_planes; i++) 763 if (sizes[i] < pixm->plane_fmt[i].sizeimage) 764 return -EINVAL; 765 } else { 766 *num_planes = pixm->num_planes; 767 for (i = 0; i < pixm->num_planes; i++) 768 sizes[i] = pixm->plane_fmt[i].sizeimage; 769 } 770 771 return 0; 772 } 773 774 static int rkisp1_vb2_buf_init(struct vb2_buffer *vb) 775 { 776 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 777 struct rkisp1_buffer *ispbuf = 778 container_of(vbuf, struct rkisp1_buffer, vb); 779 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 780 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt; 781 unsigned int i; 782 783 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr)); 784 for (i = 0; i < pixm->num_planes; i++) 785 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i); 786 787 /* Convert to non-MPLANE */ 788 if (pixm->num_planes == 1) { 789 ispbuf->buff_addr[RKISP1_PLANE_CB] = 790 ispbuf->buff_addr[RKISP1_PLANE_Y] + 791 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y); 792 ispbuf->buff_addr[RKISP1_PLANE_CR] = 793 ispbuf->buff_addr[RKISP1_PLANE_CB] + 794 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB); 795 } 796 797 /* 798 * uv swap can be supported for planar formats by switching 799 * the address of cb and cr 800 */ 801 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap) 802 swap(ispbuf->buff_addr[RKISP1_PLANE_CR], 803 ispbuf->buff_addr[RKISP1_PLANE_CB]); 804 return 0; 805 } 806 807 static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb) 808 { 809 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 810 struct rkisp1_buffer *ispbuf = 811 container_of(vbuf, struct rkisp1_buffer, vb); 812 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 813 814 spin_lock_irq(&cap->buf.lock); 815 list_add_tail(&ispbuf->queue, &cap->buf.queue); 816 spin_unlock_irq(&cap->buf.lock); 817 } 818 819 static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb) 820 { 821 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv; 822 unsigned int i; 823 824 for (i = 0; i < cap->pix.fmt.num_planes; i++) { 825 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage; 826 827 if (vb2_plane_size(vb, i) < size) { 828 dev_err(cap->rkisp1->dev, 829 "User buffer too small (%ld < %ld)\n", 830 vb2_plane_size(vb, i), size); 831 return -EINVAL; 832 } 833 vb2_set_plane_payload(vb, i, size); 834 } 835 836 return 0; 837 } 838 839 static void rkisp1_return_all_buffers(struct rkisp1_capture *cap, 840 enum vb2_buffer_state state) 841 { 842 struct rkisp1_buffer *buf; 843 844 spin_lock_irq(&cap->buf.lock); 845 if (cap->buf.curr) { 846 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state); 847 cap->buf.curr = NULL; 848 } 849 if (cap->buf.next) { 850 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state); 851 cap->buf.next = NULL; 852 } 853 while (!list_empty(&cap->buf.queue)) { 854 buf = list_first_entry(&cap->buf.queue, 855 struct rkisp1_buffer, queue); 856 list_del(&buf->queue); 857 vb2_buffer_done(&buf->vb.vb2_buf, state); 858 } 859 spin_unlock_irq(&cap->buf.lock); 860 } 861 862 /* 863 * Most registers inside the rockchip ISP1 have shadow register since 864 * they must not be changed while processing a frame. 865 * Usually, each sub-module updates its shadow register after 866 * processing the last pixel of a frame. 867 */ 868 static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap) 869 { 870 struct rkisp1_device *rkisp1 = cap->rkisp1; 871 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1]; 872 873 cap->ops->set_data_path(cap); 874 cap->ops->config(cap); 875 876 /* Setup a buffer for the next frame */ 877 spin_lock_irq(&cap->buf.lock); 878 rkisp1_set_next_buf(cap); 879 cap->ops->enable(cap); 880 /* It's safe to configure ACTIVE and SHADOW registers for the 881 * first stream. While when the second is starting, do NOT 882 * force update because it also updates the first one. 883 * 884 * The latter case would drop one more buffer(that is 2) since 885 * there's no buffer in a shadow register when the second FE received. 886 * This's also required because the second FE maybe corrupt 887 * especially when run at 120fps. 888 */ 889 if (!other->is_streaming) { 890 /* force cfg update */ 891 rkisp1_write(rkisp1, 892 RKISP1_CIF_MI_INIT_SOFT_UPD, RKISP1_CIF_MI_INIT); 893 rkisp1_set_next_buf(cap); 894 } 895 spin_unlock_irq(&cap->buf.lock); 896 cap->is_streaming = true; 897 } 898 899 static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap) 900 { 901 int ret; 902 903 /* Stream should stop in interrupt. If it doesn't, stop it by force. */ 904 cap->is_stopping = true; 905 ret = wait_event_timeout(cap->done, 906 !cap->is_streaming, 907 msecs_to_jiffies(1000)); 908 if (!ret) { 909 cap->rkisp1->debug.stop_timeout[cap->id]++; 910 cap->ops->stop(cap); 911 cap->is_stopping = false; 912 cap->is_streaming = false; 913 } 914 } 915 916 /* 917 * rkisp1_pipeline_stream_disable - disable nodes in the pipeline 918 * 919 * Call s_stream(false) in the reverse order from 920 * rkisp1_pipeline_stream_enable() and disable the DMA engine. 921 * Should be called before media_pipeline_stop() 922 */ 923 static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap) 924 __must_hold(&cap->rkisp1->stream_lock) 925 { 926 struct rkisp1_device *rkisp1 = cap->rkisp1; 927 928 rkisp1_cap_stream_disable(cap); 929 930 /* 931 * If the other capture is streaming, isp and sensor nodes shouldn't 932 * be disabled, skip them. 933 */ 934 if (rkisp1->pipe.streaming_count < 2) { 935 v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream, 936 false); 937 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 938 } 939 940 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 941 false); 942 } 943 944 /* 945 * rkisp1_pipeline_stream_enable - enable nodes in the pipeline 946 * 947 * Enable the DMA Engine and call s_stream(true) through the pipeline. 948 * Should be called after media_pipeline_start() 949 */ 950 static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap) 951 __must_hold(&cap->rkisp1->stream_lock) 952 { 953 struct rkisp1_device *rkisp1 = cap->rkisp1; 954 int ret; 955 956 rkisp1_cap_stream_enable(cap); 957 958 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, 959 s_stream, true); 960 if (ret) 961 goto err_disable_cap; 962 963 /* 964 * If the other capture is streaming, isp and sensor nodes are already 965 * enabled, skip them. 966 */ 967 if (rkisp1->pipe.streaming_count > 1) 968 return 0; 969 970 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true); 971 if (ret) 972 goto err_disable_rsz; 973 974 ret = v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream, 975 true); 976 if (ret) 977 goto err_disable_isp; 978 979 return 0; 980 981 err_disable_isp: 982 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false); 983 err_disable_rsz: 984 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream, 985 false); 986 err_disable_cap: 987 rkisp1_cap_stream_disable(cap); 988 989 return ret; 990 } 991 992 static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue) 993 { 994 struct rkisp1_capture *cap = queue->drv_priv; 995 struct rkisp1_vdev_node *node = &cap->vnode; 996 struct rkisp1_device *rkisp1 = cap->rkisp1; 997 int ret; 998 999 mutex_lock(&cap->rkisp1->stream_lock); 1000 1001 rkisp1_pipeline_stream_disable(cap); 1002 1003 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR); 1004 1005 v4l2_pipeline_pm_put(&node->vdev.entity); 1006 ret = pm_runtime_put(rkisp1->dev); 1007 if (ret < 0) 1008 dev_err(rkisp1->dev, "power down failed error:%d\n", ret); 1009 1010 rkisp1_dummy_buf_destroy(cap); 1011 1012 media_pipeline_stop(&node->vdev.entity); 1013 1014 mutex_unlock(&cap->rkisp1->stream_lock); 1015 } 1016 1017 static int 1018 rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count) 1019 { 1020 struct rkisp1_capture *cap = queue->drv_priv; 1021 struct media_entity *entity = &cap->vnode.vdev.entity; 1022 int ret; 1023 1024 mutex_lock(&cap->rkisp1->stream_lock); 1025 1026 ret = media_pipeline_start(entity, &cap->rkisp1->pipe); 1027 if (ret) { 1028 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret); 1029 goto err_ret_buffers; 1030 } 1031 1032 ret = rkisp1_dummy_buf_create(cap); 1033 if (ret) 1034 goto err_pipeline_stop; 1035 1036 ret = pm_runtime_resume_and_get(cap->rkisp1->dev); 1037 if (ret < 0) { 1038 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret); 1039 goto err_destroy_dummy; 1040 } 1041 ret = v4l2_pipeline_pm_get(entity); 1042 if (ret) { 1043 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret); 1044 goto err_pipe_pm_put; 1045 } 1046 1047 ret = rkisp1_pipeline_stream_enable(cap); 1048 if (ret) 1049 goto err_v4l2_pm_put; 1050 1051 mutex_unlock(&cap->rkisp1->stream_lock); 1052 1053 return 0; 1054 1055 err_v4l2_pm_put: 1056 v4l2_pipeline_pm_put(entity); 1057 err_pipe_pm_put: 1058 pm_runtime_put(cap->rkisp1->dev); 1059 err_destroy_dummy: 1060 rkisp1_dummy_buf_destroy(cap); 1061 err_pipeline_stop: 1062 media_pipeline_stop(entity); 1063 err_ret_buffers: 1064 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED); 1065 mutex_unlock(&cap->rkisp1->stream_lock); 1066 1067 return ret; 1068 } 1069 1070 static const struct vb2_ops rkisp1_vb2_ops = { 1071 .queue_setup = rkisp1_vb2_queue_setup, 1072 .buf_init = rkisp1_vb2_buf_init, 1073 .buf_queue = rkisp1_vb2_buf_queue, 1074 .buf_prepare = rkisp1_vb2_buf_prepare, 1075 .wait_prepare = vb2_ops_wait_prepare, 1076 .wait_finish = vb2_ops_wait_finish, 1077 .stop_streaming = rkisp1_vb2_stop_streaming, 1078 .start_streaming = rkisp1_vb2_start_streaming, 1079 }; 1080 1081 /* ---------------------------------------------------------------------------- 1082 * IOCTLs operations 1083 */ 1084 1085 static const struct v4l2_format_info * 1086 rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm, 1087 enum rkisp1_stream_id id) 1088 { 1089 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0]; 1090 const struct v4l2_format_info *info; 1091 unsigned int i; 1092 u32 stride; 1093 1094 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt)); 1095 info = v4l2_format_info(pixm->pixelformat); 1096 pixm->num_planes = info->mem_planes; 1097 stride = info->bpp[0] * pixm->width; 1098 /* Self path supports custom stride but Main path doesn't */ 1099 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride) 1100 plane_y->bytesperline = stride; 1101 plane_y->sizeimage = plane_y->bytesperline * pixm->height; 1102 1103 /* normalize stride to pixels per line */ 1104 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]); 1105 1106 for (i = 1; i < info->comp_planes; i++) { 1107 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i]; 1108 1109 /* bytesperline for other components derive from Y component */ 1110 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) * 1111 info->bpp[i]; 1112 plane->sizeimage = plane->bytesperline * 1113 DIV_ROUND_UP(pixm->height, info->vdiv); 1114 } 1115 1116 /* 1117 * If pixfmt is packed, then plane_fmt[0] should contain the total size 1118 * considering all components. plane_fmt[i] for i > 0 should be ignored 1119 * by userspace as mem_planes == 1, but we are keeping information there 1120 * for convenience. 1121 */ 1122 if (info->mem_planes == 1) 1123 for (i = 1; i < info->comp_planes; i++) 1124 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage; 1125 1126 return info; 1127 } 1128 1129 static const struct rkisp1_capture_fmt_cfg * 1130 rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt) 1131 { 1132 unsigned int i; 1133 1134 for (i = 0; i < cap->config->fmt_size; i++) { 1135 if (cap->config->fmts[i].fourcc == pixelfmt) 1136 return &cap->config->fmts[i]; 1137 } 1138 return NULL; 1139 } 1140 1141 static void rkisp1_try_fmt(const struct rkisp1_capture *cap, 1142 struct v4l2_pix_format_mplane *pixm, 1143 const struct rkisp1_capture_fmt_cfg **fmt_cfg, 1144 const struct v4l2_format_info **fmt_info) 1145 { 1146 const struct rkisp1_capture_config *config = cap->config; 1147 const struct rkisp1_capture_fmt_cfg *fmt; 1148 const struct v4l2_format_info *info; 1149 const unsigned int max_widths[] = { RKISP1_RSZ_MP_SRC_MAX_WIDTH, 1150 RKISP1_RSZ_SP_SRC_MAX_WIDTH }; 1151 const unsigned int max_heights[] = { RKISP1_RSZ_MP_SRC_MAX_HEIGHT, 1152 RKISP1_RSZ_SP_SRC_MAX_HEIGHT}; 1153 1154 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat); 1155 if (!fmt) { 1156 fmt = config->fmts; 1157 pixm->pixelformat = fmt->fourcc; 1158 } 1159 1160 pixm->width = clamp_t(u32, pixm->width, 1161 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]); 1162 pixm->height = clamp_t(u32, pixm->height, 1163 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]); 1164 1165 pixm->field = V4L2_FIELD_NONE; 1166 pixm->colorspace = V4L2_COLORSPACE_DEFAULT; 1167 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1168 pixm->quantization = V4L2_QUANTIZATION_DEFAULT; 1169 1170 info = rkisp1_fill_pixfmt(pixm, cap->id); 1171 1172 if (fmt_cfg) 1173 *fmt_cfg = fmt; 1174 if (fmt_info) 1175 *fmt_info = info; 1176 } 1177 1178 static void rkisp1_set_fmt(struct rkisp1_capture *cap, 1179 struct v4l2_pix_format_mplane *pixm) 1180 { 1181 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info); 1182 cap->pix.fmt = *pixm; 1183 1184 /* SP supports custom stride in number of pixels of the Y plane */ 1185 if (cap->id == RKISP1_SELFPATH) 1186 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline / 1187 cap->pix.info->bpp[0]; 1188 } 1189 1190 static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh, 1191 struct v4l2_format *f) 1192 { 1193 struct rkisp1_capture *cap = video_drvdata(file); 1194 1195 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL); 1196 1197 return 0; 1198 } 1199 1200 static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv, 1201 struct v4l2_fmtdesc *f) 1202 { 1203 struct rkisp1_capture *cap = video_drvdata(file); 1204 const struct rkisp1_capture_fmt_cfg *fmt = NULL; 1205 unsigned int i, n = 0; 1206 1207 if (!f->mbus_code) { 1208 if (f->index >= cap->config->fmt_size) 1209 return -EINVAL; 1210 1211 fmt = &cap->config->fmts[f->index]; 1212 f->pixelformat = fmt->fourcc; 1213 return 0; 1214 } 1215 1216 for (i = 0; i < cap->config->fmt_size; i++) { 1217 if (cap->config->fmts[i].mbus != f->mbus_code) 1218 continue; 1219 1220 if (n++ == f->index) { 1221 f->pixelformat = cap->config->fmts[i].fourcc; 1222 return 0; 1223 } 1224 } 1225 return -EINVAL; 1226 } 1227 1228 static int rkisp1_s_fmt_vid_cap_mplane(struct file *file, 1229 void *priv, struct v4l2_format *f) 1230 { 1231 struct rkisp1_capture *cap = video_drvdata(file); 1232 struct rkisp1_vdev_node *node = 1233 rkisp1_vdev_to_node(&cap->vnode.vdev); 1234 1235 if (vb2_is_busy(&node->buf_queue)) 1236 return -EBUSY; 1237 1238 rkisp1_set_fmt(cap, &f->fmt.pix_mp); 1239 1240 return 0; 1241 } 1242 1243 static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh, 1244 struct v4l2_format *f) 1245 { 1246 struct rkisp1_capture *cap = video_drvdata(file); 1247 1248 f->fmt.pix_mp = cap->pix.fmt; 1249 1250 return 0; 1251 } 1252 1253 static int 1254 rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 1255 { 1256 struct rkisp1_capture *cap_dev = video_drvdata(file); 1257 struct rkisp1_device *rkisp1 = cap_dev->rkisp1; 1258 1259 strscpy(cap->driver, rkisp1->dev->driver->name, sizeof(cap->driver)); 1260 strscpy(cap->card, rkisp1->dev->driver->name, sizeof(cap->card)); 1261 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info)); 1262 1263 return 0; 1264 } 1265 1266 static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = { 1267 .vidioc_reqbufs = vb2_ioctl_reqbufs, 1268 .vidioc_querybuf = vb2_ioctl_querybuf, 1269 .vidioc_create_bufs = vb2_ioctl_create_bufs, 1270 .vidioc_qbuf = vb2_ioctl_qbuf, 1271 .vidioc_expbuf = vb2_ioctl_expbuf, 1272 .vidioc_dqbuf = vb2_ioctl_dqbuf, 1273 .vidioc_prepare_buf = vb2_ioctl_prepare_buf, 1274 .vidioc_streamon = vb2_ioctl_streamon, 1275 .vidioc_streamoff = vb2_ioctl_streamoff, 1276 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane, 1277 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane, 1278 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane, 1279 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane, 1280 .vidioc_querycap = rkisp1_querycap, 1281 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1282 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1283 }; 1284 1285 static int rkisp1_capture_link_validate(struct media_link *link) 1286 { 1287 struct video_device *vdev = 1288 media_entity_to_video_device(link->sink->entity); 1289 struct v4l2_subdev *sd = 1290 media_entity_to_v4l2_subdev(link->source->entity); 1291 struct rkisp1_capture *cap = video_get_drvdata(vdev); 1292 const struct rkisp1_capture_fmt_cfg *fmt = 1293 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat); 1294 struct v4l2_subdev_format sd_fmt; 1295 int ret; 1296 1297 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; 1298 sd_fmt.pad = link->source->index; 1299 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt); 1300 if (ret) 1301 return ret; 1302 1303 if (sd_fmt.format.height != cap->pix.fmt.height || 1304 sd_fmt.format.width != cap->pix.fmt.width || 1305 sd_fmt.format.code != fmt->mbus) 1306 return -EPIPE; 1307 1308 return 0; 1309 } 1310 1311 /* ---------------------------------------------------------------------------- 1312 * core functions 1313 */ 1314 1315 static const struct media_entity_operations rkisp1_media_ops = { 1316 .link_validate = rkisp1_capture_link_validate, 1317 }; 1318 1319 static const struct v4l2_file_operations rkisp1_fops = { 1320 .open = v4l2_fh_open, 1321 .release = vb2_fop_release, 1322 .unlocked_ioctl = video_ioctl2, 1323 .poll = vb2_fop_poll, 1324 .mmap = vb2_fop_mmap, 1325 }; 1326 1327 static void rkisp1_unregister_capture(struct rkisp1_capture *cap) 1328 { 1329 media_entity_cleanup(&cap->vnode.vdev.entity); 1330 vb2_video_unregister_device(&cap->vnode.vdev); 1331 } 1332 1333 void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1) 1334 { 1335 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH]; 1336 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH]; 1337 1338 rkisp1_unregister_capture(mp); 1339 rkisp1_unregister_capture(sp); 1340 } 1341 1342 static int rkisp1_register_capture(struct rkisp1_capture *cap) 1343 { 1344 const char * const dev_names[] = {RKISP1_MP_DEV_NAME, 1345 RKISP1_SP_DEV_NAME}; 1346 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev; 1347 struct video_device *vdev = &cap->vnode.vdev; 1348 struct rkisp1_vdev_node *node; 1349 struct vb2_queue *q; 1350 int ret; 1351 1352 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name)); 1353 node = rkisp1_vdev_to_node(vdev); 1354 mutex_init(&node->vlock); 1355 1356 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops; 1357 vdev->release = video_device_release_empty; 1358 vdev->fops = &rkisp1_fops; 1359 vdev->minor = -1; 1360 vdev->v4l2_dev = v4l2_dev; 1361 vdev->lock = &node->vlock; 1362 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE | 1363 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC; 1364 vdev->entity.ops = &rkisp1_media_ops; 1365 video_set_drvdata(vdev, cap); 1366 vdev->vfl_dir = VFL_DIR_RX; 1367 node->pad.flags = MEDIA_PAD_FL_SINK; 1368 1369 q = &node->buf_queue; 1370 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1371 q->io_modes = VB2_MMAP | VB2_DMABUF; 1372 q->drv_priv = cap; 1373 q->ops = &rkisp1_vb2_ops; 1374 q->mem_ops = &vb2_dma_contig_memops; 1375 q->buf_struct_size = sizeof(struct rkisp1_buffer); 1376 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED; 1377 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; 1378 q->lock = &node->vlock; 1379 q->dev = cap->rkisp1->dev; 1380 ret = vb2_queue_init(q); 1381 if (ret) { 1382 dev_err(cap->rkisp1->dev, 1383 "vb2 queue init failed (err=%d)\n", ret); 1384 return ret; 1385 } 1386 1387 vdev->queue = q; 1388 1389 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1); 1390 if (ret) { 1391 dev_err(cap->rkisp1->dev, 1392 "failed to register %s, ret=%d\n", vdev->name, ret); 1393 return ret; 1394 } 1395 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name, 1396 vdev->num); 1397 1398 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad); 1399 if (ret) { 1400 video_unregister_device(vdev); 1401 return ret; 1402 } 1403 1404 return 0; 1405 } 1406 1407 static void 1408 rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id) 1409 { 1410 struct rkisp1_capture *cap = &rkisp1->capture_devs[id]; 1411 struct v4l2_pix_format_mplane pixm; 1412 1413 memset(cap, 0, sizeof(*cap)); 1414 cap->id = id; 1415 cap->rkisp1 = rkisp1; 1416 1417 INIT_LIST_HEAD(&cap->buf.queue); 1418 init_waitqueue_head(&cap->done); 1419 spin_lock_init(&cap->buf.lock); 1420 if (cap->id == RKISP1_SELFPATH) { 1421 cap->ops = &rkisp1_capture_ops_sp; 1422 cap->config = &rkisp1_capture_config_sp; 1423 } else { 1424 cap->ops = &rkisp1_capture_ops_mp; 1425 cap->config = &rkisp1_capture_config_mp; 1426 } 1427 1428 cap->is_streaming = false; 1429 1430 memset(&pixm, 0, sizeof(pixm)); 1431 pixm.pixelformat = V4L2_PIX_FMT_YUYV; 1432 pixm.width = RKISP1_DEFAULT_WIDTH; 1433 pixm.height = RKISP1_DEFAULT_HEIGHT; 1434 rkisp1_set_fmt(cap, &pixm); 1435 } 1436 1437 int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1) 1438 { 1439 struct rkisp1_capture *cap; 1440 unsigned int i, j; 1441 int ret; 1442 1443 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) { 1444 rkisp1_capture_init(rkisp1, i); 1445 cap = &rkisp1->capture_devs[i]; 1446 cap->rkisp1 = rkisp1; 1447 ret = rkisp1_register_capture(cap); 1448 if (ret) 1449 goto err_unreg_capture_devs; 1450 } 1451 1452 return 0; 1453 1454 err_unreg_capture_devs: 1455 for (j = 0; j < i; j++) { 1456 cap = &rkisp1->capture_devs[j]; 1457 rkisp1_unregister_capture(cap); 1458 } 1459 1460 return ret; 1461 } 1462