1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: Jacob Chen <jacob-chen@iotwrt.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/fs.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/timer.h> 19 20 #include <linux/platform_device.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-event.h> 23 #include <media/v4l2-ioctl.h> 24 #include <media/v4l2-mem2mem.h> 25 #include <media/videobuf2-dma-sg.h> 26 #include <media/videobuf2-v4l2.h> 27 28 #include "rga-hw.h" 29 #include "rga.h" 30 31 static int debug; 32 module_param(debug, int, 0644); 33 34 static void device_run(void *prv) 35 { 36 struct rga_ctx *ctx = prv; 37 struct rockchip_rga *rga = ctx->rga; 38 struct vb2_v4l2_buffer *src, *dst; 39 unsigned long flags; 40 41 spin_lock_irqsave(&rga->ctrl_lock, flags); 42 43 rga->curr = ctx; 44 45 src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 46 dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 47 48 rga_buf_map(&src->vb2_buf); 49 rga_buf_map(&dst->vb2_buf); 50 51 rga_hw_start(rga); 52 53 spin_unlock_irqrestore(&rga->ctrl_lock, flags); 54 } 55 56 static irqreturn_t rga_isr(int irq, void *prv) 57 { 58 struct rockchip_rga *rga = prv; 59 int intr; 60 61 intr = rga_read(rga, RGA_INT) & 0xf; 62 63 rga_mod(rga, RGA_INT, intr << 4, 0xf << 4); 64 65 if (intr & 0x04) { 66 struct vb2_v4l2_buffer *src, *dst; 67 struct rga_ctx *ctx = rga->curr; 68 69 WARN_ON(!ctx); 70 71 rga->curr = NULL; 72 73 src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 74 dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 75 76 WARN_ON(!src); 77 WARN_ON(!dst); 78 79 v4l2_m2m_buf_copy_metadata(src, dst, true); 80 81 v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE); 82 v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE); 83 v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx); 84 } 85 86 return IRQ_HANDLED; 87 } 88 89 static const struct v4l2_m2m_ops rga_m2m_ops = { 90 .device_run = device_run, 91 }; 92 93 static int 94 queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq) 95 { 96 struct rga_ctx *ctx = priv; 97 int ret; 98 99 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT; 100 src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 101 src_vq->drv_priv = ctx; 102 src_vq->ops = &rga_qops; 103 src_vq->mem_ops = &vb2_dma_sg_memops; 104 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 105 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 106 src_vq->lock = &ctx->rga->mutex; 107 src_vq->dev = ctx->rga->v4l2_dev.dev; 108 109 ret = vb2_queue_init(src_vq); 110 if (ret) 111 return ret; 112 113 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; 114 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 115 dst_vq->drv_priv = ctx; 116 dst_vq->ops = &rga_qops; 117 dst_vq->mem_ops = &vb2_dma_sg_memops; 118 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer); 119 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 120 dst_vq->lock = &ctx->rga->mutex; 121 dst_vq->dev = ctx->rga->v4l2_dev.dev; 122 123 return vb2_queue_init(dst_vq); 124 } 125 126 static int rga_s_ctrl(struct v4l2_ctrl *ctrl) 127 { 128 struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx, 129 ctrl_handler); 130 unsigned long flags; 131 132 spin_lock_irqsave(&ctx->rga->ctrl_lock, flags); 133 switch (ctrl->id) { 134 case V4L2_CID_HFLIP: 135 ctx->hflip = ctrl->val; 136 break; 137 case V4L2_CID_VFLIP: 138 ctx->vflip = ctrl->val; 139 break; 140 case V4L2_CID_ROTATE: 141 ctx->rotate = ctrl->val; 142 break; 143 case V4L2_CID_BG_COLOR: 144 ctx->fill_color = ctrl->val; 145 break; 146 } 147 spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags); 148 return 0; 149 } 150 151 static const struct v4l2_ctrl_ops rga_ctrl_ops = { 152 .s_ctrl = rga_s_ctrl, 153 }; 154 155 static int rga_setup_ctrls(struct rga_ctx *ctx) 156 { 157 struct rockchip_rga *rga = ctx->rga; 158 159 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4); 160 161 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 162 V4L2_CID_HFLIP, 0, 1, 1, 0); 163 164 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 165 V4L2_CID_VFLIP, 0, 1, 1, 0); 166 167 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 168 V4L2_CID_ROTATE, 0, 270, 90, 0); 169 170 v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops, 171 V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0); 172 173 if (ctx->ctrl_handler.error) { 174 int err = ctx->ctrl_handler.error; 175 176 v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__); 177 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 178 return err; 179 } 180 181 return 0; 182 } 183 184 static struct rga_fmt formats[] = { 185 { 186 .fourcc = V4L2_PIX_FMT_ARGB32, 187 .color_swap = RGA_COLOR_ALPHA_SWAP, 188 .hw_format = RGA_COLOR_FMT_ABGR8888, 189 .depth = 32, 190 .uv_factor = 1, 191 .y_div = 1, 192 .x_div = 1, 193 }, 194 { 195 .fourcc = V4L2_PIX_FMT_ABGR32, 196 .color_swap = RGA_COLOR_RB_SWAP, 197 .hw_format = RGA_COLOR_FMT_ABGR8888, 198 .depth = 32, 199 .uv_factor = 1, 200 .y_div = 1, 201 .x_div = 1, 202 }, 203 { 204 .fourcc = V4L2_PIX_FMT_XBGR32, 205 .color_swap = RGA_COLOR_RB_SWAP, 206 .hw_format = RGA_COLOR_FMT_XBGR8888, 207 .depth = 32, 208 .uv_factor = 1, 209 .y_div = 1, 210 .x_div = 1, 211 }, 212 { 213 .fourcc = V4L2_PIX_FMT_RGB24, 214 .color_swap = RGA_COLOR_NONE_SWAP, 215 .hw_format = RGA_COLOR_FMT_RGB888, 216 .depth = 24, 217 .uv_factor = 1, 218 .y_div = 1, 219 .x_div = 1, 220 }, 221 { 222 .fourcc = V4L2_PIX_FMT_BGR24, 223 .color_swap = RGA_COLOR_RB_SWAP, 224 .hw_format = RGA_COLOR_FMT_RGB888, 225 .depth = 24, 226 .uv_factor = 1, 227 .y_div = 1, 228 .x_div = 1, 229 }, 230 { 231 .fourcc = V4L2_PIX_FMT_ARGB444, 232 .color_swap = RGA_COLOR_RB_SWAP, 233 .hw_format = RGA_COLOR_FMT_ABGR4444, 234 .depth = 16, 235 .uv_factor = 1, 236 .y_div = 1, 237 .x_div = 1, 238 }, 239 { 240 .fourcc = V4L2_PIX_FMT_ARGB555, 241 .color_swap = RGA_COLOR_RB_SWAP, 242 .hw_format = RGA_COLOR_FMT_ABGR1555, 243 .depth = 16, 244 .uv_factor = 1, 245 .y_div = 1, 246 .x_div = 1, 247 }, 248 { 249 .fourcc = V4L2_PIX_FMT_RGB565, 250 .color_swap = RGA_COLOR_RB_SWAP, 251 .hw_format = RGA_COLOR_FMT_BGR565, 252 .depth = 16, 253 .uv_factor = 1, 254 .y_div = 1, 255 .x_div = 1, 256 }, 257 { 258 .fourcc = V4L2_PIX_FMT_NV21, 259 .color_swap = RGA_COLOR_UV_SWAP, 260 .hw_format = RGA_COLOR_FMT_YUV420SP, 261 .depth = 12, 262 .uv_factor = 4, 263 .y_div = 2, 264 .x_div = 1, 265 }, 266 { 267 .fourcc = V4L2_PIX_FMT_NV61, 268 .color_swap = RGA_COLOR_UV_SWAP, 269 .hw_format = RGA_COLOR_FMT_YUV422SP, 270 .depth = 16, 271 .uv_factor = 2, 272 .y_div = 1, 273 .x_div = 1, 274 }, 275 { 276 .fourcc = V4L2_PIX_FMT_NV12, 277 .color_swap = RGA_COLOR_NONE_SWAP, 278 .hw_format = RGA_COLOR_FMT_YUV420SP, 279 .depth = 12, 280 .uv_factor = 4, 281 .y_div = 2, 282 .x_div = 1, 283 }, 284 { 285 .fourcc = V4L2_PIX_FMT_NV16, 286 .color_swap = RGA_COLOR_NONE_SWAP, 287 .hw_format = RGA_COLOR_FMT_YUV422SP, 288 .depth = 16, 289 .uv_factor = 2, 290 .y_div = 1, 291 .x_div = 1, 292 }, 293 { 294 .fourcc = V4L2_PIX_FMT_YUV420, 295 .color_swap = RGA_COLOR_NONE_SWAP, 296 .hw_format = RGA_COLOR_FMT_YUV420P, 297 .depth = 12, 298 .uv_factor = 4, 299 .y_div = 2, 300 .x_div = 2, 301 }, 302 { 303 .fourcc = V4L2_PIX_FMT_YUV422P, 304 .color_swap = RGA_COLOR_NONE_SWAP, 305 .hw_format = RGA_COLOR_FMT_YUV422P, 306 .depth = 16, 307 .uv_factor = 2, 308 .y_div = 1, 309 .x_div = 2, 310 }, 311 { 312 .fourcc = V4L2_PIX_FMT_YVU420, 313 .color_swap = RGA_COLOR_UV_SWAP, 314 .hw_format = RGA_COLOR_FMT_YUV420P, 315 .depth = 12, 316 .uv_factor = 4, 317 .y_div = 2, 318 .x_div = 2, 319 }, 320 }; 321 322 #define NUM_FORMATS ARRAY_SIZE(formats) 323 324 static struct rga_fmt *rga_fmt_find(struct v4l2_format *f) 325 { 326 unsigned int i; 327 328 for (i = 0; i < NUM_FORMATS; i++) { 329 if (formats[i].fourcc == f->fmt.pix.pixelformat) 330 return &formats[i]; 331 } 332 return NULL; 333 } 334 335 static struct rga_frame def_frame = { 336 .width = DEFAULT_WIDTH, 337 .height = DEFAULT_HEIGHT, 338 .colorspace = V4L2_COLORSPACE_DEFAULT, 339 .crop.left = 0, 340 .crop.top = 0, 341 .crop.width = DEFAULT_WIDTH, 342 .crop.height = DEFAULT_HEIGHT, 343 .fmt = &formats[0], 344 }; 345 346 struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type) 347 { 348 switch (type) { 349 case V4L2_BUF_TYPE_VIDEO_OUTPUT: 350 return &ctx->in; 351 case V4L2_BUF_TYPE_VIDEO_CAPTURE: 352 return &ctx->out; 353 default: 354 return ERR_PTR(-EINVAL); 355 } 356 } 357 358 static int rga_open(struct file *file) 359 { 360 struct rockchip_rga *rga = video_drvdata(file); 361 struct rga_ctx *ctx = NULL; 362 int ret = 0; 363 364 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 365 if (!ctx) 366 return -ENOMEM; 367 ctx->rga = rga; 368 /* Set default formats */ 369 ctx->in = def_frame; 370 ctx->out = def_frame; 371 372 if (mutex_lock_interruptible(&rga->mutex)) { 373 kfree(ctx); 374 return -ERESTARTSYS; 375 } 376 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init); 377 if (IS_ERR(ctx->fh.m2m_ctx)) { 378 ret = PTR_ERR(ctx->fh.m2m_ctx); 379 mutex_unlock(&rga->mutex); 380 kfree(ctx); 381 return ret; 382 } 383 v4l2_fh_init(&ctx->fh, video_devdata(file)); 384 file->private_data = &ctx->fh; 385 v4l2_fh_add(&ctx->fh); 386 387 rga_setup_ctrls(ctx); 388 389 /* Write the default values to the ctx struct */ 390 v4l2_ctrl_handler_setup(&ctx->ctrl_handler); 391 392 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 393 mutex_unlock(&rga->mutex); 394 395 return 0; 396 } 397 398 static int rga_release(struct file *file) 399 { 400 struct rga_ctx *ctx = 401 container_of(file->private_data, struct rga_ctx, fh); 402 struct rockchip_rga *rga = ctx->rga; 403 404 mutex_lock(&rga->mutex); 405 406 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 407 408 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 409 v4l2_fh_del(&ctx->fh); 410 v4l2_fh_exit(&ctx->fh); 411 kfree(ctx); 412 413 mutex_unlock(&rga->mutex); 414 415 return 0; 416 } 417 418 static const struct v4l2_file_operations rga_fops = { 419 .owner = THIS_MODULE, 420 .open = rga_open, 421 .release = rga_release, 422 .poll = v4l2_m2m_fop_poll, 423 .unlocked_ioctl = video_ioctl2, 424 .mmap = v4l2_m2m_fop_mmap, 425 }; 426 427 static int 428 vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap) 429 { 430 strscpy(cap->driver, RGA_NAME, sizeof(cap->driver)); 431 strscpy(cap->card, "rockchip-rga", sizeof(cap->card)); 432 strscpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info)); 433 434 return 0; 435 } 436 437 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f) 438 { 439 struct rga_fmt *fmt; 440 441 if (f->index >= NUM_FORMATS) 442 return -EINVAL; 443 444 fmt = &formats[f->index]; 445 f->pixelformat = fmt->fourcc; 446 447 return 0; 448 } 449 450 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f) 451 { 452 struct rga_ctx *ctx = prv; 453 struct vb2_queue *vq; 454 struct rga_frame *frm; 455 456 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 457 if (!vq) 458 return -EINVAL; 459 frm = rga_get_frame(ctx, f->type); 460 if (IS_ERR(frm)) 461 return PTR_ERR(frm); 462 463 f->fmt.pix.width = frm->width; 464 f->fmt.pix.height = frm->height; 465 f->fmt.pix.field = V4L2_FIELD_NONE; 466 f->fmt.pix.pixelformat = frm->fmt->fourcc; 467 f->fmt.pix.bytesperline = frm->stride; 468 f->fmt.pix.sizeimage = frm->size; 469 f->fmt.pix.colorspace = frm->colorspace; 470 471 return 0; 472 } 473 474 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f) 475 { 476 struct rga_fmt *fmt; 477 478 fmt = rga_fmt_find(f); 479 if (!fmt) { 480 fmt = &formats[0]; 481 f->fmt.pix.pixelformat = fmt->fourcc; 482 } 483 484 f->fmt.pix.field = V4L2_FIELD_NONE; 485 486 if (f->fmt.pix.width > MAX_WIDTH) 487 f->fmt.pix.width = MAX_WIDTH; 488 if (f->fmt.pix.height > MAX_HEIGHT) 489 f->fmt.pix.height = MAX_HEIGHT; 490 491 if (f->fmt.pix.width < MIN_WIDTH) 492 f->fmt.pix.width = MIN_WIDTH; 493 if (f->fmt.pix.height < MIN_HEIGHT) 494 f->fmt.pix.height = MIN_HEIGHT; 495 496 if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) 497 f->fmt.pix.bytesperline = f->fmt.pix.width; 498 else 499 f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; 500 501 f->fmt.pix.sizeimage = 502 f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3; 503 504 return 0; 505 } 506 507 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f) 508 { 509 struct rga_ctx *ctx = prv; 510 struct rockchip_rga *rga = ctx->rga; 511 struct vb2_queue *vq; 512 struct rga_frame *frm; 513 struct rga_fmt *fmt; 514 int ret = 0; 515 516 /* Adjust all values accordingly to the hardware capabilities 517 * and chosen format. 518 */ 519 ret = vidioc_try_fmt(file, prv, f); 520 if (ret) 521 return ret; 522 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type); 523 if (vb2_is_busy(vq)) { 524 v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type); 525 return -EBUSY; 526 } 527 frm = rga_get_frame(ctx, f->type); 528 if (IS_ERR(frm)) 529 return PTR_ERR(frm); 530 fmt = rga_fmt_find(f); 531 if (!fmt) 532 return -EINVAL; 533 frm->width = f->fmt.pix.width; 534 frm->height = f->fmt.pix.height; 535 frm->size = f->fmt.pix.sizeimage; 536 frm->fmt = fmt; 537 frm->stride = f->fmt.pix.bytesperline; 538 frm->colorspace = f->fmt.pix.colorspace; 539 540 /* Reset crop settings */ 541 frm->crop.left = 0; 542 frm->crop.top = 0; 543 frm->crop.width = frm->width; 544 frm->crop.height = frm->height; 545 546 return 0; 547 } 548 549 static int vidioc_g_selection(struct file *file, void *prv, 550 struct v4l2_selection *s) 551 { 552 struct rga_ctx *ctx = prv; 553 struct rga_frame *f; 554 bool use_frame = false; 555 556 f = rga_get_frame(ctx, s->type); 557 if (IS_ERR(f)) 558 return PTR_ERR(f); 559 560 switch (s->target) { 561 case V4L2_SEL_TGT_COMPOSE_DEFAULT: 562 case V4L2_SEL_TGT_COMPOSE_BOUNDS: 563 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 564 return -EINVAL; 565 break; 566 case V4L2_SEL_TGT_CROP_DEFAULT: 567 case V4L2_SEL_TGT_CROP_BOUNDS: 568 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 569 return -EINVAL; 570 break; 571 case V4L2_SEL_TGT_COMPOSE: 572 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 573 return -EINVAL; 574 use_frame = true; 575 break; 576 case V4L2_SEL_TGT_CROP: 577 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 578 return -EINVAL; 579 use_frame = true; 580 break; 581 default: 582 return -EINVAL; 583 } 584 585 if (use_frame) { 586 s->r = f->crop; 587 } else { 588 s->r.left = 0; 589 s->r.top = 0; 590 s->r.width = f->width; 591 s->r.height = f->height; 592 } 593 594 return 0; 595 } 596 597 static int vidioc_s_selection(struct file *file, void *prv, 598 struct v4l2_selection *s) 599 { 600 struct rga_ctx *ctx = prv; 601 struct rockchip_rga *rga = ctx->rga; 602 struct rga_frame *f; 603 int ret = 0; 604 605 f = rga_get_frame(ctx, s->type); 606 if (IS_ERR(f)) 607 return PTR_ERR(f); 608 609 switch (s->target) { 610 case V4L2_SEL_TGT_COMPOSE: 611 /* 612 * COMPOSE target is only valid for capture buffer type, return 613 * error for output buffer type 614 */ 615 if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 616 return -EINVAL; 617 break; 618 case V4L2_SEL_TGT_CROP: 619 /* 620 * CROP target is only valid for output buffer type, return 621 * error for capture buffer type 622 */ 623 if (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) 624 return -EINVAL; 625 break; 626 /* 627 * bound and default crop/compose targets are invalid targets to 628 * try/set 629 */ 630 default: 631 return -EINVAL; 632 } 633 634 if (s->r.top < 0 || s->r.left < 0) { 635 v4l2_dbg(debug, 1, &rga->v4l2_dev, 636 "doesn't support negative values for top & left.\n"); 637 return -EINVAL; 638 } 639 640 if (s->r.left + s->r.width > f->width || 641 s->r.top + s->r.height > f->height || 642 s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) { 643 v4l2_dbg(debug, 1, &rga->v4l2_dev, "unsupported crop value.\n"); 644 return -EINVAL; 645 } 646 647 f->crop = s->r; 648 649 return ret; 650 } 651 652 static const struct v4l2_ioctl_ops rga_ioctl_ops = { 653 .vidioc_querycap = vidioc_querycap, 654 655 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt, 656 .vidioc_g_fmt_vid_cap = vidioc_g_fmt, 657 .vidioc_try_fmt_vid_cap = vidioc_try_fmt, 658 .vidioc_s_fmt_vid_cap = vidioc_s_fmt, 659 660 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt, 661 .vidioc_g_fmt_vid_out = vidioc_g_fmt, 662 .vidioc_try_fmt_vid_out = vidioc_try_fmt, 663 .vidioc_s_fmt_vid_out = vidioc_s_fmt, 664 665 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 666 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 667 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 668 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 669 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 670 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 671 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 672 673 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 674 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 675 676 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 677 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 678 679 .vidioc_g_selection = vidioc_g_selection, 680 .vidioc_s_selection = vidioc_s_selection, 681 }; 682 683 static const struct video_device rga_videodev = { 684 .name = "rockchip-rga", 685 .fops = &rga_fops, 686 .ioctl_ops = &rga_ioctl_ops, 687 .minor = -1, 688 .release = video_device_release, 689 .vfl_dir = VFL_DIR_M2M, 690 .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING, 691 }; 692 693 static int rga_enable_clocks(struct rockchip_rga *rga) 694 { 695 int ret; 696 697 ret = clk_prepare_enable(rga->sclk); 698 if (ret) { 699 dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret); 700 return ret; 701 } 702 703 ret = clk_prepare_enable(rga->aclk); 704 if (ret) { 705 dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret); 706 goto err_disable_sclk; 707 } 708 709 ret = clk_prepare_enable(rga->hclk); 710 if (ret) { 711 dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret); 712 goto err_disable_aclk; 713 } 714 715 return 0; 716 717 err_disable_aclk: 718 clk_disable_unprepare(rga->aclk); 719 err_disable_sclk: 720 clk_disable_unprepare(rga->sclk); 721 722 return ret; 723 } 724 725 static void rga_disable_clocks(struct rockchip_rga *rga) 726 { 727 clk_disable_unprepare(rga->sclk); 728 clk_disable_unprepare(rga->hclk); 729 clk_disable_unprepare(rga->aclk); 730 } 731 732 static int rga_parse_dt(struct rockchip_rga *rga) 733 { 734 struct reset_control *core_rst, *axi_rst, *ahb_rst; 735 736 core_rst = devm_reset_control_get(rga->dev, "core"); 737 if (IS_ERR(core_rst)) { 738 dev_err(rga->dev, "failed to get core reset controller\n"); 739 return PTR_ERR(core_rst); 740 } 741 742 axi_rst = devm_reset_control_get(rga->dev, "axi"); 743 if (IS_ERR(axi_rst)) { 744 dev_err(rga->dev, "failed to get axi reset controller\n"); 745 return PTR_ERR(axi_rst); 746 } 747 748 ahb_rst = devm_reset_control_get(rga->dev, "ahb"); 749 if (IS_ERR(ahb_rst)) { 750 dev_err(rga->dev, "failed to get ahb reset controller\n"); 751 return PTR_ERR(ahb_rst); 752 } 753 754 reset_control_assert(core_rst); 755 udelay(1); 756 reset_control_deassert(core_rst); 757 758 reset_control_assert(axi_rst); 759 udelay(1); 760 reset_control_deassert(axi_rst); 761 762 reset_control_assert(ahb_rst); 763 udelay(1); 764 reset_control_deassert(ahb_rst); 765 766 rga->sclk = devm_clk_get(rga->dev, "sclk"); 767 if (IS_ERR(rga->sclk)) { 768 dev_err(rga->dev, "failed to get sclk clock\n"); 769 return PTR_ERR(rga->sclk); 770 } 771 772 rga->aclk = devm_clk_get(rga->dev, "aclk"); 773 if (IS_ERR(rga->aclk)) { 774 dev_err(rga->dev, "failed to get aclk clock\n"); 775 return PTR_ERR(rga->aclk); 776 } 777 778 rga->hclk = devm_clk_get(rga->dev, "hclk"); 779 if (IS_ERR(rga->hclk)) { 780 dev_err(rga->dev, "failed to get hclk clock\n"); 781 return PTR_ERR(rga->hclk); 782 } 783 784 return 0; 785 } 786 787 static int rga_probe(struct platform_device *pdev) 788 { 789 struct rockchip_rga *rga; 790 struct video_device *vfd; 791 int ret = 0; 792 int irq; 793 794 if (!pdev->dev.of_node) 795 return -ENODEV; 796 797 rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL); 798 if (!rga) 799 return -ENOMEM; 800 801 rga->dev = &pdev->dev; 802 spin_lock_init(&rga->ctrl_lock); 803 mutex_init(&rga->mutex); 804 805 ret = rga_parse_dt(rga); 806 if (ret) 807 return dev_err_probe(&pdev->dev, ret, "Unable to parse OF data\n"); 808 809 pm_runtime_enable(rga->dev); 810 811 rga->regs = devm_platform_ioremap_resource(pdev, 0); 812 if (IS_ERR(rga->regs)) { 813 ret = PTR_ERR(rga->regs); 814 goto err_put_clk; 815 } 816 817 irq = platform_get_irq(pdev, 0); 818 if (irq < 0) { 819 ret = irq; 820 goto err_put_clk; 821 } 822 823 ret = devm_request_irq(rga->dev, irq, rga_isr, 0, 824 dev_name(rga->dev), rga); 825 if (ret < 0) { 826 dev_err(rga->dev, "failed to request irq\n"); 827 goto err_put_clk; 828 } 829 830 ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev); 831 if (ret) 832 goto err_put_clk; 833 vfd = video_device_alloc(); 834 if (!vfd) { 835 v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n"); 836 ret = -ENOMEM; 837 goto unreg_v4l2_dev; 838 } 839 *vfd = rga_videodev; 840 vfd->lock = &rga->mutex; 841 vfd->v4l2_dev = &rga->v4l2_dev; 842 843 video_set_drvdata(vfd, rga); 844 rga->vfd = vfd; 845 846 platform_set_drvdata(pdev, rga); 847 rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops); 848 if (IS_ERR(rga->m2m_dev)) { 849 v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n"); 850 ret = PTR_ERR(rga->m2m_dev); 851 goto rel_vdev; 852 } 853 854 ret = pm_runtime_resume_and_get(rga->dev); 855 if (ret < 0) 856 goto rel_m2m; 857 858 rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF; 859 rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F; 860 861 v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n", 862 rga->version.major, rga->version.minor); 863 864 pm_runtime_put(rga->dev); 865 866 /* Create CMD buffer */ 867 rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE, 868 &rga->cmdbuf_phy, GFP_KERNEL, 869 DMA_ATTR_WRITE_COMBINE); 870 if (!rga->cmdbuf_virt) { 871 ret = -ENOMEM; 872 goto rel_m2m; 873 } 874 875 rga->src_mmu_pages = 876 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3); 877 if (!rga->src_mmu_pages) { 878 ret = -ENOMEM; 879 goto free_dma; 880 } 881 rga->dst_mmu_pages = 882 (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3); 883 if (!rga->dst_mmu_pages) { 884 ret = -ENOMEM; 885 goto free_src_pages; 886 } 887 888 def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3; 889 def_frame.size = def_frame.stride * def_frame.height; 890 891 ret = video_register_device(vfd, VFL_TYPE_VIDEO, -1); 892 if (ret) { 893 v4l2_err(&rga->v4l2_dev, "Failed to register video device\n"); 894 goto free_dst_pages; 895 } 896 897 v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n", 898 vfd->name, video_device_node_name(vfd)); 899 900 return 0; 901 902 free_dst_pages: 903 free_pages((unsigned long)rga->dst_mmu_pages, 3); 904 free_src_pages: 905 free_pages((unsigned long)rga->src_mmu_pages, 3); 906 free_dma: 907 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt, 908 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE); 909 rel_m2m: 910 v4l2_m2m_release(rga->m2m_dev); 911 rel_vdev: 912 video_device_release(vfd); 913 unreg_v4l2_dev: 914 v4l2_device_unregister(&rga->v4l2_dev); 915 err_put_clk: 916 pm_runtime_disable(rga->dev); 917 918 return ret; 919 } 920 921 static void rga_remove(struct platform_device *pdev) 922 { 923 struct rockchip_rga *rga = platform_get_drvdata(pdev); 924 925 dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, rga->cmdbuf_virt, 926 rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE); 927 928 free_pages((unsigned long)rga->src_mmu_pages, 3); 929 free_pages((unsigned long)rga->dst_mmu_pages, 3); 930 931 v4l2_info(&rga->v4l2_dev, "Removing\n"); 932 933 v4l2_m2m_release(rga->m2m_dev); 934 video_unregister_device(rga->vfd); 935 v4l2_device_unregister(&rga->v4l2_dev); 936 937 pm_runtime_disable(rga->dev); 938 } 939 940 static int __maybe_unused rga_runtime_suspend(struct device *dev) 941 { 942 struct rockchip_rga *rga = dev_get_drvdata(dev); 943 944 rga_disable_clocks(rga); 945 946 return 0; 947 } 948 949 static int __maybe_unused rga_runtime_resume(struct device *dev) 950 { 951 struct rockchip_rga *rga = dev_get_drvdata(dev); 952 953 return rga_enable_clocks(rga); 954 } 955 956 static const struct dev_pm_ops rga_pm = { 957 SET_RUNTIME_PM_OPS(rga_runtime_suspend, 958 rga_runtime_resume, NULL) 959 }; 960 961 static const struct of_device_id rockchip_rga_match[] = { 962 { 963 .compatible = "rockchip,rk3288-rga", 964 }, 965 { 966 .compatible = "rockchip,rk3399-rga", 967 }, 968 {}, 969 }; 970 971 MODULE_DEVICE_TABLE(of, rockchip_rga_match); 972 973 static struct platform_driver rga_pdrv = { 974 .probe = rga_probe, 975 .remove_new = rga_remove, 976 .driver = { 977 .name = RGA_NAME, 978 .pm = &rga_pm, 979 .of_match_table = rockchip_rga_match, 980 }, 981 }; 982 983 module_platform_driver(rga_pdrv); 984 985 MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>"); 986 MODULE_DESCRIPTION("Rockchip Raster 2d Graphic Acceleration Unit"); 987 MODULE_LICENSE("GPL"); 988