1ee4a77a3SMauro Carvalho Chehab // SPDX-License-Identifier: GPL-2.0+
2ee4a77a3SMauro Carvalho Chehab /*
3ee4a77a3SMauro Carvalho Chehab * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface
4ee4a77a3SMauro Carvalho Chehab *
5ee4a77a3SMauro Carvalho Chehab * Copyright (C) 2015 Renesas Electronics Corporation
6ee4a77a3SMauro Carvalho Chehab *
7ee4a77a3SMauro Carvalho Chehab * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8ee4a77a3SMauro Carvalho Chehab */
9ee4a77a3SMauro Carvalho Chehab
10ee4a77a3SMauro Carvalho Chehab #include <linux/device.h>
11ee4a77a3SMauro Carvalho Chehab #include <linux/dma-mapping.h>
12ee4a77a3SMauro Carvalho Chehab #include <linux/slab.h>
13ee4a77a3SMauro Carvalho Chehab
14ee4a77a3SMauro Carvalho Chehab #include <media/media-entity.h>
15ee4a77a3SMauro Carvalho Chehab #include <media/v4l2-subdev.h>
16ee4a77a3SMauro Carvalho Chehab #include <media/vsp1.h>
17ee4a77a3SMauro Carvalho Chehab
18ee4a77a3SMauro Carvalho Chehab #include "vsp1.h"
19ee4a77a3SMauro Carvalho Chehab #include "vsp1_brx.h"
20ee4a77a3SMauro Carvalho Chehab #include "vsp1_dl.h"
21ee4a77a3SMauro Carvalho Chehab #include "vsp1_drm.h"
22ee4a77a3SMauro Carvalho Chehab #include "vsp1_lif.h"
23ee4a77a3SMauro Carvalho Chehab #include "vsp1_pipe.h"
24ee4a77a3SMauro Carvalho Chehab #include "vsp1_rwpf.h"
25ee4a77a3SMauro Carvalho Chehab #include "vsp1_uif.h"
26ee4a77a3SMauro Carvalho Chehab
27ee4a77a3SMauro Carvalho Chehab #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
28ee4a77a3SMauro Carvalho Chehab
29ee4a77a3SMauro Carvalho Chehab /* -----------------------------------------------------------------------------
30ee4a77a3SMauro Carvalho Chehab * Interrupt Handling
31ee4a77a3SMauro Carvalho Chehab */
32ee4a77a3SMauro Carvalho Chehab
vsp1_du_pipeline_frame_end(struct vsp1_pipeline * pipe,unsigned int completion)33ee4a77a3SMauro Carvalho Chehab static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
34ee4a77a3SMauro Carvalho Chehab unsigned int completion)
35ee4a77a3SMauro Carvalho Chehab {
36ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
37ee4a77a3SMauro Carvalho Chehab
38ee4a77a3SMauro Carvalho Chehab if (drm_pipe->du_complete) {
39ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *uif = drm_pipe->uif;
40ee4a77a3SMauro Carvalho Chehab unsigned int status = completion
41ee4a77a3SMauro Carvalho Chehab & (VSP1_DU_STATUS_COMPLETE |
42ee4a77a3SMauro Carvalho Chehab VSP1_DU_STATUS_WRITEBACK);
43ee4a77a3SMauro Carvalho Chehab u32 crc;
44ee4a77a3SMauro Carvalho Chehab
45ee4a77a3SMauro Carvalho Chehab crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;
46ee4a77a3SMauro Carvalho Chehab drm_pipe->du_complete(drm_pipe->du_private, status, crc);
47ee4a77a3SMauro Carvalho Chehab }
48ee4a77a3SMauro Carvalho Chehab
49ee4a77a3SMauro Carvalho Chehab if (completion & VSP1_DL_FRAME_END_INTERNAL) {
50ee4a77a3SMauro Carvalho Chehab drm_pipe->force_brx_release = false;
51ee4a77a3SMauro Carvalho Chehab wake_up(&drm_pipe->wait_queue);
52ee4a77a3SMauro Carvalho Chehab }
53ee4a77a3SMauro Carvalho Chehab }
54ee4a77a3SMauro Carvalho Chehab
55ee4a77a3SMauro Carvalho Chehab /* -----------------------------------------------------------------------------
56ee4a77a3SMauro Carvalho Chehab * Pipeline Configuration
57ee4a77a3SMauro Carvalho Chehab */
58ee4a77a3SMauro Carvalho Chehab
59ee4a77a3SMauro Carvalho Chehab /*
60ee4a77a3SMauro Carvalho Chehab * Insert the UIF in the pipeline between the prev and next entities. If no UIF
61ee4a77a3SMauro Carvalho Chehab * is available connect the two entities directly.
62ee4a77a3SMauro Carvalho Chehab */
vsp1_du_insert_uif(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_entity * uif,struct vsp1_entity * prev,unsigned int prev_pad,struct vsp1_entity * next,unsigned int next_pad)63ee4a77a3SMauro Carvalho Chehab static int vsp1_du_insert_uif(struct vsp1_device *vsp1,
64ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe,
65ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *uif,
66ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *prev, unsigned int prev_pad,
67ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *next, unsigned int next_pad)
68ee4a77a3SMauro Carvalho Chehab {
69e3a69496SLaurent Pinchart struct v4l2_subdev_format format = {
70e3a69496SLaurent Pinchart .which = V4L2_SUBDEV_FORMAT_ACTIVE,
71e3a69496SLaurent Pinchart };
72ee4a77a3SMauro Carvalho Chehab int ret;
73ee4a77a3SMauro Carvalho Chehab
74ee4a77a3SMauro Carvalho Chehab if (!uif) {
75ee4a77a3SMauro Carvalho Chehab /*
76ee4a77a3SMauro Carvalho Chehab * If there's no UIF to be inserted, connect the previous and
77ee4a77a3SMauro Carvalho Chehab * next entities directly.
78ee4a77a3SMauro Carvalho Chehab */
79ee4a77a3SMauro Carvalho Chehab prev->sink = next;
80ee4a77a3SMauro Carvalho Chehab prev->sink_pad = next_pad;
81ee4a77a3SMauro Carvalho Chehab return 0;
82ee4a77a3SMauro Carvalho Chehab }
83ee4a77a3SMauro Carvalho Chehab
84ee4a77a3SMauro Carvalho Chehab prev->sink = uif;
85ee4a77a3SMauro Carvalho Chehab prev->sink_pad = UIF_PAD_SINK;
86ee4a77a3SMauro Carvalho Chehab
87ee4a77a3SMauro Carvalho Chehab format.pad = prev_pad;
88ee4a77a3SMauro Carvalho Chehab
89ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format);
90ee4a77a3SMauro Carvalho Chehab if (ret < 0)
91ee4a77a3SMauro Carvalho Chehab return ret;
92ee4a77a3SMauro Carvalho Chehab
93ee4a77a3SMauro Carvalho Chehab format.pad = UIF_PAD_SINK;
94ee4a77a3SMauro Carvalho Chehab
95ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format);
96ee4a77a3SMauro Carvalho Chehab if (ret < 0)
97ee4a77a3SMauro Carvalho Chehab return ret;
98ee4a77a3SMauro Carvalho Chehab
99ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n",
100ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
101ee4a77a3SMauro Carvalho Chehab format.format.code);
102ee4a77a3SMauro Carvalho Chehab
103ee4a77a3SMauro Carvalho Chehab /*
104ee4a77a3SMauro Carvalho Chehab * The UIF doesn't mangle the format between its sink and source pads,
105ee4a77a3SMauro Carvalho Chehab * so there is no need to retrieve the format on its source pad.
106ee4a77a3SMauro Carvalho Chehab */
107ee4a77a3SMauro Carvalho Chehab
108ee4a77a3SMauro Carvalho Chehab uif->sink = next;
109ee4a77a3SMauro Carvalho Chehab uif->sink_pad = next_pad;
110ee4a77a3SMauro Carvalho Chehab
111ee4a77a3SMauro Carvalho Chehab return 0;
112ee4a77a3SMauro Carvalho Chehab }
113ee4a77a3SMauro Carvalho Chehab
114ee4a77a3SMauro Carvalho Chehab /* Setup one RPF and the connected BRx sink pad. */
vsp1_du_pipeline_setup_rpf(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_rwpf * rpf,struct vsp1_entity * uif,unsigned int brx_input)115ee4a77a3SMauro Carvalho Chehab static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
116ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe,
117ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *rpf,
118ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *uif,
119ee4a77a3SMauro Carvalho Chehab unsigned int brx_input)
120ee4a77a3SMauro Carvalho Chehab {
121e3a69496SLaurent Pinchart struct v4l2_subdev_selection sel = {
122e3a69496SLaurent Pinchart .which = V4L2_SUBDEV_FORMAT_ACTIVE,
123e3a69496SLaurent Pinchart };
124e3a69496SLaurent Pinchart struct v4l2_subdev_format format = {
125e3a69496SLaurent Pinchart .which = V4L2_SUBDEV_FORMAT_ACTIVE,
126e3a69496SLaurent Pinchart };
127ee4a77a3SMauro Carvalho Chehab const struct v4l2_rect *crop;
128ee4a77a3SMauro Carvalho Chehab int ret;
129ee4a77a3SMauro Carvalho Chehab
130ee4a77a3SMauro Carvalho Chehab /*
131ee4a77a3SMauro Carvalho Chehab * Configure the format on the RPF sink pad and propagate it up to the
132ee4a77a3SMauro Carvalho Chehab * BRx sink pad.
133ee4a77a3SMauro Carvalho Chehab */
134ee4a77a3SMauro Carvalho Chehab crop = &vsp1->drm->inputs[rpf->entity.index].crop;
135ee4a77a3SMauro Carvalho Chehab
136ee4a77a3SMauro Carvalho Chehab format.pad = RWPF_PAD_SINK;
137ee4a77a3SMauro Carvalho Chehab format.format.width = crop->width + crop->left;
138ee4a77a3SMauro Carvalho Chehab format.format.height = crop->height + crop->top;
139ee4a77a3SMauro Carvalho Chehab format.format.code = rpf->fmtinfo->mbus;
140ee4a77a3SMauro Carvalho Chehab format.format.field = V4L2_FIELD_NONE;
141ee4a77a3SMauro Carvalho Chehab
142ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
143ee4a77a3SMauro Carvalho Chehab &format);
144ee4a77a3SMauro Carvalho Chehab if (ret < 0)
145ee4a77a3SMauro Carvalho Chehab return ret;
146ee4a77a3SMauro Carvalho Chehab
147ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev,
148ee4a77a3SMauro Carvalho Chehab "%s: set format %ux%u (%x) on RPF%u sink\n",
149ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
150ee4a77a3SMauro Carvalho Chehab format.format.code, rpf->entity.index);
151ee4a77a3SMauro Carvalho Chehab
152ee4a77a3SMauro Carvalho Chehab sel.pad = RWPF_PAD_SINK;
153ee4a77a3SMauro Carvalho Chehab sel.target = V4L2_SEL_TGT_CROP;
154ee4a77a3SMauro Carvalho Chehab sel.r = *crop;
155ee4a77a3SMauro Carvalho Chehab
156ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
157ee4a77a3SMauro Carvalho Chehab &sel);
158ee4a77a3SMauro Carvalho Chehab if (ret < 0)
159ee4a77a3SMauro Carvalho Chehab return ret;
160ee4a77a3SMauro Carvalho Chehab
161ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev,
162ee4a77a3SMauro Carvalho Chehab "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
163ee4a77a3SMauro Carvalho Chehab __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
164ee4a77a3SMauro Carvalho Chehab rpf->entity.index);
165ee4a77a3SMauro Carvalho Chehab
166ee4a77a3SMauro Carvalho Chehab /*
167ee4a77a3SMauro Carvalho Chehab * RPF source, hardcode the format to ARGB8888 to turn on format
168ee4a77a3SMauro Carvalho Chehab * conversion if needed.
169ee4a77a3SMauro Carvalho Chehab */
170ee4a77a3SMauro Carvalho Chehab format.pad = RWPF_PAD_SOURCE;
171ee4a77a3SMauro Carvalho Chehab
172ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
173ee4a77a3SMauro Carvalho Chehab &format);
174ee4a77a3SMauro Carvalho Chehab if (ret < 0)
175ee4a77a3SMauro Carvalho Chehab return ret;
176ee4a77a3SMauro Carvalho Chehab
177ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev,
178ee4a77a3SMauro Carvalho Chehab "%s: got format %ux%u (%x) on RPF%u source\n",
179ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
180ee4a77a3SMauro Carvalho Chehab format.format.code, rpf->entity.index);
181ee4a77a3SMauro Carvalho Chehab
182ee4a77a3SMauro Carvalho Chehab format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
183ee4a77a3SMauro Carvalho Chehab
184ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
185ee4a77a3SMauro Carvalho Chehab &format);
186ee4a77a3SMauro Carvalho Chehab if (ret < 0)
187ee4a77a3SMauro Carvalho Chehab return ret;
188ee4a77a3SMauro Carvalho Chehab
189ee4a77a3SMauro Carvalho Chehab /* Insert and configure the UIF if available. */
190ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
191ee4a77a3SMauro Carvalho Chehab pipe->brx, brx_input);
192ee4a77a3SMauro Carvalho Chehab if (ret < 0)
193ee4a77a3SMauro Carvalho Chehab return ret;
194ee4a77a3SMauro Carvalho Chehab
195ee4a77a3SMauro Carvalho Chehab /* BRx sink, propagate the format from the RPF source. */
196ee4a77a3SMauro Carvalho Chehab format.pad = brx_input;
197ee4a77a3SMauro Carvalho Chehab
198ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
199ee4a77a3SMauro Carvalho Chehab &format);
200ee4a77a3SMauro Carvalho Chehab if (ret < 0)
201ee4a77a3SMauro Carvalho Chehab return ret;
202ee4a77a3SMauro Carvalho Chehab
203ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
204ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
205ee4a77a3SMauro Carvalho Chehab format.format.code, BRX_NAME(pipe->brx), format.pad);
206ee4a77a3SMauro Carvalho Chehab
207ee4a77a3SMauro Carvalho Chehab sel.pad = brx_input;
208ee4a77a3SMauro Carvalho Chehab sel.target = V4L2_SEL_TGT_COMPOSE;
209ee4a77a3SMauro Carvalho Chehab sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
210ee4a77a3SMauro Carvalho Chehab
211ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
212ee4a77a3SMauro Carvalho Chehab &sel);
213ee4a77a3SMauro Carvalho Chehab if (ret < 0)
214ee4a77a3SMauro Carvalho Chehab return ret;
215ee4a77a3SMauro Carvalho Chehab
216ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
217ee4a77a3SMauro Carvalho Chehab __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
218ee4a77a3SMauro Carvalho Chehab BRX_NAME(pipe->brx), sel.pad);
219ee4a77a3SMauro Carvalho Chehab
220ee4a77a3SMauro Carvalho Chehab return 0;
221ee4a77a3SMauro Carvalho Chehab }
222ee4a77a3SMauro Carvalho Chehab
223ee4a77a3SMauro Carvalho Chehab /* Setup the BRx source pad. */
224ee4a77a3SMauro Carvalho Chehab static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
225ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe);
226ee4a77a3SMauro Carvalho Chehab static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
227ee4a77a3SMauro Carvalho Chehab
vsp1_du_pipeline_setup_brx(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)228ee4a77a3SMauro Carvalho Chehab static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,
229ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe)
230ee4a77a3SMauro Carvalho Chehab {
231ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
232ee4a77a3SMauro Carvalho Chehab struct v4l2_subdev_format format = {
233ee4a77a3SMauro Carvalho Chehab .which = V4L2_SUBDEV_FORMAT_ACTIVE,
234ee4a77a3SMauro Carvalho Chehab };
235ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *brx;
236ee4a77a3SMauro Carvalho Chehab int ret;
237ee4a77a3SMauro Carvalho Chehab
238ee4a77a3SMauro Carvalho Chehab /*
239ee4a77a3SMauro Carvalho Chehab * Pick a BRx:
240ee4a77a3SMauro Carvalho Chehab * - If we need more than two inputs, use the BRU.
241ee4a77a3SMauro Carvalho Chehab * - Otherwise, if we are not forced to release our BRx, keep it.
242ee4a77a3SMauro Carvalho Chehab * - Else, use any free BRx (randomly starting with the BRU).
243ee4a77a3SMauro Carvalho Chehab */
244ee4a77a3SMauro Carvalho Chehab if (pipe->num_inputs > 2)
245ee4a77a3SMauro Carvalho Chehab brx = &vsp1->bru->entity;
246ee4a77a3SMauro Carvalho Chehab else if (pipe->brx && !drm_pipe->force_brx_release)
247ee4a77a3SMauro Carvalho Chehab brx = pipe->brx;
248ee4a77a3SMauro Carvalho Chehab else if (vsp1_feature(vsp1, VSP1_HAS_BRU) && !vsp1->bru->entity.pipe)
249ee4a77a3SMauro Carvalho Chehab brx = &vsp1->bru->entity;
250ee4a77a3SMauro Carvalho Chehab else
251ee4a77a3SMauro Carvalho Chehab brx = &vsp1->brs->entity;
252ee4a77a3SMauro Carvalho Chehab
253ee4a77a3SMauro Carvalho Chehab /* Switch BRx if needed. */
254ee4a77a3SMauro Carvalho Chehab if (brx != pipe->brx) {
255ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *released_brx = NULL;
256ee4a77a3SMauro Carvalho Chehab
257ee4a77a3SMauro Carvalho Chehab /* Release our BRx if we have one. */
258ee4a77a3SMauro Carvalho Chehab if (pipe->brx) {
259ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
260ee4a77a3SMauro Carvalho Chehab __func__, pipe->lif->index,
261ee4a77a3SMauro Carvalho Chehab BRX_NAME(pipe->brx));
262ee4a77a3SMauro Carvalho Chehab
263ee4a77a3SMauro Carvalho Chehab /*
264ee4a77a3SMauro Carvalho Chehab * The BRx might be acquired by the other pipeline in
265ee4a77a3SMauro Carvalho Chehab * the next step. We must thus remove it from the list
266ee4a77a3SMauro Carvalho Chehab * of entities for this pipeline. The other pipeline's
267ee4a77a3SMauro Carvalho Chehab * hardware configuration will reconfigure the BRx
268ee4a77a3SMauro Carvalho Chehab * routing.
269ee4a77a3SMauro Carvalho Chehab *
270ee4a77a3SMauro Carvalho Chehab * However, if the other pipeline doesn't acquire our
271ee4a77a3SMauro Carvalho Chehab * BRx, we need to keep it in the list, otherwise the
272ee4a77a3SMauro Carvalho Chehab * hardware configuration step won't disconnect it from
273ee4a77a3SMauro Carvalho Chehab * the pipeline. To solve this, store the released BRx
274ee4a77a3SMauro Carvalho Chehab * pointer to add it back to the list of entities later
275ee4a77a3SMauro Carvalho Chehab * if it isn't acquired by the other pipeline.
276ee4a77a3SMauro Carvalho Chehab */
277ee4a77a3SMauro Carvalho Chehab released_brx = pipe->brx;
278ee4a77a3SMauro Carvalho Chehab
279ee4a77a3SMauro Carvalho Chehab list_del(&pipe->brx->list_pipe);
280ee4a77a3SMauro Carvalho Chehab pipe->brx->sink = NULL;
281ee4a77a3SMauro Carvalho Chehab pipe->brx->pipe = NULL;
282ee4a77a3SMauro Carvalho Chehab pipe->brx = NULL;
283ee4a77a3SMauro Carvalho Chehab }
284ee4a77a3SMauro Carvalho Chehab
285ee4a77a3SMauro Carvalho Chehab /*
286ee4a77a3SMauro Carvalho Chehab * If the BRx we need is in use, force the owner pipeline to
287ee4a77a3SMauro Carvalho Chehab * switch to the other BRx and wait until the switch completes.
288ee4a77a3SMauro Carvalho Chehab */
289ee4a77a3SMauro Carvalho Chehab if (brx->pipe) {
290ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *owner_pipe;
291ee4a77a3SMauro Carvalho Chehab
292ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
293ee4a77a3SMauro Carvalho Chehab __func__, pipe->lif->index, BRX_NAME(brx));
294ee4a77a3SMauro Carvalho Chehab
295ee4a77a3SMauro Carvalho Chehab owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
296ee4a77a3SMauro Carvalho Chehab owner_pipe->force_brx_release = true;
297ee4a77a3SMauro Carvalho Chehab
298ee4a77a3SMauro Carvalho Chehab vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
299ee4a77a3SMauro Carvalho Chehab vsp1_du_pipeline_configure(&owner_pipe->pipe);
300ee4a77a3SMauro Carvalho Chehab
301ee4a77a3SMauro Carvalho Chehab ret = wait_event_timeout(owner_pipe->wait_queue,
302ee4a77a3SMauro Carvalho Chehab !owner_pipe->force_brx_release,
303ee4a77a3SMauro Carvalho Chehab msecs_to_jiffies(500));
304ee4a77a3SMauro Carvalho Chehab if (ret == 0)
305ee4a77a3SMauro Carvalho Chehab dev_warn(vsp1->dev,
306ee4a77a3SMauro Carvalho Chehab "DRM pipeline %u reconfiguration timeout\n",
307ee4a77a3SMauro Carvalho Chehab owner_pipe->pipe.lif->index);
308ee4a77a3SMauro Carvalho Chehab }
309ee4a77a3SMauro Carvalho Chehab
310ee4a77a3SMauro Carvalho Chehab /*
311ee4a77a3SMauro Carvalho Chehab * If the BRx we have released previously hasn't been acquired
312ee4a77a3SMauro Carvalho Chehab * by the other pipeline, add it back to the entities list (with
313ee4a77a3SMauro Carvalho Chehab * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
314ee4a77a3SMauro Carvalho Chehab * disconnect it from the hardware pipeline.
315ee4a77a3SMauro Carvalho Chehab */
316ee4a77a3SMauro Carvalho Chehab if (released_brx && !released_brx->pipe)
317ee4a77a3SMauro Carvalho Chehab list_add_tail(&released_brx->list_pipe,
318ee4a77a3SMauro Carvalho Chehab &pipe->entities);
319ee4a77a3SMauro Carvalho Chehab
320ee4a77a3SMauro Carvalho Chehab /* Add the BRx to the pipeline. */
321ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
322ee4a77a3SMauro Carvalho Chehab __func__, pipe->lif->index, BRX_NAME(brx));
323ee4a77a3SMauro Carvalho Chehab
324ee4a77a3SMauro Carvalho Chehab pipe->brx = brx;
325ee4a77a3SMauro Carvalho Chehab pipe->brx->pipe = pipe;
326ee4a77a3SMauro Carvalho Chehab pipe->brx->sink = &pipe->output->entity;
327ee4a77a3SMauro Carvalho Chehab pipe->brx->sink_pad = 0;
328ee4a77a3SMauro Carvalho Chehab
329ee4a77a3SMauro Carvalho Chehab list_add_tail(&pipe->brx->list_pipe, &pipe->entities);
330ee4a77a3SMauro Carvalho Chehab }
331ee4a77a3SMauro Carvalho Chehab
332ee4a77a3SMauro Carvalho Chehab /*
333ee4a77a3SMauro Carvalho Chehab * Configure the format on the BRx source and verify that it matches the
334ee4a77a3SMauro Carvalho Chehab * requested format. We don't set the media bus code as it is configured
335ee4a77a3SMauro Carvalho Chehab * on the BRx sink pad 0 and propagated inside the entity, not on the
336ee4a77a3SMauro Carvalho Chehab * source pad.
337ee4a77a3SMauro Carvalho Chehab */
338ee4a77a3SMauro Carvalho Chehab format.pad = brx->source_pad;
339ee4a77a3SMauro Carvalho Chehab format.format.width = drm_pipe->width;
340ee4a77a3SMauro Carvalho Chehab format.format.height = drm_pipe->height;
341ee4a77a3SMauro Carvalho Chehab format.format.field = V4L2_FIELD_NONE;
342ee4a77a3SMauro Carvalho Chehab
343ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&brx->subdev, pad, set_fmt, NULL,
344ee4a77a3SMauro Carvalho Chehab &format);
345ee4a77a3SMauro Carvalho Chehab if (ret < 0)
346ee4a77a3SMauro Carvalho Chehab return ret;
347ee4a77a3SMauro Carvalho Chehab
348ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
349ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
350ee4a77a3SMauro Carvalho Chehab format.format.code, BRX_NAME(brx), brx->source_pad);
351ee4a77a3SMauro Carvalho Chehab
352ee4a77a3SMauro Carvalho Chehab if (format.format.width != drm_pipe->width ||
353ee4a77a3SMauro Carvalho Chehab format.format.height != drm_pipe->height) {
354ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
355ee4a77a3SMauro Carvalho Chehab return -EPIPE;
356ee4a77a3SMauro Carvalho Chehab }
357ee4a77a3SMauro Carvalho Chehab
358ee4a77a3SMauro Carvalho Chehab return 0;
359ee4a77a3SMauro Carvalho Chehab }
360ee4a77a3SMauro Carvalho Chehab
rpf_zpos(struct vsp1_device * vsp1,struct vsp1_rwpf * rpf)361ee4a77a3SMauro Carvalho Chehab static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
362ee4a77a3SMauro Carvalho Chehab {
363ee4a77a3SMauro Carvalho Chehab return vsp1->drm->inputs[rpf->entity.index].zpos;
364ee4a77a3SMauro Carvalho Chehab }
365ee4a77a3SMauro Carvalho Chehab
366ee4a77a3SMauro Carvalho Chehab /* Setup the input side of the pipeline (RPFs and BRx). */
vsp1_du_pipeline_setup_inputs(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)367ee4a77a3SMauro Carvalho Chehab static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
368ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe)
369ee4a77a3SMauro Carvalho Chehab {
370ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
371ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
372ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *uif;
373ee4a77a3SMauro Carvalho Chehab bool use_uif = false;
374ee4a77a3SMauro Carvalho Chehab struct vsp1_brx *brx;
375ee4a77a3SMauro Carvalho Chehab unsigned int i;
376ee4a77a3SMauro Carvalho Chehab int ret;
377ee4a77a3SMauro Carvalho Chehab
378ee4a77a3SMauro Carvalho Chehab /* Count the number of enabled inputs and sort them by Z-order. */
379ee4a77a3SMauro Carvalho Chehab pipe->num_inputs = 0;
380ee4a77a3SMauro Carvalho Chehab
381ee4a77a3SMauro Carvalho Chehab for (i = 0; i < vsp1->info->rpf_count; ++i) {
382ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *rpf = vsp1->rpf[i];
383ee4a77a3SMauro Carvalho Chehab unsigned int j;
384ee4a77a3SMauro Carvalho Chehab
385ee4a77a3SMauro Carvalho Chehab if (!pipe->inputs[i])
386ee4a77a3SMauro Carvalho Chehab continue;
387ee4a77a3SMauro Carvalho Chehab
388ee4a77a3SMauro Carvalho Chehab /* Insert the RPF in the sorted RPFs array. */
389ee4a77a3SMauro Carvalho Chehab for (j = pipe->num_inputs++; j > 0; --j) {
390ee4a77a3SMauro Carvalho Chehab if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
391ee4a77a3SMauro Carvalho Chehab break;
392ee4a77a3SMauro Carvalho Chehab inputs[j] = inputs[j-1];
393ee4a77a3SMauro Carvalho Chehab }
394ee4a77a3SMauro Carvalho Chehab
395ee4a77a3SMauro Carvalho Chehab inputs[j] = rpf;
396ee4a77a3SMauro Carvalho Chehab }
397ee4a77a3SMauro Carvalho Chehab
398ee4a77a3SMauro Carvalho Chehab /*
399ee4a77a3SMauro Carvalho Chehab * Setup the BRx. This must be done before setting up the RPF input
400ee4a77a3SMauro Carvalho Chehab * pipelines as the BRx sink compose rectangles depend on the BRx source
401ee4a77a3SMauro Carvalho Chehab * format.
402ee4a77a3SMauro Carvalho Chehab */
403ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
404ee4a77a3SMauro Carvalho Chehab if (ret < 0) {
405ee4a77a3SMauro Carvalho Chehab dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
406ee4a77a3SMauro Carvalho Chehab BRX_NAME(pipe->brx));
407ee4a77a3SMauro Carvalho Chehab return ret;
408ee4a77a3SMauro Carvalho Chehab }
409ee4a77a3SMauro Carvalho Chehab
410ee4a77a3SMauro Carvalho Chehab brx = to_brx(&pipe->brx->subdev);
411ee4a77a3SMauro Carvalho Chehab
412ee4a77a3SMauro Carvalho Chehab /* Setup the RPF input pipeline for every enabled input. */
413ee4a77a3SMauro Carvalho Chehab for (i = 0; i < pipe->brx->source_pad; ++i) {
414ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *rpf = inputs[i];
415ee4a77a3SMauro Carvalho Chehab
416ee4a77a3SMauro Carvalho Chehab if (!rpf) {
417ee4a77a3SMauro Carvalho Chehab brx->inputs[i].rpf = NULL;
418ee4a77a3SMauro Carvalho Chehab continue;
419ee4a77a3SMauro Carvalho Chehab }
420ee4a77a3SMauro Carvalho Chehab
421ee4a77a3SMauro Carvalho Chehab if (!rpf->entity.pipe) {
422ee4a77a3SMauro Carvalho Chehab rpf->entity.pipe = pipe;
423ee4a77a3SMauro Carvalho Chehab list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
424ee4a77a3SMauro Carvalho Chehab }
425ee4a77a3SMauro Carvalho Chehab
426ee4a77a3SMauro Carvalho Chehab brx->inputs[i].rpf = rpf;
427ee4a77a3SMauro Carvalho Chehab rpf->brx_input = i;
428ee4a77a3SMauro Carvalho Chehab rpf->entity.sink = pipe->brx;
429ee4a77a3SMauro Carvalho Chehab rpf->entity.sink_pad = i;
430ee4a77a3SMauro Carvalho Chehab
431ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
432ee4a77a3SMauro Carvalho Chehab __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
433ee4a77a3SMauro Carvalho Chehab
434ee4a77a3SMauro Carvalho Chehab uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE &&
435ee4a77a3SMauro Carvalho Chehab drm_pipe->crc.index == i ? drm_pipe->uif : NULL;
436ee4a77a3SMauro Carvalho Chehab if (uif)
437ee4a77a3SMauro Carvalho Chehab use_uif = true;
438ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
439ee4a77a3SMauro Carvalho Chehab if (ret < 0) {
440ee4a77a3SMauro Carvalho Chehab dev_err(vsp1->dev,
441ee4a77a3SMauro Carvalho Chehab "%s: failed to setup RPF.%u\n",
442ee4a77a3SMauro Carvalho Chehab __func__, rpf->entity.index);
443ee4a77a3SMauro Carvalho Chehab return ret;
444ee4a77a3SMauro Carvalho Chehab }
445ee4a77a3SMauro Carvalho Chehab }
446ee4a77a3SMauro Carvalho Chehab
447ee4a77a3SMauro Carvalho Chehab /* Insert and configure the UIF at the BRx output if available. */
448ee4a77a3SMauro Carvalho Chehab uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL;
449ee4a77a3SMauro Carvalho Chehab if (uif)
450ee4a77a3SMauro Carvalho Chehab use_uif = true;
451ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_insert_uif(vsp1, pipe, uif,
452ee4a77a3SMauro Carvalho Chehab pipe->brx, pipe->brx->source_pad,
453ee4a77a3SMauro Carvalho Chehab &pipe->output->entity, 0);
454ee4a77a3SMauro Carvalho Chehab if (ret < 0)
455ee4a77a3SMauro Carvalho Chehab dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n",
456ee4a77a3SMauro Carvalho Chehab __func__, BRX_NAME(pipe->brx));
457ee4a77a3SMauro Carvalho Chehab
458ee4a77a3SMauro Carvalho Chehab /* If the DRM pipe does not have a UIF there is nothing we can update. */
459ee4a77a3SMauro Carvalho Chehab if (!drm_pipe->uif)
460ee4a77a3SMauro Carvalho Chehab return 0;
461ee4a77a3SMauro Carvalho Chehab
462ee4a77a3SMauro Carvalho Chehab /*
463ee4a77a3SMauro Carvalho Chehab * If the UIF is not in use schedule it for removal by setting its pipe
464ee4a77a3SMauro Carvalho Chehab * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the
465ee4a77a3SMauro Carvalho Chehab * hardware pipeline and from the pipeline's list of entities. Otherwise
466ee4a77a3SMauro Carvalho Chehab * make sure it is present in the pipeline's list of entities if it
467ee4a77a3SMauro Carvalho Chehab * wasn't already.
468ee4a77a3SMauro Carvalho Chehab */
469ee4a77a3SMauro Carvalho Chehab if (!use_uif) {
470ee4a77a3SMauro Carvalho Chehab drm_pipe->uif->pipe = NULL;
471ee4a77a3SMauro Carvalho Chehab } else if (!drm_pipe->uif->pipe) {
472ee4a77a3SMauro Carvalho Chehab drm_pipe->uif->pipe = pipe;
473ee4a77a3SMauro Carvalho Chehab list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
474ee4a77a3SMauro Carvalho Chehab }
475ee4a77a3SMauro Carvalho Chehab
476ee4a77a3SMauro Carvalho Chehab return 0;
477ee4a77a3SMauro Carvalho Chehab }
478ee4a77a3SMauro Carvalho Chehab
479ee4a77a3SMauro Carvalho Chehab /* Setup the output side of the pipeline (WPF and LIF). */
vsp1_du_pipeline_setup_output(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)480ee4a77a3SMauro Carvalho Chehab static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
481ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe)
482ee4a77a3SMauro Carvalho Chehab {
483ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
484*e18a7e9aSLaurent Pinchart struct v4l2_subdev_format format = {
485*e18a7e9aSLaurent Pinchart .which = V4L2_SUBDEV_FORMAT_ACTIVE,
486*e18a7e9aSLaurent Pinchart };
487ee4a77a3SMauro Carvalho Chehab int ret;
488ee4a77a3SMauro Carvalho Chehab
489ee4a77a3SMauro Carvalho Chehab format.pad = RWPF_PAD_SINK;
490ee4a77a3SMauro Carvalho Chehab format.format.width = drm_pipe->width;
491ee4a77a3SMauro Carvalho Chehab format.format.height = drm_pipe->height;
492ee4a77a3SMauro Carvalho Chehab format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
493ee4a77a3SMauro Carvalho Chehab format.format.field = V4L2_FIELD_NONE;
494ee4a77a3SMauro Carvalho Chehab
495ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
496ee4a77a3SMauro Carvalho Chehab &format);
497ee4a77a3SMauro Carvalho Chehab if (ret < 0)
498ee4a77a3SMauro Carvalho Chehab return ret;
499ee4a77a3SMauro Carvalho Chehab
500ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
501ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
502ee4a77a3SMauro Carvalho Chehab format.format.code, pipe->output->entity.index);
503ee4a77a3SMauro Carvalho Chehab
504ee4a77a3SMauro Carvalho Chehab format.pad = RWPF_PAD_SOURCE;
505ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
506ee4a77a3SMauro Carvalho Chehab &format);
507ee4a77a3SMauro Carvalho Chehab if (ret < 0)
508ee4a77a3SMauro Carvalho Chehab return ret;
509ee4a77a3SMauro Carvalho Chehab
510ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
511ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
512ee4a77a3SMauro Carvalho Chehab format.format.code, pipe->output->entity.index);
513ee4a77a3SMauro Carvalho Chehab
514ee4a77a3SMauro Carvalho Chehab format.pad = LIF_PAD_SINK;
515ee4a77a3SMauro Carvalho Chehab ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
516ee4a77a3SMauro Carvalho Chehab &format);
517ee4a77a3SMauro Carvalho Chehab if (ret < 0)
518ee4a77a3SMauro Carvalho Chehab return ret;
519ee4a77a3SMauro Carvalho Chehab
520ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
521ee4a77a3SMauro Carvalho Chehab __func__, format.format.width, format.format.height,
522ee4a77a3SMauro Carvalho Chehab format.format.code, pipe->lif->index);
523ee4a77a3SMauro Carvalho Chehab
524ee4a77a3SMauro Carvalho Chehab /*
525ee4a77a3SMauro Carvalho Chehab * Verify that the format at the output of the pipeline matches the
526ee4a77a3SMauro Carvalho Chehab * requested frame size and media bus code.
527ee4a77a3SMauro Carvalho Chehab */
528ee4a77a3SMauro Carvalho Chehab if (format.format.width != drm_pipe->width ||
529ee4a77a3SMauro Carvalho Chehab format.format.height != drm_pipe->height ||
530ee4a77a3SMauro Carvalho Chehab format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
531ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
532ee4a77a3SMauro Carvalho Chehab pipe->lif->index);
533ee4a77a3SMauro Carvalho Chehab return -EPIPE;
534ee4a77a3SMauro Carvalho Chehab }
535ee4a77a3SMauro Carvalho Chehab
536ee4a77a3SMauro Carvalho Chehab return 0;
537ee4a77a3SMauro Carvalho Chehab }
538ee4a77a3SMauro Carvalho Chehab
539ee4a77a3SMauro Carvalho Chehab /* Configure all entities in the pipeline. */
vsp1_du_pipeline_configure(struct vsp1_pipeline * pipe)540ee4a77a3SMauro Carvalho Chehab static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
541ee4a77a3SMauro Carvalho Chehab {
542ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
543ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *entity;
544ee4a77a3SMauro Carvalho Chehab struct vsp1_entity *next;
545ee4a77a3SMauro Carvalho Chehab struct vsp1_dl_list *dl;
546ee4a77a3SMauro Carvalho Chehab struct vsp1_dl_body *dlb;
547ee4a77a3SMauro Carvalho Chehab unsigned int dl_flags = 0;
548ee4a77a3SMauro Carvalho Chehab
549ee4a77a3SMauro Carvalho Chehab if (drm_pipe->force_brx_release)
550ee4a77a3SMauro Carvalho Chehab dl_flags |= VSP1_DL_FRAME_END_INTERNAL;
551ee4a77a3SMauro Carvalho Chehab if (pipe->output->writeback)
552ee4a77a3SMauro Carvalho Chehab dl_flags |= VSP1_DL_FRAME_END_WRITEBACK;
553ee4a77a3SMauro Carvalho Chehab
554ee4a77a3SMauro Carvalho Chehab dl = vsp1_dl_list_get(pipe->output->dlm);
555ee4a77a3SMauro Carvalho Chehab dlb = vsp1_dl_list_get_body0(dl);
556ee4a77a3SMauro Carvalho Chehab
557ee4a77a3SMauro Carvalho Chehab list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
558ee4a77a3SMauro Carvalho Chehab /* Disconnect unused entities from the pipeline. */
559ee4a77a3SMauro Carvalho Chehab if (!entity->pipe) {
560ee4a77a3SMauro Carvalho Chehab vsp1_dl_body_write(dlb, entity->route->reg,
561ee4a77a3SMauro Carvalho Chehab VI6_DPR_NODE_UNUSED);
562ee4a77a3SMauro Carvalho Chehab
563ee4a77a3SMauro Carvalho Chehab entity->sink = NULL;
564ee4a77a3SMauro Carvalho Chehab list_del(&entity->list_pipe);
565ee4a77a3SMauro Carvalho Chehab
566ee4a77a3SMauro Carvalho Chehab continue;
567ee4a77a3SMauro Carvalho Chehab }
568ee4a77a3SMauro Carvalho Chehab
569ee4a77a3SMauro Carvalho Chehab vsp1_entity_route_setup(entity, pipe, dlb);
570ee4a77a3SMauro Carvalho Chehab vsp1_entity_configure_stream(entity, pipe, dl, dlb);
571ee4a77a3SMauro Carvalho Chehab vsp1_entity_configure_frame(entity, pipe, dl, dlb);
572ee4a77a3SMauro Carvalho Chehab vsp1_entity_configure_partition(entity, pipe, dl, dlb);
573ee4a77a3SMauro Carvalho Chehab }
574ee4a77a3SMauro Carvalho Chehab
575ee4a77a3SMauro Carvalho Chehab vsp1_dl_list_commit(dl, dl_flags);
576ee4a77a3SMauro Carvalho Chehab }
577ee4a77a3SMauro Carvalho Chehab
vsp1_du_pipeline_set_rwpf_format(struct vsp1_device * vsp1,struct vsp1_rwpf * rwpf,u32 pixelformat,unsigned int pitch)578ee4a77a3SMauro Carvalho Chehab static int vsp1_du_pipeline_set_rwpf_format(struct vsp1_device *vsp1,
579ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *rwpf,
580ee4a77a3SMauro Carvalho Chehab u32 pixelformat, unsigned int pitch)
581ee4a77a3SMauro Carvalho Chehab {
582ee4a77a3SMauro Carvalho Chehab const struct vsp1_format_info *fmtinfo;
583ee4a77a3SMauro Carvalho Chehab unsigned int chroma_hsub;
584ee4a77a3SMauro Carvalho Chehab
585ee4a77a3SMauro Carvalho Chehab fmtinfo = vsp1_get_format_info(vsp1, pixelformat);
586ee4a77a3SMauro Carvalho Chehab if (!fmtinfo) {
587ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "Unsupported pixel format %08x\n",
588ee4a77a3SMauro Carvalho Chehab pixelformat);
589ee4a77a3SMauro Carvalho Chehab return -EINVAL;
590ee4a77a3SMauro Carvalho Chehab }
591ee4a77a3SMauro Carvalho Chehab
592ee4a77a3SMauro Carvalho Chehab /*
593ee4a77a3SMauro Carvalho Chehab * Only formats with three planes can affect the chroma planes pitch.
594ee4a77a3SMauro Carvalho Chehab * All formats with two planes have a horizontal subsampling value of 2,
595ee4a77a3SMauro Carvalho Chehab * but combine U and V in a single chroma plane, which thus results in
596ee4a77a3SMauro Carvalho Chehab * the luma plane and chroma plane having the same pitch.
597ee4a77a3SMauro Carvalho Chehab */
598ee4a77a3SMauro Carvalho Chehab chroma_hsub = (fmtinfo->planes == 3) ? fmtinfo->hsub : 1;
599ee4a77a3SMauro Carvalho Chehab
600ee4a77a3SMauro Carvalho Chehab rwpf->fmtinfo = fmtinfo;
601ee4a77a3SMauro Carvalho Chehab rwpf->format.num_planes = fmtinfo->planes;
602ee4a77a3SMauro Carvalho Chehab rwpf->format.plane_fmt[0].bytesperline = pitch;
603ee4a77a3SMauro Carvalho Chehab rwpf->format.plane_fmt[1].bytesperline = pitch / chroma_hsub;
604ee4a77a3SMauro Carvalho Chehab
605ee4a77a3SMauro Carvalho Chehab return 0;
606ee4a77a3SMauro Carvalho Chehab }
607ee4a77a3SMauro Carvalho Chehab
608ee4a77a3SMauro Carvalho Chehab /* -----------------------------------------------------------------------------
609ee4a77a3SMauro Carvalho Chehab * DU Driver API
610ee4a77a3SMauro Carvalho Chehab */
611ee4a77a3SMauro Carvalho Chehab
vsp1_du_init(struct device * dev)612ee4a77a3SMauro Carvalho Chehab int vsp1_du_init(struct device *dev)
613ee4a77a3SMauro Carvalho Chehab {
614ee4a77a3SMauro Carvalho Chehab struct vsp1_device *vsp1 = dev_get_drvdata(dev);
615ee4a77a3SMauro Carvalho Chehab
616ee4a77a3SMauro Carvalho Chehab if (!vsp1)
617ee4a77a3SMauro Carvalho Chehab return -EPROBE_DEFER;
618ee4a77a3SMauro Carvalho Chehab
619ee4a77a3SMauro Carvalho Chehab return 0;
620ee4a77a3SMauro Carvalho Chehab }
621ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_init);
622ee4a77a3SMauro Carvalho Chehab
623ee4a77a3SMauro Carvalho Chehab /**
624ee4a77a3SMauro Carvalho Chehab * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
625ee4a77a3SMauro Carvalho Chehab * @dev: the VSP device
626ee4a77a3SMauro Carvalho Chehab * @pipe_index: the DRM pipeline index
627ee4a77a3SMauro Carvalho Chehab * @cfg: the LIF configuration
628ee4a77a3SMauro Carvalho Chehab *
629ee4a77a3SMauro Carvalho Chehab * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
630ee4a77a3SMauro Carvalho Chehab * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
631ee4a77a3SMauro Carvalho Chehab * source pads, and the LIF sink pad.
632ee4a77a3SMauro Carvalho Chehab *
633ee4a77a3SMauro Carvalho Chehab * The @pipe_index argument selects which DRM pipeline to setup. The number of
634ee4a77a3SMauro Carvalho Chehab * available pipelines depend on the VSP instance.
635ee4a77a3SMauro Carvalho Chehab *
636ee4a77a3SMauro Carvalho Chehab * As the media bus code on the blend unit source pad is conditioned by the
637ee4a77a3SMauro Carvalho Chehab * configuration of its sink 0 pad, we also set up the formats on all blend unit
638ee4a77a3SMauro Carvalho Chehab * sinks, even if the configuration will be overwritten later by
639ee4a77a3SMauro Carvalho Chehab * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
640ee4a77a3SMauro Carvalho Chehab * a well defined state.
641ee4a77a3SMauro Carvalho Chehab *
642ee4a77a3SMauro Carvalho Chehab * Return 0 on success or a negative error code on failure.
643ee4a77a3SMauro Carvalho Chehab */
vsp1_du_setup_lif(struct device * dev,unsigned int pipe_index,const struct vsp1_du_lif_config * cfg)644ee4a77a3SMauro Carvalho Chehab int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
645ee4a77a3SMauro Carvalho Chehab const struct vsp1_du_lif_config *cfg)
646ee4a77a3SMauro Carvalho Chehab {
647ee4a77a3SMauro Carvalho Chehab struct vsp1_device *vsp1 = dev_get_drvdata(dev);
648ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe;
649ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe;
650ee4a77a3SMauro Carvalho Chehab unsigned long flags;
651ee4a77a3SMauro Carvalho Chehab unsigned int i;
652ee4a77a3SMauro Carvalho Chehab int ret;
653ee4a77a3SMauro Carvalho Chehab
654ee4a77a3SMauro Carvalho Chehab if (pipe_index >= vsp1->info->lif_count)
655ee4a77a3SMauro Carvalho Chehab return -EINVAL;
656ee4a77a3SMauro Carvalho Chehab
657ee4a77a3SMauro Carvalho Chehab drm_pipe = &vsp1->drm->pipe[pipe_index];
658ee4a77a3SMauro Carvalho Chehab pipe = &drm_pipe->pipe;
659ee4a77a3SMauro Carvalho Chehab
660ee4a77a3SMauro Carvalho Chehab if (!cfg) {
661ee4a77a3SMauro Carvalho Chehab struct vsp1_brx *brx;
662ee4a77a3SMauro Carvalho Chehab
663ee4a77a3SMauro Carvalho Chehab mutex_lock(&vsp1->drm->lock);
664ee4a77a3SMauro Carvalho Chehab
665ee4a77a3SMauro Carvalho Chehab brx = to_brx(&pipe->brx->subdev);
666ee4a77a3SMauro Carvalho Chehab
667ee4a77a3SMauro Carvalho Chehab /*
668ee4a77a3SMauro Carvalho Chehab * NULL configuration means the CRTC is being disabled, stop
669ee4a77a3SMauro Carvalho Chehab * the pipeline and turn the light off.
670ee4a77a3SMauro Carvalho Chehab */
671ee4a77a3SMauro Carvalho Chehab ret = vsp1_pipeline_stop(pipe);
672ee4a77a3SMauro Carvalho Chehab if (ret == -ETIMEDOUT)
673ee4a77a3SMauro Carvalho Chehab dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
674ee4a77a3SMauro Carvalho Chehab
675ee4a77a3SMauro Carvalho Chehab for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
676ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *rpf = pipe->inputs[i];
677ee4a77a3SMauro Carvalho Chehab
678ee4a77a3SMauro Carvalho Chehab if (!rpf)
679ee4a77a3SMauro Carvalho Chehab continue;
680ee4a77a3SMauro Carvalho Chehab
681ee4a77a3SMauro Carvalho Chehab /*
682ee4a77a3SMauro Carvalho Chehab * Remove the RPF from the pipe and the list of BRx
683ee4a77a3SMauro Carvalho Chehab * inputs.
684ee4a77a3SMauro Carvalho Chehab */
685ee4a77a3SMauro Carvalho Chehab WARN_ON(!rpf->entity.pipe);
686ee4a77a3SMauro Carvalho Chehab rpf->entity.pipe = NULL;
687ee4a77a3SMauro Carvalho Chehab list_del(&rpf->entity.list_pipe);
688ee4a77a3SMauro Carvalho Chehab pipe->inputs[i] = NULL;
689ee4a77a3SMauro Carvalho Chehab
690ee4a77a3SMauro Carvalho Chehab brx->inputs[rpf->brx_input].rpf = NULL;
691ee4a77a3SMauro Carvalho Chehab }
692ee4a77a3SMauro Carvalho Chehab
693ee4a77a3SMauro Carvalho Chehab drm_pipe->du_complete = NULL;
694ee4a77a3SMauro Carvalho Chehab pipe->num_inputs = 0;
695ee4a77a3SMauro Carvalho Chehab
696ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
697ee4a77a3SMauro Carvalho Chehab __func__, pipe->lif->index,
698ee4a77a3SMauro Carvalho Chehab BRX_NAME(pipe->brx));
699ee4a77a3SMauro Carvalho Chehab
700ee4a77a3SMauro Carvalho Chehab list_del(&pipe->brx->list_pipe);
701ee4a77a3SMauro Carvalho Chehab pipe->brx->pipe = NULL;
702ee4a77a3SMauro Carvalho Chehab pipe->brx = NULL;
703ee4a77a3SMauro Carvalho Chehab
704ee4a77a3SMauro Carvalho Chehab mutex_unlock(&vsp1->drm->lock);
705ee4a77a3SMauro Carvalho Chehab
706ee4a77a3SMauro Carvalho Chehab vsp1_dlm_reset(pipe->output->dlm);
707ee4a77a3SMauro Carvalho Chehab vsp1_device_put(vsp1);
708ee4a77a3SMauro Carvalho Chehab
709ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
710ee4a77a3SMauro Carvalho Chehab
711ee4a77a3SMauro Carvalho Chehab return 0;
712ee4a77a3SMauro Carvalho Chehab }
713ee4a77a3SMauro Carvalho Chehab
7141dc30075STomi Valkeinen /* Reset the underrun counter */
7151dc30075STomi Valkeinen pipe->underrun_count = 0;
7161dc30075STomi Valkeinen
717ee4a77a3SMauro Carvalho Chehab drm_pipe->width = cfg->width;
718ee4a77a3SMauro Carvalho Chehab drm_pipe->height = cfg->height;
719ee4a77a3SMauro Carvalho Chehab pipe->interlaced = cfg->interlaced;
720ee4a77a3SMauro Carvalho Chehab
721ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u%s\n",
722ee4a77a3SMauro Carvalho Chehab __func__, pipe_index, cfg->width, cfg->height,
723ee4a77a3SMauro Carvalho Chehab pipe->interlaced ? "i" : "");
724ee4a77a3SMauro Carvalho Chehab
725ee4a77a3SMauro Carvalho Chehab mutex_lock(&vsp1->drm->lock);
726ee4a77a3SMauro Carvalho Chehab
727ee4a77a3SMauro Carvalho Chehab /* Setup formats through the pipeline. */
728ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
729ee4a77a3SMauro Carvalho Chehab if (ret < 0)
730ee4a77a3SMauro Carvalho Chehab goto unlock;
731ee4a77a3SMauro Carvalho Chehab
732ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
733ee4a77a3SMauro Carvalho Chehab if (ret < 0)
734ee4a77a3SMauro Carvalho Chehab goto unlock;
735ee4a77a3SMauro Carvalho Chehab
736ee4a77a3SMauro Carvalho Chehab /* Enable the VSP1. */
737ee4a77a3SMauro Carvalho Chehab ret = vsp1_device_get(vsp1);
738ee4a77a3SMauro Carvalho Chehab if (ret < 0)
739ee4a77a3SMauro Carvalho Chehab goto unlock;
740ee4a77a3SMauro Carvalho Chehab
741ee4a77a3SMauro Carvalho Chehab /*
742ee4a77a3SMauro Carvalho Chehab * Register a callback to allow us to notify the DRM driver of frame
743ee4a77a3SMauro Carvalho Chehab * completion events.
744ee4a77a3SMauro Carvalho Chehab */
745ee4a77a3SMauro Carvalho Chehab drm_pipe->du_complete = cfg->callback;
746ee4a77a3SMauro Carvalho Chehab drm_pipe->du_private = cfg->callback_data;
747ee4a77a3SMauro Carvalho Chehab
748ee4a77a3SMauro Carvalho Chehab /* Disable the display interrupts. */
749ee4a77a3SMauro Carvalho Chehab vsp1_write(vsp1, VI6_DISP_IRQ_STA(pipe_index), 0);
750ee4a77a3SMauro Carvalho Chehab vsp1_write(vsp1, VI6_DISP_IRQ_ENB(pipe_index), 0);
751ee4a77a3SMauro Carvalho Chehab
752ee4a77a3SMauro Carvalho Chehab /* Configure all entities in the pipeline. */
753ee4a77a3SMauro Carvalho Chehab vsp1_du_pipeline_configure(pipe);
754ee4a77a3SMauro Carvalho Chehab
755ee4a77a3SMauro Carvalho Chehab unlock:
756ee4a77a3SMauro Carvalho Chehab mutex_unlock(&vsp1->drm->lock);
757ee4a77a3SMauro Carvalho Chehab
758ee4a77a3SMauro Carvalho Chehab if (ret < 0)
759ee4a77a3SMauro Carvalho Chehab return ret;
760ee4a77a3SMauro Carvalho Chehab
761ee4a77a3SMauro Carvalho Chehab /* Start the pipeline. */
762ee4a77a3SMauro Carvalho Chehab spin_lock_irqsave(&pipe->irqlock, flags);
763ee4a77a3SMauro Carvalho Chehab vsp1_pipeline_run(pipe);
764ee4a77a3SMauro Carvalho Chehab spin_unlock_irqrestore(&pipe->irqlock, flags);
765ee4a77a3SMauro Carvalho Chehab
766ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
767ee4a77a3SMauro Carvalho Chehab
768ee4a77a3SMauro Carvalho Chehab return 0;
769ee4a77a3SMauro Carvalho Chehab }
770ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
771ee4a77a3SMauro Carvalho Chehab
772ee4a77a3SMauro Carvalho Chehab /**
773ee4a77a3SMauro Carvalho Chehab * vsp1_du_atomic_begin - Prepare for an atomic update
774ee4a77a3SMauro Carvalho Chehab * @dev: the VSP device
775ee4a77a3SMauro Carvalho Chehab * @pipe_index: the DRM pipeline index
776ee4a77a3SMauro Carvalho Chehab */
vsp1_du_atomic_begin(struct device * dev,unsigned int pipe_index)777ee4a77a3SMauro Carvalho Chehab void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
778ee4a77a3SMauro Carvalho Chehab {
779ee4a77a3SMauro Carvalho Chehab }
780ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
781ee4a77a3SMauro Carvalho Chehab
782ee4a77a3SMauro Carvalho Chehab /**
783ee4a77a3SMauro Carvalho Chehab * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
784ee4a77a3SMauro Carvalho Chehab * @dev: the VSP device
785ee4a77a3SMauro Carvalho Chehab * @pipe_index: the DRM pipeline index
786ee4a77a3SMauro Carvalho Chehab * @rpf_index: index of the RPF to setup (0-based)
787ee4a77a3SMauro Carvalho Chehab * @cfg: the RPF configuration
788ee4a77a3SMauro Carvalho Chehab *
789ee4a77a3SMauro Carvalho Chehab * Configure the VSP to perform image composition through RPF @rpf_index as
790ee4a77a3SMauro Carvalho Chehab * described by the @cfg configuration. The image to compose is referenced by
791ee4a77a3SMauro Carvalho Chehab * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
792ee4a77a3SMauro Carvalho Chehab * composition rectangle. The Z-order is configurable with higher @zpos values
793ee4a77a3SMauro Carvalho Chehab * displayed on top.
794ee4a77a3SMauro Carvalho Chehab *
795ee4a77a3SMauro Carvalho Chehab * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
796ee4a77a3SMauro Carvalho Chehab * function on a disabled RPF is allowed.
797ee4a77a3SMauro Carvalho Chehab *
798ee4a77a3SMauro Carvalho Chehab * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
799ee4a77a3SMauro Carvalho Chehab * value. The memory pitch is configurable to allow for padding at end of lines,
800ee4a77a3SMauro Carvalho Chehab * or simply for images that extend beyond the crop rectangle boundaries. The
801ee4a77a3SMauro Carvalho Chehab * @cfg.pitch value is expressed in bytes and applies to all planes for
802ee4a77a3SMauro Carvalho Chehab * multiplanar formats.
803ee4a77a3SMauro Carvalho Chehab *
804ee4a77a3SMauro Carvalho Chehab * The source memory buffer is referenced by the DMA address of its planes in
805ee4a77a3SMauro Carvalho Chehab * the @cfg.mem array. Up to two planes are supported. The second plane DMA
806ee4a77a3SMauro Carvalho Chehab * address is ignored for formats using a single plane.
807ee4a77a3SMauro Carvalho Chehab *
808ee4a77a3SMauro Carvalho Chehab * This function isn't reentrant, the caller needs to serialize calls.
809ee4a77a3SMauro Carvalho Chehab *
810ee4a77a3SMauro Carvalho Chehab * Return 0 on success or a negative error code on failure.
811ee4a77a3SMauro Carvalho Chehab */
vsp1_du_atomic_update(struct device * dev,unsigned int pipe_index,unsigned int rpf_index,const struct vsp1_du_atomic_config * cfg)812ee4a77a3SMauro Carvalho Chehab int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
813ee4a77a3SMauro Carvalho Chehab unsigned int rpf_index,
814ee4a77a3SMauro Carvalho Chehab const struct vsp1_du_atomic_config *cfg)
815ee4a77a3SMauro Carvalho Chehab {
816ee4a77a3SMauro Carvalho Chehab struct vsp1_device *vsp1 = dev_get_drvdata(dev);
817ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
818ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *rpf;
819ee4a77a3SMauro Carvalho Chehab int ret;
820ee4a77a3SMauro Carvalho Chehab
821ee4a77a3SMauro Carvalho Chehab if (rpf_index >= vsp1->info->rpf_count)
822ee4a77a3SMauro Carvalho Chehab return -EINVAL;
823ee4a77a3SMauro Carvalho Chehab
824ee4a77a3SMauro Carvalho Chehab rpf = vsp1->rpf[rpf_index];
825ee4a77a3SMauro Carvalho Chehab
826ee4a77a3SMauro Carvalho Chehab if (!cfg) {
827ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
828ee4a77a3SMauro Carvalho Chehab rpf_index);
829ee4a77a3SMauro Carvalho Chehab
830ee4a77a3SMauro Carvalho Chehab /*
831ee4a77a3SMauro Carvalho Chehab * Remove the RPF from the pipeline's inputs. Keep it in the
832ee4a77a3SMauro Carvalho Chehab * pipeline's entity list to let vsp1_du_pipeline_configure()
833ee4a77a3SMauro Carvalho Chehab * remove it from the hardware pipeline.
834ee4a77a3SMauro Carvalho Chehab */
835ee4a77a3SMauro Carvalho Chehab rpf->entity.pipe = NULL;
836ee4a77a3SMauro Carvalho Chehab drm_pipe->pipe.inputs[rpf_index] = NULL;
837ee4a77a3SMauro Carvalho Chehab return 0;
838ee4a77a3SMauro Carvalho Chehab }
839ee4a77a3SMauro Carvalho Chehab
840ee4a77a3SMauro Carvalho Chehab dev_dbg(vsp1->dev,
841ee4a77a3SMauro Carvalho Chehab "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
842ee4a77a3SMauro Carvalho Chehab __func__, rpf_index,
843ee4a77a3SMauro Carvalho Chehab cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,
844ee4a77a3SMauro Carvalho Chehab cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,
845ee4a77a3SMauro Carvalho Chehab cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],
846ee4a77a3SMauro Carvalho Chehab &cfg->mem[2], cfg->zpos);
847ee4a77a3SMauro Carvalho Chehab
848ee4a77a3SMauro Carvalho Chehab /*
849ee4a77a3SMauro Carvalho Chehab * Store the format, stride, memory buffer address, crop and compose
850ee4a77a3SMauro Carvalho Chehab * rectangles and Z-order position and for the input.
851ee4a77a3SMauro Carvalho Chehab */
852ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_pipeline_set_rwpf_format(vsp1, rpf, cfg->pixelformat,
853ee4a77a3SMauro Carvalho Chehab cfg->pitch);
854ee4a77a3SMauro Carvalho Chehab if (ret < 0)
855ee4a77a3SMauro Carvalho Chehab return ret;
856ee4a77a3SMauro Carvalho Chehab
857ee4a77a3SMauro Carvalho Chehab rpf->alpha = cfg->alpha;
858ee4a77a3SMauro Carvalho Chehab
859ee4a77a3SMauro Carvalho Chehab rpf->mem.addr[0] = cfg->mem[0];
860ee4a77a3SMauro Carvalho Chehab rpf->mem.addr[1] = cfg->mem[1];
861ee4a77a3SMauro Carvalho Chehab rpf->mem.addr[2] = cfg->mem[2];
862ee4a77a3SMauro Carvalho Chehab
8630efb6fd3STakanari Hayama rpf->format.flags = cfg->premult ? V4L2_PIX_FMT_FLAG_PREMUL_ALPHA : 0;
8640efb6fd3STakanari Hayama
865ee4a77a3SMauro Carvalho Chehab vsp1->drm->inputs[rpf_index].crop = cfg->src;
866ee4a77a3SMauro Carvalho Chehab vsp1->drm->inputs[rpf_index].compose = cfg->dst;
867ee4a77a3SMauro Carvalho Chehab vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
868ee4a77a3SMauro Carvalho Chehab
869ee4a77a3SMauro Carvalho Chehab drm_pipe->pipe.inputs[rpf_index] = rpf;
870ee4a77a3SMauro Carvalho Chehab
871ee4a77a3SMauro Carvalho Chehab return 0;
872ee4a77a3SMauro Carvalho Chehab }
873ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
874ee4a77a3SMauro Carvalho Chehab
875ee4a77a3SMauro Carvalho Chehab /**
876ee4a77a3SMauro Carvalho Chehab * vsp1_du_atomic_flush - Commit an atomic update
877ee4a77a3SMauro Carvalho Chehab * @dev: the VSP device
878ee4a77a3SMauro Carvalho Chehab * @pipe_index: the DRM pipeline index
879ee4a77a3SMauro Carvalho Chehab * @cfg: atomic pipe configuration
880ee4a77a3SMauro Carvalho Chehab */
vsp1_du_atomic_flush(struct device * dev,unsigned int pipe_index,const struct vsp1_du_atomic_pipe_config * cfg)881ee4a77a3SMauro Carvalho Chehab void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
882ee4a77a3SMauro Carvalho Chehab const struct vsp1_du_atomic_pipe_config *cfg)
883ee4a77a3SMauro Carvalho Chehab {
884ee4a77a3SMauro Carvalho Chehab struct vsp1_device *vsp1 = dev_get_drvdata(dev);
885ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
886ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe = &drm_pipe->pipe;
887ee4a77a3SMauro Carvalho Chehab int ret;
888ee4a77a3SMauro Carvalho Chehab
889ee4a77a3SMauro Carvalho Chehab drm_pipe->crc = cfg->crc;
890ee4a77a3SMauro Carvalho Chehab
891ee4a77a3SMauro Carvalho Chehab mutex_lock(&vsp1->drm->lock);
892ee4a77a3SMauro Carvalho Chehab
893ee4a77a3SMauro Carvalho Chehab if (cfg->writeback.pixelformat) {
894ee4a77a3SMauro Carvalho Chehab const struct vsp1_du_writeback_config *wb_cfg = &cfg->writeback;
895ee4a77a3SMauro Carvalho Chehab
896ee4a77a3SMauro Carvalho Chehab ret = vsp1_du_pipeline_set_rwpf_format(vsp1, pipe->output,
897ee4a77a3SMauro Carvalho Chehab wb_cfg->pixelformat,
898ee4a77a3SMauro Carvalho Chehab wb_cfg->pitch);
899ee4a77a3SMauro Carvalho Chehab if (WARN_ON(ret < 0))
900ee4a77a3SMauro Carvalho Chehab goto done;
901ee4a77a3SMauro Carvalho Chehab
902ee4a77a3SMauro Carvalho Chehab pipe->output->mem.addr[0] = wb_cfg->mem[0];
903ee4a77a3SMauro Carvalho Chehab pipe->output->mem.addr[1] = wb_cfg->mem[1];
904ee4a77a3SMauro Carvalho Chehab pipe->output->mem.addr[2] = wb_cfg->mem[2];
905ee4a77a3SMauro Carvalho Chehab pipe->output->writeback = true;
906ee4a77a3SMauro Carvalho Chehab }
907ee4a77a3SMauro Carvalho Chehab
908ee4a77a3SMauro Carvalho Chehab vsp1_du_pipeline_setup_inputs(vsp1, pipe);
909ee4a77a3SMauro Carvalho Chehab vsp1_du_pipeline_configure(pipe);
910ee4a77a3SMauro Carvalho Chehab
911ee4a77a3SMauro Carvalho Chehab done:
912ee4a77a3SMauro Carvalho Chehab mutex_unlock(&vsp1->drm->lock);
913ee4a77a3SMauro Carvalho Chehab }
914ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
915ee4a77a3SMauro Carvalho Chehab
vsp1_du_map_sg(struct device * dev,struct sg_table * sgt)916ee4a77a3SMauro Carvalho Chehab int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)
917ee4a77a3SMauro Carvalho Chehab {
918ee4a77a3SMauro Carvalho Chehab struct vsp1_device *vsp1 = dev_get_drvdata(dev);
919ee4a77a3SMauro Carvalho Chehab
920ee4a77a3SMauro Carvalho Chehab /*
921ee4a77a3SMauro Carvalho Chehab * As all the buffers allocated by the DU driver are coherent, we can
922ee4a77a3SMauro Carvalho Chehab * skip cache sync. This will need to be revisited when support for
923ee4a77a3SMauro Carvalho Chehab * non-coherent buffers will be added to the DU driver.
924ee4a77a3SMauro Carvalho Chehab */
925ee4a77a3SMauro Carvalho Chehab return dma_map_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE,
926ee4a77a3SMauro Carvalho Chehab DMA_ATTR_SKIP_CPU_SYNC);
927ee4a77a3SMauro Carvalho Chehab }
928ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_map_sg);
929ee4a77a3SMauro Carvalho Chehab
vsp1_du_unmap_sg(struct device * dev,struct sg_table * sgt)930ee4a77a3SMauro Carvalho Chehab void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)
931ee4a77a3SMauro Carvalho Chehab {
932ee4a77a3SMauro Carvalho Chehab struct vsp1_device *vsp1 = dev_get_drvdata(dev);
933ee4a77a3SMauro Carvalho Chehab
934ee4a77a3SMauro Carvalho Chehab dma_unmap_sgtable(vsp1->bus_master, sgt, DMA_TO_DEVICE,
935ee4a77a3SMauro Carvalho Chehab DMA_ATTR_SKIP_CPU_SYNC);
936ee4a77a3SMauro Carvalho Chehab }
937ee4a77a3SMauro Carvalho Chehab EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
938ee4a77a3SMauro Carvalho Chehab
939ee4a77a3SMauro Carvalho Chehab /* -----------------------------------------------------------------------------
940ee4a77a3SMauro Carvalho Chehab * Initialization
941ee4a77a3SMauro Carvalho Chehab */
942ee4a77a3SMauro Carvalho Chehab
vsp1_drm_init(struct vsp1_device * vsp1)943ee4a77a3SMauro Carvalho Chehab int vsp1_drm_init(struct vsp1_device *vsp1)
944ee4a77a3SMauro Carvalho Chehab {
945ee4a77a3SMauro Carvalho Chehab unsigned int i;
946ee4a77a3SMauro Carvalho Chehab
947ee4a77a3SMauro Carvalho Chehab vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
948ee4a77a3SMauro Carvalho Chehab if (!vsp1->drm)
949ee4a77a3SMauro Carvalho Chehab return -ENOMEM;
950ee4a77a3SMauro Carvalho Chehab
951ee4a77a3SMauro Carvalho Chehab mutex_init(&vsp1->drm->lock);
952ee4a77a3SMauro Carvalho Chehab
953ee4a77a3SMauro Carvalho Chehab /* Create one DRM pipeline per LIF. */
954ee4a77a3SMauro Carvalho Chehab for (i = 0; i < vsp1->info->lif_count; ++i) {
955ee4a77a3SMauro Carvalho Chehab struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
956ee4a77a3SMauro Carvalho Chehab struct vsp1_pipeline *pipe = &drm_pipe->pipe;
957ee4a77a3SMauro Carvalho Chehab
958ee4a77a3SMauro Carvalho Chehab init_waitqueue_head(&drm_pipe->wait_queue);
959ee4a77a3SMauro Carvalho Chehab
960ee4a77a3SMauro Carvalho Chehab vsp1_pipeline_init(pipe);
961ee4a77a3SMauro Carvalho Chehab
962ee4a77a3SMauro Carvalho Chehab pipe->frame_end = vsp1_du_pipeline_frame_end;
963ee4a77a3SMauro Carvalho Chehab
964ee4a77a3SMauro Carvalho Chehab /*
965ee4a77a3SMauro Carvalho Chehab * The output side of the DRM pipeline is static, add the
966ee4a77a3SMauro Carvalho Chehab * corresponding entities manually.
967ee4a77a3SMauro Carvalho Chehab */
968ee4a77a3SMauro Carvalho Chehab pipe->output = vsp1->wpf[i];
969ee4a77a3SMauro Carvalho Chehab pipe->lif = &vsp1->lif[i]->entity;
970ee4a77a3SMauro Carvalho Chehab
971ee4a77a3SMauro Carvalho Chehab pipe->output->entity.pipe = pipe;
972ee4a77a3SMauro Carvalho Chehab pipe->output->entity.sink = pipe->lif;
973ee4a77a3SMauro Carvalho Chehab pipe->output->entity.sink_pad = 0;
974ee4a77a3SMauro Carvalho Chehab list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
975ee4a77a3SMauro Carvalho Chehab
976ee4a77a3SMauro Carvalho Chehab pipe->lif->pipe = pipe;
977ee4a77a3SMauro Carvalho Chehab list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
978ee4a77a3SMauro Carvalho Chehab
979ee4a77a3SMauro Carvalho Chehab /*
980ee4a77a3SMauro Carvalho Chehab * CRC computation is initially disabled, don't add the UIF to
981ee4a77a3SMauro Carvalho Chehab * the pipeline.
982ee4a77a3SMauro Carvalho Chehab */
983ee4a77a3SMauro Carvalho Chehab if (i < vsp1->info->uif_count)
984ee4a77a3SMauro Carvalho Chehab drm_pipe->uif = &vsp1->uif[i]->entity;
985ee4a77a3SMauro Carvalho Chehab }
986ee4a77a3SMauro Carvalho Chehab
987ee4a77a3SMauro Carvalho Chehab /* Disable all RPFs initially. */
988ee4a77a3SMauro Carvalho Chehab for (i = 0; i < vsp1->info->rpf_count; ++i) {
989ee4a77a3SMauro Carvalho Chehab struct vsp1_rwpf *input = vsp1->rpf[i];
990ee4a77a3SMauro Carvalho Chehab
991ee4a77a3SMauro Carvalho Chehab INIT_LIST_HEAD(&input->entity.list_pipe);
992ee4a77a3SMauro Carvalho Chehab }
993ee4a77a3SMauro Carvalho Chehab
994ee4a77a3SMauro Carvalho Chehab return 0;
995ee4a77a3SMauro Carvalho Chehab }
996ee4a77a3SMauro Carvalho Chehab
vsp1_drm_cleanup(struct vsp1_device * vsp1)997ee4a77a3SMauro Carvalho Chehab void vsp1_drm_cleanup(struct vsp1_device *vsp1)
998ee4a77a3SMauro Carvalho Chehab {
999ee4a77a3SMauro Carvalho Chehab mutex_destroy(&vsp1->drm->lock);
1000ee4a77a3SMauro Carvalho Chehab }
1001