1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver
4  *
5  * Copyright (C) 2022 Renesas Electronics Corp.
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/of_device.h>
15 #include <linux/of_graph.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19 #include <linux/sys_soc.h>
20 #include <linux/units.h>
21 
22 #include <media/v4l2-ctrls.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-fwnode.h>
25 #include <media/v4l2-mc.h>
26 #include <media/v4l2-subdev.h>
27 
28 /* LINK registers */
29 /* Module Configuration Register */
30 #define CSI2nMCG			0x0
31 #define CSI2nMCG_SDLN			GENMASK(11, 8)
32 
33 /* Module Control Register 0 */
34 #define CSI2nMCT0			0x10
35 #define CSI2nMCT0_VDLN(x)		((x) << 0)
36 
37 /* Module Control Register 2 */
38 #define CSI2nMCT2			0x18
39 #define CSI2nMCT2_FRRSKW(x)		((x) << 16)
40 #define CSI2nMCT2_FRRCLK(x)		((x) << 0)
41 
42 /* Module Control Register 3 */
43 #define CSI2nMCT3			0x1c
44 #define CSI2nMCT3_RXEN			BIT(0)
45 
46 /* Reset Control Register */
47 #define CSI2nRTCT			0x28
48 #define CSI2nRTCT_VSRST			BIT(0)
49 
50 /* Reset Status Register */
51 #define CSI2nRTST			0x2c
52 #define CSI2nRTST_VSRSTS		BIT(0)
53 
54 /* Receive Data Type Enable Low Register */
55 #define CSI2nDTEL			0x60
56 
57 /* Receive Data Type Enable High Register */
58 #define CSI2nDTEH			0x64
59 
60 /* DPHY registers */
61 /* D-PHY Control Register 0 */
62 #define CSIDPHYCTRL0			0x400
63 #define CSIDPHYCTRL0_EN_LDO1200		BIT(1)
64 #define CSIDPHYCTRL0_EN_BGR		BIT(0)
65 
66 /* D-PHY Timing Register 0 */
67 #define CSIDPHYTIM0			0x404
68 #define CSIDPHYTIM0_TCLK_MISS(x)	((x) << 24)
69 #define CSIDPHYTIM0_T_INIT(x)		((x) << 0)
70 
71 /* D-PHY Timing Register 1 */
72 #define CSIDPHYTIM1			0x408
73 #define CSIDPHYTIM1_THS_PREPARE(x)	((x) << 24)
74 #define CSIDPHYTIM1_TCLK_PREPARE(x)	((x) << 16)
75 #define CSIDPHYTIM1_THS_SETTLE(x)	((x) << 8)
76 #define CSIDPHYTIM1_TCLK_SETTLE(x)	((x) << 0)
77 
78 /* D-PHY Skew Adjustment Function */
79 #define CSIDPHYSKW0			0x460
80 #define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x)	((x) & 0x3)
81 #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x)	(((x) & 0x3) << 4)
82 #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x)	(((x) & 0x3) << 8)
83 #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x)	(((x) & 0x3) << 12)
84 #define CSIDPHYSKW0_DEFAULT_SKW		(CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(1) | \
85 					 CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(1) | \
86 					 CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(1) | \
87 					 CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(1))
88 
89 #define VSRSTS_RETRIES			20
90 
91 #define RZG2L_CSI2_MIN_WIDTH		320
92 #define RZG2L_CSI2_MIN_HEIGHT		240
93 #define RZG2L_CSI2_MAX_WIDTH		2800
94 #define RZG2L_CSI2_MAX_HEIGHT		4095
95 
96 #define RZG2L_CSI2_DEFAULT_WIDTH	RZG2L_CSI2_MIN_WIDTH
97 #define RZG2L_CSI2_DEFAULT_HEIGHT	RZG2L_CSI2_MIN_HEIGHT
98 #define RZG2L_CSI2_DEFAULT_FMT		MEDIA_BUS_FMT_UYVY8_1X16
99 
100 enum rzg2l_csi2_pads {
101 	RZG2L_CSI2_SINK = 0,
102 	RZG2L_CSI2_SOURCE,
103 	NR_OF_RZG2L_CSI2_PAD,
104 };
105 
106 struct rzg2l_csi2 {
107 	struct device *dev;
108 	void __iomem *base;
109 	struct reset_control *presetn;
110 	struct reset_control *cmn_rstb;
111 	struct clk *sysclk;
112 	unsigned long vclk_rate;
113 
114 	struct v4l2_subdev subdev;
115 	struct media_pad pads[NR_OF_RZG2L_CSI2_PAD];
116 
117 	struct v4l2_async_notifier notifier;
118 	struct v4l2_subdev *remote_source;
119 
120 	unsigned short lanes;
121 	unsigned long hsfreq;
122 
123 	bool dphy_enabled;
124 };
125 
126 struct rzg2l_csi2_timings {
127 	u32 t_init;
128 	u32 tclk_miss;
129 	u32 tclk_settle;
130 	u32 ths_settle;
131 	u32 tclk_prepare;
132 	u32 ths_prepare;
133 	u32 max_hsfreq;
134 };
135 
136 static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = {
137 	{
138 		.max_hsfreq = 80,
139 		.t_init = 79801,
140 		.tclk_miss = 4,
141 		.tclk_settle = 23,
142 		.ths_settle = 31,
143 		.tclk_prepare = 10,
144 		.ths_prepare = 19,
145 	},
146 	{
147 		.max_hsfreq = 125,
148 		.t_init = 79801,
149 		.tclk_miss = 4,
150 		.tclk_settle = 23,
151 		.ths_settle = 28,
152 		.tclk_prepare = 10,
153 		.ths_prepare = 19,
154 	},
155 	{
156 		.max_hsfreq = 250,
157 		.t_init = 79801,
158 		.tclk_miss = 4,
159 		.tclk_settle = 23,
160 		.ths_settle = 22,
161 		.tclk_prepare = 10,
162 		.ths_prepare = 16,
163 	},
164 	{
165 		.max_hsfreq = 360,
166 		.t_init = 79801,
167 		.tclk_miss = 4,
168 		.tclk_settle = 18,
169 		.ths_settle = 19,
170 		.tclk_prepare = 10,
171 		.ths_prepare = 10,
172 	},
173 	{
174 		.max_hsfreq = 1500,
175 		.t_init = 79801,
176 		.tclk_miss = 4,
177 		.tclk_settle = 18,
178 		.ths_settle = 18,
179 		.tclk_prepare = 10,
180 		.ths_prepare = 10,
181 	},
182 };
183 
184 struct rzg2l_csi2_format {
185 	u32 code;
186 	unsigned int datatype;
187 	unsigned int bpp;
188 };
189 
190 static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = {
191 	{ .code = MEDIA_BUS_FMT_UYVY8_1X16,	.datatype = 0x1e, .bpp = 16 },
192 };
193 
194 static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd)
195 {
196 	return container_of(sd, struct rzg2l_csi2, subdev);
197 }
198 
199 static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code)
200 {
201 	unsigned int i;
202 
203 	for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_formats); i++)
204 		if (rzg2l_csi2_formats[i].code == code)
205 			return &rzg2l_csi2_formats[i];
206 
207 	return NULL;
208 }
209 
210 static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n)
211 {
212 	return container_of(n, struct rzg2l_csi2, notifier);
213 }
214 
215 static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg)
216 {
217 	return ioread32(csi2->base + reg);
218 }
219 
220 static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg,
221 			     u32 data)
222 {
223 	iowrite32(data, csi2->base + reg);
224 }
225 
226 static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set)
227 {
228 	rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) | set);
229 }
230 
231 static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr)
232 {
233 	rzg2l_csi2_write(csi2, reg, rzg2l_csi2_read(csi2, reg) & ~clr);
234 }
235 
236 static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2)
237 {
238 	struct v4l2_subdev *source = csi2->remote_source;
239 	const struct rzg2l_csi2_format *format;
240 	const struct v4l2_mbus_framefmt *fmt;
241 	struct v4l2_subdev_state *state;
242 	struct v4l2_ctrl *ctrl;
243 	u64 mbps;
244 
245 	/* Read the pixel rate control from remote. */
246 	ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE);
247 	if (!ctrl) {
248 		dev_err(csi2->dev, "no pixel rate control in subdev %s\n",
249 			source->name);
250 		return -EINVAL;
251 	}
252 
253 	state = v4l2_subdev_lock_and_get_active_state(&csi2->subdev);
254 	fmt = v4l2_subdev_get_pad_format(&csi2->subdev, state, RZG2L_CSI2_SINK);
255 	format = rzg2l_csi2_code_to_fmt(fmt->code);
256 	v4l2_subdev_unlock_state(state);
257 
258 	/*
259 	 * Calculate hsfreq in Mbps
260 	 * hsfreq = (pixel_rate * bits_per_sample) / number_of_lanes
261 	 */
262 	mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * format->bpp;
263 	do_div(mbps, csi2->lanes * 1000000);
264 
265 	return mbps;
266 }
267 
268 /* -----------------------------------------------------------------------------
269  * DPHY setting
270  */
271 
272 static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2)
273 {
274 	int ret;
275 
276 	/* Reset the CRU (D-PHY) */
277 	ret = reset_control_assert(csi2->cmn_rstb);
278 	if (ret)
279 		return ret;
280 
281 	/* Stop the D-PHY clock */
282 	clk_disable_unprepare(csi2->sysclk);
283 
284 	/* Cancel the EN_LDO1200 register setting */
285 	rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);
286 
287 	/* Cancel the EN_BGR register setting */
288 	rzg2l_csi2_clr(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);
289 
290 	csi2->dphy_enabled = false;
291 
292 	return 0;
293 }
294 
295 static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2)
296 {
297 	const struct rzg2l_csi2_timings *dphy_timing;
298 	u32 dphytim0, dphytim1;
299 	unsigned int i;
300 	int mbps;
301 	int ret;
302 
303 	mbps = rzg2l_csi2_calc_mbps(csi2);
304 	if (mbps < 0)
305 		return mbps;
306 
307 	csi2->hsfreq = mbps;
308 
309 	/* Set DPHY timing parameters */
310 	for (i = 0; i < ARRAY_SIZE(rzg2l_csi2_global_timings); ++i) {
311 		dphy_timing = &rzg2l_csi2_global_timings[i];
312 
313 		if (csi2->hsfreq <= dphy_timing->max_hsfreq)
314 			break;
315 	}
316 
317 	if (i >= ARRAY_SIZE(rzg2l_csi2_global_timings))
318 		return -EINVAL;
319 
320 	/* Set D-PHY timing parameters */
321 	dphytim0 = CSIDPHYTIM0_TCLK_MISS(dphy_timing->tclk_miss) |
322 			CSIDPHYTIM0_T_INIT(dphy_timing->t_init);
323 	dphytim1 = CSIDPHYTIM1_THS_PREPARE(dphy_timing->ths_prepare) |
324 			CSIDPHYTIM1_TCLK_PREPARE(dphy_timing->tclk_prepare) |
325 			CSIDPHYTIM1_THS_SETTLE(dphy_timing->ths_settle) |
326 			CSIDPHYTIM1_TCLK_SETTLE(dphy_timing->tclk_settle);
327 	rzg2l_csi2_write(csi2, CSIDPHYTIM0, dphytim0);
328 	rzg2l_csi2_write(csi2, CSIDPHYTIM1, dphytim1);
329 
330 	/* Enable D-PHY power control 0 */
331 	rzg2l_csi2_write(csi2, CSIDPHYSKW0, CSIDPHYSKW0_DEFAULT_SKW);
332 
333 	/* Set the EN_BGR bit */
334 	rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_BGR);
335 
336 	/* Delay 20us to be stable */
337 	usleep_range(20, 40);
338 
339 	/* Enable D-PHY power control 1 */
340 	rzg2l_csi2_set(csi2, CSIDPHYCTRL0, CSIDPHYCTRL0_EN_LDO1200);
341 
342 	/* Delay 10us to be stable */
343 	usleep_range(10, 20);
344 
345 	/* Start supplying the internal clock for the D-PHY block */
346 	ret = clk_prepare_enable(csi2->sysclk);
347 	if (ret)
348 		rzg2l_csi2_dphy_disable(csi2);
349 
350 	csi2->dphy_enabled = true;
351 
352 	return ret;
353 }
354 
355 static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on)
356 {
357 	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
358 
359 	if (on)
360 		return rzg2l_csi2_dphy_enable(csi2);
361 
362 	return rzg2l_csi2_dphy_disable(csi2);
363 }
364 
365 static void rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2)
366 {
367 	unsigned long vclk_rate = csi2->vclk_rate / HZ_PER_MHZ;
368 	u32 frrskw, frrclk, frrskw_coeff, frrclk_coeff;
369 
370 	/* Select data lanes */
371 	rzg2l_csi2_write(csi2, CSI2nMCT0, CSI2nMCT0_VDLN(csi2->lanes));
372 
373 	frrskw_coeff = 3 * vclk_rate * 8;
374 	frrclk_coeff = frrskw_coeff / 2;
375 	frrskw = DIV_ROUND_UP(frrskw_coeff, csi2->hsfreq);
376 	frrclk = DIV_ROUND_UP(frrclk_coeff, csi2->hsfreq);
377 	rzg2l_csi2_write(csi2, CSI2nMCT2, CSI2nMCT2_FRRSKW(frrskw) |
378 			 CSI2nMCT2_FRRCLK(frrclk));
379 
380 	/*
381 	 * Select data type.
382 	 * FS, FE, LS, LE, Generic Short Packet Codes 1 to 8,
383 	 * Generic Long Packet Data Types 1 to 4 YUV422 8-bit,
384 	 * RGB565, RGB888, RAW8 to RAW20, User-defined 8-bit
385 	 * data types 1 to 8
386 	 */
387 	rzg2l_csi2_write(csi2, CSI2nDTEL, 0xf778ff0f);
388 	rzg2l_csi2_write(csi2, CSI2nDTEH, 0x00ffff1f);
389 
390 	/* Enable LINK reception */
391 	rzg2l_csi2_write(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);
392 }
393 
394 static void rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2)
395 {
396 	unsigned int timeout = VSRSTS_RETRIES;
397 
398 	/* Stop LINK reception */
399 	rzg2l_csi2_clr(csi2, CSI2nMCT3, CSI2nMCT3_RXEN);
400 
401 	/* Request a software reset of the LINK Video Pixel Interface */
402 	rzg2l_csi2_write(csi2, CSI2nRTCT, CSI2nRTCT_VSRST);
403 
404 	/* Make sure CSI2nRTST.VSRSTS bit is cleared */
405 	while (--timeout) {
406 		if (!(rzg2l_csi2_read(csi2, CSI2nRTST) & CSI2nRTST_VSRSTS))
407 			break;
408 		usleep_range(100, 200);
409 	}
410 
411 	if (!timeout)
412 		dev_err(csi2->dev, "Clearing CSI2nRTST.VSRSTS timed out\n");
413 }
414 
415 static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on)
416 {
417 	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
418 
419 	if (on)
420 		rzg2l_csi2_mipi_link_enable(csi2);
421 	else
422 		rzg2l_csi2_mipi_link_disable(csi2);
423 
424 	return 0;
425 }
426 
427 static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable)
428 {
429 	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
430 	int s_stream_ret = 0;
431 	int ret;
432 
433 	if (enable) {
434 		ret = pm_runtime_resume_and_get(csi2->dev);
435 		if (ret)
436 			return ret;
437 
438 		ret = rzg2l_csi2_mipi_link_setting(sd, 1);
439 		if (ret)
440 			goto err_pm_put;
441 
442 		ret = reset_control_deassert(csi2->cmn_rstb);
443 		if (ret)
444 			goto err_mipi_link_disable;
445 	}
446 
447 	ret = v4l2_subdev_call(csi2->remote_source, video, s_stream, enable);
448 	if (ret)
449 		s_stream_ret = ret;
450 
451 	if (enable && ret)
452 		goto err_assert_rstb;
453 
454 	if (!enable) {
455 		ret = rzg2l_csi2_dphy_setting(sd, 0);
456 		if (ret && !s_stream_ret)
457 			s_stream_ret = ret;
458 		ret = rzg2l_csi2_mipi_link_setting(sd, 0);
459 		if (ret && !s_stream_ret)
460 			s_stream_ret = ret;
461 
462 		pm_runtime_put_sync(csi2->dev);
463 	}
464 
465 	return s_stream_ret;
466 
467 err_assert_rstb:
468 	reset_control_assert(csi2->cmn_rstb);
469 err_mipi_link_disable:
470 	rzg2l_csi2_mipi_link_setting(sd, 0);
471 err_pm_put:
472 	pm_runtime_put_sync(csi2->dev);
473 	return ret;
474 }
475 
476 static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags)
477 {
478 	return rzg2l_csi2_dphy_setting(sd, 1);
479 }
480 
481 static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd)
482 {
483 	struct rzg2l_csi2 *csi2 = sd_to_csi2(sd);
484 
485 	/*
486 	 * In ideal case D-PHY will be disabled in s_stream(0) callback
487 	 * as mentioned in the HW manual. The below will only happen when
488 	 * pre_streamon succeeds and further down the line s_stream(1)
489 	 * fails so we need to undo things in post_streamoff.
490 	 */
491 	if (csi2->dphy_enabled)
492 		return rzg2l_csi2_dphy_setting(sd, 0);
493 
494 	return 0;
495 }
496 
497 static int rzg2l_csi2_set_format(struct v4l2_subdev *sd,
498 				 struct v4l2_subdev_state *state,
499 				 struct v4l2_subdev_format *fmt)
500 {
501 	struct v4l2_mbus_framefmt *src_format;
502 	struct v4l2_mbus_framefmt *sink_format;
503 
504 	src_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CSI2_SOURCE);
505 	if (fmt->pad == RZG2L_CSI2_SOURCE) {
506 		fmt->format = *src_format;
507 		return 0;
508 	}
509 
510 	sink_format = v4l2_subdev_get_pad_format(sd, state, RZG2L_CSI2_SINK);
511 
512 	if (!rzg2l_csi2_code_to_fmt(fmt->format.code))
513 		sink_format->code = rzg2l_csi2_formats[0].code;
514 	else
515 		sink_format->code = fmt->format.code;
516 
517 	sink_format->field = V4L2_FIELD_NONE;
518 	sink_format->colorspace = fmt->format.colorspace;
519 	sink_format->xfer_func = fmt->format.xfer_func;
520 	sink_format->ycbcr_enc = fmt->format.ycbcr_enc;
521 	sink_format->quantization = fmt->format.quantization;
522 	sink_format->width = clamp_t(u32, fmt->format.width,
523 				     RZG2L_CSI2_MIN_WIDTH, RZG2L_CSI2_MAX_WIDTH);
524 	sink_format->height = clamp_t(u32, fmt->format.height,
525 				      RZG2L_CSI2_MIN_HEIGHT, RZG2L_CSI2_MAX_HEIGHT);
526 	fmt->format = *sink_format;
527 
528 	/* propagate format to source pad */
529 	*src_format = *sink_format;
530 
531 	return 0;
532 }
533 
534 static int rzg2l_csi2_init_config(struct v4l2_subdev *sd,
535 				  struct v4l2_subdev_state *sd_state)
536 {
537 	struct v4l2_subdev_format fmt = { .pad = RZG2L_CSI2_SINK, };
538 
539 	fmt.format.width = RZG2L_CSI2_DEFAULT_WIDTH;
540 	fmt.format.height = RZG2L_CSI2_DEFAULT_HEIGHT;
541 	fmt.format.field = V4L2_FIELD_NONE;
542 	fmt.format.code = RZG2L_CSI2_DEFAULT_FMT;
543 	fmt.format.colorspace = V4L2_COLORSPACE_SRGB;
544 	fmt.format.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
545 	fmt.format.quantization = V4L2_QUANTIZATION_DEFAULT;
546 	fmt.format.xfer_func = V4L2_XFER_FUNC_DEFAULT;
547 
548 	return rzg2l_csi2_set_format(sd, sd_state, &fmt);
549 }
550 
551 static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd,
552 				     struct v4l2_subdev_state *sd_state,
553 				     struct v4l2_subdev_mbus_code_enum *code)
554 {
555 	if (code->index >= ARRAY_SIZE(rzg2l_csi2_formats))
556 		return -EINVAL;
557 
558 	code->code = rzg2l_csi2_formats[code->index].code;
559 
560 	return 0;
561 }
562 
563 static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd,
564 				      struct v4l2_subdev_state *sd_state,
565 				      struct v4l2_subdev_frame_size_enum *fse)
566 {
567 	if (fse->index != 0)
568 		return -EINVAL;
569 
570 	fse->min_width = RZG2L_CSI2_MIN_WIDTH;
571 	fse->min_height = RZG2L_CSI2_MIN_HEIGHT;
572 	fse->max_width = RZG2L_CSI2_MAX_WIDTH;
573 	fse->max_height = RZG2L_CSI2_MAX_HEIGHT;
574 
575 	return 0;
576 }
577 
578 static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = {
579 	.s_stream = rzg2l_csi2_s_stream,
580 	.pre_streamon = rzg2l_csi2_pre_streamon,
581 	.post_streamoff = rzg2l_csi2_post_streamoff,
582 };
583 
584 static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = {
585 	.enum_mbus_code = rzg2l_csi2_enum_mbus_code,
586 	.init_cfg = rzg2l_csi2_init_config,
587 	.enum_frame_size = rzg2l_csi2_enum_frame_size,
588 	.set_fmt = rzg2l_csi2_set_format,
589 	.get_fmt = v4l2_subdev_get_fmt,
590 };
591 
592 static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = {
593 	.video	= &rzg2l_csi2_video_ops,
594 	.pad	= &rzg2l_csi2_pad_ops,
595 };
596 
597 /* -----------------------------------------------------------------------------
598  * Async handling and registration of subdevices and links.
599  */
600 
601 static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier,
602 				   struct v4l2_subdev *subdev,
603 				   struct v4l2_async_subdev *asd)
604 {
605 	struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);
606 
607 	csi2->remote_source = subdev;
608 
609 	dev_dbg(csi2->dev, "Bound subdev: %s pad\n", subdev->name);
610 
611 	return media_create_pad_link(&subdev->entity, RZG2L_CSI2_SINK,
612 				     &csi2->subdev.entity, 0,
613 				     MEDIA_LNK_FL_ENABLED |
614 				     MEDIA_LNK_FL_IMMUTABLE);
615 }
616 
617 static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier,
618 				     struct v4l2_subdev *subdev,
619 				     struct v4l2_async_subdev *asd)
620 {
621 	struct rzg2l_csi2 *csi2 = notifier_to_csi2(notifier);
622 
623 	csi2->remote_source = NULL;
624 
625 	dev_dbg(csi2->dev, "Unbind subdev %s\n", subdev->name);
626 }
627 
628 static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = {
629 	.bound = rzg2l_csi2_notify_bound,
630 	.unbind = rzg2l_csi2_notify_unbind,
631 };
632 
633 static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2,
634 				 struct v4l2_fwnode_endpoint *vep)
635 {
636 	/* Only port 0 endpoint 0 is valid. */
637 	if (vep->base.port || vep->base.id)
638 		return -ENOTCONN;
639 
640 	csi2->lanes = vep->bus.mipi_csi2.num_data_lanes;
641 
642 	return 0;
643 }
644 
645 static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2)
646 {
647 	struct v4l2_fwnode_endpoint v4l2_ep = {
648 		.bus_type = V4L2_MBUS_CSI2_DPHY
649 	};
650 	struct v4l2_async_subdev *asd;
651 	struct fwnode_handle *fwnode;
652 	struct fwnode_handle *ep;
653 	int ret;
654 
655 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csi2->dev), 0, 0, 0);
656 	if (!ep) {
657 		dev_err(csi2->dev, "Not connected to subdevice\n");
658 		return -EINVAL;
659 	}
660 
661 	ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep);
662 	if (ret) {
663 		dev_err(csi2->dev, "Could not parse v4l2 endpoint\n");
664 		fwnode_handle_put(ep);
665 		return -EINVAL;
666 	}
667 
668 	ret = rzg2l_csi2_parse_v4l2(csi2, &v4l2_ep);
669 	if (ret) {
670 		fwnode_handle_put(ep);
671 		return ret;
672 	}
673 
674 	fwnode = fwnode_graph_get_remote_endpoint(ep);
675 	fwnode_handle_put(ep);
676 
677 	v4l2_async_nf_init(&csi2->notifier);
678 	csi2->notifier.ops = &rzg2l_csi2_notify_ops;
679 
680 	asd = v4l2_async_nf_add_fwnode(&csi2->notifier, fwnode,
681 				       struct v4l2_async_subdev);
682 	fwnode_handle_put(fwnode);
683 	if (IS_ERR(asd))
684 		return PTR_ERR(asd);
685 
686 	ret = v4l2_async_subdev_nf_register(&csi2->subdev, &csi2->notifier);
687 	if (ret)
688 		v4l2_async_nf_cleanup(&csi2->notifier);
689 
690 	return ret;
691 }
692 
693 static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2)
694 {
695 	int lanes;
696 	int ret;
697 
698 	if (csi2->lanes != 1 && csi2->lanes != 2 && csi2->lanes != 4) {
699 		dev_err(csi2->dev, "Unsupported number of data-lanes: %u\n",
700 			csi2->lanes);
701 		return -EINVAL;
702 	}
703 
704 	ret = pm_runtime_resume_and_get(csi2->dev);
705 	if (ret)
706 		return ret;
707 
708 	/* Checking the maximum lanes support for CSI-2 module */
709 	lanes = (rzg2l_csi2_read(csi2, CSI2nMCG) & CSI2nMCG_SDLN) >> 8;
710 	if (lanes < csi2->lanes) {
711 		dev_err(csi2->dev,
712 			"Failed to support %d data lanes\n", csi2->lanes);
713 		ret = -EINVAL;
714 	}
715 
716 	pm_runtime_put_sync(csi2->dev);
717 
718 	return ret;
719 }
720 
721 /* -----------------------------------------------------------------------------
722  * Platform Device Driver.
723  */
724 
725 static const struct media_entity_operations rzg2l_csi2_entity_ops = {
726 	.link_validate = v4l2_subdev_link_validate,
727 };
728 
729 static int rzg2l_csi2_probe(struct platform_device *pdev)
730 {
731 	struct rzg2l_csi2 *csi2;
732 	struct clk *vclk;
733 	int ret;
734 
735 	csi2 = devm_kzalloc(&pdev->dev, sizeof(*csi2), GFP_KERNEL);
736 	if (!csi2)
737 		return -ENOMEM;
738 
739 	csi2->base = devm_platform_ioremap_resource(pdev, 0);
740 	if (IS_ERR(csi2->base))
741 		return PTR_ERR(csi2->base);
742 
743 	csi2->cmn_rstb = devm_reset_control_get_exclusive(&pdev->dev, "cmn-rstb");
744 	if (IS_ERR(csi2->cmn_rstb))
745 		return dev_err_probe(&pdev->dev, PTR_ERR(csi2->cmn_rstb),
746 				     "Failed to get cpg cmn-rstb\n");
747 
748 	csi2->presetn = devm_reset_control_get_shared(&pdev->dev, "presetn");
749 	if (IS_ERR(csi2->presetn))
750 		return dev_err_probe(&pdev->dev, PTR_ERR(csi2->presetn),
751 				     "Failed to get cpg presetn\n");
752 
753 	csi2->sysclk = devm_clk_get(&pdev->dev, "system");
754 	if (IS_ERR(csi2->sysclk))
755 		return dev_err_probe(&pdev->dev, PTR_ERR(csi2->sysclk),
756 				     "Failed to get system clk\n");
757 
758 	vclk = clk_get(&pdev->dev, "video");
759 	if (IS_ERR(vclk))
760 		return dev_err_probe(&pdev->dev, PTR_ERR(vclk),
761 				     "Failed to get video clock\n");
762 	csi2->vclk_rate = clk_get_rate(vclk);
763 	clk_put(vclk);
764 
765 	csi2->dev = &pdev->dev;
766 
767 	platform_set_drvdata(pdev, csi2);
768 
769 	ret = rzg2l_csi2_parse_dt(csi2);
770 	if (ret)
771 		return ret;
772 
773 	pm_runtime_enable(&pdev->dev);
774 
775 	ret = rzg2l_validate_csi2_lanes(csi2);
776 	if (ret)
777 		goto error_pm;
778 
779 	csi2->subdev.dev = &pdev->dev;
780 	v4l2_subdev_init(&csi2->subdev, &rzg2l_csi2_subdev_ops);
781 	v4l2_set_subdevdata(&csi2->subdev, &pdev->dev);
782 	snprintf(csi2->subdev.name, sizeof(csi2->subdev.name),
783 		 "csi-%s", dev_name(&pdev->dev));
784 	csi2->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
785 
786 	csi2->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
787 	csi2->subdev.entity.ops = &rzg2l_csi2_entity_ops;
788 
789 	csi2->pads[RZG2L_CSI2_SINK].flags = MEDIA_PAD_FL_SINK;
790 	/*
791 	 * TODO: RZ/G2L CSI2 supports 4 virtual channels, as virtual
792 	 * channels should be implemented by streams API which is under
793 	 * development lets hardcode to VC0 for now.
794 	 */
795 	csi2->pads[RZG2L_CSI2_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
796 	ret = media_entity_pads_init(&csi2->subdev.entity, 2, csi2->pads);
797 	if (ret)
798 		goto error_pm;
799 
800 	ret = v4l2_subdev_init_finalize(&csi2->subdev);
801 	if (ret < 0)
802 		goto error_async;
803 
804 	ret = v4l2_async_register_subdev(&csi2->subdev);
805 	if (ret < 0)
806 		goto error_subdev;
807 
808 	return 0;
809 
810 error_subdev:
811 	v4l2_subdev_cleanup(&csi2->subdev);
812 error_async:
813 	v4l2_async_nf_unregister(&csi2->notifier);
814 	v4l2_async_nf_cleanup(&csi2->notifier);
815 	media_entity_cleanup(&csi2->subdev.entity);
816 error_pm:
817 	pm_runtime_disable(&pdev->dev);
818 
819 	return ret;
820 }
821 
822 static void rzg2l_csi2_remove(struct platform_device *pdev)
823 {
824 	struct rzg2l_csi2 *csi2 = platform_get_drvdata(pdev);
825 
826 	v4l2_async_nf_unregister(&csi2->notifier);
827 	v4l2_async_nf_cleanup(&csi2->notifier);
828 	v4l2_async_unregister_subdev(&csi2->subdev);
829 	v4l2_subdev_cleanup(&csi2->subdev);
830 	media_entity_cleanup(&csi2->subdev.entity);
831 	pm_runtime_disable(&pdev->dev);
832 }
833 
834 static int __maybe_unused rzg2l_csi2_pm_runtime_suspend(struct device *dev)
835 {
836 	struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);
837 
838 	reset_control_assert(csi2->presetn);
839 
840 	return 0;
841 }
842 
843 static int __maybe_unused rzg2l_csi2_pm_runtime_resume(struct device *dev)
844 {
845 	struct rzg2l_csi2 *csi2 = dev_get_drvdata(dev);
846 
847 	return reset_control_deassert(csi2->presetn);
848 }
849 
850 static const struct dev_pm_ops rzg2l_csi2_pm_ops = {
851 	SET_RUNTIME_PM_OPS(rzg2l_csi2_pm_runtime_suspend, rzg2l_csi2_pm_runtime_resume, NULL)
852 };
853 
854 static const struct of_device_id rzg2l_csi2_of_table[] = {
855 	{ .compatible = "renesas,rzg2l-csi2", },
856 	{ /* sentinel */ }
857 };
858 
859 static struct platform_driver rzg2l_csi2_pdrv = {
860 	.remove_new = rzg2l_csi2_remove,
861 	.probe	= rzg2l_csi2_probe,
862 	.driver	= {
863 		.name = "rzg2l-csi2",
864 		.of_match_table = rzg2l_csi2_of_table,
865 		.pm = &rzg2l_csi2_pm_ops,
866 	},
867 };
868 
869 module_platform_driver(rzg2l_csi2_pdrv);
870 
871 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
872 MODULE_DESCRIPTION("Renesas RZ/G2L MIPI CSI2 receiver driver");
873 MODULE_LICENSE("GPL");
874