1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Author: Mikhail Ulyanov 4 * Copyright (C) 2014-2015 Cogent Embedded, Inc. <source@cogentembedded.com> 5 * Copyright (C) 2014-2015 Renesas Electronics Corporation 6 * 7 * This is based on the drivers/media/platform/samsung/s5p-jpeg driver by 8 * Andrzej Pietrasiewicz and Jacek Anaszewski. 9 * Some portions of code inspired by VSP1 driver by Laurent Pinchart. 10 * 11 * TODO in order of priority: 12 * 1) Rotation 13 * 2) Cropping 14 * 3) V4L2_CID_JPEG_ACTIVE_MARKER 15 */ 16 17 #include <asm/unaligned.h> 18 #include <linux/clk.h> 19 #include <linux/err.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/kernel.h> 23 #include <linux/module.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <linux/spinlock.h> 29 #include <linux/string.h> 30 #include <linux/videodev2.h> 31 #include <media/jpeg.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-event.h> 35 #include <media/v4l2-fh.h> 36 #include <media/v4l2-mem2mem.h> 37 #include <media/v4l2-ioctl.h> 38 #include <media/videobuf2-v4l2.h> 39 #include <media/videobuf2-dma-contig.h> 40 41 42 #define DRV_NAME "rcar_jpu" 43 44 /* 45 * Align JPEG header end to cache line to make sure we will not have any issues 46 * with cache; additionally to requirement (33.3.27 R01UH0501EJ0100 Rev.1.00) 47 */ 48 #define JPU_JPEG_HDR_SIZE (ALIGN(0x258, L1_CACHE_BYTES)) 49 #define JPU_JPEG_MAX_BYTES_PER_PIXEL 2 /* 16 bit precision format */ 50 #define JPU_JPEG_MIN_SIZE 25 /* SOI + SOF + EOI */ 51 #define JPU_JPEG_QTBL_SIZE 0x40 52 #define JPU_JPEG_HDCTBL_SIZE 0x1c 53 #define JPU_JPEG_HACTBL_SIZE 0xb2 54 #define JPU_JPEG_HEIGHT_OFFSET 0x91 55 #define JPU_JPEG_WIDTH_OFFSET 0x93 56 #define JPU_JPEG_SUBS_OFFSET 0x97 57 #define JPU_JPEG_QTBL_LUM_OFFSET 0x07 58 #define JPU_JPEG_QTBL_CHR_OFFSET 0x4c 59 #define JPU_JPEG_HDCTBL_LUM_OFFSET 0xa4 60 #define JPU_JPEG_HACTBL_LUM_OFFSET 0xc5 61 #define JPU_JPEG_HDCTBL_CHR_OFFSET 0x17c 62 #define JPU_JPEG_HACTBL_CHR_OFFSET 0x19d 63 #define JPU_JPEG_PADDING_OFFSET 0x24f 64 #define JPU_JPEG_LUM 0x00 65 #define JPU_JPEG_CHR 0x01 66 #define JPU_JPEG_DC 0x00 67 #define JPU_JPEG_AC 0x10 68 69 #define JPU_JPEG_422 0x21 70 #define JPU_JPEG_420 0x22 71 72 #define JPU_JPEG_DEFAULT_422_PIX_FMT V4L2_PIX_FMT_NV16M 73 #define JPU_JPEG_DEFAULT_420_PIX_FMT V4L2_PIX_FMT_NV12M 74 75 #define JPU_RESET_TIMEOUT 100 /* ms */ 76 #define JPU_JOB_TIMEOUT 300 /* ms */ 77 #define JPU_MAX_QUALITY 4 78 #define JPU_WIDTH_MIN 16 79 #define JPU_HEIGHT_MIN 16 80 #define JPU_WIDTH_MAX 4096 81 #define JPU_HEIGHT_MAX 4096 82 #define JPU_MEMALIGN 8 83 84 /* Flags that indicate a format can be used for capture/output */ 85 #define JPU_FMT_TYPE_OUTPUT 0 86 #define JPU_FMT_TYPE_CAPTURE 1 87 #define JPU_ENC_CAPTURE (1 << 0) 88 #define JPU_ENC_OUTPUT (1 << 1) 89 #define JPU_DEC_CAPTURE (1 << 2) 90 #define JPU_DEC_OUTPUT (1 << 3) 91 92 /* 93 * JPEG registers and bits 94 */ 95 96 /* JPEG code mode register */ 97 #define JCMOD 0x00 98 #define JCMOD_PCTR (1 << 7) 99 #define JCMOD_MSKIP_ENABLE (1 << 5) 100 #define JCMOD_DSP_ENC (0 << 3) 101 #define JCMOD_DSP_DEC (1 << 3) 102 #define JCMOD_REDU (7 << 0) 103 #define JCMOD_REDU_422 (1 << 0) 104 #define JCMOD_REDU_420 (2 << 0) 105 106 /* JPEG code command register */ 107 #define JCCMD 0x04 108 #define JCCMD_SRST (1 << 12) 109 #define JCCMD_JEND (1 << 2) 110 #define JCCMD_JSRT (1 << 0) 111 112 /* JPEG code quantization table number register */ 113 #define JCQTN 0x0c 114 #define JCQTN_SHIFT(t) (((t) - 1) << 1) 115 116 /* JPEG code Huffman table number register */ 117 #define JCHTN 0x10 118 #define JCHTN_AC_SHIFT(t) (((t) << 1) - 1) 119 #define JCHTN_DC_SHIFT(t) (((t) - 1) << 1) 120 121 #define JCVSZU 0x1c /* JPEG code vertical size upper register */ 122 #define JCVSZD 0x20 /* JPEG code vertical size lower register */ 123 #define JCHSZU 0x24 /* JPEG code horizontal size upper register */ 124 #define JCHSZD 0x28 /* JPEG code horizontal size lower register */ 125 #define JCSZ_MASK 0xff /* JPEG code h/v size register contains only 1 byte*/ 126 127 #define JCDTCU 0x2c /* JPEG code data count upper register */ 128 #define JCDTCM 0x30 /* JPEG code data count middle register */ 129 #define JCDTCD 0x34 /* JPEG code data count lower register */ 130 131 /* JPEG interrupt enable register */ 132 #define JINTE 0x38 133 #define JINTE_ERR (7 << 5) /* INT5 + INT6 + INT7 */ 134 #define JINTE_TRANSF_COMPL (1 << 10) 135 136 /* JPEG interrupt status register */ 137 #define JINTS 0x3c 138 #define JINTS_MASK 0x7c68 139 #define JINTS_ERR (1 << 5) 140 #define JINTS_PROCESS_COMPL (1 << 6) 141 #define JINTS_TRANSF_COMPL (1 << 10) 142 143 #define JCDERR 0x40 /* JPEG code decode error register */ 144 #define JCDERR_MASK 0xf /* JPEG code decode error register mask*/ 145 146 /* JPEG interface encoding */ 147 #define JIFECNT 0x70 148 #define JIFECNT_INFT_422 0 149 #define JIFECNT_INFT_420 1 150 #define JIFECNT_SWAP_WB (3 << 4) /* to JPU */ 151 152 #define JIFESYA1 0x74 /* encode source Y address register 1 */ 153 #define JIFESCA1 0x78 /* encode source C address register 1 */ 154 #define JIFESYA2 0x7c /* encode source Y address register 2 */ 155 #define JIFESCA2 0x80 /* encode source C address register 2 */ 156 #define JIFESMW 0x84 /* encode source memory width register */ 157 #define JIFESVSZ 0x88 /* encode source vertical size register */ 158 #define JIFESHSZ 0x8c /* encode source horizontal size register */ 159 #define JIFEDA1 0x90 /* encode destination address register 1 */ 160 #define JIFEDA2 0x94 /* encode destination address register 2 */ 161 162 /* JPEG decoding control register */ 163 #define JIFDCNT 0xa0 164 #define JIFDCNT_SWAP_WB (3 << 1) /* from JPU */ 165 166 #define JIFDSA1 0xa4 /* decode source address register 1 */ 167 #define JIFDDMW 0xb0 /* decode destination memory width register */ 168 #define JIFDDVSZ 0xb4 /* decode destination vert. size register */ 169 #define JIFDDHSZ 0xb8 /* decode destination horiz. size register */ 170 #define JIFDDYA1 0xbc /* decode destination Y address register 1 */ 171 #define JIFDDCA1 0xc0 /* decode destination C address register 1 */ 172 173 #define JCQTBL(n) (0x10000 + (n) * 0x40) /* quantization tables regs */ 174 #define JCHTBD(n) (0x10100 + (n) * 0x100) /* Huffman table DC regs */ 175 #define JCHTBA(n) (0x10120 + (n) * 0x100) /* Huffman table AC regs */ 176 177 /** 178 * struct jpu - JPEG IP abstraction 179 * @mutex: the mutex protecting this structure 180 * @lock: spinlock protecting the device contexts 181 * @v4l2_dev: v4l2 device for mem2mem mode 182 * @vfd_encoder: video device node for encoder mem2mem mode 183 * @vfd_decoder: video device node for decoder mem2mem mode 184 * @m2m_dev: v4l2 mem2mem device data 185 * @curr: pointer to current context 186 * @regs: JPEG IP registers mapping 187 * @irq: JPEG IP irq 188 * @clk: JPEG IP clock 189 * @dev: JPEG IP struct device 190 * @ref_count: reference counter 191 */ 192 struct jpu { 193 struct mutex mutex; 194 spinlock_t lock; 195 struct v4l2_device v4l2_dev; 196 struct video_device vfd_encoder; 197 struct video_device vfd_decoder; 198 struct v4l2_m2m_dev *m2m_dev; 199 struct jpu_ctx *curr; 200 201 void __iomem *regs; 202 unsigned int irq; 203 struct clk *clk; 204 struct device *dev; 205 int ref_count; 206 }; 207 208 /** 209 * struct jpu_buffer - driver's specific video buffer 210 * @buf: m2m buffer 211 * @compr_quality: destination image quality in compression mode 212 * @subsampling: source image subsampling in decompression mode 213 */ 214 struct jpu_buffer { 215 struct v4l2_m2m_buffer buf; 216 unsigned short compr_quality; 217 unsigned char subsampling; 218 }; 219 220 /** 221 * struct jpu_fmt - driver's internal format data 222 * @fourcc: the fourcc code, 0 if not applicable 223 * @colorspace: the colorspace specifier 224 * @bpp: number of bits per pixel per plane 225 * @h_align: horizontal alignment order (align to 2^h_align) 226 * @v_align: vertical alignment order (align to 2^v_align) 227 * @subsampling: (horizontal:4 | vertical:4) subsampling factor 228 * @num_planes: number of planes 229 * @types: types of queue this format is applicable to 230 */ 231 struct jpu_fmt { 232 u32 fourcc; 233 u32 colorspace; 234 u8 bpp[2]; 235 u8 h_align; 236 u8 v_align; 237 u8 subsampling; 238 u8 num_planes; 239 u16 types; 240 }; 241 242 /** 243 * struct jpu_q_data - parameters of one queue 244 * @fmtinfo: driver-specific format of this queue 245 * @format: multiplanar format of this queue 246 * @sequence: sequence number 247 */ 248 struct jpu_q_data { 249 struct jpu_fmt *fmtinfo; 250 struct v4l2_pix_format_mplane format; 251 unsigned int sequence; 252 }; 253 254 /** 255 * struct jpu_ctx - the device context data 256 * @jpu: JPEG IP device for this context 257 * @encoder: compression (encode) operation or decompression (decode) 258 * @compr_quality: destination image quality in compression (encode) mode 259 * @out_q: source (output) queue information 260 * @cap_q: destination (capture) queue information 261 * @fh: file handler 262 * @ctrl_handler: controls handler 263 */ 264 struct jpu_ctx { 265 struct jpu *jpu; 266 bool encoder; 267 unsigned short compr_quality; 268 struct jpu_q_data out_q; 269 struct jpu_q_data cap_q; 270 struct v4l2_fh fh; 271 struct v4l2_ctrl_handler ctrl_handler; 272 }; 273 274 /** 275 * jpeg_buffer - description of memory containing input JPEG data 276 * @end: end position in the buffer 277 * @curr: current position in the buffer 278 */ 279 struct jpeg_buffer { 280 void *end; 281 void *curr; 282 }; 283 284 static struct jpu_fmt jpu_formats[] = { 285 { V4L2_PIX_FMT_JPEG, V4L2_COLORSPACE_JPEG, 286 {0, 0}, 0, 0, 0, 1, JPU_ENC_CAPTURE | JPU_DEC_OUTPUT }, 287 { V4L2_PIX_FMT_NV16M, V4L2_COLORSPACE_SRGB, 288 {8, 8}, 2, 2, JPU_JPEG_422, 2, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE }, 289 { V4L2_PIX_FMT_NV12M, V4L2_COLORSPACE_SRGB, 290 {8, 4}, 2, 2, JPU_JPEG_420, 2, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE }, 291 { V4L2_PIX_FMT_NV16, V4L2_COLORSPACE_SRGB, 292 {16, 0}, 2, 2, JPU_JPEG_422, 1, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE }, 293 { V4L2_PIX_FMT_NV12, V4L2_COLORSPACE_SRGB, 294 {12, 0}, 2, 2, JPU_JPEG_420, 1, JPU_ENC_OUTPUT | JPU_DEC_CAPTURE }, 295 }; 296 297 static const u8 zigzag[] = { 298 0x03, 0x02, 0x0b, 0x13, 0x0a, 0x01, 0x00, 0x09, 299 0x12, 0x1b, 0x23, 0x1a, 0x11, 0x08, 0x07, 0x06, 300 0x0f, 0x10, 0x19, 0x22, 0x2b, 0x33, 0x2a, 0x21, 301 0x18, 0x17, 0x0e, 0x05, 0x04, 0x0d, 0x16, 0x1f, 302 0x20, 0x29, 0x32, 0x3b, 0x3a, 0x31, 0x28, 0x27, 303 0x1e, 0x15, 0x0e, 0x14, 0x10, 0x26, 0x2f, 0x30, 304 0x39, 0x38, 0x37, 0x2e, 0x25, 0x1c, 0x24, 0x2b, 305 0x36, 0x3f, 0x3e, 0x35, 0x2c, 0x34, 0x3d, 0x3c 306 }; 307 308 #define QTBL_SIZE (ALIGN(JPU_JPEG_QTBL_SIZE, \ 309 sizeof(unsigned int)) / sizeof(unsigned int)) 310 #define HDCTBL_SIZE (ALIGN(JPU_JPEG_HDCTBL_SIZE, \ 311 sizeof(unsigned int)) / sizeof(unsigned int)) 312 #define HACTBL_SIZE (ALIGN(JPU_JPEG_HACTBL_SIZE, \ 313 sizeof(unsigned int)) / sizeof(unsigned int)) 314 /* 315 * Start of image; Quantization tables 316 * SOF0 (17 bytes payload) is Baseline DCT - Sample precision, height, width, 317 * Number of image components, (Ci:8 - Hi:4 - Vi:4 - Tq:8) * 3 - Y,Cb,Cr; 318 * Huffman tables; Padding with 0xff (33.3.27 R01UH0501EJ0100 Rev.1.00) 319 */ 320 #define JPU_JPEG_HDR_BLOB { \ 321 0xff, JPEG_MARKER_SOI, 0xff, JPEG_MARKER_DQT, 0x00, \ 322 JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_LUM, \ 323 [JPU_JPEG_QTBL_LUM_OFFSET ... \ 324 JPU_JPEG_QTBL_LUM_OFFSET + JPU_JPEG_QTBL_SIZE - 1] = 0x00, \ 325 0xff, JPEG_MARKER_DQT, 0x00, JPU_JPEG_QTBL_SIZE + 0x3, JPU_JPEG_CHR, \ 326 [JPU_JPEG_QTBL_CHR_OFFSET ... JPU_JPEG_QTBL_CHR_OFFSET + \ 327 JPU_JPEG_QTBL_SIZE - 1] = 0x00, \ 328 0xff, JPEG_MARKER_SOF0, 0x00, 0x11, 0x08, \ 329 [JPU_JPEG_HEIGHT_OFFSET ... JPU_JPEG_HEIGHT_OFFSET + 1] = 0x00, \ 330 [JPU_JPEG_WIDTH_OFFSET ... JPU_JPEG_WIDTH_OFFSET + 1] = 0x00, \ 331 0x03, 0x01, [JPU_JPEG_SUBS_OFFSET] = 0x00, JPU_JPEG_LUM, \ 332 0x02, 0x11, JPU_JPEG_CHR, 0x03, 0x11, JPU_JPEG_CHR, \ 333 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, \ 334 JPU_JPEG_LUM | JPU_JPEG_DC, \ 335 [JPU_JPEG_HDCTBL_LUM_OFFSET ... \ 336 JPU_JPEG_HDCTBL_LUM_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \ 337 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, \ 338 JPU_JPEG_LUM | JPU_JPEG_AC, \ 339 [JPU_JPEG_HACTBL_LUM_OFFSET ... \ 340 JPU_JPEG_HACTBL_LUM_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \ 341 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HDCTBL_SIZE + 0x3, \ 342 JPU_JPEG_CHR | JPU_JPEG_DC, \ 343 [JPU_JPEG_HDCTBL_CHR_OFFSET ... \ 344 JPU_JPEG_HDCTBL_CHR_OFFSET + JPU_JPEG_HDCTBL_SIZE - 1] = 0x00, \ 345 0xff, JPEG_MARKER_DHT, 0x00, JPU_JPEG_HACTBL_SIZE + 0x3, \ 346 JPU_JPEG_CHR | JPU_JPEG_AC, \ 347 [JPU_JPEG_HACTBL_CHR_OFFSET ... \ 348 JPU_JPEG_HACTBL_CHR_OFFSET + JPU_JPEG_HACTBL_SIZE - 1] = 0x00, \ 349 [JPU_JPEG_PADDING_OFFSET ... JPU_JPEG_HDR_SIZE - 1] = 0xff \ 350 } 351 352 static unsigned char jpeg_hdrs[JPU_MAX_QUALITY][JPU_JPEG_HDR_SIZE] = { 353 [0 ... JPU_MAX_QUALITY - 1] = JPU_JPEG_HDR_BLOB 354 }; 355 356 static const unsigned int qtbl_lum[JPU_MAX_QUALITY][QTBL_SIZE] = { 357 { 358 0x14101927, 0x322e3e44, 0x10121726, 0x26354144, 359 0x19171f26, 0x35414444, 0x27262635, 0x41444444, 360 0x32263541, 0x44444444, 0x2e354144, 0x44444444, 361 0x3e414444, 0x44444444, 0x44444444, 0x44444444 362 }, 363 { 364 0x100b0b10, 0x171b1f1e, 0x0b0c0c0f, 0x1417171e, 365 0x0b0c0d10, 0x171a232f, 0x100f1017, 0x1a252f40, 366 0x1714171a, 0x27334040, 0x1b171a25, 0x33404040, 367 0x1f17232f, 0x40404040, 0x1e1e2f40, 0x40404040 368 }, 369 { 370 0x0c08080c, 0x11151817, 0x0809090b, 0x0f131217, 371 0x08090a0c, 0x13141b24, 0x0c0b0c15, 0x141c2435, 372 0x110f1314, 0x1e27333b, 0x1513141c, 0x27333b3b, 373 0x18121b24, 0x333b3b3b, 0x17172435, 0x3b3b3b3b 374 }, 375 { 376 0x08060608, 0x0c0e1011, 0x06060608, 0x0a0d0c0f, 377 0x06060708, 0x0d0e1218, 0x0808080e, 0x0d131823, 378 0x0c0a0d0d, 0x141a2227, 0x0e0d0e13, 0x1a222727, 379 0x100c1318, 0x22272727, 0x110f1823, 0x27272727 380 } 381 }; 382 383 static const unsigned int qtbl_chr[JPU_MAX_QUALITY][QTBL_SIZE] = { 384 { 385 0x15192026, 0x36444444, 0x191c1826, 0x36444444, 386 0x2018202b, 0x42444444, 0x26262b35, 0x44444444, 387 0x36424444, 0x44444444, 0x44444444, 0x44444444, 388 0x44444444, 0x44444444, 0x44444444, 0x44444444 389 }, 390 { 391 0x110f1115, 0x141a2630, 0x0f131211, 0x141a232b, 392 0x11121416, 0x1a1e2e35, 0x1511161c, 0x1e273540, 393 0x14141a1e, 0x27304040, 0x1a1a1e27, 0x303f4040, 394 0x26232e35, 0x40404040, 0x302b3540, 0x40404040 395 }, 396 { 397 0x0d0b0d10, 0x14141d25, 0x0b0e0e0e, 0x10141a20, 398 0x0d0e0f11, 0x14172328, 0x100e1115, 0x171e2832, 399 0x14101417, 0x1e25323b, 0x1414171e, 0x25303b3b, 400 0x1d1a2328, 0x323b3b3b, 0x25202832, 0x3b3b3b3b 401 }, 402 { 403 0x0908090b, 0x0e111318, 0x080a090b, 0x0e0d1116, 404 0x09090d0e, 0x0d0f171a, 0x0b0b0e0e, 0x0f141a21, 405 0x0e0e0d0f, 0x14182127, 0x110d0f14, 0x18202727, 406 0x1311171a, 0x21272727, 0x18161a21, 0x27272727 407 } 408 }; 409 410 static const unsigned int hdctbl_lum[HDCTBL_SIZE] = { 411 0x00010501, 0x01010101, 0x01000000, 0x00000000, 412 0x00010203, 0x04050607, 0x08090a0b 413 }; 414 415 static const unsigned int hdctbl_chr[HDCTBL_SIZE] = { 416 0x00010501, 0x01010101, 0x01000000, 0x00000000, 417 0x00010203, 0x04050607, 0x08090a0b 418 }; 419 420 static const unsigned int hactbl_lum[HACTBL_SIZE] = { 421 0x00020103, 0x03020403, 0x05050404, 0x0000017d, 0x01020300, 0x04110512, 422 0x21314106, 0x13516107, 0x22711432, 0x8191a108, 0x2342b1c1, 0x1552d1f0, 423 0x24336272, 0x82090a16, 0x1718191a, 0x25262728, 0x292a3435, 0x36373839, 424 0x3a434445, 0x46474849, 0x4a535455, 0x56575859, 0x5a636465, 0x66676869, 425 0x6a737475, 0x76777879, 0x7a838485, 0x86878889, 0x8a929394, 0x95969798, 426 0x999aa2a3, 0xa4a5a6a7, 0xa8a9aab2, 0xb3b4b5b6, 0xb7b8b9ba, 0xc2c3c4c5, 427 0xc6c7c8c9, 0xcad2d3d4, 0xd5d6d7d8, 0xd9dae1e2, 0xe3e4e5e6, 0xe7e8e9ea, 428 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fa0000 429 }; 430 431 static const unsigned int hactbl_chr[HACTBL_SIZE] = { 432 0x00020103, 0x03020403, 0x05050404, 0x0000017d, 0x01020300, 0x04110512, 433 0x21314106, 0x13516107, 0x22711432, 0x8191a108, 0x2342b1c1, 0x1552d1f0, 434 0x24336272, 0x82090a16, 0x1718191a, 0x25262728, 0x292a3435, 0x36373839, 435 0x3a434445, 0x46474849, 0x4a535455, 0x56575859, 0x5a636465, 0x66676869, 436 0x6a737475, 0x76777879, 0x7a838485, 0x86878889, 0x8a929394, 0x95969798, 437 0x999aa2a3, 0xa4a5a6a7, 0xa8a9aab2, 0xb3b4b5b6, 0xb7b8b9ba, 0xc2c3c4c5, 438 0xc6c7c8c9, 0xcad2d3d4, 0xd5d6d7d8, 0xd9dae1e2, 0xe3e4e5e6, 0xe7e8e9ea, 439 0xf1f2f3f4, 0xf5f6f7f8, 0xf9fa0000 440 }; 441 442 static const char *error_to_text[16] = { 443 "Normal", 444 "SOI not detected", 445 "SOF1 to SOFF detected", 446 "Subsampling not detected", 447 "SOF accuracy error", 448 "DQT accuracy error", 449 "Component error 1", 450 "Component error 2", 451 "SOF0, DQT, and DHT not detected when SOS detected", 452 "SOS not detected", 453 "EOI not detected", 454 "Restart interval data number error detected", 455 "Image size error", 456 "Last MCU data number error", 457 "Block data number error", 458 "Unknown" 459 }; 460 461 static struct jpu_buffer *vb2_to_jpu_buffer(struct vb2_v4l2_buffer *vb) 462 { 463 struct v4l2_m2m_buffer *b = 464 container_of(vb, struct v4l2_m2m_buffer, vb); 465 466 return container_of(b, struct jpu_buffer, buf); 467 } 468 469 static u32 jpu_read(struct jpu *jpu, unsigned int reg) 470 { 471 return ioread32(jpu->regs + reg); 472 } 473 474 static void jpu_write(struct jpu *jpu, u32 val, unsigned int reg) 475 { 476 iowrite32(val, jpu->regs + reg); 477 } 478 479 static struct jpu_ctx *ctrl_to_ctx(struct v4l2_ctrl *c) 480 { 481 return container_of(c->handler, struct jpu_ctx, ctrl_handler); 482 } 483 484 static struct jpu_ctx *fh_to_ctx(struct v4l2_fh *fh) 485 { 486 return container_of(fh, struct jpu_ctx, fh); 487 } 488 489 static void jpu_set_tbl(struct jpu *jpu, u32 reg, const unsigned int *tbl, 490 unsigned int len) { 491 unsigned int i; 492 493 for (i = 0; i < len; i++) 494 jpu_write(jpu, tbl[i], reg + (i << 2)); 495 } 496 497 static void jpu_set_qtbl(struct jpu *jpu, unsigned short quality) 498 { 499 jpu_set_tbl(jpu, JCQTBL(0), qtbl_lum[quality], QTBL_SIZE); 500 jpu_set_tbl(jpu, JCQTBL(1), qtbl_chr[quality], QTBL_SIZE); 501 } 502 503 static void jpu_set_htbl(struct jpu *jpu) 504 { 505 jpu_set_tbl(jpu, JCHTBD(0), hdctbl_lum, HDCTBL_SIZE); 506 jpu_set_tbl(jpu, JCHTBA(0), hactbl_lum, HACTBL_SIZE); 507 jpu_set_tbl(jpu, JCHTBD(1), hdctbl_chr, HDCTBL_SIZE); 508 jpu_set_tbl(jpu, JCHTBA(1), hactbl_chr, HACTBL_SIZE); 509 } 510 511 static int jpu_wait_reset(struct jpu *jpu) 512 { 513 unsigned long timeout; 514 515 timeout = jiffies + msecs_to_jiffies(JPU_RESET_TIMEOUT); 516 517 while (jpu_read(jpu, JCCMD) & JCCMD_SRST) { 518 if (time_after(jiffies, timeout)) { 519 dev_err(jpu->dev, "timed out in reset\n"); 520 return -ETIMEDOUT; 521 } 522 schedule(); 523 } 524 525 return 0; 526 } 527 528 static int jpu_reset(struct jpu *jpu) 529 { 530 jpu_write(jpu, JCCMD_SRST, JCCMD); 531 return jpu_wait_reset(jpu); 532 } 533 534 /* 535 * ============================================================================ 536 * video ioctl operations 537 * ============================================================================ 538 */ 539 static void put_qtbl(u8 *p, const u8 *qtbl) 540 { 541 unsigned int i; 542 543 for (i = 0; i < ARRAY_SIZE(zigzag); i++) 544 p[i] = *(qtbl + zigzag[i]); 545 } 546 547 static void put_htbl(u8 *p, const u8 *htbl, unsigned int len) 548 { 549 unsigned int i, j; 550 551 for (i = 0; i < len; i += 4) 552 for (j = 0; j < 4 && (i + j) < len; ++j) 553 p[i + j] = htbl[i + 3 - j]; 554 } 555 556 static void jpu_generate_hdr(unsigned short quality, unsigned char *p) 557 { 558 put_qtbl(p + JPU_JPEG_QTBL_LUM_OFFSET, (const u8 *)qtbl_lum[quality]); 559 put_qtbl(p + JPU_JPEG_QTBL_CHR_OFFSET, (const u8 *)qtbl_chr[quality]); 560 561 put_htbl(p + JPU_JPEG_HDCTBL_LUM_OFFSET, (const u8 *)hdctbl_lum, 562 JPU_JPEG_HDCTBL_SIZE); 563 put_htbl(p + JPU_JPEG_HACTBL_LUM_OFFSET, (const u8 *)hactbl_lum, 564 JPU_JPEG_HACTBL_SIZE); 565 566 put_htbl(p + JPU_JPEG_HDCTBL_CHR_OFFSET, (const u8 *)hdctbl_chr, 567 JPU_JPEG_HDCTBL_SIZE); 568 put_htbl(p + JPU_JPEG_HACTBL_CHR_OFFSET, (const u8 *)hactbl_chr, 569 JPU_JPEG_HACTBL_SIZE); 570 } 571 572 static int get_byte(struct jpeg_buffer *buf) 573 { 574 if (buf->curr >= buf->end) 575 return -1; 576 577 return *(u8 *)buf->curr++; 578 } 579 580 static int get_word_be(struct jpeg_buffer *buf, unsigned int *word) 581 { 582 if (buf->end - buf->curr < 2) 583 return -1; 584 585 *word = get_unaligned_be16(buf->curr); 586 buf->curr += 2; 587 588 return 0; 589 } 590 591 static void skip(struct jpeg_buffer *buf, unsigned long len) 592 { 593 buf->curr += min((unsigned long)(buf->end - buf->curr), len); 594 } 595 596 static u8 jpu_parse_hdr(void *buffer, unsigned long size, unsigned int *width, 597 unsigned int *height) 598 { 599 struct jpeg_buffer jpeg_buffer; 600 unsigned int word; 601 bool soi = false; 602 603 jpeg_buffer.end = buffer + size; 604 jpeg_buffer.curr = buffer; 605 606 /* 607 * basic size check and EOI - we don't want to let JPU cross 608 * buffer bounds in any case. Hope it's stopping by EOI. 609 */ 610 if (size < JPU_JPEG_MIN_SIZE || 611 *(u8 *)(buffer + size - 1) != JPEG_MARKER_EOI) 612 return 0; 613 614 for (;;) { 615 int c; 616 617 /* skip preceding filler bytes */ 618 do 619 c = get_byte(&jpeg_buffer); 620 while (c == 0xff || c == 0); 621 622 if (!soi && c == JPEG_MARKER_SOI) { 623 soi = true; 624 continue; 625 } else if (soi != (c != JPEG_MARKER_SOI)) 626 return 0; 627 628 switch (c) { 629 case JPEG_MARKER_SOF0: /* SOF0: baseline JPEG */ 630 skip(&jpeg_buffer, 3); /* segment length and bpp */ 631 if (get_word_be(&jpeg_buffer, height) || 632 get_word_be(&jpeg_buffer, width) || 633 get_byte(&jpeg_buffer) != 3) /* YCbCr only */ 634 return 0; 635 636 skip(&jpeg_buffer, 1); 637 return get_byte(&jpeg_buffer); 638 case JPEG_MARKER_DHT: 639 case JPEG_MARKER_DQT: 640 case JPEG_MARKER_COM: 641 case JPEG_MARKER_DRI: 642 case JPEG_MARKER_APP0 ... JPEG_MARKER_APP0 + 0x0f: 643 if (get_word_be(&jpeg_buffer, &word)) 644 return 0; 645 skip(&jpeg_buffer, (long)word - 2); 646 break; 647 case 0: 648 break; 649 default: 650 return 0; 651 } 652 } 653 654 return 0; 655 } 656 657 static int jpu_querycap(struct file *file, void *priv, 658 struct v4l2_capability *cap) 659 { 660 struct jpu_ctx *ctx = fh_to_ctx(priv); 661 662 if (ctx->encoder) 663 strscpy(cap->card, DRV_NAME " encoder", sizeof(cap->card)); 664 else 665 strscpy(cap->card, DRV_NAME " decoder", sizeof(cap->card)); 666 667 strscpy(cap->driver, DRV_NAME, sizeof(cap->driver)); 668 memset(cap->reserved, 0, sizeof(cap->reserved)); 669 670 return 0; 671 } 672 673 static struct jpu_fmt *jpu_find_format(bool encoder, u32 pixelformat, 674 unsigned int fmt_type) 675 { 676 unsigned int i, fmt_flag; 677 678 if (encoder) 679 fmt_flag = fmt_type == JPU_FMT_TYPE_OUTPUT ? JPU_ENC_OUTPUT : 680 JPU_ENC_CAPTURE; 681 else 682 fmt_flag = fmt_type == JPU_FMT_TYPE_OUTPUT ? JPU_DEC_OUTPUT : 683 JPU_DEC_CAPTURE; 684 685 for (i = 0; i < ARRAY_SIZE(jpu_formats); i++) { 686 struct jpu_fmt *fmt = &jpu_formats[i]; 687 688 if (fmt->fourcc == pixelformat && fmt->types & fmt_flag) 689 return fmt; 690 } 691 692 return NULL; 693 } 694 695 static int jpu_enum_fmt(struct v4l2_fmtdesc *f, u32 type) 696 { 697 unsigned int i, num = 0; 698 699 for (i = 0; i < ARRAY_SIZE(jpu_formats); ++i) { 700 if (jpu_formats[i].types & type) { 701 if (num == f->index) 702 break; 703 ++num; 704 } 705 } 706 707 if (i >= ARRAY_SIZE(jpu_formats)) 708 return -EINVAL; 709 710 f->pixelformat = jpu_formats[i].fourcc; 711 712 return 0; 713 } 714 715 static int jpu_enum_fmt_cap(struct file *file, void *priv, 716 struct v4l2_fmtdesc *f) 717 { 718 struct jpu_ctx *ctx = fh_to_ctx(priv); 719 720 return jpu_enum_fmt(f, ctx->encoder ? JPU_ENC_CAPTURE : 721 JPU_DEC_CAPTURE); 722 } 723 724 static int jpu_enum_fmt_out(struct file *file, void *priv, 725 struct v4l2_fmtdesc *f) 726 { 727 struct jpu_ctx *ctx = fh_to_ctx(priv); 728 729 return jpu_enum_fmt(f, ctx->encoder ? JPU_ENC_OUTPUT : JPU_DEC_OUTPUT); 730 } 731 732 static struct jpu_q_data *jpu_get_q_data(struct jpu_ctx *ctx, 733 enum v4l2_buf_type type) 734 { 735 if (V4L2_TYPE_IS_OUTPUT(type)) 736 return &ctx->out_q; 737 else 738 return &ctx->cap_q; 739 } 740 741 static void jpu_bound_align_image(u32 *w, unsigned int w_min, 742 unsigned int w_max, unsigned int w_align, 743 u32 *h, unsigned int h_min, 744 unsigned int h_max, unsigned int h_align) 745 { 746 unsigned int width, height, w_step, h_step; 747 748 width = *w; 749 height = *h; 750 751 w_step = 1U << w_align; 752 h_step = 1U << h_align; 753 v4l_bound_align_image(w, w_min, w_max, w_align, h, h_min, h_max, 754 h_align, 3); 755 756 if (*w < width && *w + w_step < w_max) 757 *w += w_step; 758 if (*h < height && *h + h_step < h_max) 759 *h += h_step; 760 } 761 762 static int __jpu_try_fmt(struct jpu_ctx *ctx, struct jpu_fmt **fmtinfo, 763 struct v4l2_pix_format_mplane *pix, 764 enum v4l2_buf_type type) 765 { 766 struct jpu_fmt *fmt; 767 unsigned int f_type, w, h; 768 769 f_type = V4L2_TYPE_IS_OUTPUT(type) ? JPU_FMT_TYPE_OUTPUT : 770 JPU_FMT_TYPE_CAPTURE; 771 772 fmt = jpu_find_format(ctx->encoder, pix->pixelformat, f_type); 773 if (!fmt) { 774 unsigned int pixelformat; 775 776 dev_dbg(ctx->jpu->dev, "unknown format; set default format\n"); 777 if (ctx->encoder) 778 pixelformat = f_type == JPU_FMT_TYPE_OUTPUT ? 779 V4L2_PIX_FMT_NV16M : V4L2_PIX_FMT_JPEG; 780 else 781 pixelformat = f_type == JPU_FMT_TYPE_CAPTURE ? 782 V4L2_PIX_FMT_NV16M : V4L2_PIX_FMT_JPEG; 783 fmt = jpu_find_format(ctx->encoder, pixelformat, f_type); 784 } 785 786 pix->pixelformat = fmt->fourcc; 787 pix->colorspace = fmt->colorspace; 788 pix->field = V4L2_FIELD_NONE; 789 pix->num_planes = fmt->num_planes; 790 791 jpu_bound_align_image(&pix->width, JPU_WIDTH_MIN, JPU_WIDTH_MAX, 792 fmt->h_align, &pix->height, JPU_HEIGHT_MIN, 793 JPU_HEIGHT_MAX, fmt->v_align); 794 795 w = pix->width; 796 h = pix->height; 797 798 if (fmt->fourcc == V4L2_PIX_FMT_JPEG) { 799 /* ignore userspaces's sizeimage for encoding */ 800 if (pix->plane_fmt[0].sizeimage <= 0 || ctx->encoder) 801 pix->plane_fmt[0].sizeimage = JPU_JPEG_HDR_SIZE + 802 (JPU_JPEG_MAX_BYTES_PER_PIXEL * w * h); 803 pix->plane_fmt[0].bytesperline = 0; 804 } else { 805 unsigned int i, bpl = 0; 806 807 for (i = 0; i < pix->num_planes; ++i) 808 bpl = max(bpl, pix->plane_fmt[i].bytesperline); 809 810 bpl = clamp_t(unsigned int, bpl, w, JPU_WIDTH_MAX); 811 bpl = round_up(bpl, JPU_MEMALIGN); 812 813 for (i = 0; i < pix->num_planes; ++i) { 814 pix->plane_fmt[i].bytesperline = bpl; 815 pix->plane_fmt[i].sizeimage = bpl * h * fmt->bpp[i] / 8; 816 } 817 } 818 819 if (fmtinfo) 820 *fmtinfo = fmt; 821 822 return 0; 823 } 824 825 static int jpu_try_fmt(struct file *file, void *priv, struct v4l2_format *f) 826 { 827 struct jpu_ctx *ctx = fh_to_ctx(priv); 828 829 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type)) 830 return -EINVAL; 831 832 return __jpu_try_fmt(ctx, NULL, &f->fmt.pix_mp, f->type); 833 } 834 835 static int jpu_s_fmt(struct file *file, void *priv, struct v4l2_format *f) 836 { 837 struct vb2_queue *vq; 838 struct jpu_ctx *ctx = fh_to_ctx(priv); 839 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 840 struct jpu_fmt *fmtinfo; 841 struct jpu_q_data *q_data; 842 int ret; 843 844 vq = v4l2_m2m_get_vq(m2m_ctx, f->type); 845 if (!vq) 846 return -EINVAL; 847 848 if (vb2_is_busy(vq)) { 849 v4l2_err(&ctx->jpu->v4l2_dev, "%s queue busy\n", __func__); 850 return -EBUSY; 851 } 852 853 ret = __jpu_try_fmt(ctx, &fmtinfo, &f->fmt.pix_mp, f->type); 854 if (ret < 0) 855 return ret; 856 857 q_data = jpu_get_q_data(ctx, f->type); 858 859 q_data->format = f->fmt.pix_mp; 860 q_data->fmtinfo = fmtinfo; 861 862 return 0; 863 } 864 865 static int jpu_g_fmt(struct file *file, void *priv, struct v4l2_format *f) 866 { 867 struct jpu_q_data *q_data; 868 struct jpu_ctx *ctx = fh_to_ctx(priv); 869 870 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type)) 871 return -EINVAL; 872 873 q_data = jpu_get_q_data(ctx, f->type); 874 f->fmt.pix_mp = q_data->format; 875 876 return 0; 877 } 878 879 /* 880 * V4L2 controls 881 */ 882 static int jpu_s_ctrl(struct v4l2_ctrl *ctrl) 883 { 884 struct jpu_ctx *ctx = ctrl_to_ctx(ctrl); 885 unsigned long flags; 886 887 spin_lock_irqsave(&ctx->jpu->lock, flags); 888 if (ctrl->id == V4L2_CID_JPEG_COMPRESSION_QUALITY) 889 ctx->compr_quality = ctrl->val; 890 spin_unlock_irqrestore(&ctx->jpu->lock, flags); 891 892 return 0; 893 } 894 895 static const struct v4l2_ctrl_ops jpu_ctrl_ops = { 896 .s_ctrl = jpu_s_ctrl, 897 }; 898 899 static int jpu_streamon(struct file *file, void *priv, enum v4l2_buf_type type) 900 { 901 struct jpu_ctx *ctx = fh_to_ctx(priv); 902 struct jpu_q_data *src_q_data, *dst_q_data, *orig, adj, *ref; 903 enum v4l2_buf_type adj_type; 904 905 src_q_data = jpu_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 906 dst_q_data = jpu_get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 907 908 if (ctx->encoder) { 909 adj = *src_q_data; 910 orig = src_q_data; 911 ref = dst_q_data; 912 adj_type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 913 } else { 914 adj = *dst_q_data; 915 orig = dst_q_data; 916 ref = src_q_data; 917 adj_type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 918 } 919 920 adj.format.width = ref->format.width; 921 adj.format.height = ref->format.height; 922 923 __jpu_try_fmt(ctx, NULL, &adj.format, adj_type); 924 925 if (adj.format.width != orig->format.width || 926 adj.format.height != orig->format.height) { 927 dev_err(ctx->jpu->dev, "src and dst formats do not match.\n"); 928 /* maybe we can return -EPIPE here? */ 929 return -EINVAL; 930 } 931 932 return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type); 933 } 934 935 static const struct v4l2_ioctl_ops jpu_ioctl_ops = { 936 .vidioc_querycap = jpu_querycap, 937 938 .vidioc_enum_fmt_vid_cap = jpu_enum_fmt_cap, 939 .vidioc_enum_fmt_vid_out = jpu_enum_fmt_out, 940 .vidioc_g_fmt_vid_cap_mplane = jpu_g_fmt, 941 .vidioc_g_fmt_vid_out_mplane = jpu_g_fmt, 942 .vidioc_try_fmt_vid_cap_mplane = jpu_try_fmt, 943 .vidioc_try_fmt_vid_out_mplane = jpu_try_fmt, 944 .vidioc_s_fmt_vid_cap_mplane = jpu_s_fmt, 945 .vidioc_s_fmt_vid_out_mplane = jpu_s_fmt, 946 947 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 948 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 949 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 950 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 951 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 952 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 953 954 .vidioc_streamon = jpu_streamon, 955 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 956 957 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 958 .vidioc_unsubscribe_event = v4l2_event_unsubscribe 959 }; 960 961 static int jpu_controls_create(struct jpu_ctx *ctx) 962 { 963 struct v4l2_ctrl *ctrl; 964 int ret; 965 966 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 1); 967 968 ctrl = v4l2_ctrl_new_std(&ctx->ctrl_handler, &jpu_ctrl_ops, 969 V4L2_CID_JPEG_COMPRESSION_QUALITY, 970 0, JPU_MAX_QUALITY - 1, 1, 0); 971 972 if (ctx->ctrl_handler.error) { 973 ret = ctx->ctrl_handler.error; 974 goto error_free; 975 } 976 977 if (!ctx->encoder) 978 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE | 979 V4L2_CTRL_FLAG_READ_ONLY; 980 981 ret = v4l2_ctrl_handler_setup(&ctx->ctrl_handler); 982 if (ret < 0) 983 goto error_free; 984 985 return 0; 986 987 error_free: 988 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 989 return ret; 990 } 991 992 /* 993 * ============================================================================ 994 * Queue operations 995 * ============================================================================ 996 */ 997 static int jpu_queue_setup(struct vb2_queue *vq, 998 unsigned int *nbuffers, unsigned int *nplanes, 999 unsigned int sizes[], struct device *alloc_devs[]) 1000 { 1001 struct jpu_ctx *ctx = vb2_get_drv_priv(vq); 1002 struct jpu_q_data *q_data; 1003 unsigned int i; 1004 1005 q_data = jpu_get_q_data(ctx, vq->type); 1006 1007 if (*nplanes) { 1008 if (*nplanes != q_data->format.num_planes) 1009 return -EINVAL; 1010 1011 for (i = 0; i < *nplanes; i++) { 1012 unsigned int q_size = q_data->format.plane_fmt[i].sizeimage; 1013 1014 if (sizes[i] < q_size) 1015 return -EINVAL; 1016 } 1017 return 0; 1018 } 1019 1020 *nplanes = q_data->format.num_planes; 1021 1022 for (i = 0; i < *nplanes; i++) 1023 sizes[i] = q_data->format.plane_fmt[i].sizeimage; 1024 1025 return 0; 1026 } 1027 1028 static int jpu_buf_prepare(struct vb2_buffer *vb) 1029 { 1030 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1031 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1032 struct jpu_q_data *q_data; 1033 unsigned int i; 1034 1035 q_data = jpu_get_q_data(ctx, vb->vb2_queue->type); 1036 1037 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { 1038 if (vbuf->field == V4L2_FIELD_ANY) 1039 vbuf->field = V4L2_FIELD_NONE; 1040 if (vbuf->field != V4L2_FIELD_NONE) { 1041 dev_err(ctx->jpu->dev, "%s field isn't supported\n", 1042 __func__); 1043 return -EINVAL; 1044 } 1045 } 1046 1047 for (i = 0; i < q_data->format.num_planes; i++) { 1048 unsigned long size = q_data->format.plane_fmt[i].sizeimage; 1049 1050 if (vb2_plane_size(vb, i) < size) { 1051 dev_err(ctx->jpu->dev, 1052 "%s: data will not fit into plane (%lu < %lu)\n", 1053 __func__, vb2_plane_size(vb, i), size); 1054 return -EINVAL; 1055 } 1056 1057 /* decoder capture queue */ 1058 if (!ctx->encoder && V4L2_TYPE_IS_CAPTURE(vb->vb2_queue->type)) 1059 vb2_set_plane_payload(vb, i, size); 1060 } 1061 1062 return 0; 1063 } 1064 1065 static void jpu_buf_queue(struct vb2_buffer *vb) 1066 { 1067 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1068 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1069 1070 if (!ctx->encoder && V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { 1071 struct jpu_buffer *jpu_buf = vb2_to_jpu_buffer(vbuf); 1072 struct jpu_q_data *q_data, adjust; 1073 void *buffer = vb2_plane_vaddr(vb, 0); 1074 unsigned long buf_size = vb2_get_plane_payload(vb, 0); 1075 unsigned int width, height; 1076 1077 u8 subsampling = jpu_parse_hdr(buffer, buf_size, &width, 1078 &height); 1079 1080 /* check if JPEG data basic parsing was successful */ 1081 if (subsampling != JPU_JPEG_422 && subsampling != JPU_JPEG_420) 1082 goto format_error; 1083 1084 q_data = &ctx->out_q; 1085 1086 adjust = *q_data; 1087 adjust.format.width = width; 1088 adjust.format.height = height; 1089 1090 __jpu_try_fmt(ctx, &adjust.fmtinfo, &adjust.format, 1091 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 1092 1093 if (adjust.format.width != q_data->format.width || 1094 adjust.format.height != q_data->format.height) 1095 goto format_error; 1096 1097 /* 1098 * keep subsampling in buffer to check it 1099 * for compatibility in device_run 1100 */ 1101 jpu_buf->subsampling = subsampling; 1102 } 1103 1104 if (ctx->fh.m2m_ctx) 1105 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 1106 1107 return; 1108 1109 format_error: 1110 dev_err(ctx->jpu->dev, "incompatible or corrupted JPEG data\n"); 1111 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); 1112 } 1113 1114 static void jpu_buf_finish(struct vb2_buffer *vb) 1115 { 1116 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1117 struct jpu_buffer *jpu_buf = vb2_to_jpu_buffer(vbuf); 1118 struct jpu_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1119 struct jpu_q_data *q_data = &ctx->out_q; 1120 enum v4l2_buf_type type = vb->vb2_queue->type; 1121 u8 *buffer; 1122 1123 if (vb->state == VB2_BUF_STATE_DONE) 1124 vbuf->sequence = jpu_get_q_data(ctx, type)->sequence++; 1125 1126 if (!ctx->encoder || vb->state != VB2_BUF_STATE_DONE || 1127 V4L2_TYPE_IS_OUTPUT(type)) 1128 return; 1129 1130 buffer = vb2_plane_vaddr(vb, 0); 1131 1132 memcpy(buffer, jpeg_hdrs[jpu_buf->compr_quality], JPU_JPEG_HDR_SIZE); 1133 *(__be16 *)(buffer + JPU_JPEG_HEIGHT_OFFSET) = 1134 cpu_to_be16(q_data->format.height); 1135 *(__be16 *)(buffer + JPU_JPEG_WIDTH_OFFSET) = 1136 cpu_to_be16(q_data->format.width); 1137 *(buffer + JPU_JPEG_SUBS_OFFSET) = q_data->fmtinfo->subsampling; 1138 } 1139 1140 static int jpu_start_streaming(struct vb2_queue *vq, unsigned count) 1141 { 1142 struct jpu_ctx *ctx = vb2_get_drv_priv(vq); 1143 struct jpu_q_data *q_data = jpu_get_q_data(ctx, vq->type); 1144 1145 q_data->sequence = 0; 1146 return 0; 1147 } 1148 1149 static void jpu_stop_streaming(struct vb2_queue *vq) 1150 { 1151 struct jpu_ctx *ctx = vb2_get_drv_priv(vq); 1152 struct vb2_v4l2_buffer *vb; 1153 unsigned long flags; 1154 1155 for (;;) { 1156 if (V4L2_TYPE_IS_OUTPUT(vq->type)) 1157 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1158 else 1159 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1160 if (vb == NULL) 1161 return; 1162 spin_lock_irqsave(&ctx->jpu->lock, flags); 1163 v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR); 1164 spin_unlock_irqrestore(&ctx->jpu->lock, flags); 1165 } 1166 } 1167 1168 static const struct vb2_ops jpu_qops = { 1169 .queue_setup = jpu_queue_setup, 1170 .buf_prepare = jpu_buf_prepare, 1171 .buf_queue = jpu_buf_queue, 1172 .buf_finish = jpu_buf_finish, 1173 .start_streaming = jpu_start_streaming, 1174 .stop_streaming = jpu_stop_streaming, 1175 .wait_prepare = vb2_ops_wait_prepare, 1176 .wait_finish = vb2_ops_wait_finish, 1177 }; 1178 1179 static int jpu_queue_init(void *priv, struct vb2_queue *src_vq, 1180 struct vb2_queue *dst_vq) 1181 { 1182 struct jpu_ctx *ctx = priv; 1183 int ret; 1184 1185 memset(src_vq, 0, sizeof(*src_vq)); 1186 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 1187 src_vq->io_modes = VB2_MMAP | VB2_DMABUF; 1188 src_vq->drv_priv = ctx; 1189 src_vq->buf_struct_size = sizeof(struct jpu_buffer); 1190 src_vq->ops = &jpu_qops; 1191 src_vq->mem_ops = &vb2_dma_contig_memops; 1192 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 1193 src_vq->lock = &ctx->jpu->mutex; 1194 src_vq->dev = ctx->jpu->v4l2_dev.dev; 1195 1196 ret = vb2_queue_init(src_vq); 1197 if (ret) 1198 return ret; 1199 1200 memset(dst_vq, 0, sizeof(*dst_vq)); 1201 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 1202 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF; 1203 dst_vq->drv_priv = ctx; 1204 dst_vq->buf_struct_size = sizeof(struct jpu_buffer); 1205 dst_vq->ops = &jpu_qops; 1206 dst_vq->mem_ops = &vb2_dma_contig_memops; 1207 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 1208 dst_vq->lock = &ctx->jpu->mutex; 1209 dst_vq->dev = ctx->jpu->v4l2_dev.dev; 1210 1211 return vb2_queue_init(dst_vq); 1212 } 1213 1214 /* 1215 * ============================================================================ 1216 * Device file operations 1217 * ============================================================================ 1218 */ 1219 static int jpu_open(struct file *file) 1220 { 1221 struct jpu *jpu = video_drvdata(file); 1222 struct video_device *vfd = video_devdata(file); 1223 struct jpu_ctx *ctx; 1224 int ret; 1225 1226 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 1227 if (!ctx) 1228 return -ENOMEM; 1229 1230 v4l2_fh_init(&ctx->fh, vfd); 1231 ctx->fh.ctrl_handler = &ctx->ctrl_handler; 1232 file->private_data = &ctx->fh; 1233 v4l2_fh_add(&ctx->fh); 1234 1235 ctx->jpu = jpu; 1236 ctx->encoder = vfd == &jpu->vfd_encoder; 1237 1238 __jpu_try_fmt(ctx, &ctx->out_q.fmtinfo, &ctx->out_q.format, 1239 V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 1240 __jpu_try_fmt(ctx, &ctx->cap_q.fmtinfo, &ctx->cap_q.format, 1241 V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); 1242 1243 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(jpu->m2m_dev, ctx, jpu_queue_init); 1244 if (IS_ERR(ctx->fh.m2m_ctx)) { 1245 ret = PTR_ERR(ctx->fh.m2m_ctx); 1246 goto v4l_prepare_rollback; 1247 } 1248 1249 ret = jpu_controls_create(ctx); 1250 if (ret < 0) 1251 goto v4l_prepare_rollback; 1252 1253 if (mutex_lock_interruptible(&jpu->mutex)) { 1254 ret = -ERESTARTSYS; 1255 goto v4l_prepare_rollback; 1256 } 1257 1258 if (jpu->ref_count == 0) { 1259 ret = clk_prepare_enable(jpu->clk); 1260 if (ret < 0) 1261 goto device_prepare_rollback; 1262 /* ...issue software reset */ 1263 ret = jpu_reset(jpu); 1264 if (ret) 1265 goto jpu_reset_rollback; 1266 } 1267 1268 jpu->ref_count++; 1269 1270 mutex_unlock(&jpu->mutex); 1271 return 0; 1272 1273 jpu_reset_rollback: 1274 clk_disable_unprepare(jpu->clk); 1275 device_prepare_rollback: 1276 mutex_unlock(&jpu->mutex); 1277 v4l_prepare_rollback: 1278 v4l2_fh_del(&ctx->fh); 1279 v4l2_fh_exit(&ctx->fh); 1280 kfree(ctx); 1281 return ret; 1282 } 1283 1284 static int jpu_release(struct file *file) 1285 { 1286 struct jpu *jpu = video_drvdata(file); 1287 struct jpu_ctx *ctx = fh_to_ctx(file->private_data); 1288 1289 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 1290 v4l2_ctrl_handler_free(&ctx->ctrl_handler); 1291 v4l2_fh_del(&ctx->fh); 1292 v4l2_fh_exit(&ctx->fh); 1293 kfree(ctx); 1294 1295 mutex_lock(&jpu->mutex); 1296 if (--jpu->ref_count == 0) 1297 clk_disable_unprepare(jpu->clk); 1298 mutex_unlock(&jpu->mutex); 1299 1300 return 0; 1301 } 1302 1303 static const struct v4l2_file_operations jpu_fops = { 1304 .owner = THIS_MODULE, 1305 .open = jpu_open, 1306 .release = jpu_release, 1307 .unlocked_ioctl = video_ioctl2, 1308 .poll = v4l2_m2m_fop_poll, 1309 .mmap = v4l2_m2m_fop_mmap, 1310 }; 1311 1312 /* 1313 * ============================================================================ 1314 * mem2mem callbacks 1315 * ============================================================================ 1316 */ 1317 static void jpu_cleanup(struct jpu_ctx *ctx, bool reset) 1318 { 1319 /* remove current buffers and finish job */ 1320 struct vb2_v4l2_buffer *src_buf, *dst_buf; 1321 unsigned long flags; 1322 1323 spin_lock_irqsave(&ctx->jpu->lock, flags); 1324 1325 src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1326 dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1327 1328 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); 1329 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); 1330 1331 /* ...and give it a chance on next run */ 1332 if (reset) 1333 jpu_write(ctx->jpu, JCCMD_SRST, JCCMD); 1334 1335 spin_unlock_irqrestore(&ctx->jpu->lock, flags); 1336 1337 v4l2_m2m_job_finish(ctx->jpu->m2m_dev, ctx->fh.m2m_ctx); 1338 } 1339 1340 static void jpu_device_run(void *priv) 1341 { 1342 struct jpu_ctx *ctx = priv; 1343 struct jpu *jpu = ctx->jpu; 1344 struct jpu_buffer *jpu_buf; 1345 struct jpu_q_data *q_data; 1346 struct vb2_v4l2_buffer *src_buf, *dst_buf; 1347 unsigned int w, h, bpl; 1348 unsigned char num_planes, subsampling; 1349 unsigned long flags; 1350 1351 /* ...wait until module reset completes; we have mutex locked here */ 1352 if (jpu_wait_reset(jpu)) { 1353 jpu_cleanup(ctx, true); 1354 return; 1355 } 1356 1357 spin_lock_irqsave(&ctx->jpu->lock, flags); 1358 1359 jpu->curr = ctx; 1360 1361 src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); 1362 dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); 1363 1364 if (ctx->encoder) { 1365 jpu_buf = vb2_to_jpu_buffer(dst_buf); 1366 q_data = &ctx->out_q; 1367 } else { 1368 jpu_buf = vb2_to_jpu_buffer(src_buf); 1369 q_data = &ctx->cap_q; 1370 } 1371 1372 w = q_data->format.width; 1373 h = q_data->format.height; 1374 bpl = q_data->format.plane_fmt[0].bytesperline; 1375 num_planes = q_data->fmtinfo->num_planes; 1376 subsampling = q_data->fmtinfo->subsampling; 1377 1378 if (ctx->encoder) { 1379 unsigned long src_1_addr, src_2_addr, dst_addr; 1380 unsigned int redu, inft; 1381 1382 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); 1383 src_1_addr = 1384 vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); 1385 if (num_planes > 1) 1386 src_2_addr = vb2_dma_contig_plane_dma_addr( 1387 &src_buf->vb2_buf, 1); 1388 else 1389 src_2_addr = src_1_addr + w * h; 1390 1391 jpu_buf->compr_quality = ctx->compr_quality; 1392 1393 if (subsampling == JPU_JPEG_420) { 1394 redu = JCMOD_REDU_420; 1395 inft = JIFECNT_INFT_420; 1396 } else { 1397 redu = JCMOD_REDU_422; 1398 inft = JIFECNT_INFT_422; 1399 } 1400 1401 /* only no marker mode works for encoding */ 1402 jpu_write(jpu, JCMOD_DSP_ENC | JCMOD_PCTR | redu | 1403 JCMOD_MSKIP_ENABLE, JCMOD); 1404 1405 jpu_write(jpu, JIFECNT_SWAP_WB | inft, JIFECNT); 1406 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT); 1407 jpu_write(jpu, JINTE_TRANSF_COMPL, JINTE); 1408 1409 /* Y and C components source addresses */ 1410 jpu_write(jpu, src_1_addr, JIFESYA1); 1411 jpu_write(jpu, src_2_addr, JIFESCA1); 1412 1413 /* memory width */ 1414 jpu_write(jpu, bpl, JIFESMW); 1415 1416 jpu_write(jpu, (w >> 8) & JCSZ_MASK, JCHSZU); 1417 jpu_write(jpu, w & JCSZ_MASK, JCHSZD); 1418 1419 jpu_write(jpu, (h >> 8) & JCSZ_MASK, JCVSZU); 1420 jpu_write(jpu, h & JCSZ_MASK, JCVSZD); 1421 1422 jpu_write(jpu, w, JIFESHSZ); 1423 jpu_write(jpu, h, JIFESVSZ); 1424 1425 jpu_write(jpu, dst_addr + JPU_JPEG_HDR_SIZE, JIFEDA1); 1426 1427 jpu_write(jpu, 0 << JCQTN_SHIFT(1) | 1 << JCQTN_SHIFT(2) | 1428 1 << JCQTN_SHIFT(3), JCQTN); 1429 1430 jpu_write(jpu, 0 << JCHTN_AC_SHIFT(1) | 0 << JCHTN_DC_SHIFT(1) | 1431 1 << JCHTN_AC_SHIFT(2) | 1 << JCHTN_DC_SHIFT(2) | 1432 1 << JCHTN_AC_SHIFT(3) | 1 << JCHTN_DC_SHIFT(3), 1433 JCHTN); 1434 1435 jpu_set_qtbl(jpu, ctx->compr_quality); 1436 jpu_set_htbl(jpu); 1437 } else { 1438 unsigned long src_addr, dst_1_addr, dst_2_addr; 1439 1440 if (jpu_buf->subsampling != subsampling) { 1441 dev_err(ctx->jpu->dev, 1442 "src and dst formats do not match.\n"); 1443 spin_unlock_irqrestore(&ctx->jpu->lock, flags); 1444 jpu_cleanup(ctx, false); 1445 return; 1446 } 1447 1448 src_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0); 1449 dst_1_addr = 1450 vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0); 1451 if (q_data->fmtinfo->num_planes > 1) 1452 dst_2_addr = vb2_dma_contig_plane_dma_addr( 1453 &dst_buf->vb2_buf, 1); 1454 else 1455 dst_2_addr = dst_1_addr + w * h; 1456 1457 /* ...set up decoder operation */ 1458 jpu_write(jpu, JCMOD_DSP_DEC | JCMOD_PCTR, JCMOD); 1459 jpu_write(jpu, JIFECNT_SWAP_WB, JIFECNT); 1460 jpu_write(jpu, JIFDCNT_SWAP_WB, JIFDCNT); 1461 1462 /* ...enable interrupts on transfer completion and d-g error */ 1463 jpu_write(jpu, JINTE_TRANSF_COMPL | JINTE_ERR, JINTE); 1464 1465 /* ...set source/destination addresses of encoded data */ 1466 jpu_write(jpu, src_addr, JIFDSA1); 1467 jpu_write(jpu, dst_1_addr, JIFDDYA1); 1468 jpu_write(jpu, dst_2_addr, JIFDDCA1); 1469 1470 jpu_write(jpu, bpl, JIFDDMW); 1471 } 1472 1473 /* ...start encoder/decoder operation */ 1474 jpu_write(jpu, JCCMD_JSRT, JCCMD); 1475 1476 spin_unlock_irqrestore(&ctx->jpu->lock, flags); 1477 } 1478 1479 static const struct v4l2_m2m_ops jpu_m2m_ops = { 1480 .device_run = jpu_device_run, 1481 }; 1482 1483 /* 1484 * ============================================================================ 1485 * IRQ handler 1486 * ============================================================================ 1487 */ 1488 static irqreturn_t jpu_irq_handler(int irq, void *dev_id) 1489 { 1490 struct jpu *jpu = dev_id; 1491 struct jpu_ctx *curr_ctx; 1492 struct vb2_v4l2_buffer *src_buf, *dst_buf; 1493 unsigned int int_status; 1494 1495 int_status = jpu_read(jpu, JINTS); 1496 1497 /* ...spurious interrupt */ 1498 if (!((JINTS_TRANSF_COMPL | JINTS_PROCESS_COMPL | JINTS_ERR) & 1499 int_status)) 1500 return IRQ_NONE; 1501 1502 /* ...clear interrupts */ 1503 jpu_write(jpu, ~(int_status & JINTS_MASK), JINTS); 1504 if (int_status & (JINTS_ERR | JINTS_PROCESS_COMPL)) 1505 jpu_write(jpu, JCCMD_JEND, JCCMD); 1506 1507 spin_lock(&jpu->lock); 1508 1509 if ((int_status & JINTS_PROCESS_COMPL) && 1510 !(int_status & JINTS_TRANSF_COMPL)) 1511 goto handled; 1512 1513 curr_ctx = v4l2_m2m_get_curr_priv(jpu->m2m_dev); 1514 if (!curr_ctx) { 1515 /* ...instance is not running */ 1516 dev_err(jpu->dev, "no active context for m2m\n"); 1517 goto handled; 1518 } 1519 1520 src_buf = v4l2_m2m_src_buf_remove(curr_ctx->fh.m2m_ctx); 1521 dst_buf = v4l2_m2m_dst_buf_remove(curr_ctx->fh.m2m_ctx); 1522 1523 if (int_status & JINTS_TRANSF_COMPL) { 1524 if (curr_ctx->encoder) { 1525 unsigned long payload_size = jpu_read(jpu, JCDTCU) << 16 1526 | jpu_read(jpu, JCDTCM) << 8 1527 | jpu_read(jpu, JCDTCD); 1528 vb2_set_plane_payload(&dst_buf->vb2_buf, 0, 1529 payload_size + JPU_JPEG_HDR_SIZE); 1530 } 1531 1532 dst_buf->field = src_buf->field; 1533 dst_buf->vb2_buf.timestamp = src_buf->vb2_buf.timestamp; 1534 if (src_buf->flags & V4L2_BUF_FLAG_TIMECODE) 1535 dst_buf->timecode = src_buf->timecode; 1536 dst_buf->flags = src_buf->flags & 1537 (V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_KEYFRAME | 1538 V4L2_BUF_FLAG_PFRAME | V4L2_BUF_FLAG_BFRAME | 1539 V4L2_BUF_FLAG_TSTAMP_SRC_MASK); 1540 1541 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE); 1542 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE); 1543 } else if (int_status & JINTS_ERR) { 1544 unsigned char error = jpu_read(jpu, JCDERR) & JCDERR_MASK; 1545 1546 dev_dbg(jpu->dev, "processing error: %#X: %s\n", error, 1547 error_to_text[error]); 1548 1549 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_ERROR); 1550 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_ERROR); 1551 } 1552 1553 jpu->curr = NULL; 1554 1555 /* ...reset JPU after completion */ 1556 jpu_write(jpu, JCCMD_SRST, JCCMD); 1557 spin_unlock(&jpu->lock); 1558 1559 v4l2_m2m_job_finish(jpu->m2m_dev, curr_ctx->fh.m2m_ctx); 1560 1561 return IRQ_HANDLED; 1562 1563 handled: 1564 spin_unlock(&jpu->lock); 1565 return IRQ_HANDLED; 1566 } 1567 1568 /* 1569 * ============================================================================ 1570 * Driver basic infrastructure 1571 * ============================================================================ 1572 */ 1573 static const struct of_device_id jpu_dt_ids[] = { 1574 { .compatible = "renesas,jpu-r8a7790" }, /* H2 */ 1575 { .compatible = "renesas,jpu-r8a7791" }, /* M2-W */ 1576 { .compatible = "renesas,jpu-r8a7792" }, /* V2H */ 1577 { .compatible = "renesas,jpu-r8a7793" }, /* M2-N */ 1578 { .compatible = "renesas,rcar-gen2-jpu" }, 1579 { }, 1580 }; 1581 MODULE_DEVICE_TABLE(of, jpu_dt_ids); 1582 1583 static int jpu_probe(struct platform_device *pdev) 1584 { 1585 struct jpu *jpu; 1586 int ret; 1587 unsigned int i; 1588 1589 jpu = devm_kzalloc(&pdev->dev, sizeof(*jpu), GFP_KERNEL); 1590 if (!jpu) 1591 return -ENOMEM; 1592 1593 mutex_init(&jpu->mutex); 1594 spin_lock_init(&jpu->lock); 1595 jpu->dev = &pdev->dev; 1596 1597 /* memory-mapped registers */ 1598 jpu->regs = devm_platform_ioremap_resource(pdev, 0); 1599 if (IS_ERR(jpu->regs)) 1600 return PTR_ERR(jpu->regs); 1601 1602 /* interrupt service routine registration */ 1603 jpu->irq = ret = platform_get_irq(pdev, 0); 1604 if (ret < 0) { 1605 dev_err(&pdev->dev, "cannot find IRQ\n"); 1606 return ret; 1607 } 1608 1609 ret = devm_request_irq(&pdev->dev, jpu->irq, jpu_irq_handler, 0, 1610 dev_name(&pdev->dev), jpu); 1611 if (ret) { 1612 dev_err(&pdev->dev, "cannot claim IRQ %d\n", jpu->irq); 1613 return ret; 1614 } 1615 1616 /* clocks */ 1617 jpu->clk = devm_clk_get(&pdev->dev, NULL); 1618 if (IS_ERR(jpu->clk)) { 1619 dev_err(&pdev->dev, "cannot get clock\n"); 1620 return PTR_ERR(jpu->clk); 1621 } 1622 1623 /* v4l2 device */ 1624 ret = v4l2_device_register(&pdev->dev, &jpu->v4l2_dev); 1625 if (ret) { 1626 dev_err(&pdev->dev, "Failed to register v4l2 device\n"); 1627 return ret; 1628 } 1629 1630 /* mem2mem device */ 1631 jpu->m2m_dev = v4l2_m2m_init(&jpu_m2m_ops); 1632 if (IS_ERR(jpu->m2m_dev)) { 1633 v4l2_err(&jpu->v4l2_dev, "Failed to init mem2mem device\n"); 1634 ret = PTR_ERR(jpu->m2m_dev); 1635 goto device_register_rollback; 1636 } 1637 1638 /* fill in quantization and Huffman tables for encoder */ 1639 for (i = 0; i < JPU_MAX_QUALITY; i++) 1640 jpu_generate_hdr(i, (unsigned char *)jpeg_hdrs[i]); 1641 1642 strscpy(jpu->vfd_encoder.name, DRV_NAME, sizeof(jpu->vfd_encoder.name)); 1643 jpu->vfd_encoder.fops = &jpu_fops; 1644 jpu->vfd_encoder.ioctl_ops = &jpu_ioctl_ops; 1645 jpu->vfd_encoder.minor = -1; 1646 jpu->vfd_encoder.release = video_device_release_empty; 1647 jpu->vfd_encoder.lock = &jpu->mutex; 1648 jpu->vfd_encoder.v4l2_dev = &jpu->v4l2_dev; 1649 jpu->vfd_encoder.vfl_dir = VFL_DIR_M2M; 1650 jpu->vfd_encoder.device_caps = V4L2_CAP_STREAMING | 1651 V4L2_CAP_VIDEO_M2M_MPLANE; 1652 1653 ret = video_register_device(&jpu->vfd_encoder, VFL_TYPE_VIDEO, -1); 1654 if (ret) { 1655 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n"); 1656 goto m2m_init_rollback; 1657 } 1658 1659 video_set_drvdata(&jpu->vfd_encoder, jpu); 1660 1661 strscpy(jpu->vfd_decoder.name, DRV_NAME, sizeof(jpu->vfd_decoder.name)); 1662 jpu->vfd_decoder.fops = &jpu_fops; 1663 jpu->vfd_decoder.ioctl_ops = &jpu_ioctl_ops; 1664 jpu->vfd_decoder.minor = -1; 1665 jpu->vfd_decoder.release = video_device_release_empty; 1666 jpu->vfd_decoder.lock = &jpu->mutex; 1667 jpu->vfd_decoder.v4l2_dev = &jpu->v4l2_dev; 1668 jpu->vfd_decoder.vfl_dir = VFL_DIR_M2M; 1669 jpu->vfd_decoder.device_caps = V4L2_CAP_STREAMING | 1670 V4L2_CAP_VIDEO_M2M_MPLANE; 1671 1672 ret = video_register_device(&jpu->vfd_decoder, VFL_TYPE_VIDEO, -1); 1673 if (ret) { 1674 v4l2_err(&jpu->v4l2_dev, "Failed to register video device\n"); 1675 goto enc_vdev_register_rollback; 1676 } 1677 1678 video_set_drvdata(&jpu->vfd_decoder, jpu); 1679 platform_set_drvdata(pdev, jpu); 1680 1681 v4l2_info(&jpu->v4l2_dev, "encoder device registered as /dev/video%d\n", 1682 jpu->vfd_encoder.num); 1683 v4l2_info(&jpu->v4l2_dev, "decoder device registered as /dev/video%d\n", 1684 jpu->vfd_decoder.num); 1685 1686 return 0; 1687 1688 enc_vdev_register_rollback: 1689 video_unregister_device(&jpu->vfd_encoder); 1690 1691 m2m_init_rollback: 1692 v4l2_m2m_release(jpu->m2m_dev); 1693 1694 device_register_rollback: 1695 v4l2_device_unregister(&jpu->v4l2_dev); 1696 1697 return ret; 1698 } 1699 1700 static void jpu_remove(struct platform_device *pdev) 1701 { 1702 struct jpu *jpu = platform_get_drvdata(pdev); 1703 1704 video_unregister_device(&jpu->vfd_decoder); 1705 video_unregister_device(&jpu->vfd_encoder); 1706 v4l2_m2m_release(jpu->m2m_dev); 1707 v4l2_device_unregister(&jpu->v4l2_dev); 1708 } 1709 1710 #ifdef CONFIG_PM_SLEEP 1711 static int jpu_suspend(struct device *dev) 1712 { 1713 struct jpu *jpu = dev_get_drvdata(dev); 1714 1715 if (jpu->ref_count == 0) 1716 return 0; 1717 1718 clk_disable_unprepare(jpu->clk); 1719 1720 return 0; 1721 } 1722 1723 static int jpu_resume(struct device *dev) 1724 { 1725 struct jpu *jpu = dev_get_drvdata(dev); 1726 1727 if (jpu->ref_count == 0) 1728 return 0; 1729 1730 clk_prepare_enable(jpu->clk); 1731 1732 return 0; 1733 } 1734 #endif 1735 1736 static const struct dev_pm_ops jpu_pm_ops = { 1737 SET_SYSTEM_SLEEP_PM_OPS(jpu_suspend, jpu_resume) 1738 }; 1739 1740 static struct platform_driver jpu_driver = { 1741 .probe = jpu_probe, 1742 .remove_new = jpu_remove, 1743 .driver = { 1744 .of_match_table = jpu_dt_ids, 1745 .name = DRV_NAME, 1746 .pm = &jpu_pm_ops, 1747 }, 1748 }; 1749 1750 module_platform_driver(jpu_driver); 1751 1752 MODULE_ALIAS("platform:" DRV_NAME); 1753 MODULE_AUTHOR("Mikhail Ulianov <mikhail.ulyanov@cogentembedded.com>"); 1754 MODULE_DESCRIPTION("Renesas R-Car JPEG processing unit driver"); 1755 MODULE_LICENSE("GPL v2"); 1756