1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Renesas R-Car Fine Display Processor 4 * 5 * Video format converter and frame deinterlacer device. 6 * 7 * Author: Kieran Bingham, <kieran@bingham.xyz> 8 * Copyright (c) 2016 Renesas Electronics Corporation. 9 * 10 * This code is developed and inspired from the vim2m, rcar_jpu, 11 * m2m-deinterlace, and vsp1 drivers. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/fs.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/sched.h> 25 #include <linux/slab.h> 26 #include <linux/timer.h> 27 #include <media/rcar-fcp.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-event.h> 31 #include <media/v4l2-ioctl.h> 32 #include <media/v4l2-mem2mem.h> 33 #include <media/videobuf2-dma-contig.h> 34 35 static unsigned int debug; 36 module_param(debug, uint, 0644); 37 MODULE_PARM_DESC(debug, "activate debug info"); 38 39 /* Minimum and maximum frame width/height */ 40 #define FDP1_MIN_W 80U 41 #define FDP1_MIN_H 80U 42 43 #define FDP1_MAX_W 3840U 44 #define FDP1_MAX_H 2160U 45 46 #define FDP1_MAX_PLANES 3U 47 #define FDP1_MAX_STRIDE 8190U 48 49 /* Flags that indicate a format can be used for capture/output */ 50 #define FDP1_CAPTURE BIT(0) 51 #define FDP1_OUTPUT BIT(1) 52 53 #define DRIVER_NAME "rcar_fdp1" 54 55 /* Number of Job's to have available on the processing queue */ 56 #define FDP1_NUMBER_JOBS 8 57 58 #define dprintk(fdp1, fmt, arg...) \ 59 v4l2_dbg(1, debug, &fdp1->v4l2_dev, "%s: " fmt, __func__, ## arg) 60 61 /* 62 * FDP1 registers and bits 63 */ 64 65 /* FDP1 start register - Imm */ 66 #define FD1_CTL_CMD 0x0000 67 #define FD1_CTL_CMD_STRCMD BIT(0) 68 69 /* Sync generator register - Imm */ 70 #define FD1_CTL_SGCMD 0x0004 71 #define FD1_CTL_SGCMD_SGEN BIT(0) 72 73 /* Register set end register - Imm */ 74 #define FD1_CTL_REGEND 0x0008 75 #define FD1_CTL_REGEND_REGEND BIT(0) 76 77 /* Channel activation register - Vupdt */ 78 #define FD1_CTL_CHACT 0x000c 79 #define FD1_CTL_CHACT_SMW BIT(9) 80 #define FD1_CTL_CHACT_WR BIT(8) 81 #define FD1_CTL_CHACT_SMR BIT(3) 82 #define FD1_CTL_CHACT_RD2 BIT(2) 83 #define FD1_CTL_CHACT_RD1 BIT(1) 84 #define FD1_CTL_CHACT_RD0 BIT(0) 85 86 /* Operation Mode Register - Vupdt */ 87 #define FD1_CTL_OPMODE 0x0010 88 #define FD1_CTL_OPMODE_PRG BIT(4) 89 #define FD1_CTL_OPMODE_VIMD_INTERRUPT (0 << 0) 90 #define FD1_CTL_OPMODE_VIMD_BESTEFFORT (1 << 0) 91 #define FD1_CTL_OPMODE_VIMD_NOINTERRUPT (2 << 0) 92 93 #define FD1_CTL_VPERIOD 0x0014 94 #define FD1_CTL_CLKCTRL 0x0018 95 #define FD1_CTL_CLKCTRL_CSTP_N BIT(0) 96 97 /* Software reset register */ 98 #define FD1_CTL_SRESET 0x001c 99 #define FD1_CTL_SRESET_SRST BIT(0) 100 101 /* Control status register (V-update-status) */ 102 #define FD1_CTL_STATUS 0x0024 103 #define FD1_CTL_STATUS_VINT_CNT_MASK GENMASK(31, 16) 104 #define FD1_CTL_STATUS_VINT_CNT_SHIFT 16 105 #define FD1_CTL_STATUS_SGREGSET BIT(10) 106 #define FD1_CTL_STATUS_SGVERR BIT(9) 107 #define FD1_CTL_STATUS_SGFREND BIT(8) 108 #define FD1_CTL_STATUS_BSY BIT(0) 109 110 #define FD1_CTL_VCYCLE_STAT 0x0028 111 112 /* Interrupt enable register */ 113 #define FD1_CTL_IRQENB 0x0038 114 /* Interrupt status register */ 115 #define FD1_CTL_IRQSTA 0x003c 116 /* Interrupt control register */ 117 #define FD1_CTL_IRQFSET 0x0040 118 119 /* Common IRQ Bit settings */ 120 #define FD1_CTL_IRQ_VERE BIT(16) 121 #define FD1_CTL_IRQ_VINTE BIT(4) 122 #define FD1_CTL_IRQ_FREE BIT(0) 123 #define FD1_CTL_IRQ_MASK (FD1_CTL_IRQ_VERE | \ 124 FD1_CTL_IRQ_VINTE | \ 125 FD1_CTL_IRQ_FREE) 126 127 /* RPF */ 128 #define FD1_RPF_SIZE 0x0060 129 #define FD1_RPF_SIZE_MASK GENMASK(12, 0) 130 #define FD1_RPF_SIZE_H_SHIFT 16 131 #define FD1_RPF_SIZE_V_SHIFT 0 132 133 #define FD1_RPF_FORMAT 0x0064 134 #define FD1_RPF_FORMAT_CIPM BIT(16) 135 #define FD1_RPF_FORMAT_RSPYCS BIT(13) 136 #define FD1_RPF_FORMAT_RSPUVS BIT(12) 137 #define FD1_RPF_FORMAT_CF BIT(8) 138 139 #define FD1_RPF_PSTRIDE 0x0068 140 #define FD1_RPF_PSTRIDE_Y_SHIFT 16 141 #define FD1_RPF_PSTRIDE_C_SHIFT 0 142 143 /* RPF0 Source Component Y Address register */ 144 #define FD1_RPF0_ADDR_Y 0x006c 145 146 /* RPF1 Current Picture Registers */ 147 #define FD1_RPF1_ADDR_Y 0x0078 148 #define FD1_RPF1_ADDR_C0 0x007c 149 #define FD1_RPF1_ADDR_C1 0x0080 150 151 /* RPF2 next picture register */ 152 #define FD1_RPF2_ADDR_Y 0x0084 153 154 #define FD1_RPF_SMSK_ADDR 0x0090 155 #define FD1_RPF_SWAP 0x0094 156 157 /* WPF */ 158 #define FD1_WPF_FORMAT 0x00c0 159 #define FD1_WPF_FORMAT_PDV_SHIFT 24 160 #define FD1_WPF_FORMAT_FCNL BIT(20) 161 #define FD1_WPF_FORMAT_WSPYCS BIT(15) 162 #define FD1_WPF_FORMAT_WSPUVS BIT(14) 163 #define FD1_WPF_FORMAT_WRTM_601_16 (0 << 9) 164 #define FD1_WPF_FORMAT_WRTM_601_0 (1 << 9) 165 #define FD1_WPF_FORMAT_WRTM_709_16 (2 << 9) 166 #define FD1_WPF_FORMAT_CSC BIT(8) 167 168 #define FD1_WPF_RNDCTL 0x00c4 169 #define FD1_WPF_RNDCTL_CBRM BIT(28) 170 #define FD1_WPF_RNDCTL_CLMD_NOCLIP (0 << 12) 171 #define FD1_WPF_RNDCTL_CLMD_CLIP_16_235 (1 << 12) 172 #define FD1_WPF_RNDCTL_CLMD_CLIP_1_254 (2 << 12) 173 174 #define FD1_WPF_PSTRIDE 0x00c8 175 #define FD1_WPF_PSTRIDE_Y_SHIFT 16 176 #define FD1_WPF_PSTRIDE_C_SHIFT 0 177 178 /* WPF Destination picture */ 179 #define FD1_WPF_ADDR_Y 0x00cc 180 #define FD1_WPF_ADDR_C0 0x00d0 181 #define FD1_WPF_ADDR_C1 0x00d4 182 #define FD1_WPF_SWAP 0x00d8 183 #define FD1_WPF_SWAP_OSWAP_SHIFT 0 184 #define FD1_WPF_SWAP_SSWAP_SHIFT 4 185 186 /* WPF/RPF Common */ 187 #define FD1_RWPF_SWAP_BYTE BIT(0) 188 #define FD1_RWPF_SWAP_WORD BIT(1) 189 #define FD1_RWPF_SWAP_LWRD BIT(2) 190 #define FD1_RWPF_SWAP_LLWD BIT(3) 191 192 /* IPC */ 193 #define FD1_IPC_MODE 0x0100 194 #define FD1_IPC_MODE_DLI BIT(8) 195 #define FD1_IPC_MODE_DIM_ADAPT2D3D (0 << 0) 196 #define FD1_IPC_MODE_DIM_FIXED2D (1 << 0) 197 #define FD1_IPC_MODE_DIM_FIXED3D (2 << 0) 198 #define FD1_IPC_MODE_DIM_PREVFIELD (3 << 0) 199 #define FD1_IPC_MODE_DIM_NEXTFIELD (4 << 0) 200 201 #define FD1_IPC_SMSK_THRESH 0x0104 202 #define FD1_IPC_SMSK_THRESH_CONST 0x00010002 203 204 #define FD1_IPC_COMB_DET 0x0108 205 #define FD1_IPC_COMB_DET_CONST 0x00200040 206 207 #define FD1_IPC_MOTDEC 0x010c 208 #define FD1_IPC_MOTDEC_CONST 0x00008020 209 210 /* DLI registers */ 211 #define FD1_IPC_DLI_BLEND 0x0120 212 #define FD1_IPC_DLI_BLEND_CONST 0x0080ff02 213 214 #define FD1_IPC_DLI_HGAIN 0x0124 215 #define FD1_IPC_DLI_HGAIN_CONST 0x001000ff 216 217 #define FD1_IPC_DLI_SPRS 0x0128 218 #define FD1_IPC_DLI_SPRS_CONST 0x009004ff 219 220 #define FD1_IPC_DLI_ANGLE 0x012c 221 #define FD1_IPC_DLI_ANGLE_CONST 0x0004080c 222 223 #define FD1_IPC_DLI_ISOPIX0 0x0130 224 #define FD1_IPC_DLI_ISOPIX0_CONST 0xff10ff10 225 226 #define FD1_IPC_DLI_ISOPIX1 0x0134 227 #define FD1_IPC_DLI_ISOPIX1_CONST 0x0000ff10 228 229 /* Sensor registers */ 230 #define FD1_IPC_SENSOR_TH0 0x0140 231 #define FD1_IPC_SENSOR_TH0_CONST 0x20208080 232 233 #define FD1_IPC_SENSOR_TH1 0x0144 234 #define FD1_IPC_SENSOR_TH1_CONST 0 235 236 #define FD1_IPC_SENSOR_CTL0 0x0170 237 #define FD1_IPC_SENSOR_CTL0_CONST 0x00002201 238 239 #define FD1_IPC_SENSOR_CTL1 0x0174 240 #define FD1_IPC_SENSOR_CTL1_CONST 0 241 242 #define FD1_IPC_SENSOR_CTL2 0x0178 243 #define FD1_IPC_SENSOR_CTL2_X_SHIFT 16 244 #define FD1_IPC_SENSOR_CTL2_Y_SHIFT 0 245 246 #define FD1_IPC_SENSOR_CTL3 0x017c 247 #define FD1_IPC_SENSOR_CTL3_0_SHIFT 16 248 #define FD1_IPC_SENSOR_CTL3_1_SHIFT 0 249 250 /* Line memory pixel number register */ 251 #define FD1_IPC_LMEM 0x01e0 252 #define FD1_IPC_LMEM_LINEAR 1024 253 #define FD1_IPC_LMEM_TILE 960 254 255 /* Internal Data (HW Version) */ 256 #define FD1_IP_INTDATA 0x0800 257 /* R-Car Gen2 HW manual says zero, but actual value matches R-Car H3 ES1.x */ 258 #define FD1_IP_GEN2 0x02010101 259 #define FD1_IP_M3W 0x02010202 260 #define FD1_IP_H3 0x02010203 261 #define FD1_IP_M3N 0x02010204 262 #define FD1_IP_E3 0x02010205 263 264 /* LUTs */ 265 #define FD1_LUT_DIF_ADJ 0x1000 266 #define FD1_LUT_SAD_ADJ 0x1400 267 #define FD1_LUT_BLD_GAIN 0x1800 268 #define FD1_LUT_DIF_GAIN 0x1c00 269 #define FD1_LUT_MDET 0x2000 270 271 /** 272 * struct fdp1_fmt - The FDP1 internal format data 273 * @fourcc: the fourcc code, to match the V4L2 API 274 * @bpp: bits per pixel per plane 275 * @num_planes: number of planes 276 * @hsub: horizontal subsampling factor 277 * @vsub: vertical subsampling factor 278 * @fmt: 7-bit format code for the fdp1 hardware 279 * @swap_yc: the Y and C components are swapped (Y comes before C) 280 * @swap_uv: the U and V components are swapped (V comes before U) 281 * @swap: swap register control 282 * @types: types of queue this format is applicable to 283 */ 284 struct fdp1_fmt { 285 u32 fourcc; 286 u8 bpp[3]; 287 u8 num_planes; 288 u8 hsub; 289 u8 vsub; 290 u8 fmt; 291 bool swap_yc; 292 bool swap_uv; 293 u8 swap; 294 u8 types; 295 }; 296 297 static const struct fdp1_fmt fdp1_formats[] = { 298 /* RGB formats are only supported by the Write Pixel Formatter */ 299 300 { V4L2_PIX_FMT_RGB332, { 8, 0, 0 }, 1, 1, 1, 0x00, false, false, 301 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 302 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 303 FDP1_CAPTURE }, 304 { V4L2_PIX_FMT_XRGB444, { 16, 0, 0 }, 1, 1, 1, 0x01, false, false, 305 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 306 FD1_RWPF_SWAP_WORD, 307 FDP1_CAPTURE }, 308 { V4L2_PIX_FMT_XRGB555, { 16, 0, 0 }, 1, 1, 1, 0x04, false, false, 309 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 310 FD1_RWPF_SWAP_WORD, 311 FDP1_CAPTURE }, 312 { V4L2_PIX_FMT_RGB565, { 16, 0, 0 }, 1, 1, 1, 0x06, false, false, 313 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 314 FD1_RWPF_SWAP_WORD, 315 FDP1_CAPTURE }, 316 { V4L2_PIX_FMT_ABGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 317 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD, 318 FDP1_CAPTURE }, 319 { V4L2_PIX_FMT_XBGR32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 320 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD, 321 FDP1_CAPTURE }, 322 { V4L2_PIX_FMT_ARGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 323 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 324 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 325 FDP1_CAPTURE }, 326 { V4L2_PIX_FMT_XRGB32, { 32, 0, 0 }, 1, 1, 1, 0x13, false, false, 327 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 328 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 329 FDP1_CAPTURE }, 330 { V4L2_PIX_FMT_RGB24, { 24, 0, 0 }, 1, 1, 1, 0x15, false, false, 331 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 332 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 333 FDP1_CAPTURE }, 334 { V4L2_PIX_FMT_BGR24, { 24, 0, 0 }, 1, 1, 1, 0x18, false, false, 335 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 336 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 337 FDP1_CAPTURE }, 338 { V4L2_PIX_FMT_ARGB444, { 16, 0, 0 }, 1, 1, 1, 0x19, false, false, 339 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 340 FD1_RWPF_SWAP_WORD, 341 FDP1_CAPTURE }, 342 { V4L2_PIX_FMT_ARGB555, { 16, 0, 0 }, 1, 1, 1, 0x1b, false, false, 343 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 344 FD1_RWPF_SWAP_WORD, 345 FDP1_CAPTURE }, 346 347 /* YUV Formats are supported by Read and Write Pixel Formatters */ 348 349 { V4L2_PIX_FMT_NV16M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, false, 350 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 351 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 352 FDP1_CAPTURE | FDP1_OUTPUT }, 353 { V4L2_PIX_FMT_NV61M, { 8, 16, 0 }, 2, 2, 1, 0x41, false, true, 354 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 355 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 356 FDP1_CAPTURE | FDP1_OUTPUT }, 357 { V4L2_PIX_FMT_NV12M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, false, 358 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 359 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 360 FDP1_CAPTURE | FDP1_OUTPUT }, 361 { V4L2_PIX_FMT_NV21M, { 8, 16, 0 }, 2, 2, 2, 0x42, false, true, 362 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 363 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 364 FDP1_CAPTURE | FDP1_OUTPUT }, 365 { V4L2_PIX_FMT_UYVY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, false, 366 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 367 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 368 FDP1_CAPTURE | FDP1_OUTPUT }, 369 { V4L2_PIX_FMT_VYUY, { 16, 0, 0 }, 1, 2, 1, 0x47, false, true, 370 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 371 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 372 FDP1_CAPTURE | FDP1_OUTPUT }, 373 { V4L2_PIX_FMT_YUYV, { 16, 0, 0 }, 1, 2, 1, 0x47, true, false, 374 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 375 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 376 FDP1_CAPTURE | FDP1_OUTPUT }, 377 { V4L2_PIX_FMT_YVYU, { 16, 0, 0 }, 1, 2, 1, 0x47, true, true, 378 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 379 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 380 FDP1_CAPTURE | FDP1_OUTPUT }, 381 { V4L2_PIX_FMT_YUV444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, false, 382 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 383 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 384 FDP1_CAPTURE | FDP1_OUTPUT }, 385 { V4L2_PIX_FMT_YVU444M, { 8, 8, 8 }, 3, 1, 1, 0x4a, false, true, 386 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 387 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 388 FDP1_CAPTURE | FDP1_OUTPUT }, 389 { V4L2_PIX_FMT_YUV422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, false, 390 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 391 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 392 FDP1_CAPTURE | FDP1_OUTPUT }, 393 { V4L2_PIX_FMT_YVU422M, { 8, 8, 8 }, 3, 2, 1, 0x4b, false, true, 394 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 395 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 396 FDP1_CAPTURE | FDP1_OUTPUT }, 397 { V4L2_PIX_FMT_YUV420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, false, 398 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 399 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 400 FDP1_CAPTURE | FDP1_OUTPUT }, 401 { V4L2_PIX_FMT_YVU420M, { 8, 8, 8 }, 3, 2, 2, 0x4c, false, true, 402 FD1_RWPF_SWAP_LLWD | FD1_RWPF_SWAP_LWRD | 403 FD1_RWPF_SWAP_WORD | FD1_RWPF_SWAP_BYTE, 404 FDP1_CAPTURE | FDP1_OUTPUT }, 405 }; 406 407 static int fdp1_fmt_is_rgb(const struct fdp1_fmt *fmt) 408 { 409 return fmt->fmt <= 0x1b; /* Last RGB code */ 410 } 411 412 /* 413 * FDP1 Lookup tables range from 0...255 only 414 * 415 * Each table must be less than 256 entries, and all tables 416 * are padded out to 256 entries by duplicating the last value. 417 */ 418 static const u8 fdp1_diff_adj[] = { 419 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf, 420 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3, 421 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff, 422 }; 423 424 static const u8 fdp1_sad_adj[] = { 425 0x00, 0x24, 0x43, 0x5e, 0x76, 0x8c, 0x9e, 0xaf, 426 0xbd, 0xc9, 0xd4, 0xdd, 0xe4, 0xea, 0xef, 0xf3, 427 0xf6, 0xf9, 0xfb, 0xfc, 0xfd, 0xfe, 0xfe, 0xff, 428 }; 429 430 static const u8 fdp1_bld_gain[] = { 431 0x80, 432 }; 433 434 static const u8 fdp1_dif_gain[] = { 435 0x80, 436 }; 437 438 static const u8 fdp1_mdet[] = { 439 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 440 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, 441 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 442 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, 443 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 444 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 445 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 446 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, 447 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 448 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f, 449 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 450 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 451 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 452 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 453 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 454 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f, 455 0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87, 456 0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f, 457 0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 458 0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f, 459 0xa0, 0xa1, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7, 460 0xa8, 0xa9, 0xaa, 0xab, 0xac, 0xad, 0xae, 0xaf, 461 0xb0, 0xb1, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6, 0xb7, 462 0xb8, 0xb9, 0xba, 0xbb, 0xbc, 0xbd, 0xbe, 0xbf, 463 0xc0, 0xc1, 0xc2, 0xc3, 0xc4, 0xc5, 0xc6, 0xc7, 464 0xc8, 0xc9, 0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 465 0xd0, 0xd1, 0xd2, 0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 466 0xd8, 0xd9, 0xda, 0xdb, 0xdc, 0xdd, 0xde, 0xdf, 467 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 468 0xe8, 0xe9, 0xea, 0xeb, 0xec, 0xed, 0xee, 0xef, 469 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 470 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff 471 }; 472 473 /* Per-queue, driver-specific private data */ 474 struct fdp1_q_data { 475 const struct fdp1_fmt *fmt; 476 struct v4l2_pix_format_mplane format; 477 478 unsigned int vsize; 479 unsigned int stride_y; 480 unsigned int stride_c; 481 }; 482 483 static const struct fdp1_fmt *fdp1_find_format(u32 pixelformat) 484 { 485 const struct fdp1_fmt *fmt; 486 unsigned int i; 487 488 for (i = 0; i < ARRAY_SIZE(fdp1_formats); i++) { 489 fmt = &fdp1_formats[i]; 490 if (fmt->fourcc == pixelformat) 491 return fmt; 492 } 493 494 return NULL; 495 } 496 497 enum fdp1_deint_mode { 498 FDP1_PROGRESSIVE = 0, /* Must be zero when !deinterlacing */ 499 FDP1_ADAPT2D3D, 500 FDP1_FIXED2D, 501 FDP1_FIXED3D, 502 FDP1_PREVFIELD, 503 FDP1_NEXTFIELD, 504 }; 505 506 #define FDP1_DEINT_MODE_USES_NEXT(mode) \ 507 (mode == FDP1_ADAPT2D3D || \ 508 mode == FDP1_FIXED3D || \ 509 mode == FDP1_NEXTFIELD) 510 511 #define FDP1_DEINT_MODE_USES_PREV(mode) \ 512 (mode == FDP1_ADAPT2D3D || \ 513 mode == FDP1_FIXED3D || \ 514 mode == FDP1_PREVFIELD) 515 516 /* 517 * FDP1 operates on potentially 3 fields, which are tracked 518 * from the VB buffers using this context structure. 519 * Will always be a field or a full frame, never two fields. 520 */ 521 struct fdp1_field_buffer { 522 struct vb2_v4l2_buffer *vb; 523 dma_addr_t addrs[3]; 524 525 /* Should be NONE:TOP:BOTTOM only */ 526 enum v4l2_field field; 527 528 /* Flag to indicate this is the last field in the vb */ 529 bool last_field; 530 531 /* Buffer queue lists */ 532 struct list_head list; 533 }; 534 535 struct fdp1_buffer { 536 struct v4l2_m2m_buffer m2m_buf; 537 struct fdp1_field_buffer fields[2]; 538 unsigned int num_fields; 539 }; 540 541 static inline struct fdp1_buffer *to_fdp1_buffer(struct vb2_v4l2_buffer *vb) 542 { 543 return container_of(vb, struct fdp1_buffer, m2m_buf.vb); 544 } 545 546 struct fdp1_job { 547 struct fdp1_field_buffer *previous; 548 struct fdp1_field_buffer *active; 549 struct fdp1_field_buffer *next; 550 struct fdp1_field_buffer *dst; 551 552 /* A job can only be on one list at a time */ 553 struct list_head list; 554 }; 555 556 struct fdp1_dev { 557 struct v4l2_device v4l2_dev; 558 struct video_device vfd; 559 560 struct mutex dev_mutex; 561 spinlock_t irqlock; 562 spinlock_t device_process_lock; 563 564 void __iomem *regs; 565 unsigned int irq; 566 struct device *dev; 567 568 /* Job Queues */ 569 struct fdp1_job jobs[FDP1_NUMBER_JOBS]; 570 struct list_head free_job_list; 571 struct list_head queued_job_list; 572 struct list_head hw_job_list; 573 574 unsigned int clk_rate; 575 576 struct rcar_fcp_device *fcp; 577 struct v4l2_m2m_dev *m2m_dev; 578 }; 579 580 struct fdp1_ctx { 581 struct v4l2_fh fh; 582 struct fdp1_dev *fdp1; 583 584 struct v4l2_ctrl_handler hdl; 585 unsigned int sequence; 586 587 /* Processed buffers in this transaction */ 588 u8 num_processed; 589 590 /* Transaction length (i.e. how many buffers per transaction) */ 591 u32 translen; 592 593 /* Abort requested by m2m */ 594 int aborting; 595 596 /* Deinterlace processing mode */ 597 enum fdp1_deint_mode deint_mode; 598 599 /* 600 * Adaptive 2D/3D mode uses a shared mask 601 * This is allocated at streamon, if the ADAPT2D3D mode 602 * is requested 603 */ 604 unsigned int smsk_size; 605 dma_addr_t smsk_addr[2]; 606 void *smsk_cpu; 607 608 /* Capture pipeline, can specify an alpha value 609 * for supported formats. 0-255 only 610 */ 611 unsigned char alpha; 612 613 /* Source and destination queue data */ 614 struct fdp1_q_data out_q; /* HW Source */ 615 struct fdp1_q_data cap_q; /* HW Destination */ 616 617 /* 618 * Field Queues 619 * Interlaced fields are used on 3 occasions, and tracked in this list. 620 * 621 * V4L2 Buffers are tracked inside the fdp1_buffer 622 * and released when the last 'field' completes 623 */ 624 struct list_head fields_queue; 625 unsigned int buffers_queued; 626 627 /* 628 * For de-interlacing we need to track our previous buffer 629 * while preparing our job lists. 630 */ 631 struct fdp1_field_buffer *previous; 632 }; 633 634 static inline struct fdp1_ctx *fh_to_ctx(struct v4l2_fh *fh) 635 { 636 return container_of(fh, struct fdp1_ctx, fh); 637 } 638 639 static struct fdp1_q_data *get_q_data(struct fdp1_ctx *ctx, 640 enum v4l2_buf_type type) 641 { 642 if (V4L2_TYPE_IS_OUTPUT(type)) 643 return &ctx->out_q; 644 else 645 return &ctx->cap_q; 646 } 647 648 /* 649 * list_remove_job: Take the first item off the specified job list 650 * 651 * Returns: pointer to a job, or NULL if the list is empty. 652 */ 653 static struct fdp1_job *list_remove_job(struct fdp1_dev *fdp1, 654 struct list_head *list) 655 { 656 struct fdp1_job *job; 657 unsigned long flags; 658 659 spin_lock_irqsave(&fdp1->irqlock, flags); 660 job = list_first_entry_or_null(list, struct fdp1_job, list); 661 if (job) 662 list_del(&job->list); 663 spin_unlock_irqrestore(&fdp1->irqlock, flags); 664 665 return job; 666 } 667 668 /* 669 * list_add_job: Add a job to the specified job list 670 * 671 * Returns: void - always succeeds 672 */ 673 static void list_add_job(struct fdp1_dev *fdp1, 674 struct list_head *list, 675 struct fdp1_job *job) 676 { 677 unsigned long flags; 678 679 spin_lock_irqsave(&fdp1->irqlock, flags); 680 list_add_tail(&job->list, list); 681 spin_unlock_irqrestore(&fdp1->irqlock, flags); 682 } 683 684 static struct fdp1_job *fdp1_job_alloc(struct fdp1_dev *fdp1) 685 { 686 return list_remove_job(fdp1, &fdp1->free_job_list); 687 } 688 689 static void fdp1_job_free(struct fdp1_dev *fdp1, struct fdp1_job *job) 690 { 691 /* Ensure that all residue from previous jobs is gone */ 692 memset(job, 0, sizeof(struct fdp1_job)); 693 694 list_add_job(fdp1, &fdp1->free_job_list, job); 695 } 696 697 static void queue_job(struct fdp1_dev *fdp1, struct fdp1_job *job) 698 { 699 list_add_job(fdp1, &fdp1->queued_job_list, job); 700 } 701 702 static struct fdp1_job *get_queued_job(struct fdp1_dev *fdp1) 703 { 704 return list_remove_job(fdp1, &fdp1->queued_job_list); 705 } 706 707 static void queue_hw_job(struct fdp1_dev *fdp1, struct fdp1_job *job) 708 { 709 list_add_job(fdp1, &fdp1->hw_job_list, job); 710 } 711 712 static struct fdp1_job *get_hw_queued_job(struct fdp1_dev *fdp1) 713 { 714 return list_remove_job(fdp1, &fdp1->hw_job_list); 715 } 716 717 /* 718 * Buffer lists handling 719 */ 720 static void fdp1_field_complete(struct fdp1_ctx *ctx, 721 struct fdp1_field_buffer *fbuf) 722 { 723 /* job->previous may be on the first field */ 724 if (!fbuf) 725 return; 726 727 if (fbuf->last_field) 728 v4l2_m2m_buf_done(fbuf->vb, VB2_BUF_STATE_DONE); 729 } 730 731 static void fdp1_queue_field(struct fdp1_ctx *ctx, 732 struct fdp1_field_buffer *fbuf) 733 { 734 unsigned long flags; 735 736 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 737 list_add_tail(&fbuf->list, &ctx->fields_queue); 738 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 739 740 ctx->buffers_queued++; 741 } 742 743 static struct fdp1_field_buffer *fdp1_dequeue_field(struct fdp1_ctx *ctx) 744 { 745 struct fdp1_field_buffer *fbuf; 746 unsigned long flags; 747 748 ctx->buffers_queued--; 749 750 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 751 fbuf = list_first_entry_or_null(&ctx->fields_queue, 752 struct fdp1_field_buffer, list); 753 if (fbuf) 754 list_del(&fbuf->list); 755 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 756 757 return fbuf; 758 } 759 760 /* 761 * Return the next field in the queue - or NULL, 762 * without removing the item from the list 763 */ 764 static struct fdp1_field_buffer *fdp1_peek_queued_field(struct fdp1_ctx *ctx) 765 { 766 struct fdp1_field_buffer *fbuf; 767 unsigned long flags; 768 769 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 770 fbuf = list_first_entry_or_null(&ctx->fields_queue, 771 struct fdp1_field_buffer, list); 772 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 773 774 return fbuf; 775 } 776 777 static u32 fdp1_read(struct fdp1_dev *fdp1, unsigned int reg) 778 { 779 u32 value = ioread32(fdp1->regs + reg); 780 781 if (debug >= 2) 782 dprintk(fdp1, "Read 0x%08x from 0x%04x\n", value, reg); 783 784 return value; 785 } 786 787 static void fdp1_write(struct fdp1_dev *fdp1, u32 val, unsigned int reg) 788 { 789 if (debug >= 2) 790 dprintk(fdp1, "Write 0x%08x to 0x%04x\n", val, reg); 791 792 iowrite32(val, fdp1->regs + reg); 793 } 794 795 /* IPC registers are to be programmed with constant values */ 796 static void fdp1_set_ipc_dli(struct fdp1_ctx *ctx) 797 { 798 struct fdp1_dev *fdp1 = ctx->fdp1; 799 800 fdp1_write(fdp1, FD1_IPC_SMSK_THRESH_CONST, FD1_IPC_SMSK_THRESH); 801 fdp1_write(fdp1, FD1_IPC_COMB_DET_CONST, FD1_IPC_COMB_DET); 802 fdp1_write(fdp1, FD1_IPC_MOTDEC_CONST, FD1_IPC_MOTDEC); 803 804 fdp1_write(fdp1, FD1_IPC_DLI_BLEND_CONST, FD1_IPC_DLI_BLEND); 805 fdp1_write(fdp1, FD1_IPC_DLI_HGAIN_CONST, FD1_IPC_DLI_HGAIN); 806 fdp1_write(fdp1, FD1_IPC_DLI_SPRS_CONST, FD1_IPC_DLI_SPRS); 807 fdp1_write(fdp1, FD1_IPC_DLI_ANGLE_CONST, FD1_IPC_DLI_ANGLE); 808 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX0_CONST, FD1_IPC_DLI_ISOPIX0); 809 fdp1_write(fdp1, FD1_IPC_DLI_ISOPIX1_CONST, FD1_IPC_DLI_ISOPIX1); 810 } 811 812 813 static void fdp1_set_ipc_sensor(struct fdp1_ctx *ctx) 814 { 815 struct fdp1_dev *fdp1 = ctx->fdp1; 816 struct fdp1_q_data *src_q_data = &ctx->out_q; 817 unsigned int x0, x1; 818 unsigned int hsize = src_q_data->format.width; 819 unsigned int vsize = src_q_data->format.height; 820 821 x0 = hsize / 3; 822 x1 = 2 * hsize / 3; 823 824 fdp1_write(fdp1, FD1_IPC_SENSOR_TH0_CONST, FD1_IPC_SENSOR_TH0); 825 fdp1_write(fdp1, FD1_IPC_SENSOR_TH1_CONST, FD1_IPC_SENSOR_TH1); 826 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL0_CONST, FD1_IPC_SENSOR_CTL0); 827 fdp1_write(fdp1, FD1_IPC_SENSOR_CTL1_CONST, FD1_IPC_SENSOR_CTL1); 828 829 fdp1_write(fdp1, ((hsize - 1) << FD1_IPC_SENSOR_CTL2_X_SHIFT) | 830 ((vsize - 1) << FD1_IPC_SENSOR_CTL2_Y_SHIFT), 831 FD1_IPC_SENSOR_CTL2); 832 833 fdp1_write(fdp1, (x0 << FD1_IPC_SENSOR_CTL3_0_SHIFT) | 834 (x1 << FD1_IPC_SENSOR_CTL3_1_SHIFT), 835 FD1_IPC_SENSOR_CTL3); 836 } 837 838 /* 839 * fdp1_write_lut: Write a padded LUT to the hw 840 * 841 * FDP1 uses constant data for de-interlacing processing, 842 * with large tables. These hardware tables are all 256 bytes 843 * long, however they often contain repeated data at the end. 844 * 845 * The last byte of the table is written to all remaining entries. 846 */ 847 static void fdp1_write_lut(struct fdp1_dev *fdp1, const u8 *lut, 848 unsigned int len, unsigned int base) 849 { 850 unsigned int i; 851 u8 pad; 852 853 /* Tables larger than the hw are clipped */ 854 len = min(len, 256u); 855 856 for (i = 0; i < len; i++) 857 fdp1_write(fdp1, lut[i], base + (i*4)); 858 859 /* Tables are padded with the last entry */ 860 pad = lut[i-1]; 861 862 for (; i < 256; i++) 863 fdp1_write(fdp1, pad, base + (i*4)); 864 } 865 866 static void fdp1_set_lut(struct fdp1_dev *fdp1) 867 { 868 fdp1_write_lut(fdp1, fdp1_diff_adj, ARRAY_SIZE(fdp1_diff_adj), 869 FD1_LUT_DIF_ADJ); 870 fdp1_write_lut(fdp1, fdp1_sad_adj, ARRAY_SIZE(fdp1_sad_adj), 871 FD1_LUT_SAD_ADJ); 872 fdp1_write_lut(fdp1, fdp1_bld_gain, ARRAY_SIZE(fdp1_bld_gain), 873 FD1_LUT_BLD_GAIN); 874 fdp1_write_lut(fdp1, fdp1_dif_gain, ARRAY_SIZE(fdp1_dif_gain), 875 FD1_LUT_DIF_GAIN); 876 fdp1_write_lut(fdp1, fdp1_mdet, ARRAY_SIZE(fdp1_mdet), 877 FD1_LUT_MDET); 878 } 879 880 static void fdp1_configure_rpf(struct fdp1_ctx *ctx, 881 struct fdp1_job *job) 882 { 883 struct fdp1_dev *fdp1 = ctx->fdp1; 884 u32 picture_size; 885 u32 pstride; 886 u32 format; 887 u32 smsk_addr; 888 889 struct fdp1_q_data *q_data = &ctx->out_q; 890 891 /* Picture size is common to Source and Destination frames */ 892 picture_size = (q_data->format.width << FD1_RPF_SIZE_H_SHIFT) 893 | (q_data->vsize << FD1_RPF_SIZE_V_SHIFT); 894 895 /* Strides */ 896 pstride = q_data->stride_y << FD1_RPF_PSTRIDE_Y_SHIFT; 897 if (q_data->format.num_planes > 1) 898 pstride |= q_data->stride_c << FD1_RPF_PSTRIDE_C_SHIFT; 899 900 /* Format control */ 901 format = q_data->fmt->fmt; 902 if (q_data->fmt->swap_yc) 903 format |= FD1_RPF_FORMAT_RSPYCS; 904 905 if (q_data->fmt->swap_uv) 906 format |= FD1_RPF_FORMAT_RSPUVS; 907 908 if (job->active->field == V4L2_FIELD_BOTTOM) { 909 format |= FD1_RPF_FORMAT_CF; /* Set for Bottom field */ 910 smsk_addr = ctx->smsk_addr[0]; 911 } else { 912 smsk_addr = ctx->smsk_addr[1]; 913 } 914 915 /* Deint mode is non-zero when deinterlacing */ 916 if (ctx->deint_mode) 917 format |= FD1_RPF_FORMAT_CIPM; 918 919 fdp1_write(fdp1, format, FD1_RPF_FORMAT); 920 fdp1_write(fdp1, q_data->fmt->swap, FD1_RPF_SWAP); 921 fdp1_write(fdp1, picture_size, FD1_RPF_SIZE); 922 fdp1_write(fdp1, pstride, FD1_RPF_PSTRIDE); 923 fdp1_write(fdp1, smsk_addr, FD1_RPF_SMSK_ADDR); 924 925 /* Previous Field Channel (CH0) */ 926 if (job->previous) 927 fdp1_write(fdp1, job->previous->addrs[0], FD1_RPF0_ADDR_Y); 928 929 /* Current Field Channel (CH1) */ 930 fdp1_write(fdp1, job->active->addrs[0], FD1_RPF1_ADDR_Y); 931 fdp1_write(fdp1, job->active->addrs[1], FD1_RPF1_ADDR_C0); 932 fdp1_write(fdp1, job->active->addrs[2], FD1_RPF1_ADDR_C1); 933 934 /* Next Field Channel (CH2) */ 935 if (job->next) 936 fdp1_write(fdp1, job->next->addrs[0], FD1_RPF2_ADDR_Y); 937 } 938 939 static void fdp1_configure_wpf(struct fdp1_ctx *ctx, 940 struct fdp1_job *job) 941 { 942 struct fdp1_dev *fdp1 = ctx->fdp1; 943 struct fdp1_q_data *src_q_data = &ctx->out_q; 944 struct fdp1_q_data *q_data = &ctx->cap_q; 945 u32 pstride; 946 u32 format; 947 u32 swap; 948 u32 rndctl; 949 950 pstride = q_data->format.plane_fmt[0].bytesperline 951 << FD1_WPF_PSTRIDE_Y_SHIFT; 952 953 if (q_data->format.num_planes > 1) 954 pstride |= q_data->format.plane_fmt[1].bytesperline 955 << FD1_WPF_PSTRIDE_C_SHIFT; 956 957 format = q_data->fmt->fmt; /* Output Format Code */ 958 959 if (q_data->fmt->swap_yc) 960 format |= FD1_WPF_FORMAT_WSPYCS; 961 962 if (q_data->fmt->swap_uv) 963 format |= FD1_WPF_FORMAT_WSPUVS; 964 965 if (fdp1_fmt_is_rgb(q_data->fmt)) { 966 /* Enable Colour Space conversion */ 967 format |= FD1_WPF_FORMAT_CSC; 968 969 /* Set WRTM */ 970 if (src_q_data->format.ycbcr_enc == V4L2_YCBCR_ENC_709) 971 format |= FD1_WPF_FORMAT_WRTM_709_16; 972 else if (src_q_data->format.quantization == 973 V4L2_QUANTIZATION_FULL_RANGE) 974 format |= FD1_WPF_FORMAT_WRTM_601_0; 975 else 976 format |= FD1_WPF_FORMAT_WRTM_601_16; 977 } 978 979 /* Set an alpha value into the Pad Value */ 980 format |= ctx->alpha << FD1_WPF_FORMAT_PDV_SHIFT; 981 982 /* Determine picture rounding and clipping */ 983 rndctl = FD1_WPF_RNDCTL_CBRM; /* Rounding Off */ 984 rndctl |= FD1_WPF_RNDCTL_CLMD_NOCLIP; 985 986 /* WPF Swap needs both ISWAP and OSWAP setting */ 987 swap = q_data->fmt->swap << FD1_WPF_SWAP_OSWAP_SHIFT; 988 swap |= src_q_data->fmt->swap << FD1_WPF_SWAP_SSWAP_SHIFT; 989 990 fdp1_write(fdp1, format, FD1_WPF_FORMAT); 991 fdp1_write(fdp1, rndctl, FD1_WPF_RNDCTL); 992 fdp1_write(fdp1, swap, FD1_WPF_SWAP); 993 fdp1_write(fdp1, pstride, FD1_WPF_PSTRIDE); 994 995 fdp1_write(fdp1, job->dst->addrs[0], FD1_WPF_ADDR_Y); 996 fdp1_write(fdp1, job->dst->addrs[1], FD1_WPF_ADDR_C0); 997 fdp1_write(fdp1, job->dst->addrs[2], FD1_WPF_ADDR_C1); 998 } 999 1000 static void fdp1_configure_deint_mode(struct fdp1_ctx *ctx, 1001 struct fdp1_job *job) 1002 { 1003 struct fdp1_dev *fdp1 = ctx->fdp1; 1004 u32 opmode = FD1_CTL_OPMODE_VIMD_NOINTERRUPT; 1005 u32 ipcmode = FD1_IPC_MODE_DLI; /* Always set */ 1006 u32 channels = FD1_CTL_CHACT_WR | FD1_CTL_CHACT_RD1; /* Always on */ 1007 1008 /* De-interlacing Mode */ 1009 switch (ctx->deint_mode) { 1010 default: 1011 case FDP1_PROGRESSIVE: 1012 dprintk(fdp1, "Progressive Mode\n"); 1013 opmode |= FD1_CTL_OPMODE_PRG; 1014 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D; 1015 break; 1016 case FDP1_ADAPT2D3D: 1017 dprintk(fdp1, "Adapt2D3D Mode\n"); 1018 if (ctx->sequence == 0 || ctx->aborting) 1019 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D; 1020 else 1021 ipcmode |= FD1_IPC_MODE_DIM_ADAPT2D3D; 1022 1023 if (ctx->sequence > 1) { 1024 channels |= FD1_CTL_CHACT_SMW; 1025 channels |= FD1_CTL_CHACT_RD0 | FD1_CTL_CHACT_RD2; 1026 } 1027 1028 if (ctx->sequence > 2) 1029 channels |= FD1_CTL_CHACT_SMR; 1030 1031 break; 1032 case FDP1_FIXED3D: 1033 dprintk(fdp1, "Fixed 3D Mode\n"); 1034 ipcmode |= FD1_IPC_MODE_DIM_FIXED3D; 1035 /* Except for first and last frame, enable all channels */ 1036 if (!(ctx->sequence == 0 || ctx->aborting)) 1037 channels |= FD1_CTL_CHACT_RD0 | FD1_CTL_CHACT_RD2; 1038 break; 1039 case FDP1_FIXED2D: 1040 dprintk(fdp1, "Fixed 2D Mode\n"); 1041 ipcmode |= FD1_IPC_MODE_DIM_FIXED2D; 1042 /* No extra channels enabled */ 1043 break; 1044 case FDP1_PREVFIELD: 1045 dprintk(fdp1, "Previous Field Mode\n"); 1046 ipcmode |= FD1_IPC_MODE_DIM_PREVFIELD; 1047 channels |= FD1_CTL_CHACT_RD0; /* Previous */ 1048 break; 1049 case FDP1_NEXTFIELD: 1050 dprintk(fdp1, "Next Field Mode\n"); 1051 ipcmode |= FD1_IPC_MODE_DIM_NEXTFIELD; 1052 channels |= FD1_CTL_CHACT_RD2; /* Next */ 1053 break; 1054 } 1055 1056 fdp1_write(fdp1, channels, FD1_CTL_CHACT); 1057 fdp1_write(fdp1, opmode, FD1_CTL_OPMODE); 1058 fdp1_write(fdp1, ipcmode, FD1_IPC_MODE); 1059 } 1060 1061 /* 1062 * fdp1_device_process() - Run the hardware 1063 * 1064 * Configure and start the hardware to generate a single frame 1065 * of output given our input parameters. 1066 */ 1067 static int fdp1_device_process(struct fdp1_ctx *ctx) 1068 1069 { 1070 struct fdp1_dev *fdp1 = ctx->fdp1; 1071 struct fdp1_job *job; 1072 unsigned long flags; 1073 1074 spin_lock_irqsave(&fdp1->device_process_lock, flags); 1075 1076 /* Get a job to process */ 1077 job = get_queued_job(fdp1); 1078 if (!job) { 1079 /* 1080 * VINT can call us to see if we can queue another job. 1081 * If we have no work to do, we simply return. 1082 */ 1083 spin_unlock_irqrestore(&fdp1->device_process_lock, flags); 1084 return 0; 1085 } 1086 1087 /* First Frame only? ... */ 1088 fdp1_write(fdp1, FD1_CTL_CLKCTRL_CSTP_N, FD1_CTL_CLKCTRL); 1089 1090 /* Set the mode, and configuration */ 1091 fdp1_configure_deint_mode(ctx, job); 1092 1093 /* DLI Static Configuration */ 1094 fdp1_set_ipc_dli(ctx); 1095 1096 /* Sensor Configuration */ 1097 fdp1_set_ipc_sensor(ctx); 1098 1099 /* Setup the source picture */ 1100 fdp1_configure_rpf(ctx, job); 1101 1102 /* Setup the destination picture */ 1103 fdp1_configure_wpf(ctx, job); 1104 1105 /* Line Memory Pixel Number Register for linear access */ 1106 fdp1_write(fdp1, FD1_IPC_LMEM_LINEAR, FD1_IPC_LMEM); 1107 1108 /* Enable Interrupts */ 1109 fdp1_write(fdp1, FD1_CTL_IRQ_MASK, FD1_CTL_IRQENB); 1110 1111 /* Finally, the Immediate Registers */ 1112 1113 /* This job is now in the HW queue */ 1114 queue_hw_job(fdp1, job); 1115 1116 /* Start the command */ 1117 fdp1_write(fdp1, FD1_CTL_CMD_STRCMD, FD1_CTL_CMD); 1118 1119 /* Registers will update to HW at next VINT */ 1120 fdp1_write(fdp1, FD1_CTL_REGEND_REGEND, FD1_CTL_REGEND); 1121 1122 /* Enable VINT Generator */ 1123 fdp1_write(fdp1, FD1_CTL_SGCMD_SGEN, FD1_CTL_SGCMD); 1124 1125 spin_unlock_irqrestore(&fdp1->device_process_lock, flags); 1126 1127 return 0; 1128 } 1129 1130 /* 1131 * mem2mem callbacks 1132 */ 1133 1134 /* 1135 * job_ready() - check whether an instance is ready to be scheduled to run 1136 */ 1137 static int fdp1_m2m_job_ready(void *priv) 1138 { 1139 struct fdp1_ctx *ctx = priv; 1140 struct fdp1_q_data *src_q_data = &ctx->out_q; 1141 int srcbufs = 1; 1142 int dstbufs = 1; 1143 1144 dprintk(ctx->fdp1, "+ Src: %d : Dst: %d\n", 1145 v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx), 1146 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx)); 1147 1148 /* One output buffer is required for each field */ 1149 if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field)) 1150 dstbufs = 2; 1151 1152 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) < srcbufs 1153 || v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) < dstbufs) { 1154 dprintk(ctx->fdp1, "Not enough buffers available\n"); 1155 return 0; 1156 } 1157 1158 return 1; 1159 } 1160 1161 static void fdp1_m2m_job_abort(void *priv) 1162 { 1163 struct fdp1_ctx *ctx = priv; 1164 1165 dprintk(ctx->fdp1, "+\n"); 1166 1167 /* Will cancel the transaction in the next interrupt handler */ 1168 ctx->aborting = 1; 1169 1170 /* Immediate abort sequence */ 1171 fdp1_write(ctx->fdp1, 0, FD1_CTL_SGCMD); 1172 fdp1_write(ctx->fdp1, FD1_CTL_SRESET_SRST, FD1_CTL_SRESET); 1173 } 1174 1175 /* 1176 * fdp1_prepare_job: Prepare and queue a new job for a single action of work 1177 * 1178 * Prepare the next field, (or frame in progressive) and an output 1179 * buffer for the hardware to perform a single operation. 1180 */ 1181 static struct fdp1_job *fdp1_prepare_job(struct fdp1_ctx *ctx) 1182 { 1183 struct vb2_v4l2_buffer *vbuf; 1184 struct fdp1_buffer *fbuf; 1185 struct fdp1_dev *fdp1 = ctx->fdp1; 1186 struct fdp1_job *job; 1187 unsigned int buffers_required = 1; 1188 1189 dprintk(fdp1, "+\n"); 1190 1191 if (FDP1_DEINT_MODE_USES_NEXT(ctx->deint_mode)) 1192 buffers_required = 2; 1193 1194 if (ctx->buffers_queued < buffers_required) 1195 return NULL; 1196 1197 job = fdp1_job_alloc(fdp1); 1198 if (!job) { 1199 dprintk(fdp1, "No free jobs currently available\n"); 1200 return NULL; 1201 } 1202 1203 job->active = fdp1_dequeue_field(ctx); 1204 if (!job->active) { 1205 /* Buffer check should prevent this ever happening */ 1206 dprintk(fdp1, "No input buffers currently available\n"); 1207 1208 fdp1_job_free(fdp1, job); 1209 return NULL; 1210 } 1211 1212 dprintk(fdp1, "+ Buffer en-route...\n"); 1213 1214 /* Source buffers have been prepared on our buffer_queue 1215 * Prepare our Output buffer 1216 */ 1217 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1218 fbuf = to_fdp1_buffer(vbuf); 1219 job->dst = &fbuf->fields[0]; 1220 1221 job->active->vb->sequence = ctx->sequence; 1222 job->dst->vb->sequence = ctx->sequence; 1223 ctx->sequence++; 1224 1225 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) { 1226 job->previous = ctx->previous; 1227 1228 /* Active buffer becomes the next job's previous buffer */ 1229 ctx->previous = job->active; 1230 } 1231 1232 if (FDP1_DEINT_MODE_USES_NEXT(ctx->deint_mode)) { 1233 /* Must be called after 'active' is dequeued */ 1234 job->next = fdp1_peek_queued_field(ctx); 1235 } 1236 1237 /* Transfer timestamps and flags from src->dst */ 1238 1239 job->dst->vb->vb2_buf.timestamp = job->active->vb->vb2_buf.timestamp; 1240 1241 job->dst->vb->flags = job->active->vb->flags & 1242 V4L2_BUF_FLAG_TSTAMP_SRC_MASK; 1243 1244 /* Ideally, the frame-end function will just 'check' to see 1245 * if there are more jobs instead 1246 */ 1247 ctx->translen++; 1248 1249 /* Finally, Put this job on the processing queue */ 1250 queue_job(fdp1, job); 1251 1252 dprintk(fdp1, "Job Queued translen = %d\n", ctx->translen); 1253 1254 return job; 1255 } 1256 1257 /* fdp1_m2m_device_run() - prepares and starts the device for an M2M task 1258 * 1259 * A single input buffer is taken and serialised into our fdp1_buffer 1260 * queue. The queue is then processed to create as many jobs as possible 1261 * from our available input. 1262 */ 1263 static void fdp1_m2m_device_run(void *priv) 1264 { 1265 struct fdp1_ctx *ctx = priv; 1266 struct fdp1_dev *fdp1 = ctx->fdp1; 1267 struct vb2_v4l2_buffer *src_vb; 1268 struct fdp1_buffer *buf; 1269 unsigned int i; 1270 1271 dprintk(fdp1, "+\n"); 1272 1273 ctx->translen = 0; 1274 1275 /* Get our incoming buffer of either one or two fields, or one frame */ 1276 src_vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1277 buf = to_fdp1_buffer(src_vb); 1278 1279 for (i = 0; i < buf->num_fields; i++) { 1280 struct fdp1_field_buffer *fbuf = &buf->fields[i]; 1281 1282 fdp1_queue_field(ctx, fbuf); 1283 dprintk(fdp1, "Queued Buffer [%d] last_field:%d\n", 1284 i, fbuf->last_field); 1285 } 1286 1287 /* Queue as many jobs as our data provides for */ 1288 while (fdp1_prepare_job(ctx)) 1289 ; 1290 1291 if (ctx->translen == 0) { 1292 dprintk(fdp1, "No jobs were processed. M2M action complete\n"); 1293 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx); 1294 return; 1295 } 1296 1297 /* Kick the job processing action */ 1298 fdp1_device_process(ctx); 1299 } 1300 1301 /* 1302 * device_frame_end: 1303 * 1304 * Handles the M2M level after a buffer completion event. 1305 */ 1306 static void device_frame_end(struct fdp1_dev *fdp1, 1307 enum vb2_buffer_state state) 1308 { 1309 struct fdp1_ctx *ctx; 1310 unsigned long flags; 1311 struct fdp1_job *job = get_hw_queued_job(fdp1); 1312 1313 dprintk(fdp1, "+\n"); 1314 1315 ctx = v4l2_m2m_get_curr_priv(fdp1->m2m_dev); 1316 1317 if (ctx == NULL) { 1318 v4l2_err(&fdp1->v4l2_dev, 1319 "Instance released before the end of transaction\n"); 1320 return; 1321 } 1322 1323 ctx->num_processed++; 1324 1325 /* 1326 * fdp1_field_complete will call buf_done only when the last vb2_buffer 1327 * reference is complete 1328 */ 1329 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) 1330 fdp1_field_complete(ctx, job->previous); 1331 else 1332 fdp1_field_complete(ctx, job->active); 1333 1334 spin_lock_irqsave(&fdp1->irqlock, flags); 1335 v4l2_m2m_buf_done(job->dst->vb, state); 1336 job->dst = NULL; 1337 spin_unlock_irqrestore(&fdp1->irqlock, flags); 1338 1339 /* Move this job back to the free job list */ 1340 fdp1_job_free(fdp1, job); 1341 1342 dprintk(fdp1, "curr_ctx->num_processed %d curr_ctx->translen %d\n", 1343 ctx->num_processed, ctx->translen); 1344 1345 if (ctx->num_processed == ctx->translen || 1346 ctx->aborting) { 1347 dprintk(ctx->fdp1, "Finishing transaction\n"); 1348 ctx->num_processed = 0; 1349 v4l2_m2m_job_finish(fdp1->m2m_dev, ctx->fh.m2m_ctx); 1350 } else { 1351 /* 1352 * For pipelined performance support, this would 1353 * be called from a VINT handler 1354 */ 1355 fdp1_device_process(ctx); 1356 } 1357 } 1358 1359 /* 1360 * video ioctls 1361 */ 1362 static int fdp1_vidioc_querycap(struct file *file, void *priv, 1363 struct v4l2_capability *cap) 1364 { 1365 strscpy(cap->driver, DRIVER_NAME, sizeof(cap->driver)); 1366 strscpy(cap->card, DRIVER_NAME, sizeof(cap->card)); 1367 snprintf(cap->bus_info, sizeof(cap->bus_info), 1368 "platform:%s", DRIVER_NAME); 1369 return 0; 1370 } 1371 1372 static int fdp1_enum_fmt(struct v4l2_fmtdesc *f, u32 type) 1373 { 1374 unsigned int i, num; 1375 1376 num = 0; 1377 1378 for (i = 0; i < ARRAY_SIZE(fdp1_formats); ++i) { 1379 if (fdp1_formats[i].types & type) { 1380 if (num == f->index) 1381 break; 1382 ++num; 1383 } 1384 } 1385 1386 /* Format not found */ 1387 if (i >= ARRAY_SIZE(fdp1_formats)) 1388 return -EINVAL; 1389 1390 /* Format found */ 1391 f->pixelformat = fdp1_formats[i].fourcc; 1392 1393 return 0; 1394 } 1395 1396 static int fdp1_enum_fmt_vid_cap(struct file *file, void *priv, 1397 struct v4l2_fmtdesc *f) 1398 { 1399 return fdp1_enum_fmt(f, FDP1_CAPTURE); 1400 } 1401 1402 static int fdp1_enum_fmt_vid_out(struct file *file, void *priv, 1403 struct v4l2_fmtdesc *f) 1404 { 1405 return fdp1_enum_fmt(f, FDP1_OUTPUT); 1406 } 1407 1408 static int fdp1_g_fmt(struct file *file, void *priv, struct v4l2_format *f) 1409 { 1410 struct fdp1_q_data *q_data; 1411 struct fdp1_ctx *ctx = fh_to_ctx(priv); 1412 1413 if (!v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type)) 1414 return -EINVAL; 1415 1416 q_data = get_q_data(ctx, f->type); 1417 f->fmt.pix_mp = q_data->format; 1418 1419 return 0; 1420 } 1421 1422 static void fdp1_compute_stride(struct v4l2_pix_format_mplane *pix, 1423 const struct fdp1_fmt *fmt) 1424 { 1425 unsigned int i; 1426 1427 /* Compute and clamp the stride and image size. */ 1428 for (i = 0; i < min_t(unsigned int, fmt->num_planes, 2U); ++i) { 1429 unsigned int hsub = i > 0 ? fmt->hsub : 1; 1430 unsigned int vsub = i > 0 ? fmt->vsub : 1; 1431 /* From VSP : TODO: Confirm alignment limits for FDP1 */ 1432 unsigned int align = 128; 1433 unsigned int bpl; 1434 1435 bpl = clamp_t(unsigned int, pix->plane_fmt[i].bytesperline, 1436 pix->width / hsub * fmt->bpp[i] / 8, 1437 round_down(FDP1_MAX_STRIDE, align)); 1438 1439 pix->plane_fmt[i].bytesperline = round_up(bpl, align); 1440 pix->plane_fmt[i].sizeimage = pix->plane_fmt[i].bytesperline 1441 * pix->height / vsub; 1442 1443 } 1444 1445 if (fmt->num_planes == 3) { 1446 /* The two chroma planes must have the same stride. */ 1447 pix->plane_fmt[2].bytesperline = pix->plane_fmt[1].bytesperline; 1448 pix->plane_fmt[2].sizeimage = pix->plane_fmt[1].sizeimage; 1449 1450 } 1451 } 1452 1453 static void fdp1_try_fmt_output(struct fdp1_ctx *ctx, 1454 const struct fdp1_fmt **fmtinfo, 1455 struct v4l2_pix_format_mplane *pix) 1456 { 1457 const struct fdp1_fmt *fmt; 1458 unsigned int width; 1459 unsigned int height; 1460 1461 /* Validate the pixel format to ensure the output queue supports it. */ 1462 fmt = fdp1_find_format(pix->pixelformat); 1463 if (!fmt || !(fmt->types & FDP1_OUTPUT)) 1464 fmt = fdp1_find_format(V4L2_PIX_FMT_YUYV); 1465 1466 if (fmtinfo) 1467 *fmtinfo = fmt; 1468 1469 pix->pixelformat = fmt->fourcc; 1470 pix->num_planes = fmt->num_planes; 1471 1472 /* 1473 * Progressive video and all interlaced field orders are acceptable. 1474 * Default to V4L2_FIELD_INTERLACED. 1475 */ 1476 if (pix->field != V4L2_FIELD_NONE && 1477 pix->field != V4L2_FIELD_ALTERNATE && 1478 !V4L2_FIELD_HAS_BOTH(pix->field)) 1479 pix->field = V4L2_FIELD_INTERLACED; 1480 1481 /* 1482 * The deinterlacer doesn't care about the colorspace, accept all values 1483 * and default to V4L2_COLORSPACE_SMPTE170M. The YUV to RGB conversion 1484 * at the output of the deinterlacer supports a subset of encodings and 1485 * quantization methods and will only be available when the colorspace 1486 * allows it. 1487 */ 1488 if (pix->colorspace == V4L2_COLORSPACE_DEFAULT) 1489 pix->colorspace = V4L2_COLORSPACE_SMPTE170M; 1490 1491 /* 1492 * Align the width and height for YUV 4:2:2 and 4:2:0 formats and clamp 1493 * them to the supported frame size range. The height boundary are 1494 * related to the full frame, divide them by two when the format passes 1495 * fields in separate buffers. 1496 */ 1497 width = round_down(pix->width, fmt->hsub); 1498 pix->width = clamp(width, FDP1_MIN_W, FDP1_MAX_W); 1499 1500 height = round_down(pix->height, fmt->vsub); 1501 if (pix->field == V4L2_FIELD_ALTERNATE) 1502 pix->height = clamp(height, FDP1_MIN_H / 2, FDP1_MAX_H / 2); 1503 else 1504 pix->height = clamp(height, FDP1_MIN_H, FDP1_MAX_H); 1505 1506 fdp1_compute_stride(pix, fmt); 1507 } 1508 1509 static void fdp1_try_fmt_capture(struct fdp1_ctx *ctx, 1510 const struct fdp1_fmt **fmtinfo, 1511 struct v4l2_pix_format_mplane *pix) 1512 { 1513 struct fdp1_q_data *src_data = &ctx->out_q; 1514 enum v4l2_colorspace colorspace; 1515 enum v4l2_ycbcr_encoding ycbcr_enc; 1516 enum v4l2_quantization quantization; 1517 const struct fdp1_fmt *fmt; 1518 bool allow_rgb; 1519 1520 /* 1521 * Validate the pixel format. We can only accept RGB output formats if 1522 * the input encoding and quantization are compatible with the format 1523 * conversions supported by the hardware. The supported combinations are 1524 * 1525 * V4L2_YCBCR_ENC_601 + V4L2_QUANTIZATION_LIM_RANGE 1526 * V4L2_YCBCR_ENC_601 + V4L2_QUANTIZATION_FULL_RANGE 1527 * V4L2_YCBCR_ENC_709 + V4L2_QUANTIZATION_LIM_RANGE 1528 */ 1529 colorspace = src_data->format.colorspace; 1530 1531 ycbcr_enc = src_data->format.ycbcr_enc; 1532 if (ycbcr_enc == V4L2_YCBCR_ENC_DEFAULT) 1533 ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(colorspace); 1534 1535 quantization = src_data->format.quantization; 1536 if (quantization == V4L2_QUANTIZATION_DEFAULT) 1537 quantization = V4L2_MAP_QUANTIZATION_DEFAULT(false, colorspace, 1538 ycbcr_enc); 1539 1540 allow_rgb = ycbcr_enc == V4L2_YCBCR_ENC_601 || 1541 (ycbcr_enc == V4L2_YCBCR_ENC_709 && 1542 quantization == V4L2_QUANTIZATION_LIM_RANGE); 1543 1544 fmt = fdp1_find_format(pix->pixelformat); 1545 if (!fmt || (!allow_rgb && fdp1_fmt_is_rgb(fmt))) 1546 fmt = fdp1_find_format(V4L2_PIX_FMT_YUYV); 1547 1548 if (fmtinfo) 1549 *fmtinfo = fmt; 1550 1551 pix->pixelformat = fmt->fourcc; 1552 pix->num_planes = fmt->num_planes; 1553 pix->field = V4L2_FIELD_NONE; 1554 1555 /* 1556 * The colorspace on the capture queue is copied from the output queue 1557 * as the hardware can't change the colorspace. It can convert YCbCr to 1558 * RGB though, in which case the encoding and quantization are set to 1559 * default values as anything else wouldn't make sense. 1560 */ 1561 pix->colorspace = src_data->format.colorspace; 1562 pix->xfer_func = src_data->format.xfer_func; 1563 1564 if (fdp1_fmt_is_rgb(fmt)) { 1565 pix->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; 1566 pix->quantization = V4L2_QUANTIZATION_DEFAULT; 1567 } else { 1568 pix->ycbcr_enc = src_data->format.ycbcr_enc; 1569 pix->quantization = src_data->format.quantization; 1570 } 1571 1572 /* 1573 * The frame width is identical to the output queue, and the height is 1574 * either doubled or identical depending on whether the output queue 1575 * field order contains one or two fields per frame. 1576 */ 1577 pix->width = src_data->format.width; 1578 if (src_data->format.field == V4L2_FIELD_ALTERNATE) 1579 pix->height = 2 * src_data->format.height; 1580 else 1581 pix->height = src_data->format.height; 1582 1583 fdp1_compute_stride(pix, fmt); 1584 } 1585 1586 static int fdp1_try_fmt(struct file *file, void *priv, struct v4l2_format *f) 1587 { 1588 struct fdp1_ctx *ctx = fh_to_ctx(priv); 1589 1590 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 1591 fdp1_try_fmt_output(ctx, NULL, &f->fmt.pix_mp); 1592 else 1593 fdp1_try_fmt_capture(ctx, NULL, &f->fmt.pix_mp); 1594 1595 dprintk(ctx->fdp1, "Try %s format: %4.4s (0x%08x) %ux%u field %u\n", 1596 V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", 1597 (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, 1598 f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); 1599 1600 return 0; 1601 } 1602 1603 static void fdp1_set_format(struct fdp1_ctx *ctx, 1604 struct v4l2_pix_format_mplane *pix, 1605 enum v4l2_buf_type type) 1606 { 1607 struct fdp1_q_data *q_data = get_q_data(ctx, type); 1608 const struct fdp1_fmt *fmtinfo; 1609 1610 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) 1611 fdp1_try_fmt_output(ctx, &fmtinfo, pix); 1612 else 1613 fdp1_try_fmt_capture(ctx, &fmtinfo, pix); 1614 1615 q_data->fmt = fmtinfo; 1616 q_data->format = *pix; 1617 1618 q_data->vsize = pix->height; 1619 if (pix->field != V4L2_FIELD_NONE) 1620 q_data->vsize /= 2; 1621 1622 q_data->stride_y = pix->plane_fmt[0].bytesperline; 1623 q_data->stride_c = pix->plane_fmt[1].bytesperline; 1624 1625 /* Adjust strides for interleaved buffers */ 1626 if (pix->field == V4L2_FIELD_INTERLACED || 1627 pix->field == V4L2_FIELD_INTERLACED_TB || 1628 pix->field == V4L2_FIELD_INTERLACED_BT) { 1629 q_data->stride_y *= 2; 1630 q_data->stride_c *= 2; 1631 } 1632 1633 /* Propagate the format from the output node to the capture node. */ 1634 if (type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { 1635 struct fdp1_q_data *dst_data = &ctx->cap_q; 1636 1637 /* 1638 * Copy the format, clear the per-plane bytes per line and image 1639 * size, override the field and double the height if needed. 1640 */ 1641 dst_data->format = q_data->format; 1642 memset(dst_data->format.plane_fmt, 0, 1643 sizeof(dst_data->format.plane_fmt)); 1644 1645 dst_data->format.field = V4L2_FIELD_NONE; 1646 if (pix->field == V4L2_FIELD_ALTERNATE) 1647 dst_data->format.height *= 2; 1648 1649 fdp1_try_fmt_capture(ctx, &dst_data->fmt, &dst_data->format); 1650 1651 dst_data->vsize = dst_data->format.height; 1652 dst_data->stride_y = dst_data->format.plane_fmt[0].bytesperline; 1653 dst_data->stride_c = dst_data->format.plane_fmt[1].bytesperline; 1654 } 1655 } 1656 1657 static int fdp1_s_fmt(struct file *file, void *priv, struct v4l2_format *f) 1658 { 1659 struct fdp1_ctx *ctx = fh_to_ctx(priv); 1660 struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; 1661 struct vb2_queue *vq = v4l2_m2m_get_vq(m2m_ctx, f->type); 1662 1663 if (vb2_is_busy(vq)) { 1664 v4l2_err(&ctx->fdp1->v4l2_dev, "%s queue busy\n", __func__); 1665 return -EBUSY; 1666 } 1667 1668 fdp1_set_format(ctx, &f->fmt.pix_mp, f->type); 1669 1670 dprintk(ctx->fdp1, "Set %s format: %4.4s (0x%08x) %ux%u field %u\n", 1671 V4L2_TYPE_IS_OUTPUT(f->type) ? "output" : "capture", 1672 (char *)&f->fmt.pix_mp.pixelformat, f->fmt.pix_mp.pixelformat, 1673 f->fmt.pix_mp.width, f->fmt.pix_mp.height, f->fmt.pix_mp.field); 1674 1675 return 0; 1676 } 1677 1678 static int fdp1_g_ctrl(struct v4l2_ctrl *ctrl) 1679 { 1680 struct fdp1_ctx *ctx = 1681 container_of(ctrl->handler, struct fdp1_ctx, hdl); 1682 struct fdp1_q_data *src_q_data = &ctx->out_q; 1683 1684 switch (ctrl->id) { 1685 case V4L2_CID_MIN_BUFFERS_FOR_CAPTURE: 1686 if (V4L2_FIELD_HAS_BOTH(src_q_data->format.field)) 1687 ctrl->val = 2; 1688 else 1689 ctrl->val = 1; 1690 return 0; 1691 } 1692 1693 return 1; 1694 } 1695 1696 static int fdp1_s_ctrl(struct v4l2_ctrl *ctrl) 1697 { 1698 struct fdp1_ctx *ctx = 1699 container_of(ctrl->handler, struct fdp1_ctx, hdl); 1700 1701 switch (ctrl->id) { 1702 case V4L2_CID_ALPHA_COMPONENT: 1703 ctx->alpha = ctrl->val; 1704 break; 1705 1706 case V4L2_CID_DEINTERLACING_MODE: 1707 ctx->deint_mode = ctrl->val; 1708 break; 1709 } 1710 1711 return 0; 1712 } 1713 1714 static const struct v4l2_ctrl_ops fdp1_ctrl_ops = { 1715 .s_ctrl = fdp1_s_ctrl, 1716 .g_volatile_ctrl = fdp1_g_ctrl, 1717 }; 1718 1719 static const char * const fdp1_ctrl_deint_menu[] = { 1720 "Progressive", 1721 "Adaptive 2D/3D", 1722 "Fixed 2D", 1723 "Fixed 3D", 1724 "Previous field", 1725 "Next field", 1726 NULL 1727 }; 1728 1729 static const struct v4l2_ioctl_ops fdp1_ioctl_ops = { 1730 .vidioc_querycap = fdp1_vidioc_querycap, 1731 1732 .vidioc_enum_fmt_vid_cap = fdp1_enum_fmt_vid_cap, 1733 .vidioc_enum_fmt_vid_out = fdp1_enum_fmt_vid_out, 1734 .vidioc_g_fmt_vid_cap_mplane = fdp1_g_fmt, 1735 .vidioc_g_fmt_vid_out_mplane = fdp1_g_fmt, 1736 .vidioc_try_fmt_vid_cap_mplane = fdp1_try_fmt, 1737 .vidioc_try_fmt_vid_out_mplane = fdp1_try_fmt, 1738 .vidioc_s_fmt_vid_cap_mplane = fdp1_s_fmt, 1739 .vidioc_s_fmt_vid_out_mplane = fdp1_s_fmt, 1740 1741 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, 1742 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, 1743 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, 1744 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, 1745 .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, 1746 .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, 1747 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, 1748 1749 .vidioc_streamon = v4l2_m2m_ioctl_streamon, 1750 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, 1751 1752 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, 1753 .vidioc_unsubscribe_event = v4l2_event_unsubscribe, 1754 }; 1755 1756 /* 1757 * Queue operations 1758 */ 1759 1760 static int fdp1_queue_setup(struct vb2_queue *vq, 1761 unsigned int *nbuffers, unsigned int *nplanes, 1762 unsigned int sizes[], 1763 struct device *alloc_ctxs[]) 1764 { 1765 struct fdp1_ctx *ctx = vb2_get_drv_priv(vq); 1766 struct fdp1_q_data *q_data; 1767 unsigned int i; 1768 1769 q_data = get_q_data(ctx, vq->type); 1770 1771 if (*nplanes) { 1772 if (*nplanes > FDP1_MAX_PLANES) 1773 return -EINVAL; 1774 1775 return 0; 1776 } 1777 1778 *nplanes = q_data->format.num_planes; 1779 1780 for (i = 0; i < *nplanes; i++) 1781 sizes[i] = q_data->format.plane_fmt[i].sizeimage; 1782 1783 return 0; 1784 } 1785 1786 static void fdp1_buf_prepare_field(struct fdp1_q_data *q_data, 1787 struct vb2_v4l2_buffer *vbuf, 1788 unsigned int field_num) 1789 { 1790 struct fdp1_buffer *buf = to_fdp1_buffer(vbuf); 1791 struct fdp1_field_buffer *fbuf = &buf->fields[field_num]; 1792 unsigned int num_fields; 1793 unsigned int i; 1794 1795 num_fields = V4L2_FIELD_HAS_BOTH(vbuf->field) ? 2 : 1; 1796 1797 fbuf->vb = vbuf; 1798 fbuf->last_field = (field_num + 1) == num_fields; 1799 1800 for (i = 0; i < vbuf->vb2_buf.num_planes; ++i) 1801 fbuf->addrs[i] = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, i); 1802 1803 switch (vbuf->field) { 1804 case V4L2_FIELD_INTERLACED: 1805 /* 1806 * Interlaced means bottom-top for 60Hz TV standards (NTSC) and 1807 * top-bottom for 50Hz. As TV standards are not applicable to 1808 * the mem-to-mem API, use the height as a heuristic. 1809 */ 1810 fbuf->field = (q_data->format.height < 576) == field_num 1811 ? V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM; 1812 break; 1813 case V4L2_FIELD_INTERLACED_TB: 1814 case V4L2_FIELD_SEQ_TB: 1815 fbuf->field = field_num ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP; 1816 break; 1817 case V4L2_FIELD_INTERLACED_BT: 1818 case V4L2_FIELD_SEQ_BT: 1819 fbuf->field = field_num ? V4L2_FIELD_TOP : V4L2_FIELD_BOTTOM; 1820 break; 1821 default: 1822 fbuf->field = vbuf->field; 1823 break; 1824 } 1825 1826 /* Buffer is completed */ 1827 if (!field_num) 1828 return; 1829 1830 /* Adjust buffer addresses for second field */ 1831 switch (vbuf->field) { 1832 case V4L2_FIELD_INTERLACED: 1833 case V4L2_FIELD_INTERLACED_TB: 1834 case V4L2_FIELD_INTERLACED_BT: 1835 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) 1836 fbuf->addrs[i] += 1837 (i == 0 ? q_data->stride_y : q_data->stride_c); 1838 break; 1839 case V4L2_FIELD_SEQ_TB: 1840 case V4L2_FIELD_SEQ_BT: 1841 for (i = 0; i < vbuf->vb2_buf.num_planes; i++) 1842 fbuf->addrs[i] += q_data->vsize * 1843 (i == 0 ? q_data->stride_y : q_data->stride_c); 1844 break; 1845 } 1846 } 1847 1848 static int fdp1_buf_prepare(struct vb2_buffer *vb) 1849 { 1850 struct fdp1_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1851 struct fdp1_q_data *q_data = get_q_data(ctx, vb->vb2_queue->type); 1852 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1853 struct fdp1_buffer *buf = to_fdp1_buffer(vbuf); 1854 unsigned int i; 1855 1856 if (V4L2_TYPE_IS_OUTPUT(vb->vb2_queue->type)) { 1857 bool field_valid = true; 1858 1859 /* Validate the buffer field. */ 1860 switch (q_data->format.field) { 1861 case V4L2_FIELD_NONE: 1862 if (vbuf->field != V4L2_FIELD_NONE) 1863 field_valid = false; 1864 break; 1865 1866 case V4L2_FIELD_ALTERNATE: 1867 if (vbuf->field != V4L2_FIELD_TOP && 1868 vbuf->field != V4L2_FIELD_BOTTOM) 1869 field_valid = false; 1870 break; 1871 1872 case V4L2_FIELD_INTERLACED: 1873 case V4L2_FIELD_SEQ_TB: 1874 case V4L2_FIELD_SEQ_BT: 1875 case V4L2_FIELD_INTERLACED_TB: 1876 case V4L2_FIELD_INTERLACED_BT: 1877 if (vbuf->field != q_data->format.field) 1878 field_valid = false; 1879 break; 1880 } 1881 1882 if (!field_valid) { 1883 dprintk(ctx->fdp1, 1884 "buffer field %u invalid for format field %u\n", 1885 vbuf->field, q_data->format.field); 1886 return -EINVAL; 1887 } 1888 } else { 1889 vbuf->field = V4L2_FIELD_NONE; 1890 } 1891 1892 /* Validate the planes sizes. */ 1893 for (i = 0; i < q_data->format.num_planes; i++) { 1894 unsigned long size = q_data->format.plane_fmt[i].sizeimage; 1895 1896 if (vb2_plane_size(vb, i) < size) { 1897 dprintk(ctx->fdp1, 1898 "data will not fit into plane [%u/%u] (%lu < %lu)\n", 1899 i, q_data->format.num_planes, 1900 vb2_plane_size(vb, i), size); 1901 return -EINVAL; 1902 } 1903 1904 /* We have known size formats all around */ 1905 vb2_set_plane_payload(vb, i, size); 1906 } 1907 1908 buf->num_fields = V4L2_FIELD_HAS_BOTH(vbuf->field) ? 2 : 1; 1909 for (i = 0; i < buf->num_fields; ++i) 1910 fdp1_buf_prepare_field(q_data, vbuf, i); 1911 1912 return 0; 1913 } 1914 1915 static void fdp1_buf_queue(struct vb2_buffer *vb) 1916 { 1917 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); 1918 struct fdp1_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); 1919 1920 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); 1921 } 1922 1923 static int fdp1_start_streaming(struct vb2_queue *q, unsigned int count) 1924 { 1925 struct fdp1_ctx *ctx = vb2_get_drv_priv(q); 1926 struct fdp1_q_data *q_data = get_q_data(ctx, q->type); 1927 1928 if (V4L2_TYPE_IS_OUTPUT(q->type)) { 1929 /* 1930 * Force our deint_mode when we are progressive, 1931 * ignoring any setting on the device from the user, 1932 * Otherwise, lock in the requested de-interlace mode. 1933 */ 1934 if (q_data->format.field == V4L2_FIELD_NONE) 1935 ctx->deint_mode = FDP1_PROGRESSIVE; 1936 1937 if (ctx->deint_mode == FDP1_ADAPT2D3D) { 1938 u32 stride; 1939 dma_addr_t smsk_base; 1940 const u32 bpp = 2; /* bytes per pixel */ 1941 1942 stride = round_up(q_data->format.width, 8); 1943 1944 ctx->smsk_size = bpp * stride * q_data->vsize; 1945 1946 ctx->smsk_cpu = dma_alloc_coherent(ctx->fdp1->dev, 1947 ctx->smsk_size, &smsk_base, GFP_KERNEL); 1948 1949 if (ctx->smsk_cpu == NULL) { 1950 dprintk(ctx->fdp1, "Failed to alloc smsk\n"); 1951 return -ENOMEM; 1952 } 1953 1954 ctx->smsk_addr[0] = smsk_base; 1955 ctx->smsk_addr[1] = smsk_base + (ctx->smsk_size/2); 1956 } 1957 } 1958 1959 return 0; 1960 } 1961 1962 static void fdp1_stop_streaming(struct vb2_queue *q) 1963 { 1964 struct fdp1_ctx *ctx = vb2_get_drv_priv(q); 1965 struct vb2_v4l2_buffer *vbuf; 1966 unsigned long flags; 1967 1968 while (1) { 1969 if (V4L2_TYPE_IS_OUTPUT(q->type)) 1970 vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); 1971 else 1972 vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); 1973 if (vbuf == NULL) 1974 break; 1975 spin_lock_irqsave(&ctx->fdp1->irqlock, flags); 1976 v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); 1977 spin_unlock_irqrestore(&ctx->fdp1->irqlock, flags); 1978 } 1979 1980 /* Empty Output queues */ 1981 if (V4L2_TYPE_IS_OUTPUT(q->type)) { 1982 /* Empty our internal queues */ 1983 struct fdp1_field_buffer *fbuf; 1984 1985 /* Free any queued buffers */ 1986 fbuf = fdp1_dequeue_field(ctx); 1987 while (fbuf != NULL) { 1988 fdp1_field_complete(ctx, fbuf); 1989 fbuf = fdp1_dequeue_field(ctx); 1990 } 1991 1992 /* Free smsk_data */ 1993 if (ctx->smsk_cpu) { 1994 dma_free_coherent(ctx->fdp1->dev, ctx->smsk_size, 1995 ctx->smsk_cpu, ctx->smsk_addr[0]); 1996 ctx->smsk_addr[0] = ctx->smsk_addr[1] = 0; 1997 ctx->smsk_cpu = NULL; 1998 } 1999 2000 WARN(!list_empty(&ctx->fields_queue), 2001 "Buffer queue not empty"); 2002 } else { 2003 /* Empty Capture queues (Jobs) */ 2004 struct fdp1_job *job; 2005 2006 job = get_queued_job(ctx->fdp1); 2007 while (job) { 2008 if (FDP1_DEINT_MODE_USES_PREV(ctx->deint_mode)) 2009 fdp1_field_complete(ctx, job->previous); 2010 else 2011 fdp1_field_complete(ctx, job->active); 2012 2013 v4l2_m2m_buf_done(job->dst->vb, VB2_BUF_STATE_ERROR); 2014 job->dst = NULL; 2015 2016 job = get_queued_job(ctx->fdp1); 2017 } 2018 2019 /* Free any held buffer in the ctx */ 2020 fdp1_field_complete(ctx, ctx->previous); 2021 2022 WARN(!list_empty(&ctx->fdp1->queued_job_list), 2023 "Queued Job List not empty"); 2024 2025 WARN(!list_empty(&ctx->fdp1->hw_job_list), 2026 "HW Job list not empty"); 2027 } 2028 } 2029 2030 static const struct vb2_ops fdp1_qops = { 2031 .queue_setup = fdp1_queue_setup, 2032 .buf_prepare = fdp1_buf_prepare, 2033 .buf_queue = fdp1_buf_queue, 2034 .start_streaming = fdp1_start_streaming, 2035 .stop_streaming = fdp1_stop_streaming, 2036 .wait_prepare = vb2_ops_wait_prepare, 2037 .wait_finish = vb2_ops_wait_finish, 2038 }; 2039 2040 static int queue_init(void *priv, struct vb2_queue *src_vq, 2041 struct vb2_queue *dst_vq) 2042 { 2043 struct fdp1_ctx *ctx = priv; 2044 int ret; 2045 2046 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; 2047 src_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; 2048 src_vq->drv_priv = ctx; 2049 src_vq->buf_struct_size = sizeof(struct fdp1_buffer); 2050 src_vq->ops = &fdp1_qops; 2051 src_vq->mem_ops = &vb2_dma_contig_memops; 2052 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 2053 src_vq->lock = &ctx->fdp1->dev_mutex; 2054 src_vq->dev = ctx->fdp1->dev; 2055 2056 ret = vb2_queue_init(src_vq); 2057 if (ret) 2058 return ret; 2059 2060 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; 2061 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; 2062 dst_vq->drv_priv = ctx; 2063 dst_vq->buf_struct_size = sizeof(struct fdp1_buffer); 2064 dst_vq->ops = &fdp1_qops; 2065 dst_vq->mem_ops = &vb2_dma_contig_memops; 2066 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; 2067 dst_vq->lock = &ctx->fdp1->dev_mutex; 2068 dst_vq->dev = ctx->fdp1->dev; 2069 2070 return vb2_queue_init(dst_vq); 2071 } 2072 2073 /* 2074 * File operations 2075 */ 2076 static int fdp1_open(struct file *file) 2077 { 2078 struct fdp1_dev *fdp1 = video_drvdata(file); 2079 struct v4l2_pix_format_mplane format; 2080 struct fdp1_ctx *ctx = NULL; 2081 struct v4l2_ctrl *ctrl; 2082 int ret = 0; 2083 2084 if (mutex_lock_interruptible(&fdp1->dev_mutex)) 2085 return -ERESTARTSYS; 2086 2087 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 2088 if (!ctx) { 2089 ret = -ENOMEM; 2090 goto done; 2091 } 2092 2093 v4l2_fh_init(&ctx->fh, video_devdata(file)); 2094 file->private_data = &ctx->fh; 2095 ctx->fdp1 = fdp1; 2096 2097 /* Initialise Queues */ 2098 INIT_LIST_HEAD(&ctx->fields_queue); 2099 2100 ctx->translen = 1; 2101 ctx->sequence = 0; 2102 2103 /* Initialise controls */ 2104 2105 v4l2_ctrl_handler_init(&ctx->hdl, 3); 2106 v4l2_ctrl_new_std_menu_items(&ctx->hdl, &fdp1_ctrl_ops, 2107 V4L2_CID_DEINTERLACING_MODE, 2108 FDP1_NEXTFIELD, BIT(0), FDP1_FIXED3D, 2109 fdp1_ctrl_deint_menu); 2110 2111 ctrl = v4l2_ctrl_new_std(&ctx->hdl, &fdp1_ctrl_ops, 2112 V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 2, 1, 1); 2113 if (ctrl) 2114 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE; 2115 2116 v4l2_ctrl_new_std(&ctx->hdl, &fdp1_ctrl_ops, 2117 V4L2_CID_ALPHA_COMPONENT, 0, 255, 1, 255); 2118 2119 if (ctx->hdl.error) { 2120 ret = ctx->hdl.error; 2121 goto error_ctx; 2122 } 2123 2124 ctx->fh.ctrl_handler = &ctx->hdl; 2125 v4l2_ctrl_handler_setup(&ctx->hdl); 2126 2127 /* Configure default parameters. */ 2128 memset(&format, 0, sizeof(format)); 2129 fdp1_set_format(ctx, &format, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); 2130 2131 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(fdp1->m2m_dev, ctx, &queue_init); 2132 2133 if (IS_ERR(ctx->fh.m2m_ctx)) { 2134 ret = PTR_ERR(ctx->fh.m2m_ctx); 2135 goto error_ctx; 2136 } 2137 2138 /* Perform any power management required */ 2139 ret = pm_runtime_resume_and_get(fdp1->dev); 2140 if (ret < 0) 2141 goto error_pm; 2142 2143 v4l2_fh_add(&ctx->fh); 2144 2145 dprintk(fdp1, "Created instance: %p, m2m_ctx: %p\n", 2146 ctx, ctx->fh.m2m_ctx); 2147 2148 mutex_unlock(&fdp1->dev_mutex); 2149 return 0; 2150 2151 error_pm: 2152 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 2153 error_ctx: 2154 v4l2_ctrl_handler_free(&ctx->hdl); 2155 kfree(ctx); 2156 done: 2157 mutex_unlock(&fdp1->dev_mutex); 2158 return ret; 2159 } 2160 2161 static int fdp1_release(struct file *file) 2162 { 2163 struct fdp1_dev *fdp1 = video_drvdata(file); 2164 struct fdp1_ctx *ctx = fh_to_ctx(file->private_data); 2165 2166 dprintk(fdp1, "Releasing instance %p\n", ctx); 2167 2168 v4l2_fh_del(&ctx->fh); 2169 v4l2_fh_exit(&ctx->fh); 2170 v4l2_ctrl_handler_free(&ctx->hdl); 2171 mutex_lock(&fdp1->dev_mutex); 2172 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx); 2173 mutex_unlock(&fdp1->dev_mutex); 2174 kfree(ctx); 2175 2176 pm_runtime_put(fdp1->dev); 2177 2178 return 0; 2179 } 2180 2181 static const struct v4l2_file_operations fdp1_fops = { 2182 .owner = THIS_MODULE, 2183 .open = fdp1_open, 2184 .release = fdp1_release, 2185 .poll = v4l2_m2m_fop_poll, 2186 .unlocked_ioctl = video_ioctl2, 2187 .mmap = v4l2_m2m_fop_mmap, 2188 }; 2189 2190 static const struct video_device fdp1_videodev = { 2191 .name = DRIVER_NAME, 2192 .vfl_dir = VFL_DIR_M2M, 2193 .fops = &fdp1_fops, 2194 .device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING, 2195 .ioctl_ops = &fdp1_ioctl_ops, 2196 .minor = -1, 2197 .release = video_device_release_empty, 2198 }; 2199 2200 static const struct v4l2_m2m_ops m2m_ops = { 2201 .device_run = fdp1_m2m_device_run, 2202 .job_ready = fdp1_m2m_job_ready, 2203 .job_abort = fdp1_m2m_job_abort, 2204 }; 2205 2206 static irqreturn_t fdp1_irq_handler(int irq, void *dev_id) 2207 { 2208 struct fdp1_dev *fdp1 = dev_id; 2209 u32 int_status; 2210 u32 ctl_status; 2211 u32 vint_cnt; 2212 u32 cycles; 2213 2214 int_status = fdp1_read(fdp1, FD1_CTL_IRQSTA); 2215 cycles = fdp1_read(fdp1, FD1_CTL_VCYCLE_STAT); 2216 ctl_status = fdp1_read(fdp1, FD1_CTL_STATUS); 2217 vint_cnt = (ctl_status & FD1_CTL_STATUS_VINT_CNT_MASK) >> 2218 FD1_CTL_STATUS_VINT_CNT_SHIFT; 2219 2220 /* Clear interrupts */ 2221 fdp1_write(fdp1, ~(int_status) & FD1_CTL_IRQ_MASK, FD1_CTL_IRQSTA); 2222 2223 if (debug >= 2) { 2224 dprintk(fdp1, "IRQ: 0x%x %s%s%s\n", int_status, 2225 int_status & FD1_CTL_IRQ_VERE ? "[Error]" : "[!E]", 2226 int_status & FD1_CTL_IRQ_VINTE ? "[VSync]" : "[!V]", 2227 int_status & FD1_CTL_IRQ_FREE ? "[FrameEnd]" : "[!F]"); 2228 2229 dprintk(fdp1, "CycleStatus = %d (%dms)\n", 2230 cycles, cycles/(fdp1->clk_rate/1000)); 2231 2232 dprintk(fdp1, 2233 "Control Status = 0x%08x : VINT_CNT = %d %s:%s:%s:%s\n", 2234 ctl_status, vint_cnt, 2235 ctl_status & FD1_CTL_STATUS_SGREGSET ? "RegSet" : "", 2236 ctl_status & FD1_CTL_STATUS_SGVERR ? "Vsync Error" : "", 2237 ctl_status & FD1_CTL_STATUS_SGFREND ? "FrameEnd" : "", 2238 ctl_status & FD1_CTL_STATUS_BSY ? "Busy" : ""); 2239 dprintk(fdp1, "***********************************\n"); 2240 } 2241 2242 /* Spurious interrupt */ 2243 if (!(FD1_CTL_IRQ_MASK & int_status)) 2244 return IRQ_NONE; 2245 2246 /* Work completed, release the frame */ 2247 if (FD1_CTL_IRQ_VERE & int_status) 2248 device_frame_end(fdp1, VB2_BUF_STATE_ERROR); 2249 else if (FD1_CTL_IRQ_FREE & int_status) 2250 device_frame_end(fdp1, VB2_BUF_STATE_DONE); 2251 2252 return IRQ_HANDLED; 2253 } 2254 2255 static int fdp1_probe(struct platform_device *pdev) 2256 { 2257 struct fdp1_dev *fdp1; 2258 struct video_device *vfd; 2259 struct device_node *fcp_node; 2260 struct clk *clk; 2261 unsigned int i; 2262 2263 int ret; 2264 int hw_version; 2265 2266 fdp1 = devm_kzalloc(&pdev->dev, sizeof(*fdp1), GFP_KERNEL); 2267 if (!fdp1) 2268 return -ENOMEM; 2269 2270 INIT_LIST_HEAD(&fdp1->free_job_list); 2271 INIT_LIST_HEAD(&fdp1->queued_job_list); 2272 INIT_LIST_HEAD(&fdp1->hw_job_list); 2273 2274 /* Initialise the jobs on the free list */ 2275 for (i = 0; i < ARRAY_SIZE(fdp1->jobs); i++) 2276 list_add(&fdp1->jobs[i].list, &fdp1->free_job_list); 2277 2278 mutex_init(&fdp1->dev_mutex); 2279 2280 spin_lock_init(&fdp1->irqlock); 2281 spin_lock_init(&fdp1->device_process_lock); 2282 fdp1->dev = &pdev->dev; 2283 platform_set_drvdata(pdev, fdp1); 2284 2285 /* Memory-mapped registers */ 2286 fdp1->regs = devm_platform_ioremap_resource(pdev, 0); 2287 if (IS_ERR(fdp1->regs)) 2288 return PTR_ERR(fdp1->regs); 2289 2290 /* Interrupt service routine registration */ 2291 ret = platform_get_irq(pdev, 0); 2292 if (ret < 0) 2293 return ret; 2294 fdp1->irq = ret; 2295 2296 ret = devm_request_irq(&pdev->dev, fdp1->irq, fdp1_irq_handler, 0, 2297 dev_name(&pdev->dev), fdp1); 2298 if (ret) { 2299 dev_err(&pdev->dev, "cannot claim IRQ %d\n", fdp1->irq); 2300 return ret; 2301 } 2302 2303 /* FCP */ 2304 fcp_node = of_parse_phandle(pdev->dev.of_node, "renesas,fcp", 0); 2305 if (fcp_node) { 2306 fdp1->fcp = rcar_fcp_get(fcp_node); 2307 of_node_put(fcp_node); 2308 if (IS_ERR(fdp1->fcp)) { 2309 dev_dbg(&pdev->dev, "FCP not found (%ld)\n", 2310 PTR_ERR(fdp1->fcp)); 2311 return PTR_ERR(fdp1->fcp); 2312 } 2313 } 2314 2315 /* Determine our clock rate */ 2316 clk = clk_get(&pdev->dev, NULL); 2317 if (IS_ERR(clk)) { 2318 ret = PTR_ERR(clk); 2319 goto put_dev; 2320 } 2321 2322 fdp1->clk_rate = clk_get_rate(clk); 2323 clk_put(clk); 2324 2325 /* V4L2 device registration */ 2326 ret = v4l2_device_register(&pdev->dev, &fdp1->v4l2_dev); 2327 if (ret) { 2328 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n"); 2329 goto put_dev; 2330 } 2331 2332 /* M2M registration */ 2333 fdp1->m2m_dev = v4l2_m2m_init(&m2m_ops); 2334 if (IS_ERR(fdp1->m2m_dev)) { 2335 v4l2_err(&fdp1->v4l2_dev, "Failed to init mem2mem device\n"); 2336 ret = PTR_ERR(fdp1->m2m_dev); 2337 goto unreg_dev; 2338 } 2339 2340 /* Video registration */ 2341 fdp1->vfd = fdp1_videodev; 2342 vfd = &fdp1->vfd; 2343 vfd->lock = &fdp1->dev_mutex; 2344 vfd->v4l2_dev = &fdp1->v4l2_dev; 2345 video_set_drvdata(vfd, fdp1); 2346 strscpy(vfd->name, fdp1_videodev.name, sizeof(vfd->name)); 2347 2348 ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0); 2349 if (ret) { 2350 v4l2_err(&fdp1->v4l2_dev, "Failed to register video device\n"); 2351 goto release_m2m; 2352 } 2353 2354 v4l2_info(&fdp1->v4l2_dev, "Device registered as /dev/video%d\n", 2355 vfd->num); 2356 2357 /* Power up the cells to read HW */ 2358 pm_runtime_enable(&pdev->dev); 2359 ret = pm_runtime_resume_and_get(fdp1->dev); 2360 if (ret < 0) 2361 goto disable_pm; 2362 2363 hw_version = fdp1_read(fdp1, FD1_IP_INTDATA); 2364 switch (hw_version) { 2365 case FD1_IP_GEN2: 2366 dprintk(fdp1, "FDP1 Version R-Car Gen2\n"); 2367 break; 2368 case FD1_IP_M3W: 2369 dprintk(fdp1, "FDP1 Version R-Car M3-W\n"); 2370 break; 2371 case FD1_IP_H3: 2372 dprintk(fdp1, "FDP1 Version R-Car H3\n"); 2373 break; 2374 case FD1_IP_M3N: 2375 dprintk(fdp1, "FDP1 Version R-Car M3-N\n"); 2376 break; 2377 case FD1_IP_E3: 2378 dprintk(fdp1, "FDP1 Version R-Car E3\n"); 2379 break; 2380 default: 2381 dev_err(fdp1->dev, "FDP1 Unidentifiable (0x%08x)\n", 2382 hw_version); 2383 } 2384 2385 /* Allow the hw to sleep until an open call puts it to use */ 2386 pm_runtime_put(fdp1->dev); 2387 2388 return 0; 2389 2390 disable_pm: 2391 pm_runtime_disable(fdp1->dev); 2392 2393 release_m2m: 2394 v4l2_m2m_release(fdp1->m2m_dev); 2395 2396 unreg_dev: 2397 v4l2_device_unregister(&fdp1->v4l2_dev); 2398 2399 put_dev: 2400 rcar_fcp_put(fdp1->fcp); 2401 return ret; 2402 } 2403 2404 static void fdp1_remove(struct platform_device *pdev) 2405 { 2406 struct fdp1_dev *fdp1 = platform_get_drvdata(pdev); 2407 2408 v4l2_m2m_release(fdp1->m2m_dev); 2409 video_unregister_device(&fdp1->vfd); 2410 v4l2_device_unregister(&fdp1->v4l2_dev); 2411 pm_runtime_disable(&pdev->dev); 2412 rcar_fcp_put(fdp1->fcp); 2413 } 2414 2415 static int __maybe_unused fdp1_pm_runtime_suspend(struct device *dev) 2416 { 2417 struct fdp1_dev *fdp1 = dev_get_drvdata(dev); 2418 2419 rcar_fcp_disable(fdp1->fcp); 2420 2421 return 0; 2422 } 2423 2424 static int __maybe_unused fdp1_pm_runtime_resume(struct device *dev) 2425 { 2426 struct fdp1_dev *fdp1 = dev_get_drvdata(dev); 2427 2428 /* Program in the static LUTs */ 2429 fdp1_set_lut(fdp1); 2430 2431 return rcar_fcp_enable(fdp1->fcp); 2432 } 2433 2434 static const struct dev_pm_ops fdp1_pm_ops = { 2435 SET_RUNTIME_PM_OPS(fdp1_pm_runtime_suspend, 2436 fdp1_pm_runtime_resume, 2437 NULL) 2438 }; 2439 2440 static const struct of_device_id fdp1_dt_ids[] = { 2441 { .compatible = "renesas,fdp1" }, 2442 { }, 2443 }; 2444 MODULE_DEVICE_TABLE(of, fdp1_dt_ids); 2445 2446 static struct platform_driver fdp1_pdrv = { 2447 .probe = fdp1_probe, 2448 .remove_new = fdp1_remove, 2449 .driver = { 2450 .name = DRIVER_NAME, 2451 .of_match_table = fdp1_dt_ids, 2452 .pm = &fdp1_pm_ops, 2453 }, 2454 }; 2455 2456 module_platform_driver(fdp1_pdrv); 2457 2458 MODULE_DESCRIPTION("Renesas R-Car Fine Display Processor Driver"); 2459 MODULE_AUTHOR("Kieran Bingham <kieran@bingham.xyz>"); 2460 MODULE_LICENSE("GPL"); 2461 MODULE_ALIAS("platform:" DRIVER_NAME); 2462