1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <linux/sys_soc.h> 19 20 #include <media/mipi-csi2.h> 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-device.h> 23 #include <media/v4l2-fwnode.h> 24 #include <media/v4l2-mc.h> 25 #include <media/v4l2-subdev.h> 26 27 struct rcar_csi2; 28 29 /* Register offsets and bits */ 30 31 /* Control Timing Select */ 32 #define TREF_REG 0x00 33 #define TREF_TREF BIT(0) 34 35 /* Software Reset */ 36 #define SRST_REG 0x04 37 #define SRST_SRST BIT(0) 38 39 /* PHY Operation Control */ 40 #define PHYCNT_REG 0x08 41 #define PHYCNT_SHUTDOWNZ BIT(17) 42 #define PHYCNT_RSTZ BIT(16) 43 #define PHYCNT_ENABLECLK BIT(4) 44 #define PHYCNT_ENABLE_3 BIT(3) 45 #define PHYCNT_ENABLE_2 BIT(2) 46 #define PHYCNT_ENABLE_1 BIT(1) 47 #define PHYCNT_ENABLE_0 BIT(0) 48 49 /* Checksum Control */ 50 #define CHKSUM_REG 0x0c 51 #define CHKSUM_ECC_EN BIT(1) 52 #define CHKSUM_CRC_EN BIT(0) 53 54 /* 55 * Channel Data Type Select 56 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 57 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 58 */ 59 #define VCDT_REG 0x10 60 #define VCDT2_REG 0x14 61 #define VCDT_VCDTN_EN BIT(15) 62 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 63 #define VCDT_SEL_DTN_ON BIT(6) 64 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 65 66 /* Frame Data Type Select */ 67 #define FRDT_REG 0x18 68 69 /* Field Detection Control */ 70 #define FLD_REG 0x1c 71 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 72 #define FLD_DET_SEL(n) (((n) & 0x3) << 4) 73 #define FLD_FLD_EN4 BIT(3) 74 #define FLD_FLD_EN3 BIT(2) 75 #define FLD_FLD_EN2 BIT(1) 76 #define FLD_FLD_EN BIT(0) 77 78 /* Automatic Standby Control */ 79 #define ASTBY_REG 0x20 80 81 /* Long Data Type Setting 0 */ 82 #define LNGDT0_REG 0x28 83 84 /* Long Data Type Setting 1 */ 85 #define LNGDT1_REG 0x2c 86 87 /* Interrupt Enable */ 88 #define INTEN_REG 0x30 89 #define INTEN_INT_AFIFO_OF BIT(27) 90 #define INTEN_INT_ERRSOTHS BIT(4) 91 #define INTEN_INT_ERRSOTSYNCHS BIT(3) 92 93 /* Interrupt Source Mask */ 94 #define INTCLOSE_REG 0x34 95 96 /* Interrupt Status Monitor */ 97 #define INTSTATE_REG 0x38 98 #define INTSTATE_INT_ULPS_START BIT(7) 99 #define INTSTATE_INT_ULPS_END BIT(6) 100 101 /* Interrupt Error Status Monitor */ 102 #define INTERRSTATE_REG 0x3c 103 104 /* Short Packet Data */ 105 #define SHPDAT_REG 0x40 106 107 /* Short Packet Count */ 108 #define SHPCNT_REG 0x44 109 110 /* LINK Operation Control */ 111 #define LINKCNT_REG 0x48 112 #define LINKCNT_MONITOR_EN BIT(31) 113 #define LINKCNT_REG_MONI_PACT_EN BIT(25) 114 #define LINKCNT_ICLK_NONSTOP BIT(24) 115 116 /* Lane Swap */ 117 #define LSWAP_REG 0x4c 118 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 119 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 120 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 121 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 122 123 /* PHY Test Interface Write Register */ 124 #define PHTW_REG 0x50 125 #define PHTW_DWEN BIT(24) 126 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 127 #define PHTW_CWEN BIT(8) 128 #define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 129 130 #define PHYFRX_REG 0x64 131 #define PHYFRX_FORCERX_MODE_3 BIT(3) 132 #define PHYFRX_FORCERX_MODE_2 BIT(2) 133 #define PHYFRX_FORCERX_MODE_1 BIT(1) 134 #define PHYFRX_FORCERX_MODE_0 BIT(0) 135 136 struct phtw_value { 137 u16 data; 138 u16 code; 139 }; 140 141 struct rcsi2_mbps_reg { 142 u16 mbps; 143 u16 reg; 144 }; 145 146 static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = { 147 { .mbps = 1500, .reg = 0xcc }, 148 { .mbps = 1550, .reg = 0x1d }, 149 { .mbps = 1600, .reg = 0x27 }, 150 { .mbps = 1650, .reg = 0x30 }, 151 { .mbps = 1700, .reg = 0x39 }, 152 { .mbps = 1750, .reg = 0x42 }, 153 { .mbps = 1800, .reg = 0x4b }, 154 { .mbps = 1850, .reg = 0x55 }, 155 { .mbps = 1900, .reg = 0x5e }, 156 { .mbps = 1950, .reg = 0x67 }, 157 { .mbps = 2000, .reg = 0x71 }, 158 { .mbps = 2050, .reg = 0x79 }, 159 { .mbps = 2100, .reg = 0x83 }, 160 { .mbps = 2150, .reg = 0x8c }, 161 { .mbps = 2200, .reg = 0x95 }, 162 { .mbps = 2250, .reg = 0x9e }, 163 { .mbps = 2300, .reg = 0xa7 }, 164 { .mbps = 2350, .reg = 0xb0 }, 165 { .mbps = 2400, .reg = 0xba }, 166 { .mbps = 2450, .reg = 0xc3 }, 167 { .mbps = 2500, .reg = 0xcc }, 168 { /* sentinel */ }, 169 }; 170 171 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = { 172 { .mbps = 80, .reg = 0x86 }, 173 { .mbps = 90, .reg = 0x86 }, 174 { .mbps = 100, .reg = 0x87 }, 175 { .mbps = 110, .reg = 0x87 }, 176 { .mbps = 120, .reg = 0x88 }, 177 { .mbps = 130, .reg = 0x88 }, 178 { .mbps = 140, .reg = 0x89 }, 179 { .mbps = 150, .reg = 0x89 }, 180 { .mbps = 160, .reg = 0x8a }, 181 { .mbps = 170, .reg = 0x8a }, 182 { .mbps = 180, .reg = 0x8b }, 183 { .mbps = 190, .reg = 0x8b }, 184 { .mbps = 205, .reg = 0x8c }, 185 { .mbps = 220, .reg = 0x8d }, 186 { .mbps = 235, .reg = 0x8e }, 187 { .mbps = 250, .reg = 0x8e }, 188 { /* sentinel */ }, 189 }; 190 191 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = { 192 { .mbps = 80, .reg = 0x00 }, 193 { .mbps = 90, .reg = 0x20 }, 194 { .mbps = 100, .reg = 0x40 }, 195 { .mbps = 110, .reg = 0x02 }, 196 { .mbps = 130, .reg = 0x22 }, 197 { .mbps = 140, .reg = 0x42 }, 198 { .mbps = 150, .reg = 0x04 }, 199 { .mbps = 170, .reg = 0x24 }, 200 { .mbps = 180, .reg = 0x44 }, 201 { .mbps = 200, .reg = 0x06 }, 202 { .mbps = 220, .reg = 0x26 }, 203 { .mbps = 240, .reg = 0x46 }, 204 { .mbps = 250, .reg = 0x08 }, 205 { .mbps = 270, .reg = 0x28 }, 206 { .mbps = 300, .reg = 0x0a }, 207 { .mbps = 330, .reg = 0x2a }, 208 { .mbps = 360, .reg = 0x4a }, 209 { .mbps = 400, .reg = 0x0c }, 210 { .mbps = 450, .reg = 0x2c }, 211 { .mbps = 500, .reg = 0x0e }, 212 { .mbps = 550, .reg = 0x2e }, 213 { .mbps = 600, .reg = 0x10 }, 214 { .mbps = 650, .reg = 0x30 }, 215 { .mbps = 700, .reg = 0x12 }, 216 { .mbps = 750, .reg = 0x32 }, 217 { .mbps = 800, .reg = 0x52 }, 218 { .mbps = 850, .reg = 0x72 }, 219 { .mbps = 900, .reg = 0x14 }, 220 { .mbps = 950, .reg = 0x34 }, 221 { .mbps = 1000, .reg = 0x54 }, 222 { .mbps = 1050, .reg = 0x74 }, 223 { .mbps = 1125, .reg = 0x16 }, 224 { /* sentinel */ }, 225 }; 226 227 /* PHY Test Interface Clear */ 228 #define PHTC_REG 0x58 229 #define PHTC_TESTCLR BIT(0) 230 231 /* PHY Frequency Control */ 232 #define PHYPLL_REG 0x68 233 #define PHYPLL_HSFREQRANGE(n) ((n) << 16) 234 235 static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = { 236 { .mbps = 80, .reg = 0x00 }, 237 { .mbps = 90, .reg = 0x10 }, 238 { .mbps = 100, .reg = 0x20 }, 239 { .mbps = 110, .reg = 0x30 }, 240 { .mbps = 120, .reg = 0x01 }, 241 { .mbps = 130, .reg = 0x11 }, 242 { .mbps = 140, .reg = 0x21 }, 243 { .mbps = 150, .reg = 0x31 }, 244 { .mbps = 160, .reg = 0x02 }, 245 { .mbps = 170, .reg = 0x12 }, 246 { .mbps = 180, .reg = 0x22 }, 247 { .mbps = 190, .reg = 0x32 }, 248 { .mbps = 205, .reg = 0x03 }, 249 { .mbps = 220, .reg = 0x13 }, 250 { .mbps = 235, .reg = 0x23 }, 251 { .mbps = 250, .reg = 0x33 }, 252 { .mbps = 275, .reg = 0x04 }, 253 { .mbps = 300, .reg = 0x14 }, 254 { .mbps = 325, .reg = 0x25 }, 255 { .mbps = 350, .reg = 0x35 }, 256 { .mbps = 400, .reg = 0x05 }, 257 { .mbps = 450, .reg = 0x16 }, 258 { .mbps = 500, .reg = 0x26 }, 259 { .mbps = 550, .reg = 0x37 }, 260 { .mbps = 600, .reg = 0x07 }, 261 { .mbps = 650, .reg = 0x18 }, 262 { .mbps = 700, .reg = 0x28 }, 263 { .mbps = 750, .reg = 0x39 }, 264 { .mbps = 800, .reg = 0x09 }, 265 { .mbps = 850, .reg = 0x19 }, 266 { .mbps = 900, .reg = 0x29 }, 267 { .mbps = 950, .reg = 0x3a }, 268 { .mbps = 1000, .reg = 0x0a }, 269 { .mbps = 1050, .reg = 0x1a }, 270 { .mbps = 1100, .reg = 0x2a }, 271 { .mbps = 1150, .reg = 0x3b }, 272 { .mbps = 1200, .reg = 0x0b }, 273 { .mbps = 1250, .reg = 0x1b }, 274 { .mbps = 1300, .reg = 0x2b }, 275 { .mbps = 1350, .reg = 0x3c }, 276 { .mbps = 1400, .reg = 0x0c }, 277 { .mbps = 1450, .reg = 0x1c }, 278 { .mbps = 1500, .reg = 0x2c }, 279 { .mbps = 1550, .reg = 0x3d }, 280 { .mbps = 1600, .reg = 0x0d }, 281 { .mbps = 1650, .reg = 0x1d }, 282 { .mbps = 1700, .reg = 0x2e }, 283 { .mbps = 1750, .reg = 0x3e }, 284 { .mbps = 1800, .reg = 0x0e }, 285 { .mbps = 1850, .reg = 0x1e }, 286 { .mbps = 1900, .reg = 0x2f }, 287 { .mbps = 1950, .reg = 0x3f }, 288 { .mbps = 2000, .reg = 0x0f }, 289 { .mbps = 2050, .reg = 0x40 }, 290 { .mbps = 2100, .reg = 0x41 }, 291 { .mbps = 2150, .reg = 0x42 }, 292 { .mbps = 2200, .reg = 0x43 }, 293 { .mbps = 2300, .reg = 0x45 }, 294 { .mbps = 2350, .reg = 0x46 }, 295 { .mbps = 2400, .reg = 0x47 }, 296 { .mbps = 2450, .reg = 0x48 }, 297 { .mbps = 2500, .reg = 0x49 }, 298 { /* sentinel */ }, 299 }; 300 301 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = { 302 { .mbps = 80, .reg = 0x00 }, 303 { .mbps = 90, .reg = 0x10 }, 304 { .mbps = 100, .reg = 0x20 }, 305 { .mbps = 110, .reg = 0x30 }, 306 { .mbps = 120, .reg = 0x01 }, 307 { .mbps = 130, .reg = 0x11 }, 308 { .mbps = 140, .reg = 0x21 }, 309 { .mbps = 150, .reg = 0x31 }, 310 { .mbps = 160, .reg = 0x02 }, 311 { .mbps = 170, .reg = 0x12 }, 312 { .mbps = 180, .reg = 0x22 }, 313 { .mbps = 190, .reg = 0x32 }, 314 { .mbps = 205, .reg = 0x03 }, 315 { .mbps = 220, .reg = 0x13 }, 316 { .mbps = 235, .reg = 0x23 }, 317 { .mbps = 250, .reg = 0x33 }, 318 { .mbps = 275, .reg = 0x04 }, 319 { .mbps = 300, .reg = 0x14 }, 320 { .mbps = 325, .reg = 0x25 }, 321 { .mbps = 350, .reg = 0x35 }, 322 { .mbps = 400, .reg = 0x05 }, 323 { .mbps = 450, .reg = 0x16 }, 324 { .mbps = 500, .reg = 0x26 }, 325 { .mbps = 550, .reg = 0x37 }, 326 { .mbps = 600, .reg = 0x07 }, 327 { .mbps = 650, .reg = 0x18 }, 328 { .mbps = 700, .reg = 0x28 }, 329 { .mbps = 750, .reg = 0x39 }, 330 { .mbps = 800, .reg = 0x09 }, 331 { .mbps = 850, .reg = 0x19 }, 332 { .mbps = 900, .reg = 0x29 }, 333 { .mbps = 950, .reg = 0x3a }, 334 { .mbps = 1000, .reg = 0x0a }, 335 { .mbps = 1050, .reg = 0x1a }, 336 { .mbps = 1100, .reg = 0x2a }, 337 { .mbps = 1150, .reg = 0x3b }, 338 { .mbps = 1200, .reg = 0x0b }, 339 { .mbps = 1250, .reg = 0x1b }, 340 { .mbps = 1300, .reg = 0x2b }, 341 { .mbps = 1350, .reg = 0x3c }, 342 { .mbps = 1400, .reg = 0x0c }, 343 { .mbps = 1450, .reg = 0x1c }, 344 { .mbps = 1500, .reg = 0x2c }, 345 { /* sentinel */ }, 346 }; 347 348 static const struct rcsi2_mbps_reg hsfreqrange_m3w[] = { 349 { .mbps = 80, .reg = 0x00 }, 350 { .mbps = 90, .reg = 0x10 }, 351 { .mbps = 100, .reg = 0x20 }, 352 { .mbps = 110, .reg = 0x30 }, 353 { .mbps = 120, .reg = 0x01 }, 354 { .mbps = 130, .reg = 0x11 }, 355 { .mbps = 140, .reg = 0x21 }, 356 { .mbps = 150, .reg = 0x31 }, 357 { .mbps = 160, .reg = 0x02 }, 358 { .mbps = 170, .reg = 0x12 }, 359 { .mbps = 180, .reg = 0x22 }, 360 { .mbps = 190, .reg = 0x32 }, 361 { .mbps = 205, .reg = 0x03 }, 362 { .mbps = 220, .reg = 0x13 }, 363 { .mbps = 235, .reg = 0x23 }, 364 { .mbps = 250, .reg = 0x33 }, 365 { .mbps = 275, .reg = 0x04 }, 366 { .mbps = 300, .reg = 0x14 }, 367 { .mbps = 325, .reg = 0x05 }, 368 { .mbps = 350, .reg = 0x15 }, 369 { .mbps = 400, .reg = 0x25 }, 370 { .mbps = 450, .reg = 0x06 }, 371 { .mbps = 500, .reg = 0x16 }, 372 { .mbps = 550, .reg = 0x07 }, 373 { .mbps = 600, .reg = 0x17 }, 374 { .mbps = 650, .reg = 0x08 }, 375 { .mbps = 700, .reg = 0x18 }, 376 { .mbps = 750, .reg = 0x09 }, 377 { .mbps = 800, .reg = 0x19 }, 378 { .mbps = 850, .reg = 0x29 }, 379 { .mbps = 900, .reg = 0x39 }, 380 { .mbps = 950, .reg = 0x0a }, 381 { .mbps = 1000, .reg = 0x1a }, 382 { .mbps = 1050, .reg = 0x2a }, 383 { .mbps = 1100, .reg = 0x3a }, 384 { .mbps = 1150, .reg = 0x0b }, 385 { .mbps = 1200, .reg = 0x1b }, 386 { .mbps = 1250, .reg = 0x2b }, 387 { .mbps = 1300, .reg = 0x3b }, 388 { .mbps = 1350, .reg = 0x0c }, 389 { .mbps = 1400, .reg = 0x1c }, 390 { .mbps = 1450, .reg = 0x2c }, 391 { .mbps = 1500, .reg = 0x3c }, 392 { /* sentinel */ }, 393 }; 394 395 /* PHY ESC Error Monitor */ 396 #define PHEERM_REG 0x74 397 398 /* PHY Clock Lane Monitor */ 399 #define PHCLM_REG 0x78 400 #define PHCLM_STOPSTATECKL BIT(0) 401 402 /* PHY Data Lane Monitor */ 403 #define PHDLM_REG 0x7c 404 405 /* CSI0CLK Frequency Configuration Preset Register */ 406 #define CSI0CLKFCPR_REG 0x260 407 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 408 409 struct rcar_csi2_format { 410 u32 code; 411 unsigned int datatype; 412 unsigned int bpp; 413 }; 414 415 static const struct rcar_csi2_format rcar_csi2_formats[] = { 416 { 417 .code = MEDIA_BUS_FMT_RGB888_1X24, 418 .datatype = MIPI_CSI2_DT_RGB888, 419 .bpp = 24, 420 }, { 421 .code = MEDIA_BUS_FMT_UYVY8_1X16, 422 .datatype = MIPI_CSI2_DT_YUV422_8B, 423 .bpp = 16, 424 }, { 425 .code = MEDIA_BUS_FMT_YUYV8_1X16, 426 .datatype = MIPI_CSI2_DT_YUV422_8B, 427 .bpp = 16, 428 }, { 429 .code = MEDIA_BUS_FMT_UYVY8_2X8, 430 .datatype = MIPI_CSI2_DT_YUV422_8B, 431 .bpp = 16, 432 }, { 433 .code = MEDIA_BUS_FMT_YUYV10_2X10, 434 .datatype = MIPI_CSI2_DT_YUV422_8B, 435 .bpp = 20, 436 }, { 437 .code = MEDIA_BUS_FMT_Y10_1X10, 438 .datatype = MIPI_CSI2_DT_RAW10, 439 .bpp = 10, 440 }, { 441 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 442 .datatype = MIPI_CSI2_DT_RAW8, 443 .bpp = 8, 444 }, { 445 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 446 .datatype = MIPI_CSI2_DT_RAW8, 447 .bpp = 8, 448 }, { 449 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 450 .datatype = MIPI_CSI2_DT_RAW8, 451 .bpp = 8, 452 }, { 453 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 454 .datatype = MIPI_CSI2_DT_RAW8, 455 .bpp = 8, 456 }, { 457 .code = MEDIA_BUS_FMT_Y8_1X8, 458 .datatype = MIPI_CSI2_DT_RAW8, 459 .bpp = 8, 460 }, 461 }; 462 463 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 464 { 465 unsigned int i; 466 467 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 468 if (rcar_csi2_formats[i].code == code) 469 return &rcar_csi2_formats[i]; 470 471 return NULL; 472 } 473 474 enum rcar_csi2_pads { 475 RCAR_CSI2_SINK, 476 RCAR_CSI2_SOURCE_VC0, 477 RCAR_CSI2_SOURCE_VC1, 478 RCAR_CSI2_SOURCE_VC2, 479 RCAR_CSI2_SOURCE_VC3, 480 NR_OF_RCAR_CSI2_PAD, 481 }; 482 483 struct rcar_csi2_info { 484 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 485 int (*phy_post_init)(struct rcar_csi2 *priv); 486 int (*start_receiver)(struct rcar_csi2 *priv); 487 void (*enter_standby)(struct rcar_csi2 *priv); 488 const struct rcsi2_mbps_reg *hsfreqrange; 489 unsigned int csi0clkfreqrange; 490 unsigned int num_channels; 491 bool clear_ulps; 492 bool use_isp; 493 bool support_dphy; 494 bool support_cphy; 495 }; 496 497 struct rcar_csi2 { 498 struct device *dev; 499 void __iomem *base; 500 const struct rcar_csi2_info *info; 501 struct reset_control *rstc; 502 503 struct v4l2_subdev subdev; 504 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 505 506 struct v4l2_async_notifier notifier; 507 struct v4l2_subdev *remote; 508 unsigned int remote_pad; 509 510 int channel_vc[4]; 511 512 struct mutex lock; /* Protects mf and stream_count. */ 513 struct v4l2_mbus_framefmt mf; 514 int stream_count; 515 516 bool cphy; 517 unsigned short lanes; 518 unsigned char lane_swap[4]; 519 }; 520 521 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 522 { 523 return container_of(sd, struct rcar_csi2, subdev); 524 } 525 526 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 527 { 528 return container_of(n, struct rcar_csi2, notifier); 529 } 530 531 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 532 { 533 return ioread32(priv->base + reg); 534 } 535 536 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 537 { 538 iowrite32(data, priv->base + reg); 539 } 540 541 static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) 542 { 543 rcsi2_write(priv, PHYCNT_REG, 0); 544 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 545 } 546 547 static void rcsi2_enter_standby(struct rcar_csi2 *priv) 548 { 549 if (priv->info->enter_standby) 550 priv->info->enter_standby(priv); 551 552 reset_control_assert(priv->rstc); 553 usleep_range(100, 150); 554 pm_runtime_put(priv->dev); 555 } 556 557 static int rcsi2_exit_standby(struct rcar_csi2 *priv) 558 { 559 int ret; 560 561 ret = pm_runtime_resume_and_get(priv->dev); 562 if (ret < 0) 563 return ret; 564 565 reset_control_deassert(priv->rstc); 566 567 return 0; 568 } 569 570 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 571 unsigned int lanes) 572 { 573 unsigned int timeout; 574 575 /* Wait for the clock and data lanes to enter LP-11 state. */ 576 for (timeout = 0; timeout <= 20; timeout++) { 577 const u32 lane_mask = (1 << lanes) - 1; 578 579 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 580 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 581 return 0; 582 583 usleep_range(1000, 2000); 584 } 585 586 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 587 588 return -ETIMEDOUT; 589 } 590 591 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 592 { 593 const struct rcsi2_mbps_reg *hsfreq; 594 const struct rcsi2_mbps_reg *hsfreq_prev = NULL; 595 596 if (mbps < priv->info->hsfreqrange->mbps) 597 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", 598 mbps, priv->info->hsfreqrange->mbps); 599 600 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) { 601 if (hsfreq->mbps >= mbps) 602 break; 603 hsfreq_prev = hsfreq; 604 } 605 606 if (!hsfreq->mbps) { 607 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 608 return -ERANGE; 609 } 610 611 if (hsfreq_prev && 612 ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps))) 613 hsfreq = hsfreq_prev; 614 615 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg)); 616 617 return 0; 618 } 619 620 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, 621 unsigned int lanes) 622 { 623 struct v4l2_subdev *source; 624 struct v4l2_ctrl *ctrl; 625 u64 mbps; 626 627 if (!priv->remote) 628 return -ENODEV; 629 630 source = priv->remote; 631 632 /* Read the pixel rate control from remote. */ 633 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE); 634 if (!ctrl) { 635 dev_err(priv->dev, "no pixel rate control in subdev %s\n", 636 source->name); 637 return -EINVAL; 638 } 639 640 /* 641 * Calculate the phypll in mbps. 642 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes) 643 * bps = link_freq * 2 644 */ 645 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp; 646 do_div(mbps, lanes * 1000000); 647 648 return mbps; 649 } 650 651 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 652 unsigned int *lanes) 653 { 654 struct v4l2_mbus_config mbus_config = { 0 }; 655 int ret; 656 657 *lanes = priv->lanes; 658 659 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 660 priv->remote_pad, &mbus_config); 661 if (ret == -ENOIOCTLCMD) { 662 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 663 return 0; 664 } 665 666 if (ret) { 667 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 668 return ret; 669 } 670 671 switch (mbus_config.type) { 672 case V4L2_MBUS_CSI2_CPHY: 673 if (!priv->cphy) 674 return -EINVAL; 675 break; 676 case V4L2_MBUS_CSI2_DPHY: 677 if (priv->cphy) 678 return -EINVAL; 679 break; 680 default: 681 dev_err(priv->dev, "Unsupported media bus type %u\n", 682 mbus_config.type); 683 return -EINVAL; 684 } 685 686 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) { 687 dev_err(priv->dev, 688 "Unsupported mbus config: too many data lanes %u\n", 689 mbus_config.bus.mipi_csi2.num_data_lanes); 690 return -EINVAL; 691 } 692 693 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes; 694 695 return 0; 696 } 697 698 static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv) 699 { 700 const struct rcar_csi2_format *format; 701 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 702 unsigned int lanes; 703 unsigned int i; 704 int mbps, ret; 705 706 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 707 priv->mf.width, priv->mf.height, 708 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i'); 709 710 /* Code is validated in set_fmt. */ 711 format = rcsi2_code_to_fmt(priv->mf.code); 712 if (!format) 713 return -EINVAL; 714 715 /* 716 * Enable all supported CSI-2 channels with virtual channel and 717 * data type matching. 718 * 719 * NOTE: It's not possible to get individual datatype for each 720 * source virtual channel. Once this is possible in V4L2 721 * it should be used here. 722 */ 723 for (i = 0; i < priv->info->num_channels; i++) { 724 u32 vcdt_part; 725 726 if (priv->channel_vc[i] < 0) 727 continue; 728 729 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN | 730 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype); 731 732 /* Store in correct reg and offset. */ 733 if (i < 2) 734 vcdt |= vcdt_part << ((i % 2) * 16); 735 else 736 vcdt2 |= vcdt_part << ((i % 2) * 16); 737 } 738 739 if (priv->mf.field == V4L2_FIELD_ALTERNATE) { 740 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 741 | FLD_FLD_EN; 742 743 if (priv->mf.height == 240) 744 fld |= FLD_FLD_NUM(0); 745 else 746 fld |= FLD_FLD_NUM(1); 747 } 748 749 /* 750 * Get the number of active data lanes inspecting the remote mbus 751 * configuration. 752 */ 753 ret = rcsi2_get_active_lanes(priv, &lanes); 754 if (ret) 755 return ret; 756 757 phycnt = PHYCNT_ENABLECLK; 758 phycnt |= (1 << lanes) - 1; 759 760 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 761 if (mbps < 0) 762 return mbps; 763 764 /* Enable interrupts. */ 765 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 766 | INTEN_INT_ERRSOTSYNCHS); 767 768 /* Init */ 769 rcsi2_write(priv, TREF_REG, TREF_TREF); 770 rcsi2_write(priv, PHTC_REG, 0); 771 772 /* Configure */ 773 if (!priv->info->use_isp) { 774 rcsi2_write(priv, VCDT_REG, vcdt); 775 if (vcdt2) 776 rcsi2_write(priv, VCDT2_REG, vcdt2); 777 } 778 779 /* Lanes are zero indexed. */ 780 rcsi2_write(priv, LSWAP_REG, 781 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 782 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 783 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 784 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 785 786 /* Start */ 787 if (priv->info->init_phtw) { 788 ret = priv->info->init_phtw(priv, mbps); 789 if (ret) 790 return ret; 791 } 792 793 if (priv->info->hsfreqrange) { 794 ret = rcsi2_set_phypll(priv, mbps); 795 if (ret) 796 return ret; 797 } 798 799 if (priv->info->csi0clkfreqrange) 800 rcsi2_write(priv, CSI0CLKFCPR_REG, 801 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 802 803 if (priv->info->use_isp) 804 rcsi2_write(priv, PHYFRX_REG, 805 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 | 806 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0); 807 808 rcsi2_write(priv, PHYCNT_REG, phycnt); 809 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 810 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 811 rcsi2_write(priv, FLD_REG, fld); 812 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 813 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 814 815 ret = rcsi2_wait_phy_start(priv, lanes); 816 if (ret) 817 return ret; 818 819 if (priv->info->use_isp) 820 rcsi2_write(priv, PHYFRX_REG, 0); 821 822 /* Run post PHY start initialization, if needed. */ 823 if (priv->info->phy_post_init) { 824 ret = priv->info->phy_post_init(priv); 825 if (ret) 826 return ret; 827 } 828 829 /* Clear Ultra Low Power interrupt. */ 830 if (priv->info->clear_ulps) 831 rcsi2_write(priv, INTSTATE_REG, 832 INTSTATE_INT_ULPS_START | 833 INTSTATE_INT_ULPS_END); 834 return 0; 835 } 836 837 static int rcsi2_start(struct rcar_csi2 *priv) 838 { 839 int ret; 840 841 ret = rcsi2_exit_standby(priv); 842 if (ret < 0) 843 return ret; 844 845 ret = priv->info->start_receiver(priv); 846 if (ret) { 847 rcsi2_enter_standby(priv); 848 return ret; 849 } 850 851 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1); 852 if (ret) { 853 rcsi2_enter_standby(priv); 854 return ret; 855 } 856 857 return 0; 858 } 859 860 static void rcsi2_stop(struct rcar_csi2 *priv) 861 { 862 rcsi2_enter_standby(priv); 863 v4l2_subdev_call(priv->remote, video, s_stream, 0); 864 } 865 866 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable) 867 { 868 struct rcar_csi2 *priv = sd_to_csi2(sd); 869 int ret = 0; 870 871 mutex_lock(&priv->lock); 872 873 if (!priv->remote) { 874 ret = -ENODEV; 875 goto out; 876 } 877 878 if (enable && priv->stream_count == 0) { 879 ret = rcsi2_start(priv); 880 if (ret) 881 goto out; 882 } else if (!enable && priv->stream_count == 1) { 883 rcsi2_stop(priv); 884 } 885 886 priv->stream_count += enable ? 1 : -1; 887 out: 888 mutex_unlock(&priv->lock); 889 890 return ret; 891 } 892 893 static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 894 struct v4l2_subdev_state *sd_state, 895 struct v4l2_subdev_format *format) 896 { 897 struct rcar_csi2 *priv = sd_to_csi2(sd); 898 struct v4l2_mbus_framefmt *framefmt; 899 900 mutex_lock(&priv->lock); 901 902 if (!rcsi2_code_to_fmt(format->format.code)) 903 format->format.code = rcar_csi2_formats[0].code; 904 905 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 906 priv->mf = format->format; 907 } else { 908 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0); 909 *framefmt = format->format; 910 } 911 912 mutex_unlock(&priv->lock); 913 914 return 0; 915 } 916 917 static int rcsi2_get_pad_format(struct v4l2_subdev *sd, 918 struct v4l2_subdev_state *sd_state, 919 struct v4l2_subdev_format *format) 920 { 921 struct rcar_csi2 *priv = sd_to_csi2(sd); 922 923 mutex_lock(&priv->lock); 924 925 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) 926 format->format = priv->mf; 927 else 928 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0); 929 930 mutex_unlock(&priv->lock); 931 932 return 0; 933 } 934 935 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = { 936 .s_stream = rcsi2_s_stream, 937 }; 938 939 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 940 .set_fmt = rcsi2_set_pad_format, 941 .get_fmt = rcsi2_get_pad_format, 942 }; 943 944 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 945 .video = &rcar_csi2_video_ops, 946 .pad = &rcar_csi2_pad_ops, 947 }; 948 949 static irqreturn_t rcsi2_irq(int irq, void *data) 950 { 951 struct rcar_csi2 *priv = data; 952 u32 status, err_status; 953 954 status = rcsi2_read(priv, INTSTATE_REG); 955 err_status = rcsi2_read(priv, INTERRSTATE_REG); 956 957 if (!status) 958 return IRQ_HANDLED; 959 960 rcsi2_write(priv, INTSTATE_REG, status); 961 962 if (!err_status) 963 return IRQ_HANDLED; 964 965 rcsi2_write(priv, INTERRSTATE_REG, err_status); 966 967 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 968 969 return IRQ_WAKE_THREAD; 970 } 971 972 static irqreturn_t rcsi2_irq_thread(int irq, void *data) 973 { 974 struct rcar_csi2 *priv = data; 975 976 mutex_lock(&priv->lock); 977 rcsi2_stop(priv); 978 usleep_range(1000, 2000); 979 if (rcsi2_start(priv)) 980 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 981 mutex_unlock(&priv->lock); 982 983 return IRQ_HANDLED; 984 } 985 986 /* ----------------------------------------------------------------------------- 987 * Async handling and registration of subdevices and links. 988 */ 989 990 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 991 struct v4l2_subdev *subdev, 992 struct v4l2_async_subdev *asd) 993 { 994 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 995 int pad; 996 997 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, 998 MEDIA_PAD_FL_SOURCE); 999 if (pad < 0) { 1000 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 1001 return pad; 1002 } 1003 1004 priv->remote = subdev; 1005 priv->remote_pad = pad; 1006 1007 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 1008 1009 return media_create_pad_link(&subdev->entity, pad, 1010 &priv->subdev.entity, 0, 1011 MEDIA_LNK_FL_ENABLED | 1012 MEDIA_LNK_FL_IMMUTABLE); 1013 } 1014 1015 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 1016 struct v4l2_subdev *subdev, 1017 struct v4l2_async_subdev *asd) 1018 { 1019 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1020 1021 priv->remote = NULL; 1022 1023 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 1024 } 1025 1026 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 1027 .bound = rcsi2_notify_bound, 1028 .unbind = rcsi2_notify_unbind, 1029 }; 1030 1031 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 1032 struct v4l2_fwnode_endpoint *vep) 1033 { 1034 unsigned int i; 1035 1036 /* Only port 0 endpoint 0 is valid. */ 1037 if (vep->base.port || vep->base.id) 1038 return -ENOTCONN; 1039 1040 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 1041 1042 switch (vep->bus_type) { 1043 case V4L2_MBUS_CSI2_DPHY: 1044 if (!priv->info->support_dphy) { 1045 dev_err(priv->dev, "D-PHY not supported\n"); 1046 return -EINVAL; 1047 } 1048 1049 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 1050 dev_err(priv->dev, 1051 "Unsupported number of data-lanes for D-PHY: %u\n", 1052 priv->lanes); 1053 return -EINVAL; 1054 } 1055 1056 priv->cphy = false; 1057 break; 1058 case V4L2_MBUS_CSI2_CPHY: 1059 if (!priv->info->support_cphy) { 1060 dev_err(priv->dev, "C-PHY not supported\n"); 1061 return -EINVAL; 1062 } 1063 1064 if (priv->lanes != 3) { 1065 dev_err(priv->dev, 1066 "Unsupported number of data-lanes for C-PHY: %u\n", 1067 priv->lanes); 1068 return -EINVAL; 1069 } 1070 1071 priv->cphy = true; 1072 break; 1073 default: 1074 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 1075 return -EINVAL; 1076 } 1077 1078 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 1079 priv->lane_swap[i] = i < priv->lanes ? 1080 vep->bus.mipi_csi2.data_lanes[i] : i; 1081 1082 /* Check for valid lane number. */ 1083 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 1084 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 1085 return -EINVAL; 1086 } 1087 } 1088 1089 return 0; 1090 } 1091 1092 static int rcsi2_parse_dt(struct rcar_csi2 *priv) 1093 { 1094 struct v4l2_async_subdev *asd; 1095 struct fwnode_handle *fwnode; 1096 struct fwnode_handle *ep; 1097 struct v4l2_fwnode_endpoint v4l2_ep = { 1098 .bus_type = V4L2_MBUS_UNKNOWN, 1099 }; 1100 int ret; 1101 1102 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); 1103 if (!ep) { 1104 dev_err(priv->dev, "Not connected to subdevice\n"); 1105 return -EINVAL; 1106 } 1107 1108 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 1109 if (ret) { 1110 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 1111 fwnode_handle_put(ep); 1112 return -EINVAL; 1113 } 1114 1115 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 1116 if (ret) { 1117 fwnode_handle_put(ep); 1118 return ret; 1119 } 1120 1121 fwnode = fwnode_graph_get_remote_endpoint(ep); 1122 fwnode_handle_put(ep); 1123 1124 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 1125 1126 v4l2_async_nf_init(&priv->notifier); 1127 priv->notifier.ops = &rcar_csi2_notify_ops; 1128 1129 asd = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, 1130 struct v4l2_async_subdev); 1131 fwnode_handle_put(fwnode); 1132 if (IS_ERR(asd)) 1133 return PTR_ERR(asd); 1134 1135 ret = v4l2_async_subdev_nf_register(&priv->subdev, &priv->notifier); 1136 if (ret) 1137 v4l2_async_nf_cleanup(&priv->notifier); 1138 1139 return ret; 1140 } 1141 1142 /* ----------------------------------------------------------------------------- 1143 * PHTW initialization sequences. 1144 * 1145 * NOTE: Magic values are from the datasheet and lack documentation. 1146 */ 1147 1148 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code) 1149 { 1150 unsigned int timeout; 1151 1152 rcsi2_write(priv, PHTW_REG, 1153 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 1154 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 1155 1156 /* Wait for DWEN and CWEN to be cleared by hardware. */ 1157 for (timeout = 0; timeout <= 20; timeout++) { 1158 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN))) 1159 return 0; 1160 1161 usleep_range(1000, 2000); 1162 } 1163 1164 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 1165 1166 return -ETIMEDOUT; 1167 } 1168 1169 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 1170 const struct phtw_value *values) 1171 { 1172 const struct phtw_value *value; 1173 int ret; 1174 1175 for (value = values; value->data || value->code; value++) { 1176 ret = rcsi2_phtw_write(priv, value->data, value->code); 1177 if (ret) 1178 return ret; 1179 } 1180 1181 return 0; 1182 } 1183 1184 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 1185 const struct rcsi2_mbps_reg *values, u16 code) 1186 { 1187 const struct rcsi2_mbps_reg *value; 1188 const struct rcsi2_mbps_reg *prev_value = NULL; 1189 1190 for (value = values; value->mbps; value++) { 1191 if (value->mbps >= mbps) 1192 break; 1193 prev_value = value; 1194 } 1195 1196 if (prev_value && 1197 ((mbps - prev_value->mbps) <= (value->mbps - mbps))) 1198 value = prev_value; 1199 1200 if (!value->mbps) { 1201 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 1202 return -ERANGE; 1203 } 1204 1205 return rcsi2_phtw_write(priv, value->reg, code); 1206 } 1207 1208 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 1209 unsigned int mbps) 1210 { 1211 static const struct phtw_value step1[] = { 1212 { .data = 0xcc, .code = 0xe2 }, 1213 { .data = 0x01, .code = 0xe3 }, 1214 { .data = 0x11, .code = 0xe4 }, 1215 { .data = 0x01, .code = 0xe5 }, 1216 { .data = 0x10, .code = 0x04 }, 1217 { /* sentinel */ }, 1218 }; 1219 1220 static const struct phtw_value step2[] = { 1221 { .data = 0x38, .code = 0x08 }, 1222 { .data = 0x01, .code = 0x00 }, 1223 { .data = 0x4b, .code = 0xac }, 1224 { .data = 0x03, .code = 0x00 }, 1225 { .data = 0x80, .code = 0x07 }, 1226 { /* sentinel */ }, 1227 }; 1228 1229 int ret; 1230 1231 ret = rcsi2_phtw_write_array(priv, step1); 1232 if (ret) 1233 return ret; 1234 1235 if (mbps != 0 && mbps <= 250) { 1236 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 1237 if (ret) 1238 return ret; 1239 1240 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 1241 0xf1); 1242 if (ret) 1243 return ret; 1244 } 1245 1246 return rcsi2_phtw_write_array(priv, step2); 1247 } 1248 1249 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 1250 { 1251 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 1252 } 1253 1254 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 1255 { 1256 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 1257 } 1258 1259 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 1260 { 1261 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 1262 } 1263 1264 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 1265 { 1266 static const struct phtw_value step1[] = { 1267 { .data = 0xee, .code = 0x34 }, 1268 { .data = 0xee, .code = 0x44 }, 1269 { .data = 0xee, .code = 0x54 }, 1270 { .data = 0xee, .code = 0x84 }, 1271 { .data = 0xee, .code = 0x94 }, 1272 { /* sentinel */ }, 1273 }; 1274 1275 return rcsi2_phtw_write_array(priv, step1); 1276 } 1277 1278 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, 1279 unsigned int mbps) 1280 { 1281 /* In case of 1500Mbps or less */ 1282 static const struct phtw_value step1[] = { 1283 { .data = 0xcc, .code = 0xe2 }, 1284 { /* sentinel */ }, 1285 }; 1286 1287 static const struct phtw_value step2[] = { 1288 { .data = 0x01, .code = 0xe3 }, 1289 { .data = 0x11, .code = 0xe4 }, 1290 { .data = 0x01, .code = 0xe5 }, 1291 { /* sentinel */ }, 1292 }; 1293 1294 /* In case of 1500Mbps or less */ 1295 static const struct phtw_value step3[] = { 1296 { .data = 0x38, .code = 0x08 }, 1297 { /* sentinel */ }, 1298 }; 1299 1300 static const struct phtw_value step4[] = { 1301 { .data = 0x01, .code = 0x00 }, 1302 { .data = 0x4b, .code = 0xac }, 1303 { .data = 0x03, .code = 0x00 }, 1304 { .data = 0x80, .code = 0x07 }, 1305 { /* sentinel */ }, 1306 }; 1307 1308 int ret; 1309 1310 if (mbps != 0 && mbps <= 1500) 1311 ret = rcsi2_phtw_write_array(priv, step1); 1312 else 1313 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); 1314 if (ret) 1315 return ret; 1316 1317 ret = rcsi2_phtw_write_array(priv, step2); 1318 if (ret) 1319 return ret; 1320 1321 if (mbps != 0 && mbps <= 1500) { 1322 ret = rcsi2_phtw_write_array(priv, step3); 1323 if (ret) 1324 return ret; 1325 } 1326 1327 ret = rcsi2_phtw_write_array(priv, step4); 1328 if (ret) 1329 return ret; 1330 1331 return ret; 1332 } 1333 1334 /* ----------------------------------------------------------------------------- 1335 * Platform Device Driver. 1336 */ 1337 1338 static int rcsi2_link_setup(struct media_entity *entity, 1339 const struct media_pad *local, 1340 const struct media_pad *remote, u32 flags) 1341 { 1342 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1343 struct rcar_csi2 *priv = sd_to_csi2(sd); 1344 struct video_device *vdev; 1345 int channel, vc; 1346 u32 id; 1347 1348 if (!is_media_entity_v4l2_video_device(remote->entity)) { 1349 dev_err(priv->dev, "Remote is not a video device\n"); 1350 return -EINVAL; 1351 } 1352 1353 vdev = media_entity_to_video_device(remote->entity); 1354 1355 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) { 1356 dev_err(priv->dev, "No renesas,id, can't configure routing\n"); 1357 return -EINVAL; 1358 } 1359 1360 channel = id % 4; 1361 1362 if (flags & MEDIA_LNK_FL_ENABLED) { 1363 if (media_pad_remote_pad_first(local)) { 1364 dev_dbg(priv->dev, 1365 "Each VC can only be routed to one output channel\n"); 1366 return -EINVAL; 1367 } 1368 1369 vc = local->index - 1; 1370 1371 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n", 1372 vc, id, channel); 1373 } else { 1374 vc = -1; 1375 } 1376 1377 priv->channel_vc[channel] = vc; 1378 1379 return 0; 1380 } 1381 1382 static const struct media_entity_operations rcar_csi2_entity_ops = { 1383 .link_setup = rcsi2_link_setup, 1384 .link_validate = v4l2_subdev_link_validate, 1385 }; 1386 1387 static int rcsi2_probe_resources(struct rcar_csi2 *priv, 1388 struct platform_device *pdev) 1389 { 1390 int irq, ret; 1391 1392 priv->base = devm_platform_ioremap_resource(pdev, 0); 1393 if (IS_ERR(priv->base)) 1394 return PTR_ERR(priv->base); 1395 1396 irq = platform_get_irq(pdev, 0); 1397 if (irq < 0) 1398 return irq; 1399 1400 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 1401 rcsi2_irq_thread, IRQF_SHARED, 1402 KBUILD_MODNAME, priv); 1403 if (ret) 1404 return ret; 1405 1406 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 1407 1408 return PTR_ERR_OR_ZERO(priv->rstc); 1409 } 1410 1411 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 1412 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1413 .start_receiver = rcsi2_start_receiver_gen3, 1414 .enter_standby = rcsi2_enter_standby_gen3, 1415 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1416 .csi0clkfreqrange = 0x20, 1417 .num_channels = 4, 1418 .clear_ulps = true, 1419 .support_dphy = true, 1420 }; 1421 1422 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 1423 .init_phtw = rcsi2_init_phtw_h3es2, 1424 .start_receiver = rcsi2_start_receiver_gen3, 1425 .enter_standby = rcsi2_enter_standby_gen3, 1426 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1427 .csi0clkfreqrange = 0x20, 1428 .num_channels = 4, 1429 .clear_ulps = true, 1430 .support_dphy = true, 1431 }; 1432 1433 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 1434 .start_receiver = rcsi2_start_receiver_gen3, 1435 .enter_standby = rcsi2_enter_standby_gen3, 1436 .hsfreqrange = hsfreqrange_m3w, 1437 .num_channels = 4, 1438 .support_dphy = true, 1439 }; 1440 1441 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { 1442 .start_receiver = rcsi2_start_receiver_gen3, 1443 .enter_standby = rcsi2_enter_standby_gen3, 1444 .hsfreqrange = hsfreqrange_m3w, 1445 .num_channels = 4, 1446 .support_dphy = true, 1447 }; 1448 1449 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 1450 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1451 .start_receiver = rcsi2_start_receiver_gen3, 1452 .enter_standby = rcsi2_enter_standby_gen3, 1453 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1454 .csi0clkfreqrange = 0x20, 1455 .num_channels = 4, 1456 .clear_ulps = true, 1457 .support_dphy = true, 1458 }; 1459 1460 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 1461 .init_phtw = rcsi2_init_phtw_v3m_e3, 1462 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 1463 .start_receiver = rcsi2_start_receiver_gen3, 1464 .enter_standby = rcsi2_enter_standby_gen3, 1465 .num_channels = 4, 1466 .support_dphy = true, 1467 }; 1468 1469 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 1470 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1471 .start_receiver = rcsi2_start_receiver_gen3, 1472 .enter_standby = rcsi2_enter_standby_gen3, 1473 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1474 .csi0clkfreqrange = 0x20, 1475 .clear_ulps = true, 1476 .support_dphy = true, 1477 }; 1478 1479 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 1480 .init_phtw = rcsi2_init_phtw_v3m_e3, 1481 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 1482 .start_receiver = rcsi2_start_receiver_gen3, 1483 .enter_standby = rcsi2_enter_standby_gen3, 1484 .num_channels = 2, 1485 .support_dphy = true, 1486 }; 1487 1488 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { 1489 .init_phtw = rcsi2_init_phtw_v3u, 1490 .start_receiver = rcsi2_start_receiver_gen3, 1491 .enter_standby = rcsi2_enter_standby_gen3, 1492 .hsfreqrange = hsfreqrange_v3u, 1493 .csi0clkfreqrange = 0x20, 1494 .clear_ulps = true, 1495 .use_isp = true, 1496 .support_dphy = true, 1497 }; 1498 1499 static const struct of_device_id rcar_csi2_of_table[] = { 1500 { 1501 .compatible = "renesas,r8a774a1-csi2", 1502 .data = &rcar_csi2_info_r8a7796, 1503 }, 1504 { 1505 .compatible = "renesas,r8a774b1-csi2", 1506 .data = &rcar_csi2_info_r8a77965, 1507 }, 1508 { 1509 .compatible = "renesas,r8a774c0-csi2", 1510 .data = &rcar_csi2_info_r8a77990, 1511 }, 1512 { 1513 .compatible = "renesas,r8a774e1-csi2", 1514 .data = &rcar_csi2_info_r8a7795, 1515 }, 1516 { 1517 .compatible = "renesas,r8a7795-csi2", 1518 .data = &rcar_csi2_info_r8a7795, 1519 }, 1520 { 1521 .compatible = "renesas,r8a7796-csi2", 1522 .data = &rcar_csi2_info_r8a7796, 1523 }, 1524 { 1525 .compatible = "renesas,r8a77961-csi2", 1526 .data = &rcar_csi2_info_r8a77961, 1527 }, 1528 { 1529 .compatible = "renesas,r8a77965-csi2", 1530 .data = &rcar_csi2_info_r8a77965, 1531 }, 1532 { 1533 .compatible = "renesas,r8a77970-csi2", 1534 .data = &rcar_csi2_info_r8a77970, 1535 }, 1536 { 1537 .compatible = "renesas,r8a77980-csi2", 1538 .data = &rcar_csi2_info_r8a77980, 1539 }, 1540 { 1541 .compatible = "renesas,r8a77990-csi2", 1542 .data = &rcar_csi2_info_r8a77990, 1543 }, 1544 { 1545 .compatible = "renesas,r8a779a0-csi2", 1546 .data = &rcar_csi2_info_r8a779a0, 1547 }, 1548 { /* sentinel */ }, 1549 }; 1550 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 1551 1552 static const struct soc_device_attribute r8a7795[] = { 1553 { 1554 .soc_id = "r8a7795", .revision = "ES2.*", 1555 .data = &rcar_csi2_info_r8a7795es2, 1556 }, 1557 { /* sentinel */ } 1558 }; 1559 1560 static int rcsi2_probe(struct platform_device *pdev) 1561 { 1562 const struct soc_device_attribute *attr; 1563 struct rcar_csi2 *priv; 1564 unsigned int i, num_pads; 1565 int ret; 1566 1567 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1568 if (!priv) 1569 return -ENOMEM; 1570 1571 priv->info = of_device_get_match_data(&pdev->dev); 1572 1573 /* 1574 * The different ES versions of r8a7795 (H3) behave differently but 1575 * share the same compatible string. 1576 */ 1577 attr = soc_device_match(r8a7795); 1578 if (attr) 1579 priv->info = attr->data; 1580 1581 priv->dev = &pdev->dev; 1582 1583 mutex_init(&priv->lock); 1584 priv->stream_count = 0; 1585 1586 ret = rcsi2_probe_resources(priv, pdev); 1587 if (ret) { 1588 dev_err(priv->dev, "Failed to get resources\n"); 1589 goto error_mutex; 1590 } 1591 1592 platform_set_drvdata(pdev, priv); 1593 1594 ret = rcsi2_parse_dt(priv); 1595 if (ret) 1596 goto error_mutex; 1597 1598 priv->subdev.owner = THIS_MODULE; 1599 priv->subdev.dev = &pdev->dev; 1600 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 1601 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 1602 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s", 1603 KBUILD_MODNAME, dev_name(&pdev->dev)); 1604 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 1605 1606 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 1607 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 1608 1609 num_pads = priv->info->use_isp ? 2 : NR_OF_RCAR_CSI2_PAD; 1610 1611 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 1612 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 1613 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 1614 1615 ret = media_entity_pads_init(&priv->subdev.entity, num_pads, 1616 priv->pads); 1617 if (ret) 1618 goto error_async; 1619 1620 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) 1621 priv->channel_vc[i] = -1; 1622 1623 pm_runtime_enable(&pdev->dev); 1624 1625 ret = v4l2_async_register_subdev(&priv->subdev); 1626 if (ret < 0) 1627 goto error_async; 1628 1629 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 1630 1631 return 0; 1632 1633 error_async: 1634 v4l2_async_nf_unregister(&priv->notifier); 1635 v4l2_async_nf_cleanup(&priv->notifier); 1636 error_mutex: 1637 mutex_destroy(&priv->lock); 1638 1639 return ret; 1640 } 1641 1642 static void rcsi2_remove(struct platform_device *pdev) 1643 { 1644 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 1645 1646 v4l2_async_nf_unregister(&priv->notifier); 1647 v4l2_async_nf_cleanup(&priv->notifier); 1648 v4l2_async_unregister_subdev(&priv->subdev); 1649 1650 pm_runtime_disable(&pdev->dev); 1651 1652 mutex_destroy(&priv->lock); 1653 } 1654 1655 static struct platform_driver rcar_csi2_pdrv = { 1656 .remove_new = rcsi2_remove, 1657 .probe = rcsi2_probe, 1658 .driver = { 1659 .name = "rcar-csi2", 1660 .suppress_bind_attrs = true, 1661 .of_match_table = rcar_csi2_of_table, 1662 }, 1663 }; 1664 1665 module_platform_driver(rcar_csi2_pdrv); 1666 1667 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 1668 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 1669 MODULE_LICENSE("GPL"); 1670