1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Renesas R-Car MIPI CSI-2 Receiver 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_graph.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/reset.h> 17 #include <linux/sys_soc.h> 18 19 #include <media/mipi-csi2.h> 20 #include <media/v4l2-ctrls.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-fwnode.h> 23 #include <media/v4l2-mc.h> 24 #include <media/v4l2-subdev.h> 25 26 struct rcar_csi2; 27 28 /* Register offsets and bits */ 29 30 /* Control Timing Select */ 31 #define TREF_REG 0x00 32 #define TREF_TREF BIT(0) 33 34 /* Software Reset */ 35 #define SRST_REG 0x04 36 #define SRST_SRST BIT(0) 37 38 /* PHY Operation Control */ 39 #define PHYCNT_REG 0x08 40 #define PHYCNT_SHUTDOWNZ BIT(17) 41 #define PHYCNT_RSTZ BIT(16) 42 #define PHYCNT_ENABLECLK BIT(4) 43 #define PHYCNT_ENABLE_3 BIT(3) 44 #define PHYCNT_ENABLE_2 BIT(2) 45 #define PHYCNT_ENABLE_1 BIT(1) 46 #define PHYCNT_ENABLE_0 BIT(0) 47 48 /* Checksum Control */ 49 #define CHKSUM_REG 0x0c 50 #define CHKSUM_ECC_EN BIT(1) 51 #define CHKSUM_CRC_EN BIT(0) 52 53 /* 54 * Channel Data Type Select 55 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1 56 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3 57 */ 58 #define VCDT_REG 0x10 59 #define VCDT2_REG 0x14 60 #define VCDT_VCDTN_EN BIT(15) 61 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8) 62 #define VCDT_SEL_DTN_ON BIT(6) 63 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0) 64 65 /* Frame Data Type Select */ 66 #define FRDT_REG 0x18 67 68 /* Field Detection Control */ 69 #define FLD_REG 0x1c 70 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16) 71 #define FLD_DET_SEL(n) (((n) & 0x3) << 4) 72 #define FLD_FLD_EN4 BIT(3) 73 #define FLD_FLD_EN3 BIT(2) 74 #define FLD_FLD_EN2 BIT(1) 75 #define FLD_FLD_EN BIT(0) 76 77 /* Automatic Standby Control */ 78 #define ASTBY_REG 0x20 79 80 /* Long Data Type Setting 0 */ 81 #define LNGDT0_REG 0x28 82 83 /* Long Data Type Setting 1 */ 84 #define LNGDT1_REG 0x2c 85 86 /* Interrupt Enable */ 87 #define INTEN_REG 0x30 88 #define INTEN_INT_AFIFO_OF BIT(27) 89 #define INTEN_INT_ERRSOTHS BIT(4) 90 #define INTEN_INT_ERRSOTSYNCHS BIT(3) 91 92 /* Interrupt Source Mask */ 93 #define INTCLOSE_REG 0x34 94 95 /* Interrupt Status Monitor */ 96 #define INTSTATE_REG 0x38 97 #define INTSTATE_INT_ULPS_START BIT(7) 98 #define INTSTATE_INT_ULPS_END BIT(6) 99 100 /* Interrupt Error Status Monitor */ 101 #define INTERRSTATE_REG 0x3c 102 103 /* Short Packet Data */ 104 #define SHPDAT_REG 0x40 105 106 /* Short Packet Count */ 107 #define SHPCNT_REG 0x44 108 109 /* LINK Operation Control */ 110 #define LINKCNT_REG 0x48 111 #define LINKCNT_MONITOR_EN BIT(31) 112 #define LINKCNT_REG_MONI_PACT_EN BIT(25) 113 #define LINKCNT_ICLK_NONSTOP BIT(24) 114 115 /* Lane Swap */ 116 #define LSWAP_REG 0x4c 117 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6) 118 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4) 119 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2) 120 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0) 121 122 /* PHY Test Interface Write Register */ 123 #define PHTW_REG 0x50 124 #define PHTW_DWEN BIT(24) 125 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16) 126 #define PHTW_CWEN BIT(8) 127 #define PHTW_TESTDIN_CODE(n) ((n & 0xff)) 128 129 #define PHYFRX_REG 0x64 130 #define PHYFRX_FORCERX_MODE_3 BIT(3) 131 #define PHYFRX_FORCERX_MODE_2 BIT(2) 132 #define PHYFRX_FORCERX_MODE_1 BIT(1) 133 #define PHYFRX_FORCERX_MODE_0 BIT(0) 134 135 struct phtw_value { 136 u16 data; 137 u16 code; 138 }; 139 140 struct rcsi2_mbps_reg { 141 u16 mbps; 142 u16 reg; 143 }; 144 145 static const struct rcsi2_mbps_reg phtw_mbps_v3u[] = { 146 { .mbps = 1500, .reg = 0xcc }, 147 { .mbps = 1550, .reg = 0x1d }, 148 { .mbps = 1600, .reg = 0x27 }, 149 { .mbps = 1650, .reg = 0x30 }, 150 { .mbps = 1700, .reg = 0x39 }, 151 { .mbps = 1750, .reg = 0x42 }, 152 { .mbps = 1800, .reg = 0x4b }, 153 { .mbps = 1850, .reg = 0x55 }, 154 { .mbps = 1900, .reg = 0x5e }, 155 { .mbps = 1950, .reg = 0x67 }, 156 { .mbps = 2000, .reg = 0x71 }, 157 { .mbps = 2050, .reg = 0x79 }, 158 { .mbps = 2100, .reg = 0x83 }, 159 { .mbps = 2150, .reg = 0x8c }, 160 { .mbps = 2200, .reg = 0x95 }, 161 { .mbps = 2250, .reg = 0x9e }, 162 { .mbps = 2300, .reg = 0xa7 }, 163 { .mbps = 2350, .reg = 0xb0 }, 164 { .mbps = 2400, .reg = 0xba }, 165 { .mbps = 2450, .reg = 0xc3 }, 166 { .mbps = 2500, .reg = 0xcc }, 167 { /* sentinel */ }, 168 }; 169 170 static const struct rcsi2_mbps_reg phtw_mbps_h3_v3h_m3n[] = { 171 { .mbps = 80, .reg = 0x86 }, 172 { .mbps = 90, .reg = 0x86 }, 173 { .mbps = 100, .reg = 0x87 }, 174 { .mbps = 110, .reg = 0x87 }, 175 { .mbps = 120, .reg = 0x88 }, 176 { .mbps = 130, .reg = 0x88 }, 177 { .mbps = 140, .reg = 0x89 }, 178 { .mbps = 150, .reg = 0x89 }, 179 { .mbps = 160, .reg = 0x8a }, 180 { .mbps = 170, .reg = 0x8a }, 181 { .mbps = 180, .reg = 0x8b }, 182 { .mbps = 190, .reg = 0x8b }, 183 { .mbps = 205, .reg = 0x8c }, 184 { .mbps = 220, .reg = 0x8d }, 185 { .mbps = 235, .reg = 0x8e }, 186 { .mbps = 250, .reg = 0x8e }, 187 { /* sentinel */ }, 188 }; 189 190 static const struct rcsi2_mbps_reg phtw_mbps_v3m_e3[] = { 191 { .mbps = 80, .reg = 0x00 }, 192 { .mbps = 90, .reg = 0x20 }, 193 { .mbps = 100, .reg = 0x40 }, 194 { .mbps = 110, .reg = 0x02 }, 195 { .mbps = 130, .reg = 0x22 }, 196 { .mbps = 140, .reg = 0x42 }, 197 { .mbps = 150, .reg = 0x04 }, 198 { .mbps = 170, .reg = 0x24 }, 199 { .mbps = 180, .reg = 0x44 }, 200 { .mbps = 200, .reg = 0x06 }, 201 { .mbps = 220, .reg = 0x26 }, 202 { .mbps = 240, .reg = 0x46 }, 203 { .mbps = 250, .reg = 0x08 }, 204 { .mbps = 270, .reg = 0x28 }, 205 { .mbps = 300, .reg = 0x0a }, 206 { .mbps = 330, .reg = 0x2a }, 207 { .mbps = 360, .reg = 0x4a }, 208 { .mbps = 400, .reg = 0x0c }, 209 { .mbps = 450, .reg = 0x2c }, 210 { .mbps = 500, .reg = 0x0e }, 211 { .mbps = 550, .reg = 0x2e }, 212 { .mbps = 600, .reg = 0x10 }, 213 { .mbps = 650, .reg = 0x30 }, 214 { .mbps = 700, .reg = 0x12 }, 215 { .mbps = 750, .reg = 0x32 }, 216 { .mbps = 800, .reg = 0x52 }, 217 { .mbps = 850, .reg = 0x72 }, 218 { .mbps = 900, .reg = 0x14 }, 219 { .mbps = 950, .reg = 0x34 }, 220 { .mbps = 1000, .reg = 0x54 }, 221 { .mbps = 1050, .reg = 0x74 }, 222 { .mbps = 1125, .reg = 0x16 }, 223 { /* sentinel */ }, 224 }; 225 226 /* PHY Test Interface Clear */ 227 #define PHTC_REG 0x58 228 #define PHTC_TESTCLR BIT(0) 229 230 /* PHY Frequency Control */ 231 #define PHYPLL_REG 0x68 232 #define PHYPLL_HSFREQRANGE(n) ((n) << 16) 233 234 static const struct rcsi2_mbps_reg hsfreqrange_v3u[] = { 235 { .mbps = 80, .reg = 0x00 }, 236 { .mbps = 90, .reg = 0x10 }, 237 { .mbps = 100, .reg = 0x20 }, 238 { .mbps = 110, .reg = 0x30 }, 239 { .mbps = 120, .reg = 0x01 }, 240 { .mbps = 130, .reg = 0x11 }, 241 { .mbps = 140, .reg = 0x21 }, 242 { .mbps = 150, .reg = 0x31 }, 243 { .mbps = 160, .reg = 0x02 }, 244 { .mbps = 170, .reg = 0x12 }, 245 { .mbps = 180, .reg = 0x22 }, 246 { .mbps = 190, .reg = 0x32 }, 247 { .mbps = 205, .reg = 0x03 }, 248 { .mbps = 220, .reg = 0x13 }, 249 { .mbps = 235, .reg = 0x23 }, 250 { .mbps = 250, .reg = 0x33 }, 251 { .mbps = 275, .reg = 0x04 }, 252 { .mbps = 300, .reg = 0x14 }, 253 { .mbps = 325, .reg = 0x25 }, 254 { .mbps = 350, .reg = 0x35 }, 255 { .mbps = 400, .reg = 0x05 }, 256 { .mbps = 450, .reg = 0x16 }, 257 { .mbps = 500, .reg = 0x26 }, 258 { .mbps = 550, .reg = 0x37 }, 259 { .mbps = 600, .reg = 0x07 }, 260 { .mbps = 650, .reg = 0x18 }, 261 { .mbps = 700, .reg = 0x28 }, 262 { .mbps = 750, .reg = 0x39 }, 263 { .mbps = 800, .reg = 0x09 }, 264 { .mbps = 850, .reg = 0x19 }, 265 { .mbps = 900, .reg = 0x29 }, 266 { .mbps = 950, .reg = 0x3a }, 267 { .mbps = 1000, .reg = 0x0a }, 268 { .mbps = 1050, .reg = 0x1a }, 269 { .mbps = 1100, .reg = 0x2a }, 270 { .mbps = 1150, .reg = 0x3b }, 271 { .mbps = 1200, .reg = 0x0b }, 272 { .mbps = 1250, .reg = 0x1b }, 273 { .mbps = 1300, .reg = 0x2b }, 274 { .mbps = 1350, .reg = 0x3c }, 275 { .mbps = 1400, .reg = 0x0c }, 276 { .mbps = 1450, .reg = 0x1c }, 277 { .mbps = 1500, .reg = 0x2c }, 278 { .mbps = 1550, .reg = 0x3d }, 279 { .mbps = 1600, .reg = 0x0d }, 280 { .mbps = 1650, .reg = 0x1d }, 281 { .mbps = 1700, .reg = 0x2e }, 282 { .mbps = 1750, .reg = 0x3e }, 283 { .mbps = 1800, .reg = 0x0e }, 284 { .mbps = 1850, .reg = 0x1e }, 285 { .mbps = 1900, .reg = 0x2f }, 286 { .mbps = 1950, .reg = 0x3f }, 287 { .mbps = 2000, .reg = 0x0f }, 288 { .mbps = 2050, .reg = 0x40 }, 289 { .mbps = 2100, .reg = 0x41 }, 290 { .mbps = 2150, .reg = 0x42 }, 291 { .mbps = 2200, .reg = 0x43 }, 292 { .mbps = 2300, .reg = 0x45 }, 293 { .mbps = 2350, .reg = 0x46 }, 294 { .mbps = 2400, .reg = 0x47 }, 295 { .mbps = 2450, .reg = 0x48 }, 296 { .mbps = 2500, .reg = 0x49 }, 297 { /* sentinel */ }, 298 }; 299 300 static const struct rcsi2_mbps_reg hsfreqrange_h3_v3h_m3n[] = { 301 { .mbps = 80, .reg = 0x00 }, 302 { .mbps = 90, .reg = 0x10 }, 303 { .mbps = 100, .reg = 0x20 }, 304 { .mbps = 110, .reg = 0x30 }, 305 { .mbps = 120, .reg = 0x01 }, 306 { .mbps = 130, .reg = 0x11 }, 307 { .mbps = 140, .reg = 0x21 }, 308 { .mbps = 150, .reg = 0x31 }, 309 { .mbps = 160, .reg = 0x02 }, 310 { .mbps = 170, .reg = 0x12 }, 311 { .mbps = 180, .reg = 0x22 }, 312 { .mbps = 190, .reg = 0x32 }, 313 { .mbps = 205, .reg = 0x03 }, 314 { .mbps = 220, .reg = 0x13 }, 315 { .mbps = 235, .reg = 0x23 }, 316 { .mbps = 250, .reg = 0x33 }, 317 { .mbps = 275, .reg = 0x04 }, 318 { .mbps = 300, .reg = 0x14 }, 319 { .mbps = 325, .reg = 0x25 }, 320 { .mbps = 350, .reg = 0x35 }, 321 { .mbps = 400, .reg = 0x05 }, 322 { .mbps = 450, .reg = 0x16 }, 323 { .mbps = 500, .reg = 0x26 }, 324 { .mbps = 550, .reg = 0x37 }, 325 { .mbps = 600, .reg = 0x07 }, 326 { .mbps = 650, .reg = 0x18 }, 327 { .mbps = 700, .reg = 0x28 }, 328 { .mbps = 750, .reg = 0x39 }, 329 { .mbps = 800, .reg = 0x09 }, 330 { .mbps = 850, .reg = 0x19 }, 331 { .mbps = 900, .reg = 0x29 }, 332 { .mbps = 950, .reg = 0x3a }, 333 { .mbps = 1000, .reg = 0x0a }, 334 { .mbps = 1050, .reg = 0x1a }, 335 { .mbps = 1100, .reg = 0x2a }, 336 { .mbps = 1150, .reg = 0x3b }, 337 { .mbps = 1200, .reg = 0x0b }, 338 { .mbps = 1250, .reg = 0x1b }, 339 { .mbps = 1300, .reg = 0x2b }, 340 { .mbps = 1350, .reg = 0x3c }, 341 { .mbps = 1400, .reg = 0x0c }, 342 { .mbps = 1450, .reg = 0x1c }, 343 { .mbps = 1500, .reg = 0x2c }, 344 { /* sentinel */ }, 345 }; 346 347 static const struct rcsi2_mbps_reg hsfreqrange_m3w[] = { 348 { .mbps = 80, .reg = 0x00 }, 349 { .mbps = 90, .reg = 0x10 }, 350 { .mbps = 100, .reg = 0x20 }, 351 { .mbps = 110, .reg = 0x30 }, 352 { .mbps = 120, .reg = 0x01 }, 353 { .mbps = 130, .reg = 0x11 }, 354 { .mbps = 140, .reg = 0x21 }, 355 { .mbps = 150, .reg = 0x31 }, 356 { .mbps = 160, .reg = 0x02 }, 357 { .mbps = 170, .reg = 0x12 }, 358 { .mbps = 180, .reg = 0x22 }, 359 { .mbps = 190, .reg = 0x32 }, 360 { .mbps = 205, .reg = 0x03 }, 361 { .mbps = 220, .reg = 0x13 }, 362 { .mbps = 235, .reg = 0x23 }, 363 { .mbps = 250, .reg = 0x33 }, 364 { .mbps = 275, .reg = 0x04 }, 365 { .mbps = 300, .reg = 0x14 }, 366 { .mbps = 325, .reg = 0x05 }, 367 { .mbps = 350, .reg = 0x15 }, 368 { .mbps = 400, .reg = 0x25 }, 369 { .mbps = 450, .reg = 0x06 }, 370 { .mbps = 500, .reg = 0x16 }, 371 { .mbps = 550, .reg = 0x07 }, 372 { .mbps = 600, .reg = 0x17 }, 373 { .mbps = 650, .reg = 0x08 }, 374 { .mbps = 700, .reg = 0x18 }, 375 { .mbps = 750, .reg = 0x09 }, 376 { .mbps = 800, .reg = 0x19 }, 377 { .mbps = 850, .reg = 0x29 }, 378 { .mbps = 900, .reg = 0x39 }, 379 { .mbps = 950, .reg = 0x0a }, 380 { .mbps = 1000, .reg = 0x1a }, 381 { .mbps = 1050, .reg = 0x2a }, 382 { .mbps = 1100, .reg = 0x3a }, 383 { .mbps = 1150, .reg = 0x0b }, 384 { .mbps = 1200, .reg = 0x1b }, 385 { .mbps = 1250, .reg = 0x2b }, 386 { .mbps = 1300, .reg = 0x3b }, 387 { .mbps = 1350, .reg = 0x0c }, 388 { .mbps = 1400, .reg = 0x1c }, 389 { .mbps = 1450, .reg = 0x2c }, 390 { .mbps = 1500, .reg = 0x3c }, 391 { /* sentinel */ }, 392 }; 393 394 /* PHY ESC Error Monitor */ 395 #define PHEERM_REG 0x74 396 397 /* PHY Clock Lane Monitor */ 398 #define PHCLM_REG 0x78 399 #define PHCLM_STOPSTATECKL BIT(0) 400 401 /* PHY Data Lane Monitor */ 402 #define PHDLM_REG 0x7c 403 404 /* CSI0CLK Frequency Configuration Preset Register */ 405 #define CSI0CLKFCPR_REG 0x260 406 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16) 407 408 struct rcar_csi2_format { 409 u32 code; 410 unsigned int datatype; 411 unsigned int bpp; 412 }; 413 414 static const struct rcar_csi2_format rcar_csi2_formats[] = { 415 { 416 .code = MEDIA_BUS_FMT_RGB888_1X24, 417 .datatype = MIPI_CSI2_DT_RGB888, 418 .bpp = 24, 419 }, { 420 .code = MEDIA_BUS_FMT_UYVY8_1X16, 421 .datatype = MIPI_CSI2_DT_YUV422_8B, 422 .bpp = 16, 423 }, { 424 .code = MEDIA_BUS_FMT_YUYV8_1X16, 425 .datatype = MIPI_CSI2_DT_YUV422_8B, 426 .bpp = 16, 427 }, { 428 .code = MEDIA_BUS_FMT_UYVY8_2X8, 429 .datatype = MIPI_CSI2_DT_YUV422_8B, 430 .bpp = 16, 431 }, { 432 .code = MEDIA_BUS_FMT_YUYV10_2X10, 433 .datatype = MIPI_CSI2_DT_YUV422_8B, 434 .bpp = 20, 435 }, { 436 .code = MEDIA_BUS_FMT_Y10_1X10, 437 .datatype = MIPI_CSI2_DT_RAW10, 438 .bpp = 10, 439 }, { 440 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 441 .datatype = MIPI_CSI2_DT_RAW8, 442 .bpp = 8, 443 }, { 444 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 445 .datatype = MIPI_CSI2_DT_RAW8, 446 .bpp = 8, 447 }, { 448 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 449 .datatype = MIPI_CSI2_DT_RAW8, 450 .bpp = 8, 451 }, { 452 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 453 .datatype = MIPI_CSI2_DT_RAW8, 454 .bpp = 8, 455 }, { 456 .code = MEDIA_BUS_FMT_Y8_1X8, 457 .datatype = MIPI_CSI2_DT_RAW8, 458 .bpp = 8, 459 }, 460 }; 461 462 static const struct rcar_csi2_format *rcsi2_code_to_fmt(unsigned int code) 463 { 464 unsigned int i; 465 466 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) 467 if (rcar_csi2_formats[i].code == code) 468 return &rcar_csi2_formats[i]; 469 470 return NULL; 471 } 472 473 enum rcar_csi2_pads { 474 RCAR_CSI2_SINK, 475 RCAR_CSI2_SOURCE_VC0, 476 RCAR_CSI2_SOURCE_VC1, 477 RCAR_CSI2_SOURCE_VC2, 478 RCAR_CSI2_SOURCE_VC3, 479 NR_OF_RCAR_CSI2_PAD, 480 }; 481 482 struct rcar_csi2_info { 483 int (*init_phtw)(struct rcar_csi2 *priv, unsigned int mbps); 484 int (*phy_post_init)(struct rcar_csi2 *priv); 485 int (*start_receiver)(struct rcar_csi2 *priv); 486 void (*enter_standby)(struct rcar_csi2 *priv); 487 const struct rcsi2_mbps_reg *hsfreqrange; 488 unsigned int csi0clkfreqrange; 489 unsigned int num_channels; 490 bool clear_ulps; 491 bool use_isp; 492 bool support_dphy; 493 bool support_cphy; 494 }; 495 496 struct rcar_csi2 { 497 struct device *dev; 498 void __iomem *base; 499 const struct rcar_csi2_info *info; 500 struct reset_control *rstc; 501 502 struct v4l2_subdev subdev; 503 struct media_pad pads[NR_OF_RCAR_CSI2_PAD]; 504 505 struct v4l2_async_notifier notifier; 506 struct v4l2_subdev *remote; 507 unsigned int remote_pad; 508 509 int channel_vc[4]; 510 511 struct mutex lock; /* Protects mf and stream_count. */ 512 struct v4l2_mbus_framefmt mf; 513 int stream_count; 514 515 bool cphy; 516 unsigned short lanes; 517 unsigned char lane_swap[4]; 518 }; 519 520 static inline struct rcar_csi2 *sd_to_csi2(struct v4l2_subdev *sd) 521 { 522 return container_of(sd, struct rcar_csi2, subdev); 523 } 524 525 static inline struct rcar_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) 526 { 527 return container_of(n, struct rcar_csi2, notifier); 528 } 529 530 static u32 rcsi2_read(struct rcar_csi2 *priv, unsigned int reg) 531 { 532 return ioread32(priv->base + reg); 533 } 534 535 static void rcsi2_write(struct rcar_csi2 *priv, unsigned int reg, u32 data) 536 { 537 iowrite32(data, priv->base + reg); 538 } 539 540 static void rcsi2_enter_standby_gen3(struct rcar_csi2 *priv) 541 { 542 rcsi2_write(priv, PHYCNT_REG, 0); 543 rcsi2_write(priv, PHTC_REG, PHTC_TESTCLR); 544 } 545 546 static void rcsi2_enter_standby(struct rcar_csi2 *priv) 547 { 548 if (priv->info->enter_standby) 549 priv->info->enter_standby(priv); 550 551 reset_control_assert(priv->rstc); 552 usleep_range(100, 150); 553 pm_runtime_put(priv->dev); 554 } 555 556 static int rcsi2_exit_standby(struct rcar_csi2 *priv) 557 { 558 int ret; 559 560 ret = pm_runtime_resume_and_get(priv->dev); 561 if (ret < 0) 562 return ret; 563 564 reset_control_deassert(priv->rstc); 565 566 return 0; 567 } 568 569 static int rcsi2_wait_phy_start(struct rcar_csi2 *priv, 570 unsigned int lanes) 571 { 572 unsigned int timeout; 573 574 /* Wait for the clock and data lanes to enter LP-11 state. */ 575 for (timeout = 0; timeout <= 20; timeout++) { 576 const u32 lane_mask = (1 << lanes) - 1; 577 578 if ((rcsi2_read(priv, PHCLM_REG) & PHCLM_STOPSTATECKL) && 579 (rcsi2_read(priv, PHDLM_REG) & lane_mask) == lane_mask) 580 return 0; 581 582 usleep_range(1000, 2000); 583 } 584 585 dev_err(priv->dev, "Timeout waiting for LP-11 state\n"); 586 587 return -ETIMEDOUT; 588 } 589 590 static int rcsi2_set_phypll(struct rcar_csi2 *priv, unsigned int mbps) 591 { 592 const struct rcsi2_mbps_reg *hsfreq; 593 const struct rcsi2_mbps_reg *hsfreq_prev = NULL; 594 595 if (mbps < priv->info->hsfreqrange->mbps) 596 dev_warn(priv->dev, "%u Mbps less than min PHY speed %u Mbps", 597 mbps, priv->info->hsfreqrange->mbps); 598 599 for (hsfreq = priv->info->hsfreqrange; hsfreq->mbps != 0; hsfreq++) { 600 if (hsfreq->mbps >= mbps) 601 break; 602 hsfreq_prev = hsfreq; 603 } 604 605 if (!hsfreq->mbps) { 606 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 607 return -ERANGE; 608 } 609 610 if (hsfreq_prev && 611 ((mbps - hsfreq_prev->mbps) <= (hsfreq->mbps - mbps))) 612 hsfreq = hsfreq_prev; 613 614 rcsi2_write(priv, PHYPLL_REG, PHYPLL_HSFREQRANGE(hsfreq->reg)); 615 616 return 0; 617 } 618 619 static int rcsi2_calc_mbps(struct rcar_csi2 *priv, unsigned int bpp, 620 unsigned int lanes) 621 { 622 struct v4l2_subdev *source; 623 struct v4l2_ctrl *ctrl; 624 u64 mbps; 625 626 if (!priv->remote) 627 return -ENODEV; 628 629 source = priv->remote; 630 631 /* Read the pixel rate control from remote. */ 632 ctrl = v4l2_ctrl_find(source->ctrl_handler, V4L2_CID_PIXEL_RATE); 633 if (!ctrl) { 634 dev_err(priv->dev, "no pixel rate control in subdev %s\n", 635 source->name); 636 return -EINVAL; 637 } 638 639 /* 640 * Calculate the phypll in mbps. 641 * link_freq = (pixel_rate * bits_per_sample) / (2 * nr_of_lanes) 642 * bps = link_freq * 2 643 */ 644 mbps = v4l2_ctrl_g_ctrl_int64(ctrl) * bpp; 645 do_div(mbps, lanes * 1000000); 646 647 return mbps; 648 } 649 650 static int rcsi2_get_active_lanes(struct rcar_csi2 *priv, 651 unsigned int *lanes) 652 { 653 struct v4l2_mbus_config mbus_config = { 0 }; 654 int ret; 655 656 *lanes = priv->lanes; 657 658 ret = v4l2_subdev_call(priv->remote, pad, get_mbus_config, 659 priv->remote_pad, &mbus_config); 660 if (ret == -ENOIOCTLCMD) { 661 dev_dbg(priv->dev, "No remote mbus configuration available\n"); 662 return 0; 663 } 664 665 if (ret) { 666 dev_err(priv->dev, "Failed to get remote mbus configuration\n"); 667 return ret; 668 } 669 670 switch (mbus_config.type) { 671 case V4L2_MBUS_CSI2_CPHY: 672 if (!priv->cphy) 673 return -EINVAL; 674 break; 675 case V4L2_MBUS_CSI2_DPHY: 676 if (priv->cphy) 677 return -EINVAL; 678 break; 679 default: 680 dev_err(priv->dev, "Unsupported media bus type %u\n", 681 mbus_config.type); 682 return -EINVAL; 683 } 684 685 if (mbus_config.bus.mipi_csi2.num_data_lanes > priv->lanes) { 686 dev_err(priv->dev, 687 "Unsupported mbus config: too many data lanes %u\n", 688 mbus_config.bus.mipi_csi2.num_data_lanes); 689 return -EINVAL; 690 } 691 692 *lanes = mbus_config.bus.mipi_csi2.num_data_lanes; 693 694 return 0; 695 } 696 697 static int rcsi2_start_receiver_gen3(struct rcar_csi2 *priv) 698 { 699 const struct rcar_csi2_format *format; 700 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; 701 unsigned int lanes; 702 unsigned int i; 703 int mbps, ret; 704 705 dev_dbg(priv->dev, "Input size (%ux%u%c)\n", 706 priv->mf.width, priv->mf.height, 707 priv->mf.field == V4L2_FIELD_NONE ? 'p' : 'i'); 708 709 /* Code is validated in set_fmt. */ 710 format = rcsi2_code_to_fmt(priv->mf.code); 711 if (!format) 712 return -EINVAL; 713 714 /* 715 * Enable all supported CSI-2 channels with virtual channel and 716 * data type matching. 717 * 718 * NOTE: It's not possible to get individual datatype for each 719 * source virtual channel. Once this is possible in V4L2 720 * it should be used here. 721 */ 722 for (i = 0; i < priv->info->num_channels; i++) { 723 u32 vcdt_part; 724 725 if (priv->channel_vc[i] < 0) 726 continue; 727 728 vcdt_part = VCDT_SEL_VC(priv->channel_vc[i]) | VCDT_VCDTN_EN | 729 VCDT_SEL_DTN_ON | VCDT_SEL_DT(format->datatype); 730 731 /* Store in correct reg and offset. */ 732 if (i < 2) 733 vcdt |= vcdt_part << ((i % 2) * 16); 734 else 735 vcdt2 |= vcdt_part << ((i % 2) * 16); 736 } 737 738 if (priv->mf.field == V4L2_FIELD_ALTERNATE) { 739 fld = FLD_DET_SEL(1) | FLD_FLD_EN4 | FLD_FLD_EN3 | FLD_FLD_EN2 740 | FLD_FLD_EN; 741 742 if (priv->mf.height == 240) 743 fld |= FLD_FLD_NUM(0); 744 else 745 fld |= FLD_FLD_NUM(1); 746 } 747 748 /* 749 * Get the number of active data lanes inspecting the remote mbus 750 * configuration. 751 */ 752 ret = rcsi2_get_active_lanes(priv, &lanes); 753 if (ret) 754 return ret; 755 756 phycnt = PHYCNT_ENABLECLK; 757 phycnt |= (1 << lanes) - 1; 758 759 mbps = rcsi2_calc_mbps(priv, format->bpp, lanes); 760 if (mbps < 0) 761 return mbps; 762 763 /* Enable interrupts. */ 764 rcsi2_write(priv, INTEN_REG, INTEN_INT_AFIFO_OF | INTEN_INT_ERRSOTHS 765 | INTEN_INT_ERRSOTSYNCHS); 766 767 /* Init */ 768 rcsi2_write(priv, TREF_REG, TREF_TREF); 769 rcsi2_write(priv, PHTC_REG, 0); 770 771 /* Configure */ 772 if (!priv->info->use_isp) { 773 rcsi2_write(priv, VCDT_REG, vcdt); 774 if (vcdt2) 775 rcsi2_write(priv, VCDT2_REG, vcdt2); 776 } 777 778 /* Lanes are zero indexed. */ 779 rcsi2_write(priv, LSWAP_REG, 780 LSWAP_L0SEL(priv->lane_swap[0] - 1) | 781 LSWAP_L1SEL(priv->lane_swap[1] - 1) | 782 LSWAP_L2SEL(priv->lane_swap[2] - 1) | 783 LSWAP_L3SEL(priv->lane_swap[3] - 1)); 784 785 /* Start */ 786 if (priv->info->init_phtw) { 787 ret = priv->info->init_phtw(priv, mbps); 788 if (ret) 789 return ret; 790 } 791 792 if (priv->info->hsfreqrange) { 793 ret = rcsi2_set_phypll(priv, mbps); 794 if (ret) 795 return ret; 796 } 797 798 if (priv->info->csi0clkfreqrange) 799 rcsi2_write(priv, CSI0CLKFCPR_REG, 800 CSI0CLKFREQRANGE(priv->info->csi0clkfreqrange)); 801 802 if (priv->info->use_isp) 803 rcsi2_write(priv, PHYFRX_REG, 804 PHYFRX_FORCERX_MODE_3 | PHYFRX_FORCERX_MODE_2 | 805 PHYFRX_FORCERX_MODE_1 | PHYFRX_FORCERX_MODE_0); 806 807 rcsi2_write(priv, PHYCNT_REG, phycnt); 808 rcsi2_write(priv, LINKCNT_REG, LINKCNT_MONITOR_EN | 809 LINKCNT_REG_MONI_PACT_EN | LINKCNT_ICLK_NONSTOP); 810 rcsi2_write(priv, FLD_REG, fld); 811 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ); 812 rcsi2_write(priv, PHYCNT_REG, phycnt | PHYCNT_SHUTDOWNZ | PHYCNT_RSTZ); 813 814 ret = rcsi2_wait_phy_start(priv, lanes); 815 if (ret) 816 return ret; 817 818 if (priv->info->use_isp) 819 rcsi2_write(priv, PHYFRX_REG, 0); 820 821 /* Run post PHY start initialization, if needed. */ 822 if (priv->info->phy_post_init) { 823 ret = priv->info->phy_post_init(priv); 824 if (ret) 825 return ret; 826 } 827 828 /* Clear Ultra Low Power interrupt. */ 829 if (priv->info->clear_ulps) 830 rcsi2_write(priv, INTSTATE_REG, 831 INTSTATE_INT_ULPS_START | 832 INTSTATE_INT_ULPS_END); 833 return 0; 834 } 835 836 static int rcsi2_start(struct rcar_csi2 *priv) 837 { 838 int ret; 839 840 ret = rcsi2_exit_standby(priv); 841 if (ret < 0) 842 return ret; 843 844 ret = priv->info->start_receiver(priv); 845 if (ret) { 846 rcsi2_enter_standby(priv); 847 return ret; 848 } 849 850 ret = v4l2_subdev_call(priv->remote, video, s_stream, 1); 851 if (ret) { 852 rcsi2_enter_standby(priv); 853 return ret; 854 } 855 856 return 0; 857 } 858 859 static void rcsi2_stop(struct rcar_csi2 *priv) 860 { 861 rcsi2_enter_standby(priv); 862 v4l2_subdev_call(priv->remote, video, s_stream, 0); 863 } 864 865 static int rcsi2_s_stream(struct v4l2_subdev *sd, int enable) 866 { 867 struct rcar_csi2 *priv = sd_to_csi2(sd); 868 int ret = 0; 869 870 mutex_lock(&priv->lock); 871 872 if (!priv->remote) { 873 ret = -ENODEV; 874 goto out; 875 } 876 877 if (enable && priv->stream_count == 0) { 878 ret = rcsi2_start(priv); 879 if (ret) 880 goto out; 881 } else if (!enable && priv->stream_count == 1) { 882 rcsi2_stop(priv); 883 } 884 885 priv->stream_count += enable ? 1 : -1; 886 out: 887 mutex_unlock(&priv->lock); 888 889 return ret; 890 } 891 892 static int rcsi2_set_pad_format(struct v4l2_subdev *sd, 893 struct v4l2_subdev_state *sd_state, 894 struct v4l2_subdev_format *format) 895 { 896 struct rcar_csi2 *priv = sd_to_csi2(sd); 897 struct v4l2_mbus_framefmt *framefmt; 898 899 mutex_lock(&priv->lock); 900 901 if (!rcsi2_code_to_fmt(format->format.code)) 902 format->format.code = rcar_csi2_formats[0].code; 903 904 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) { 905 priv->mf = format->format; 906 } else { 907 framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0); 908 *framefmt = format->format; 909 } 910 911 mutex_unlock(&priv->lock); 912 913 return 0; 914 } 915 916 static int rcsi2_get_pad_format(struct v4l2_subdev *sd, 917 struct v4l2_subdev_state *sd_state, 918 struct v4l2_subdev_format *format) 919 { 920 struct rcar_csi2 *priv = sd_to_csi2(sd); 921 922 mutex_lock(&priv->lock); 923 924 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) 925 format->format = priv->mf; 926 else 927 format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0); 928 929 mutex_unlock(&priv->lock); 930 931 return 0; 932 } 933 934 static const struct v4l2_subdev_video_ops rcar_csi2_video_ops = { 935 .s_stream = rcsi2_s_stream, 936 }; 937 938 static const struct v4l2_subdev_pad_ops rcar_csi2_pad_ops = { 939 .set_fmt = rcsi2_set_pad_format, 940 .get_fmt = rcsi2_get_pad_format, 941 }; 942 943 static const struct v4l2_subdev_ops rcar_csi2_subdev_ops = { 944 .video = &rcar_csi2_video_ops, 945 .pad = &rcar_csi2_pad_ops, 946 }; 947 948 static irqreturn_t rcsi2_irq(int irq, void *data) 949 { 950 struct rcar_csi2 *priv = data; 951 u32 status, err_status; 952 953 status = rcsi2_read(priv, INTSTATE_REG); 954 err_status = rcsi2_read(priv, INTERRSTATE_REG); 955 956 if (!status) 957 return IRQ_HANDLED; 958 959 rcsi2_write(priv, INTSTATE_REG, status); 960 961 if (!err_status) 962 return IRQ_HANDLED; 963 964 rcsi2_write(priv, INTERRSTATE_REG, err_status); 965 966 dev_info(priv->dev, "Transfer error, restarting CSI-2 receiver\n"); 967 968 return IRQ_WAKE_THREAD; 969 } 970 971 static irqreturn_t rcsi2_irq_thread(int irq, void *data) 972 { 973 struct rcar_csi2 *priv = data; 974 975 mutex_lock(&priv->lock); 976 rcsi2_stop(priv); 977 usleep_range(1000, 2000); 978 if (rcsi2_start(priv)) 979 dev_warn(priv->dev, "Failed to restart CSI-2 receiver\n"); 980 mutex_unlock(&priv->lock); 981 982 return IRQ_HANDLED; 983 } 984 985 /* ----------------------------------------------------------------------------- 986 * Async handling and registration of subdevices and links. 987 */ 988 989 static int rcsi2_notify_bound(struct v4l2_async_notifier *notifier, 990 struct v4l2_subdev *subdev, 991 struct v4l2_async_subdev *asd) 992 { 993 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 994 int pad; 995 996 pad = media_entity_get_fwnode_pad(&subdev->entity, asd->match.fwnode, 997 MEDIA_PAD_FL_SOURCE); 998 if (pad < 0) { 999 dev_err(priv->dev, "Failed to find pad for %s\n", subdev->name); 1000 return pad; 1001 } 1002 1003 priv->remote = subdev; 1004 priv->remote_pad = pad; 1005 1006 dev_dbg(priv->dev, "Bound %s pad: %d\n", subdev->name, pad); 1007 1008 return media_create_pad_link(&subdev->entity, pad, 1009 &priv->subdev.entity, 0, 1010 MEDIA_LNK_FL_ENABLED | 1011 MEDIA_LNK_FL_IMMUTABLE); 1012 } 1013 1014 static void rcsi2_notify_unbind(struct v4l2_async_notifier *notifier, 1015 struct v4l2_subdev *subdev, 1016 struct v4l2_async_subdev *asd) 1017 { 1018 struct rcar_csi2 *priv = notifier_to_csi2(notifier); 1019 1020 priv->remote = NULL; 1021 1022 dev_dbg(priv->dev, "Unbind %s\n", subdev->name); 1023 } 1024 1025 static const struct v4l2_async_notifier_operations rcar_csi2_notify_ops = { 1026 .bound = rcsi2_notify_bound, 1027 .unbind = rcsi2_notify_unbind, 1028 }; 1029 1030 static int rcsi2_parse_v4l2(struct rcar_csi2 *priv, 1031 struct v4l2_fwnode_endpoint *vep) 1032 { 1033 unsigned int i; 1034 1035 /* Only port 0 endpoint 0 is valid. */ 1036 if (vep->base.port || vep->base.id) 1037 return -ENOTCONN; 1038 1039 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; 1040 1041 switch (vep->bus_type) { 1042 case V4L2_MBUS_CSI2_DPHY: 1043 if (!priv->info->support_dphy) { 1044 dev_err(priv->dev, "D-PHY not supported\n"); 1045 return -EINVAL; 1046 } 1047 1048 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { 1049 dev_err(priv->dev, 1050 "Unsupported number of data-lanes for D-PHY: %u\n", 1051 priv->lanes); 1052 return -EINVAL; 1053 } 1054 1055 priv->cphy = false; 1056 break; 1057 case V4L2_MBUS_CSI2_CPHY: 1058 if (!priv->info->support_cphy) { 1059 dev_err(priv->dev, "C-PHY not supported\n"); 1060 return -EINVAL; 1061 } 1062 1063 if (priv->lanes != 3) { 1064 dev_err(priv->dev, 1065 "Unsupported number of data-lanes for C-PHY: %u\n", 1066 priv->lanes); 1067 return -EINVAL; 1068 } 1069 1070 priv->cphy = true; 1071 break; 1072 default: 1073 dev_err(priv->dev, "Unsupported bus: %u\n", vep->bus_type); 1074 return -EINVAL; 1075 } 1076 1077 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { 1078 priv->lane_swap[i] = i < priv->lanes ? 1079 vep->bus.mipi_csi2.data_lanes[i] : i; 1080 1081 /* Check for valid lane number. */ 1082 if (priv->lane_swap[i] < 1 || priv->lane_swap[i] > 4) { 1083 dev_err(priv->dev, "data-lanes must be in 1-4 range\n"); 1084 return -EINVAL; 1085 } 1086 } 1087 1088 return 0; 1089 } 1090 1091 static int rcsi2_parse_dt(struct rcar_csi2 *priv) 1092 { 1093 struct v4l2_async_subdev *asd; 1094 struct fwnode_handle *fwnode; 1095 struct fwnode_handle *ep; 1096 struct v4l2_fwnode_endpoint v4l2_ep = { 1097 .bus_type = V4L2_MBUS_UNKNOWN, 1098 }; 1099 int ret; 1100 1101 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); 1102 if (!ep) { 1103 dev_err(priv->dev, "Not connected to subdevice\n"); 1104 return -EINVAL; 1105 } 1106 1107 ret = v4l2_fwnode_endpoint_parse(ep, &v4l2_ep); 1108 if (ret) { 1109 dev_err(priv->dev, "Could not parse v4l2 endpoint\n"); 1110 fwnode_handle_put(ep); 1111 return -EINVAL; 1112 } 1113 1114 ret = rcsi2_parse_v4l2(priv, &v4l2_ep); 1115 if (ret) { 1116 fwnode_handle_put(ep); 1117 return ret; 1118 } 1119 1120 fwnode = fwnode_graph_get_remote_endpoint(ep); 1121 fwnode_handle_put(ep); 1122 1123 dev_dbg(priv->dev, "Found '%pOF'\n", to_of_node(fwnode)); 1124 1125 v4l2_async_nf_init(&priv->notifier); 1126 priv->notifier.ops = &rcar_csi2_notify_ops; 1127 1128 asd = v4l2_async_nf_add_fwnode(&priv->notifier, fwnode, 1129 struct v4l2_async_subdev); 1130 fwnode_handle_put(fwnode); 1131 if (IS_ERR(asd)) 1132 return PTR_ERR(asd); 1133 1134 ret = v4l2_async_subdev_nf_register(&priv->subdev, &priv->notifier); 1135 if (ret) 1136 v4l2_async_nf_cleanup(&priv->notifier); 1137 1138 return ret; 1139 } 1140 1141 /* ----------------------------------------------------------------------------- 1142 * PHTW initialization sequences. 1143 * 1144 * NOTE: Magic values are from the datasheet and lack documentation. 1145 */ 1146 1147 static int rcsi2_phtw_write(struct rcar_csi2 *priv, u16 data, u16 code) 1148 { 1149 unsigned int timeout; 1150 1151 rcsi2_write(priv, PHTW_REG, 1152 PHTW_DWEN | PHTW_TESTDIN_DATA(data) | 1153 PHTW_CWEN | PHTW_TESTDIN_CODE(code)); 1154 1155 /* Wait for DWEN and CWEN to be cleared by hardware. */ 1156 for (timeout = 0; timeout <= 20; timeout++) { 1157 if (!(rcsi2_read(priv, PHTW_REG) & (PHTW_DWEN | PHTW_CWEN))) 1158 return 0; 1159 1160 usleep_range(1000, 2000); 1161 } 1162 1163 dev_err(priv->dev, "Timeout waiting for PHTW_DWEN and/or PHTW_CWEN\n"); 1164 1165 return -ETIMEDOUT; 1166 } 1167 1168 static int rcsi2_phtw_write_array(struct rcar_csi2 *priv, 1169 const struct phtw_value *values) 1170 { 1171 const struct phtw_value *value; 1172 int ret; 1173 1174 for (value = values; value->data || value->code; value++) { 1175 ret = rcsi2_phtw_write(priv, value->data, value->code); 1176 if (ret) 1177 return ret; 1178 } 1179 1180 return 0; 1181 } 1182 1183 static int rcsi2_phtw_write_mbps(struct rcar_csi2 *priv, unsigned int mbps, 1184 const struct rcsi2_mbps_reg *values, u16 code) 1185 { 1186 const struct rcsi2_mbps_reg *value; 1187 const struct rcsi2_mbps_reg *prev_value = NULL; 1188 1189 for (value = values; value->mbps; value++) { 1190 if (value->mbps >= mbps) 1191 break; 1192 prev_value = value; 1193 } 1194 1195 if (prev_value && 1196 ((mbps - prev_value->mbps) <= (value->mbps - mbps))) 1197 value = prev_value; 1198 1199 if (!value->mbps) { 1200 dev_err(priv->dev, "Unsupported PHY speed (%u Mbps)", mbps); 1201 return -ERANGE; 1202 } 1203 1204 return rcsi2_phtw_write(priv, value->reg, code); 1205 } 1206 1207 static int __rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, 1208 unsigned int mbps) 1209 { 1210 static const struct phtw_value step1[] = { 1211 { .data = 0xcc, .code = 0xe2 }, 1212 { .data = 0x01, .code = 0xe3 }, 1213 { .data = 0x11, .code = 0xe4 }, 1214 { .data = 0x01, .code = 0xe5 }, 1215 { .data = 0x10, .code = 0x04 }, 1216 { /* sentinel */ }, 1217 }; 1218 1219 static const struct phtw_value step2[] = { 1220 { .data = 0x38, .code = 0x08 }, 1221 { .data = 0x01, .code = 0x00 }, 1222 { .data = 0x4b, .code = 0xac }, 1223 { .data = 0x03, .code = 0x00 }, 1224 { .data = 0x80, .code = 0x07 }, 1225 { /* sentinel */ }, 1226 }; 1227 1228 int ret; 1229 1230 ret = rcsi2_phtw_write_array(priv, step1); 1231 if (ret) 1232 return ret; 1233 1234 if (mbps != 0 && mbps <= 250) { 1235 ret = rcsi2_phtw_write(priv, 0x39, 0x05); 1236 if (ret) 1237 return ret; 1238 1239 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_h3_v3h_m3n, 1240 0xf1); 1241 if (ret) 1242 return ret; 1243 } 1244 1245 return rcsi2_phtw_write_array(priv, step2); 1246 } 1247 1248 static int rcsi2_init_phtw_h3_v3h_m3n(struct rcar_csi2 *priv, unsigned int mbps) 1249 { 1250 return __rcsi2_init_phtw_h3_v3h_m3n(priv, mbps); 1251 } 1252 1253 static int rcsi2_init_phtw_h3es2(struct rcar_csi2 *priv, unsigned int mbps) 1254 { 1255 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); 1256 } 1257 1258 static int rcsi2_init_phtw_v3m_e3(struct rcar_csi2 *priv, unsigned int mbps) 1259 { 1260 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); 1261 } 1262 1263 static int rcsi2_phy_post_init_v3m_e3(struct rcar_csi2 *priv) 1264 { 1265 static const struct phtw_value step1[] = { 1266 { .data = 0xee, .code = 0x34 }, 1267 { .data = 0xee, .code = 0x44 }, 1268 { .data = 0xee, .code = 0x54 }, 1269 { .data = 0xee, .code = 0x84 }, 1270 { .data = 0xee, .code = 0x94 }, 1271 { /* sentinel */ }, 1272 }; 1273 1274 return rcsi2_phtw_write_array(priv, step1); 1275 } 1276 1277 static int rcsi2_init_phtw_v3u(struct rcar_csi2 *priv, 1278 unsigned int mbps) 1279 { 1280 /* In case of 1500Mbps or less */ 1281 static const struct phtw_value step1[] = { 1282 { .data = 0xcc, .code = 0xe2 }, 1283 { /* sentinel */ }, 1284 }; 1285 1286 static const struct phtw_value step2[] = { 1287 { .data = 0x01, .code = 0xe3 }, 1288 { .data = 0x11, .code = 0xe4 }, 1289 { .data = 0x01, .code = 0xe5 }, 1290 { /* sentinel */ }, 1291 }; 1292 1293 /* In case of 1500Mbps or less */ 1294 static const struct phtw_value step3[] = { 1295 { .data = 0x38, .code = 0x08 }, 1296 { /* sentinel */ }, 1297 }; 1298 1299 static const struct phtw_value step4[] = { 1300 { .data = 0x01, .code = 0x00 }, 1301 { .data = 0x4b, .code = 0xac }, 1302 { .data = 0x03, .code = 0x00 }, 1303 { .data = 0x80, .code = 0x07 }, 1304 { /* sentinel */ }, 1305 }; 1306 1307 int ret; 1308 1309 if (mbps != 0 && mbps <= 1500) 1310 ret = rcsi2_phtw_write_array(priv, step1); 1311 else 1312 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); 1313 if (ret) 1314 return ret; 1315 1316 ret = rcsi2_phtw_write_array(priv, step2); 1317 if (ret) 1318 return ret; 1319 1320 if (mbps != 0 && mbps <= 1500) { 1321 ret = rcsi2_phtw_write_array(priv, step3); 1322 if (ret) 1323 return ret; 1324 } 1325 1326 ret = rcsi2_phtw_write_array(priv, step4); 1327 if (ret) 1328 return ret; 1329 1330 return ret; 1331 } 1332 1333 /* ----------------------------------------------------------------------------- 1334 * Platform Device Driver. 1335 */ 1336 1337 static int rcsi2_link_setup(struct media_entity *entity, 1338 const struct media_pad *local, 1339 const struct media_pad *remote, u32 flags) 1340 { 1341 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1342 struct rcar_csi2 *priv = sd_to_csi2(sd); 1343 struct video_device *vdev; 1344 int channel, vc; 1345 u32 id; 1346 1347 if (!is_media_entity_v4l2_video_device(remote->entity)) { 1348 dev_err(priv->dev, "Remote is not a video device\n"); 1349 return -EINVAL; 1350 } 1351 1352 vdev = media_entity_to_video_device(remote->entity); 1353 1354 if (of_property_read_u32(vdev->dev_parent->of_node, "renesas,id", &id)) { 1355 dev_err(priv->dev, "No renesas,id, can't configure routing\n"); 1356 return -EINVAL; 1357 } 1358 1359 channel = id % 4; 1360 1361 if (flags & MEDIA_LNK_FL_ENABLED) { 1362 if (media_pad_remote_pad_first(local)) { 1363 dev_dbg(priv->dev, 1364 "Each VC can only be routed to one output channel\n"); 1365 return -EINVAL; 1366 } 1367 1368 vc = local->index - 1; 1369 1370 dev_dbg(priv->dev, "Route VC%d to VIN%u on output channel %d\n", 1371 vc, id, channel); 1372 } else { 1373 vc = -1; 1374 } 1375 1376 priv->channel_vc[channel] = vc; 1377 1378 return 0; 1379 } 1380 1381 static const struct media_entity_operations rcar_csi2_entity_ops = { 1382 .link_setup = rcsi2_link_setup, 1383 .link_validate = v4l2_subdev_link_validate, 1384 }; 1385 1386 static int rcsi2_probe_resources(struct rcar_csi2 *priv, 1387 struct platform_device *pdev) 1388 { 1389 int irq, ret; 1390 1391 priv->base = devm_platform_ioremap_resource(pdev, 0); 1392 if (IS_ERR(priv->base)) 1393 return PTR_ERR(priv->base); 1394 1395 irq = platform_get_irq(pdev, 0); 1396 if (irq < 0) 1397 return irq; 1398 1399 ret = devm_request_threaded_irq(&pdev->dev, irq, rcsi2_irq, 1400 rcsi2_irq_thread, IRQF_SHARED, 1401 KBUILD_MODNAME, priv); 1402 if (ret) 1403 return ret; 1404 1405 priv->rstc = devm_reset_control_get(&pdev->dev, NULL); 1406 1407 return PTR_ERR_OR_ZERO(priv->rstc); 1408 } 1409 1410 static const struct rcar_csi2_info rcar_csi2_info_r8a7795 = { 1411 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1412 .start_receiver = rcsi2_start_receiver_gen3, 1413 .enter_standby = rcsi2_enter_standby_gen3, 1414 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1415 .csi0clkfreqrange = 0x20, 1416 .num_channels = 4, 1417 .clear_ulps = true, 1418 .support_dphy = true, 1419 }; 1420 1421 static const struct rcar_csi2_info rcar_csi2_info_r8a7795es2 = { 1422 .init_phtw = rcsi2_init_phtw_h3es2, 1423 .start_receiver = rcsi2_start_receiver_gen3, 1424 .enter_standby = rcsi2_enter_standby_gen3, 1425 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1426 .csi0clkfreqrange = 0x20, 1427 .num_channels = 4, 1428 .clear_ulps = true, 1429 .support_dphy = true, 1430 }; 1431 1432 static const struct rcar_csi2_info rcar_csi2_info_r8a7796 = { 1433 .start_receiver = rcsi2_start_receiver_gen3, 1434 .enter_standby = rcsi2_enter_standby_gen3, 1435 .hsfreqrange = hsfreqrange_m3w, 1436 .num_channels = 4, 1437 .support_dphy = true, 1438 }; 1439 1440 static const struct rcar_csi2_info rcar_csi2_info_r8a77961 = { 1441 .start_receiver = rcsi2_start_receiver_gen3, 1442 .enter_standby = rcsi2_enter_standby_gen3, 1443 .hsfreqrange = hsfreqrange_m3w, 1444 .num_channels = 4, 1445 .support_dphy = true, 1446 }; 1447 1448 static const struct rcar_csi2_info rcar_csi2_info_r8a77965 = { 1449 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1450 .start_receiver = rcsi2_start_receiver_gen3, 1451 .enter_standby = rcsi2_enter_standby_gen3, 1452 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1453 .csi0clkfreqrange = 0x20, 1454 .num_channels = 4, 1455 .clear_ulps = true, 1456 .support_dphy = true, 1457 }; 1458 1459 static const struct rcar_csi2_info rcar_csi2_info_r8a77970 = { 1460 .init_phtw = rcsi2_init_phtw_v3m_e3, 1461 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 1462 .start_receiver = rcsi2_start_receiver_gen3, 1463 .enter_standby = rcsi2_enter_standby_gen3, 1464 .num_channels = 4, 1465 .support_dphy = true, 1466 }; 1467 1468 static const struct rcar_csi2_info rcar_csi2_info_r8a77980 = { 1469 .init_phtw = rcsi2_init_phtw_h3_v3h_m3n, 1470 .start_receiver = rcsi2_start_receiver_gen3, 1471 .enter_standby = rcsi2_enter_standby_gen3, 1472 .hsfreqrange = hsfreqrange_h3_v3h_m3n, 1473 .csi0clkfreqrange = 0x20, 1474 .clear_ulps = true, 1475 .support_dphy = true, 1476 }; 1477 1478 static const struct rcar_csi2_info rcar_csi2_info_r8a77990 = { 1479 .init_phtw = rcsi2_init_phtw_v3m_e3, 1480 .phy_post_init = rcsi2_phy_post_init_v3m_e3, 1481 .start_receiver = rcsi2_start_receiver_gen3, 1482 .enter_standby = rcsi2_enter_standby_gen3, 1483 .num_channels = 2, 1484 .support_dphy = true, 1485 }; 1486 1487 static const struct rcar_csi2_info rcar_csi2_info_r8a779a0 = { 1488 .init_phtw = rcsi2_init_phtw_v3u, 1489 .start_receiver = rcsi2_start_receiver_gen3, 1490 .enter_standby = rcsi2_enter_standby_gen3, 1491 .hsfreqrange = hsfreqrange_v3u, 1492 .csi0clkfreqrange = 0x20, 1493 .clear_ulps = true, 1494 .use_isp = true, 1495 .support_dphy = true, 1496 }; 1497 1498 static const struct of_device_id rcar_csi2_of_table[] = { 1499 { 1500 .compatible = "renesas,r8a774a1-csi2", 1501 .data = &rcar_csi2_info_r8a7796, 1502 }, 1503 { 1504 .compatible = "renesas,r8a774b1-csi2", 1505 .data = &rcar_csi2_info_r8a77965, 1506 }, 1507 { 1508 .compatible = "renesas,r8a774c0-csi2", 1509 .data = &rcar_csi2_info_r8a77990, 1510 }, 1511 { 1512 .compatible = "renesas,r8a774e1-csi2", 1513 .data = &rcar_csi2_info_r8a7795, 1514 }, 1515 { 1516 .compatible = "renesas,r8a7795-csi2", 1517 .data = &rcar_csi2_info_r8a7795, 1518 }, 1519 { 1520 .compatible = "renesas,r8a7796-csi2", 1521 .data = &rcar_csi2_info_r8a7796, 1522 }, 1523 { 1524 .compatible = "renesas,r8a77961-csi2", 1525 .data = &rcar_csi2_info_r8a77961, 1526 }, 1527 { 1528 .compatible = "renesas,r8a77965-csi2", 1529 .data = &rcar_csi2_info_r8a77965, 1530 }, 1531 { 1532 .compatible = "renesas,r8a77970-csi2", 1533 .data = &rcar_csi2_info_r8a77970, 1534 }, 1535 { 1536 .compatible = "renesas,r8a77980-csi2", 1537 .data = &rcar_csi2_info_r8a77980, 1538 }, 1539 { 1540 .compatible = "renesas,r8a77990-csi2", 1541 .data = &rcar_csi2_info_r8a77990, 1542 }, 1543 { 1544 .compatible = "renesas,r8a779a0-csi2", 1545 .data = &rcar_csi2_info_r8a779a0, 1546 }, 1547 { /* sentinel */ }, 1548 }; 1549 MODULE_DEVICE_TABLE(of, rcar_csi2_of_table); 1550 1551 static const struct soc_device_attribute r8a7795[] = { 1552 { 1553 .soc_id = "r8a7795", .revision = "ES2.*", 1554 .data = &rcar_csi2_info_r8a7795es2, 1555 }, 1556 { /* sentinel */ } 1557 }; 1558 1559 static int rcsi2_probe(struct platform_device *pdev) 1560 { 1561 const struct soc_device_attribute *attr; 1562 struct rcar_csi2 *priv; 1563 unsigned int i, num_pads; 1564 int ret; 1565 1566 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 1567 if (!priv) 1568 return -ENOMEM; 1569 1570 priv->info = of_device_get_match_data(&pdev->dev); 1571 1572 /* 1573 * The different ES versions of r8a7795 (H3) behave differently but 1574 * share the same compatible string. 1575 */ 1576 attr = soc_device_match(r8a7795); 1577 if (attr) 1578 priv->info = attr->data; 1579 1580 priv->dev = &pdev->dev; 1581 1582 mutex_init(&priv->lock); 1583 priv->stream_count = 0; 1584 1585 ret = rcsi2_probe_resources(priv, pdev); 1586 if (ret) { 1587 dev_err(priv->dev, "Failed to get resources\n"); 1588 goto error_mutex; 1589 } 1590 1591 platform_set_drvdata(pdev, priv); 1592 1593 ret = rcsi2_parse_dt(priv); 1594 if (ret) 1595 goto error_mutex; 1596 1597 priv->subdev.owner = THIS_MODULE; 1598 priv->subdev.dev = &pdev->dev; 1599 v4l2_subdev_init(&priv->subdev, &rcar_csi2_subdev_ops); 1600 v4l2_set_subdevdata(&priv->subdev, &pdev->dev); 1601 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s %s", 1602 KBUILD_MODNAME, dev_name(&pdev->dev)); 1603 priv->subdev.flags = V4L2_SUBDEV_FL_HAS_DEVNODE; 1604 1605 priv->subdev.entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 1606 priv->subdev.entity.ops = &rcar_csi2_entity_ops; 1607 1608 num_pads = priv->info->use_isp ? 2 : NR_OF_RCAR_CSI2_PAD; 1609 1610 priv->pads[RCAR_CSI2_SINK].flags = MEDIA_PAD_FL_SINK; 1611 for (i = RCAR_CSI2_SOURCE_VC0; i < num_pads; i++) 1612 priv->pads[i].flags = MEDIA_PAD_FL_SOURCE; 1613 1614 ret = media_entity_pads_init(&priv->subdev.entity, num_pads, 1615 priv->pads); 1616 if (ret) 1617 goto error_async; 1618 1619 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) 1620 priv->channel_vc[i] = -1; 1621 1622 pm_runtime_enable(&pdev->dev); 1623 1624 ret = v4l2_async_register_subdev(&priv->subdev); 1625 if (ret < 0) 1626 goto error_async; 1627 1628 dev_info(priv->dev, "%d lanes found\n", priv->lanes); 1629 1630 return 0; 1631 1632 error_async: 1633 v4l2_async_nf_unregister(&priv->notifier); 1634 v4l2_async_nf_cleanup(&priv->notifier); 1635 error_mutex: 1636 mutex_destroy(&priv->lock); 1637 1638 return ret; 1639 } 1640 1641 static void rcsi2_remove(struct platform_device *pdev) 1642 { 1643 struct rcar_csi2 *priv = platform_get_drvdata(pdev); 1644 1645 v4l2_async_nf_unregister(&priv->notifier); 1646 v4l2_async_nf_cleanup(&priv->notifier); 1647 v4l2_async_unregister_subdev(&priv->subdev); 1648 1649 pm_runtime_disable(&pdev->dev); 1650 1651 mutex_destroy(&priv->lock); 1652 } 1653 1654 static struct platform_driver rcar_csi2_pdrv = { 1655 .remove_new = rcsi2_remove, 1656 .probe = rcsi2_probe, 1657 .driver = { 1658 .name = "rcar-csi2", 1659 .suppress_bind_attrs = true, 1660 .of_match_table = rcar_csi2_of_table, 1661 }, 1662 }; 1663 1664 module_platform_driver(rcar_csi2_pdrv); 1665 1666 MODULE_AUTHOR("Niklas Söderlund <niklas.soderlund@ragnatech.se>"); 1667 MODULE_DESCRIPTION("Renesas R-Car MIPI CSI-2 receiver driver"); 1668 MODULE_LICENSE("GPL"); 1669