1 /* 2 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2017 Linaro Ltd. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 and 7 * only version 2 as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 */ 15 #ifndef __VENUS_HFI_VENUS_IO_H__ 16 #define __VENUS_HFI_VENUS_IO_H__ 17 18 #define VBIF_BASE 0x80000 19 20 #define VBIF_AXI_HALT_CTRL0 (VBIF_BASE + 0x208) 21 #define VBIF_AXI_HALT_CTRL1 (VBIF_BASE + 0x20c) 22 23 #define VBIF_AXI_HALT_CTRL0_HALT_REQ BIT(0) 24 #define VBIF_AXI_HALT_CTRL1_HALT_ACK BIT(0) 25 #define VBIF_AXI_HALT_ACK_TIMEOUT_US 500000 26 27 #define CPU_BASE 0xc0000 28 #define CPU_CS_BASE (CPU_BASE + 0x12000) 29 #define CPU_IC_BASE (CPU_BASE + 0x1f000) 30 31 #define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE + 0x1c) 32 33 #define VIDC_CTRL_INIT (CPU_CS_BASE + 0x48) 34 #define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK 0xfffffffe 35 #define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT 1 36 #define VIDC_CTRL_INIT_CTRL_MASK 0x1 37 #define VIDC_CTRL_INIT_CTRL_SHIFT 0 38 39 /* HFI control status */ 40 #define CPU_CS_SCIACMDARG0 (CPU_CS_BASE + 0x4c) 41 #define CPU_CS_SCIACMDARG0_MASK 0xff 42 #define CPU_CS_SCIACMDARG0_SHIFT 0x0 43 #define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK 0xfe 44 #define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT 0x1 45 #define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK 0x1 46 #define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT 0x0 47 #define CPU_CS_SCIACMDARG0_PC_READY BIT(8) 48 #define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK BIT(30) 49 50 /* HFI queue table info */ 51 #define CPU_CS_SCIACMDARG1 (CPU_CS_BASE + 0x50) 52 53 /* HFI queue table address */ 54 #define CPU_CS_SCIACMDARG2 (CPU_CS_BASE + 0x54) 55 56 /* Venus cpu */ 57 #define CPU_CS_SCIACMDARG3 (CPU_CS_BASE + 0x58) 58 59 #define SFR_ADDR (CPU_CS_BASE + 0x5c) 60 #define MMAP_ADDR (CPU_CS_BASE + 0x60) 61 #define UC_REGION_ADDR (CPU_CS_BASE + 0x64) 62 #define UC_REGION_SIZE (CPU_CS_BASE + 0x68) 63 64 #define CPU_IC_SOFTINT (CPU_IC_BASE + 0x18) 65 #define CPU_IC_SOFTINT_H2A_MASK 0x8000 66 #define CPU_IC_SOFTINT_H2A_SHIFT 0xf 67 68 /* Venus wrapper */ 69 #define WRAPPER_BASE 0x000e0000 70 71 #define WRAPPER_HW_VERSION (WRAPPER_BASE + 0x00) 72 #define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK 0x78000000 73 #define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT 28 74 #define WRAPPER_HW_VERSION_MINOR_VERSION_MASK 0xfff0000 75 #define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT 16 76 #define WRAPPER_HW_VERSION_STEP_VERSION_MASK 0xffff 77 78 #define WRAPPER_CLOCK_CONFIG (WRAPPER_BASE + 0x04) 79 80 #define WRAPPER_INTR_STATUS (WRAPPER_BASE + 0x0c) 81 #define WRAPPER_INTR_STATUS_A2HWD_MASK 0x10 82 #define WRAPPER_INTR_STATUS_A2HWD_SHIFT 0x4 83 #define WRAPPER_INTR_STATUS_A2H_MASK 0x4 84 #define WRAPPER_INTR_STATUS_A2H_SHIFT 0x2 85 86 #define WRAPPER_INTR_MASK (WRAPPER_BASE + 0x10) 87 #define WRAPPER_INTR_MASK_A2HWD_BASK 0x10 88 #define WRAPPER_INTR_MASK_A2HWD_SHIFT 0x4 89 #define WRAPPER_INTR_MASK_A2HVCODEC_MASK 0x8 90 #define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT 0x3 91 #define WRAPPER_INTR_MASK_A2HCPU_MASK 0x4 92 #define WRAPPER_INTR_MASK_A2HCPU_SHIFT 0x2 93 94 #define WRAPPER_INTR_CLEAR (WRAPPER_BASE + 0x14) 95 #define WRAPPER_INTR_CLEAR_A2HWD_MASK 0x10 96 #define WRAPPER_INTR_CLEAR_A2HWD_SHIFT 0x4 97 #define WRAPPER_INTR_CLEAR_A2H_MASK 0x4 98 #define WRAPPER_INTR_CLEAR_A2H_SHIFT 0x2 99 100 #define WRAPPER_POWER_STATUS (WRAPPER_BASE + 0x44) 101 #define WRAPPER_VDEC_VCODEC_POWER_CONTROL (WRAPPER_BASE + 0x48) 102 #define WRAPPER_VENC_VCODEC_POWER_CONTROL (WRAPPER_BASE + 0x4c) 103 #define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET (WRAPPER_BASE + 0x64) 104 105 #define WRAPPER_CPU_CLOCK_CONFIG (WRAPPER_BASE + 0x2000) 106 #define WRAPPER_CPU_AXI_HALT (WRAPPER_BASE + 0x2008) 107 #define WRAPPER_CPU_AXI_HALT_STATUS (WRAPPER_BASE + 0x200c) 108 109 #define WRAPPER_CPU_CGC_DIS (WRAPPER_BASE + 0x2010) 110 #define WRAPPER_CPU_STATUS (WRAPPER_BASE + 0x2014) 111 #define WRAPPER_SW_RESET (WRAPPER_BASE + 0x3000) 112 113 #endif 114