1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2017 Linaro Ltd. 5 */ 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/io.h> 9 #include <linux/ioctl.h> 10 #include <linux/delay.h> 11 #include <linux/devcoredump.h> 12 #include <linux/list.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/types.h> 18 #include <linux/pm_runtime.h> 19 #include <media/videobuf2-v4l2.h> 20 #include <media/v4l2-mem2mem.h> 21 #include <media/v4l2-ioctl.h> 22 23 #include "core.h" 24 #include "firmware.h" 25 #include "pm_helpers.h" 26 #include "hfi_venus_io.h" 27 28 static void venus_coredump(struct venus_core *core) 29 { 30 struct device *dev; 31 phys_addr_t mem_phys; 32 size_t mem_size; 33 void *mem_va; 34 void *data; 35 36 dev = core->dev; 37 mem_phys = core->fw.mem_phys; 38 mem_size = core->fw.mem_size; 39 40 mem_va = memremap(mem_phys, mem_size, MEMREMAP_WC); 41 if (!mem_va) 42 return; 43 44 data = vmalloc(mem_size); 45 if (!data) { 46 memunmap(mem_va); 47 return; 48 } 49 50 memcpy(data, mem_va, mem_size); 51 memunmap(mem_va); 52 dev_coredumpv(dev, data, mem_size, GFP_KERNEL); 53 } 54 55 static void venus_event_notify(struct venus_core *core, u32 event) 56 { 57 struct venus_inst *inst; 58 59 switch (event) { 60 case EVT_SYS_WATCHDOG_TIMEOUT: 61 case EVT_SYS_ERROR: 62 break; 63 default: 64 return; 65 } 66 67 mutex_lock(&core->lock); 68 set_bit(0, &core->sys_error); 69 list_for_each_entry(inst, &core->instances, list) 70 inst->ops->event_notify(inst, EVT_SESSION_ERROR, NULL); 71 mutex_unlock(&core->lock); 72 73 disable_irq_nosync(core->irq); 74 schedule_delayed_work(&core->work, msecs_to_jiffies(10)); 75 } 76 77 static const struct hfi_core_ops venus_core_ops = { 78 .event_notify = venus_event_notify, 79 }; 80 81 #define RPM_WAIT_FOR_IDLE_MAX_ATTEMPTS 10 82 83 static void venus_sys_error_handler(struct work_struct *work) 84 { 85 struct venus_core *core = 86 container_of(work, struct venus_core, work.work); 87 int ret, i, max_attempts = RPM_WAIT_FOR_IDLE_MAX_ATTEMPTS; 88 const char *err_msg = ""; 89 bool failed = false; 90 91 ret = pm_runtime_get_sync(core->dev); 92 if (ret < 0) { 93 err_msg = "resume runtime PM"; 94 max_attempts = 0; 95 failed = true; 96 } 97 98 core->ops->core_deinit(core); 99 core->state = CORE_UNINIT; 100 101 for (i = 0; i < max_attempts; i++) { 102 if (!pm_runtime_active(core->dev_dec) && !pm_runtime_active(core->dev_enc)) 103 break; 104 msleep(10); 105 } 106 107 mutex_lock(&core->lock); 108 109 venus_shutdown(core); 110 111 venus_coredump(core); 112 113 pm_runtime_put_sync(core->dev); 114 115 for (i = 0; i < max_attempts; i++) { 116 if (!core->pmdomains[0] || !pm_runtime_active(core->pmdomains[0])) 117 break; 118 usleep_range(1000, 1500); 119 } 120 121 hfi_reinit(core); 122 123 ret = pm_runtime_get_sync(core->dev); 124 if (ret < 0) { 125 err_msg = "resume runtime PM"; 126 failed = true; 127 } 128 129 ret = venus_boot(core); 130 if (ret && !failed) { 131 err_msg = "boot Venus"; 132 failed = true; 133 } 134 135 ret = hfi_core_resume(core, true); 136 if (ret && !failed) { 137 err_msg = "resume HFI"; 138 failed = true; 139 } 140 141 enable_irq(core->irq); 142 143 mutex_unlock(&core->lock); 144 145 ret = hfi_core_init(core); 146 if (ret && !failed) { 147 err_msg = "init HFI"; 148 failed = true; 149 } 150 151 pm_runtime_put_sync(core->dev); 152 153 if (failed) { 154 disable_irq_nosync(core->irq); 155 dev_warn_ratelimited(core->dev, 156 "System error has occurred, recovery failed to %s\n", 157 err_msg); 158 schedule_delayed_work(&core->work, msecs_to_jiffies(10)); 159 return; 160 } 161 162 dev_warn(core->dev, "system error has occurred (recovered)\n"); 163 164 mutex_lock(&core->lock); 165 clear_bit(0, &core->sys_error); 166 wake_up_all(&core->sys_err_done); 167 mutex_unlock(&core->lock); 168 } 169 170 static u32 to_v4l2_codec_type(u32 codec) 171 { 172 switch (codec) { 173 case HFI_VIDEO_CODEC_H264: 174 return V4L2_PIX_FMT_H264; 175 case HFI_VIDEO_CODEC_H263: 176 return V4L2_PIX_FMT_H263; 177 case HFI_VIDEO_CODEC_MPEG1: 178 return V4L2_PIX_FMT_MPEG1; 179 case HFI_VIDEO_CODEC_MPEG2: 180 return V4L2_PIX_FMT_MPEG2; 181 case HFI_VIDEO_CODEC_MPEG4: 182 return V4L2_PIX_FMT_MPEG4; 183 case HFI_VIDEO_CODEC_VC1: 184 return V4L2_PIX_FMT_VC1_ANNEX_G; 185 case HFI_VIDEO_CODEC_VP8: 186 return V4L2_PIX_FMT_VP8; 187 case HFI_VIDEO_CODEC_VP9: 188 return V4L2_PIX_FMT_VP9; 189 case HFI_VIDEO_CODEC_DIVX: 190 case HFI_VIDEO_CODEC_DIVX_311: 191 return V4L2_PIX_FMT_XVID; 192 default: 193 return 0; 194 } 195 } 196 197 static int venus_enumerate_codecs(struct venus_core *core, u32 type) 198 { 199 const struct hfi_inst_ops dummy_ops = {}; 200 struct venus_inst *inst; 201 u32 codec, codecs; 202 unsigned int i; 203 int ret; 204 205 if (core->res->hfi_version != HFI_VERSION_1XX) 206 return 0; 207 208 inst = kzalloc(sizeof(*inst), GFP_KERNEL); 209 if (!inst) 210 return -ENOMEM; 211 212 mutex_init(&inst->lock); 213 inst->core = core; 214 inst->session_type = type; 215 if (type == VIDC_SESSION_TYPE_DEC) 216 codecs = core->dec_codecs; 217 else 218 codecs = core->enc_codecs; 219 220 ret = hfi_session_create(inst, &dummy_ops); 221 if (ret) 222 goto err; 223 224 for (i = 0; i < MAX_CODEC_NUM; i++) { 225 codec = (1UL << i) & codecs; 226 if (!codec) 227 continue; 228 229 ret = hfi_session_init(inst, to_v4l2_codec_type(codec)); 230 if (ret) 231 goto done; 232 233 ret = hfi_session_deinit(inst); 234 if (ret) 235 goto done; 236 } 237 238 done: 239 hfi_session_destroy(inst); 240 err: 241 mutex_destroy(&inst->lock); 242 kfree(inst); 243 244 return ret; 245 } 246 247 static void venus_assign_register_offsets(struct venus_core *core) 248 { 249 if (IS_V6(core)) { 250 core->vbif_base = core->base + VBIF_BASE; 251 core->cpu_base = core->base + CPU_BASE_V6; 252 core->cpu_cs_base = core->base + CPU_CS_BASE_V6; 253 core->cpu_ic_base = core->base + CPU_IC_BASE_V6; 254 core->wrapper_base = core->base + WRAPPER_BASE_V6; 255 core->wrapper_tz_base = core->base + WRAPPER_TZ_BASE_V6; 256 core->aon_base = core->base + AON_BASE_V6; 257 } else { 258 core->vbif_base = core->base + VBIF_BASE; 259 core->cpu_base = core->base + CPU_BASE; 260 core->cpu_cs_base = core->base + CPU_CS_BASE; 261 core->cpu_ic_base = core->base + CPU_IC_BASE; 262 core->wrapper_base = core->base + WRAPPER_BASE; 263 core->wrapper_tz_base = NULL; 264 core->aon_base = NULL; 265 } 266 } 267 268 static int venus_probe(struct platform_device *pdev) 269 { 270 struct device *dev = &pdev->dev; 271 struct venus_core *core; 272 int ret; 273 274 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL); 275 if (!core) 276 return -ENOMEM; 277 278 core->dev = dev; 279 280 core->base = devm_platform_ioremap_resource(pdev, 0); 281 if (IS_ERR(core->base)) 282 return PTR_ERR(core->base); 283 284 core->video_path = devm_of_icc_get(dev, "video-mem"); 285 if (IS_ERR(core->video_path)) 286 return PTR_ERR(core->video_path); 287 288 core->cpucfg_path = devm_of_icc_get(dev, "cpu-cfg"); 289 if (IS_ERR(core->cpucfg_path)) 290 return PTR_ERR(core->cpucfg_path); 291 292 core->irq = platform_get_irq(pdev, 0); 293 if (core->irq < 0) 294 return core->irq; 295 296 core->res = of_device_get_match_data(dev); 297 if (!core->res) 298 return -ENODEV; 299 300 mutex_init(&core->pm_lock); 301 302 core->pm_ops = venus_pm_get(core->res->hfi_version); 303 if (!core->pm_ops) 304 return -ENODEV; 305 306 if (core->pm_ops->core_get) { 307 ret = core->pm_ops->core_get(core); 308 if (ret) 309 return ret; 310 } 311 312 ret = dma_set_mask_and_coherent(dev, core->res->dma_mask); 313 if (ret) 314 goto err_core_put; 315 316 dma_set_max_seg_size(dev, UINT_MAX); 317 318 INIT_LIST_HEAD(&core->instances); 319 mutex_init(&core->lock); 320 INIT_DELAYED_WORK(&core->work, venus_sys_error_handler); 321 init_waitqueue_head(&core->sys_err_done); 322 323 ret = devm_request_threaded_irq(dev, core->irq, hfi_isr, hfi_isr_thread, 324 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 325 "venus", core); 326 if (ret) 327 goto err_core_put; 328 329 ret = hfi_create(core, &venus_core_ops); 330 if (ret) 331 goto err_core_put; 332 333 venus_assign_register_offsets(core); 334 335 ret = v4l2_device_register(dev, &core->v4l2_dev); 336 if (ret) 337 goto err_core_deinit; 338 339 platform_set_drvdata(pdev, core); 340 341 pm_runtime_enable(dev); 342 343 ret = pm_runtime_get_sync(dev); 344 if (ret < 0) 345 goto err_runtime_disable; 346 347 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 348 if (ret) 349 goto err_runtime_disable; 350 351 ret = venus_firmware_init(core); 352 if (ret) 353 goto err_of_depopulate; 354 355 ret = venus_boot(core); 356 if (ret) 357 goto err_firmware_deinit; 358 359 ret = hfi_core_resume(core, true); 360 if (ret) 361 goto err_venus_shutdown; 362 363 ret = hfi_core_init(core); 364 if (ret) 365 goto err_venus_shutdown; 366 367 ret = venus_enumerate_codecs(core, VIDC_SESSION_TYPE_DEC); 368 if (ret) 369 goto err_venus_shutdown; 370 371 ret = venus_enumerate_codecs(core, VIDC_SESSION_TYPE_ENC); 372 if (ret) 373 goto err_venus_shutdown; 374 375 ret = pm_runtime_put_sync(dev); 376 if (ret) { 377 pm_runtime_get_noresume(dev); 378 goto err_dev_unregister; 379 } 380 381 venus_dbgfs_init(core); 382 383 return 0; 384 385 err_dev_unregister: 386 v4l2_device_unregister(&core->v4l2_dev); 387 err_venus_shutdown: 388 venus_shutdown(core); 389 err_firmware_deinit: 390 venus_firmware_deinit(core); 391 err_of_depopulate: 392 of_platform_depopulate(dev); 393 err_runtime_disable: 394 pm_runtime_put_noidle(dev); 395 pm_runtime_set_suspended(dev); 396 pm_runtime_disable(dev); 397 hfi_destroy(core); 398 err_core_deinit: 399 hfi_core_deinit(core, false); 400 err_core_put: 401 if (core->pm_ops->core_put) 402 core->pm_ops->core_put(core); 403 return ret; 404 } 405 406 static int venus_remove(struct platform_device *pdev) 407 { 408 struct venus_core *core = platform_get_drvdata(pdev); 409 const struct venus_pm_ops *pm_ops = core->pm_ops; 410 struct device *dev = core->dev; 411 int ret; 412 413 ret = pm_runtime_get_sync(dev); 414 WARN_ON(ret < 0); 415 416 ret = hfi_core_deinit(core, true); 417 WARN_ON(ret); 418 419 venus_shutdown(core); 420 of_platform_depopulate(dev); 421 422 venus_firmware_deinit(core); 423 424 pm_runtime_put_sync(dev); 425 pm_runtime_disable(dev); 426 427 if (pm_ops->core_put) 428 pm_ops->core_put(core); 429 430 v4l2_device_unregister(&core->v4l2_dev); 431 432 hfi_destroy(core); 433 434 mutex_destroy(&core->pm_lock); 435 mutex_destroy(&core->lock); 436 venus_dbgfs_deinit(core); 437 438 return ret; 439 } 440 441 static void venus_core_shutdown(struct platform_device *pdev) 442 { 443 struct venus_core *core = platform_get_drvdata(pdev); 444 445 pm_runtime_get_sync(core->dev); 446 venus_shutdown(core); 447 venus_firmware_deinit(core); 448 pm_runtime_put_sync(core->dev); 449 } 450 451 static __maybe_unused int venus_runtime_suspend(struct device *dev) 452 { 453 struct venus_core *core = dev_get_drvdata(dev); 454 const struct venus_pm_ops *pm_ops = core->pm_ops; 455 int ret; 456 457 ret = hfi_core_suspend(core); 458 if (ret) 459 return ret; 460 461 if (pm_ops->core_power) { 462 ret = pm_ops->core_power(core, POWER_OFF); 463 if (ret) 464 return ret; 465 } 466 467 ret = icc_set_bw(core->cpucfg_path, 0, 0); 468 if (ret) 469 goto err_cpucfg_path; 470 471 ret = icc_set_bw(core->video_path, 0, 0); 472 if (ret) 473 goto err_video_path; 474 475 return ret; 476 477 err_video_path: 478 icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0); 479 err_cpucfg_path: 480 if (pm_ops->core_power) 481 pm_ops->core_power(core, POWER_ON); 482 483 return ret; 484 } 485 486 static __maybe_unused int venus_runtime_resume(struct device *dev) 487 { 488 struct venus_core *core = dev_get_drvdata(dev); 489 const struct venus_pm_ops *pm_ops = core->pm_ops; 490 int ret; 491 492 ret = icc_set_bw(core->video_path, kbps_to_icc(20000), 0); 493 if (ret) 494 return ret; 495 496 ret = icc_set_bw(core->cpucfg_path, kbps_to_icc(1000), 0); 497 if (ret) 498 return ret; 499 500 if (pm_ops->core_power) { 501 ret = pm_ops->core_power(core, POWER_ON); 502 if (ret) 503 return ret; 504 } 505 506 return hfi_core_resume(core, false); 507 } 508 509 static const struct dev_pm_ops venus_pm_ops = { 510 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 511 pm_runtime_force_resume) 512 SET_RUNTIME_PM_OPS(venus_runtime_suspend, venus_runtime_resume, NULL) 513 }; 514 515 static const struct freq_tbl msm8916_freq_table[] = { 516 { 352800, 228570000 }, /* 1920x1088 @ 30 + 1280x720 @ 30 */ 517 { 244800, 160000000 }, /* 1920x1088 @ 30 */ 518 { 108000, 100000000 }, /* 1280x720 @ 30 */ 519 }; 520 521 static const struct reg_val msm8916_reg_preset[] = { 522 { 0xe0020, 0x05555556 }, 523 { 0xe0024, 0x05555556 }, 524 { 0x80124, 0x00000003 }, 525 }; 526 527 static const struct venus_resources msm8916_res = { 528 .freq_tbl = msm8916_freq_table, 529 .freq_tbl_size = ARRAY_SIZE(msm8916_freq_table), 530 .reg_tbl = msm8916_reg_preset, 531 .reg_tbl_size = ARRAY_SIZE(msm8916_reg_preset), 532 .clks = { "core", "iface", "bus", }, 533 .clks_num = 3, 534 .max_load = 352800, /* 720p@30 + 1080p@30 */ 535 .hfi_version = HFI_VERSION_1XX, 536 .vmem_id = VIDC_RESOURCE_NONE, 537 .vmem_size = 0, 538 .vmem_addr = 0, 539 .dma_mask = 0xddc00000 - 1, 540 .fwname = "qcom/venus-1.8/venus.mdt", 541 }; 542 543 static const struct freq_tbl msm8996_freq_table[] = { 544 { 1944000, 520000000 }, /* 4k UHD @ 60 (decode only) */ 545 { 972000, 520000000 }, /* 4k UHD @ 30 */ 546 { 489600, 346666667 }, /* 1080p @ 60 */ 547 { 244800, 150000000 }, /* 1080p @ 30 */ 548 { 108000, 75000000 }, /* 720p @ 30 */ 549 }; 550 551 static const struct reg_val msm8996_reg_preset[] = { 552 { 0x80010, 0xffffffff }, 553 { 0x80018, 0x00001556 }, 554 { 0x8001C, 0x00001556 }, 555 }; 556 557 static const struct venus_resources msm8996_res = { 558 .freq_tbl = msm8996_freq_table, 559 .freq_tbl_size = ARRAY_SIZE(msm8996_freq_table), 560 .reg_tbl = msm8996_reg_preset, 561 .reg_tbl_size = ARRAY_SIZE(msm8996_reg_preset), 562 .clks = {"core", "iface", "bus", "mbus" }, 563 .clks_num = 4, 564 .vcodec0_clks = { "core" }, 565 .vcodec1_clks = { "core" }, 566 .vcodec_clks_num = 1, 567 .max_load = 2563200, 568 .hfi_version = HFI_VERSION_3XX, 569 .vmem_id = VIDC_RESOURCE_NONE, 570 .vmem_size = 0, 571 .vmem_addr = 0, 572 .dma_mask = 0xddc00000 - 1, 573 .fwname = "qcom/venus-4.2/venus.mdt", 574 }; 575 576 static const struct freq_tbl sdm660_freq_table[] = { 577 { 979200, 518400000 }, 578 { 489600, 441600000 }, 579 { 432000, 404000000 }, 580 { 244800, 320000000 }, 581 { 216000, 269330000 }, 582 { 108000, 133330000 }, 583 }; 584 585 static const struct reg_val sdm660_reg_preset[] = { 586 { 0x80010, 0x001f001f }, 587 { 0x80018, 0x00000156 }, 588 { 0x8001c, 0x00000156 }, 589 }; 590 591 static const struct bw_tbl sdm660_bw_table_enc[] = { 592 { 979200, 1044000, 0, 2446336, 0 }, /* 4k UHD @ 30 */ 593 { 864000, 887000, 0, 2108416, 0 }, /* 720p @ 240 */ 594 { 489600, 666000, 0, 1207296, 0 }, /* 1080p @ 60 */ 595 { 432000, 578000, 0, 1058816, 0 }, /* 720p @ 120 */ 596 { 244800, 346000, 0, 616448, 0 }, /* 1080p @ 30 */ 597 { 216000, 293000, 0, 534528, 0 }, /* 720p @ 60 */ 598 { 108000, 151000, 0, 271360, 0 }, /* 720p @ 30 */ 599 }; 600 601 static const struct bw_tbl sdm660_bw_table_dec[] = { 602 { 979200, 2365000, 0, 1892000, 0 }, /* 4k UHD @ 30 */ 603 { 864000, 1978000, 0, 1554000, 0 }, /* 720p @ 240 */ 604 { 489600, 1133000, 0, 895000, 0 }, /* 1080p @ 60 */ 605 { 432000, 994000, 0, 781000, 0 }, /* 720p @ 120 */ 606 { 244800, 580000, 0, 460000, 0 }, /* 1080p @ 30 */ 607 { 216000, 501000, 0, 301000, 0 }, /* 720p @ 60 */ 608 { 108000, 255000, 0, 202000, 0 }, /* 720p @ 30 */ 609 }; 610 611 static const struct venus_resources sdm660_res = { 612 .freq_tbl = sdm660_freq_table, 613 .freq_tbl_size = ARRAY_SIZE(sdm660_freq_table), 614 .reg_tbl = sdm660_reg_preset, 615 .reg_tbl_size = ARRAY_SIZE(sdm660_reg_preset), 616 .bw_tbl_enc = sdm660_bw_table_enc, 617 .bw_tbl_enc_size = ARRAY_SIZE(sdm660_bw_table_enc), 618 .bw_tbl_dec = sdm660_bw_table_dec, 619 .bw_tbl_dec_size = ARRAY_SIZE(sdm660_bw_table_dec), 620 .clks = {"core", "iface", "bus", "bus_throttle" }, 621 .clks_num = 4, 622 .vcodec0_clks = { "vcodec0_core" }, 623 .vcodec1_clks = { "vcodec0_core" }, 624 .vcodec_clks_num = 1, 625 .vcodec_num = 1, 626 .max_load = 1036800, 627 .hfi_version = HFI_VERSION_3XX, 628 .vmem_id = VIDC_RESOURCE_NONE, 629 .vmem_size = 0, 630 .vmem_addr = 0, 631 .cp_start = 0, 632 .cp_size = 0x79000000, 633 .cp_nonpixel_start = 0x1000000, 634 .cp_nonpixel_size = 0x28000000, 635 .dma_mask = 0xd9000000 - 1, 636 .fwname = "qcom/venus-4.4/venus.mdt", 637 }; 638 639 static const struct freq_tbl sdm845_freq_table[] = { 640 { 3110400, 533000000 }, /* 4096x2160@90 */ 641 { 2073600, 444000000 }, /* 4096x2160@60 */ 642 { 1944000, 404000000 }, /* 3840x2160@60 */ 643 { 972000, 330000000 }, /* 3840x2160@30 */ 644 { 489600, 200000000 }, /* 1920x1080@60 */ 645 { 244800, 100000000 }, /* 1920x1080@30 */ 646 }; 647 648 static const struct bw_tbl sdm845_bw_table_enc[] = { 649 { 1944000, 1612000, 0, 2416000, 0 }, /* 3840x2160@60 */ 650 { 972000, 951000, 0, 1434000, 0 }, /* 3840x2160@30 */ 651 { 489600, 723000, 0, 973000, 0 }, /* 1920x1080@60 */ 652 { 244800, 370000, 0, 495000, 0 }, /* 1920x1080@30 */ 653 }; 654 655 static const struct bw_tbl sdm845_bw_table_dec[] = { 656 { 2073600, 3929000, 0, 5551000, 0 }, /* 4096x2160@60 */ 657 { 1036800, 1987000, 0, 2797000, 0 }, /* 4096x2160@30 */ 658 { 489600, 1040000, 0, 1298000, 0 }, /* 1920x1080@60 */ 659 { 244800, 530000, 0, 659000, 0 }, /* 1920x1080@30 */ 660 }; 661 662 static const struct venus_resources sdm845_res = { 663 .freq_tbl = sdm845_freq_table, 664 .freq_tbl_size = ARRAY_SIZE(sdm845_freq_table), 665 .bw_tbl_enc = sdm845_bw_table_enc, 666 .bw_tbl_enc_size = ARRAY_SIZE(sdm845_bw_table_enc), 667 .bw_tbl_dec = sdm845_bw_table_dec, 668 .bw_tbl_dec_size = ARRAY_SIZE(sdm845_bw_table_dec), 669 .clks = {"core", "iface", "bus" }, 670 .clks_num = 3, 671 .vcodec0_clks = { "core", "bus" }, 672 .vcodec1_clks = { "core", "bus" }, 673 .vcodec_clks_num = 2, 674 .max_load = 3110400, /* 4096x2160@90 */ 675 .hfi_version = HFI_VERSION_4XX, 676 .vmem_id = VIDC_RESOURCE_NONE, 677 .vmem_size = 0, 678 .vmem_addr = 0, 679 .dma_mask = 0xe0000000 - 1, 680 .fwname = "qcom/venus-5.2/venus.mdt", 681 }; 682 683 static const struct venus_resources sdm845_res_v2 = { 684 .freq_tbl = sdm845_freq_table, 685 .freq_tbl_size = ARRAY_SIZE(sdm845_freq_table), 686 .bw_tbl_enc = sdm845_bw_table_enc, 687 .bw_tbl_enc_size = ARRAY_SIZE(sdm845_bw_table_enc), 688 .bw_tbl_dec = sdm845_bw_table_dec, 689 .bw_tbl_dec_size = ARRAY_SIZE(sdm845_bw_table_dec), 690 .clks = {"core", "iface", "bus" }, 691 .clks_num = 3, 692 .vcodec0_clks = { "vcodec0_core", "vcodec0_bus" }, 693 .vcodec1_clks = { "vcodec1_core", "vcodec1_bus" }, 694 .vcodec_clks_num = 2, 695 .vcodec_pmdomains = { "venus", "vcodec0", "vcodec1" }, 696 .vcodec_pmdomains_num = 3, 697 .opp_pmdomain = (const char *[]) { "cx", NULL }, 698 .vcodec_num = 2, 699 .max_load = 3110400, /* 4096x2160@90 */ 700 .hfi_version = HFI_VERSION_4XX, 701 .vmem_id = VIDC_RESOURCE_NONE, 702 .vmem_size = 0, 703 .vmem_addr = 0, 704 .dma_mask = 0xe0000000 - 1, 705 .cp_start = 0, 706 .cp_size = 0x70800000, 707 .cp_nonpixel_start = 0x1000000, 708 .cp_nonpixel_size = 0x24800000, 709 .fwname = "qcom/venus-5.2/venus.mdt", 710 }; 711 712 static const struct freq_tbl sc7180_freq_table[] = { 713 { 0, 500000000 }, 714 { 0, 434000000 }, 715 { 0, 340000000 }, 716 { 0, 270000000 }, 717 { 0, 150000000 }, 718 }; 719 720 static const struct bw_tbl sc7180_bw_table_enc[] = { 721 { 972000, 750000, 0, 0, 0 }, /* 3840x2160@30 */ 722 { 489600, 451000, 0, 0, 0 }, /* 1920x1080@60 */ 723 { 244800, 234000, 0, 0, 0 }, /* 1920x1080@30 */ 724 }; 725 726 static const struct bw_tbl sc7180_bw_table_dec[] = { 727 { 1036800, 1386000, 0, 1875000, 0 }, /* 4096x2160@30 */ 728 { 489600, 865000, 0, 1146000, 0 }, /* 1920x1080@60 */ 729 { 244800, 530000, 0, 583000, 0 }, /* 1920x1080@30 */ 730 }; 731 732 static const struct venus_resources sc7180_res = { 733 .freq_tbl = sc7180_freq_table, 734 .freq_tbl_size = ARRAY_SIZE(sc7180_freq_table), 735 .bw_tbl_enc = sc7180_bw_table_enc, 736 .bw_tbl_enc_size = ARRAY_SIZE(sc7180_bw_table_enc), 737 .bw_tbl_dec = sc7180_bw_table_dec, 738 .bw_tbl_dec_size = ARRAY_SIZE(sc7180_bw_table_dec), 739 .clks = {"core", "iface", "bus" }, 740 .clks_num = 3, 741 .vcodec0_clks = { "vcodec0_core", "vcodec0_bus" }, 742 .vcodec_clks_num = 2, 743 .vcodec_pmdomains = { "venus", "vcodec0" }, 744 .vcodec_pmdomains_num = 2, 745 .opp_pmdomain = (const char *[]) { "cx", NULL }, 746 .vcodec_num = 1, 747 .hfi_version = HFI_VERSION_4XX, 748 .vmem_id = VIDC_RESOURCE_NONE, 749 .vmem_size = 0, 750 .vmem_addr = 0, 751 .dma_mask = 0xe0000000 - 1, 752 .fwname = "qcom/venus-5.4/venus.mdt", 753 }; 754 755 static const struct freq_tbl sm8250_freq_table[] = { 756 { 0, 444000000 }, 757 { 0, 366000000 }, 758 { 0, 338000000 }, 759 { 0, 240000000 }, 760 }; 761 762 static const struct bw_tbl sm8250_bw_table_enc[] = { 763 { 1944000, 1954000, 0, 3711000, 0 }, /* 3840x2160@60 */ 764 { 972000, 996000, 0, 1905000, 0 }, /* 3840x2160@30 */ 765 { 489600, 645000, 0, 977000, 0 }, /* 1920x1080@60 */ 766 { 244800, 332000, 0, 498000, 0 }, /* 1920x1080@30 */ 767 }; 768 769 static const struct bw_tbl sm8250_bw_table_dec[] = { 770 { 2073600, 2403000, 0, 4113000, 0 }, /* 4096x2160@60 */ 771 { 1036800, 1224000, 0, 2079000, 0 }, /* 4096x2160@30 */ 772 { 489600, 812000, 0, 998000, 0 }, /* 1920x1080@60 */ 773 { 244800, 416000, 0, 509000, 0 }, /* 1920x1080@30 */ 774 }; 775 776 static const struct reg_val sm8250_reg_preset[] = { 777 { 0xb0088, 0 }, 778 }; 779 780 static const struct venus_resources sm8250_res = { 781 .freq_tbl = sm8250_freq_table, 782 .freq_tbl_size = ARRAY_SIZE(sm8250_freq_table), 783 .reg_tbl = sm8250_reg_preset, 784 .reg_tbl_size = ARRAY_SIZE(sm8250_reg_preset), 785 .bw_tbl_enc = sm8250_bw_table_enc, 786 .bw_tbl_enc_size = ARRAY_SIZE(sm8250_bw_table_enc), 787 .bw_tbl_dec = sm8250_bw_table_dec, 788 .bw_tbl_dec_size = ARRAY_SIZE(sm8250_bw_table_dec), 789 .clks = {"core", "iface"}, 790 .clks_num = 2, 791 .resets = { "bus", "core" }, 792 .resets_num = 2, 793 .vcodec0_clks = { "vcodec0_core" }, 794 .vcodec_clks_num = 1, 795 .vcodec_pmdomains = { "venus", "vcodec0" }, 796 .vcodec_pmdomains_num = 2, 797 .opp_pmdomain = (const char *[]) { "mx", NULL }, 798 .vcodec_num = 1, 799 .max_load = 7833600, 800 .hfi_version = HFI_VERSION_6XX, 801 .num_vpp_pipes = 4, 802 .vmem_id = VIDC_RESOURCE_NONE, 803 .vmem_size = 0, 804 .vmem_addr = 0, 805 .dma_mask = 0xe0000000 - 1, 806 .fwname = "qcom/vpu-1.0/venus.mdt", 807 }; 808 809 static const struct freq_tbl sc7280_freq_table[] = { 810 { 0, 460000000 }, 811 { 0, 424000000 }, 812 { 0, 335000000 }, 813 { 0, 240000000 }, 814 { 0, 133333333 }, 815 }; 816 817 static const struct bw_tbl sc7280_bw_table_enc[] = { 818 { 1944000, 1896000, 0, 3657000, 0 }, /* 3840x2160@60 */ 819 { 972000, 968000, 0, 1848000, 0 }, /* 3840x2160@30 */ 820 { 489600, 618000, 0, 941000, 0 }, /* 1920x1080@60 */ 821 { 244800, 318000, 0, 480000, 0 }, /* 1920x1080@30 */ 822 }; 823 824 static const struct bw_tbl sc7280_bw_table_dec[] = { 825 { 2073600, 2128000, 0, 3831000, 0 }, /* 4096x2160@60 */ 826 { 1036800, 1085000, 0, 1937000, 0 }, /* 4096x2160@30 */ 827 { 489600, 779000, 0, 998000, 0 }, /* 1920x1080@60 */ 828 { 244800, 400000, 0, 509000, 0 }, /* 1920x1080@30 */ 829 }; 830 831 static const struct reg_val sm7280_reg_preset[] = { 832 { 0xb0088, 0 }, 833 }; 834 835 static const struct venus_resources sc7280_res = { 836 .freq_tbl = sc7280_freq_table, 837 .freq_tbl_size = ARRAY_SIZE(sc7280_freq_table), 838 .reg_tbl = sm7280_reg_preset, 839 .reg_tbl_size = ARRAY_SIZE(sm7280_reg_preset), 840 .bw_tbl_enc = sc7280_bw_table_enc, 841 .bw_tbl_enc_size = ARRAY_SIZE(sc7280_bw_table_enc), 842 .bw_tbl_dec = sc7280_bw_table_dec, 843 .bw_tbl_dec_size = ARRAY_SIZE(sc7280_bw_table_dec), 844 .clks = {"core", "bus", "iface"}, 845 .clks_num = 3, 846 .vcodec0_clks = {"vcodec_core", "vcodec_bus"}, 847 .vcodec_clks_num = 2, 848 .vcodec_pmdomains = { "venus", "vcodec0" }, 849 .vcodec_pmdomains_num = 2, 850 .opp_pmdomain = (const char *[]) { "cx", NULL }, 851 .vcodec_num = 1, 852 .hfi_version = HFI_VERSION_6XX, 853 .num_vpp_pipes = 1, 854 .vmem_id = VIDC_RESOURCE_NONE, 855 .vmem_size = 0, 856 .vmem_addr = 0, 857 .dma_mask = 0xe0000000 - 1, 858 .fwname = "qcom/vpu-2.0/venus.mbn", 859 }; 860 861 static const struct of_device_id venus_dt_match[] = { 862 { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, 863 { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, 864 { .compatible = "qcom,sdm660-venus", .data = &sdm660_res, }, 865 { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, 866 { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, 867 { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, 868 { .compatible = "qcom,sc7280-venus", .data = &sc7280_res, }, 869 { .compatible = "qcom,sm8250-venus", .data = &sm8250_res, }, 870 { } 871 }; 872 MODULE_DEVICE_TABLE(of, venus_dt_match); 873 874 static struct platform_driver qcom_venus_driver = { 875 .probe = venus_probe, 876 .remove = venus_remove, 877 .driver = { 878 .name = "qcom-venus", 879 .of_match_table = venus_dt_match, 880 .pm = &venus_pm_ops, 881 }, 882 .shutdown = venus_core_shutdown, 883 }; 884 module_platform_driver(qcom_venus_driver); 885 886 MODULE_ALIAS("platform:qcom-venus"); 887 MODULE_DESCRIPTION("Qualcomm Venus video encoder and decoder driver"); 888 MODULE_LICENSE("GPL v2"); 889