1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2017 Linaro Ltd. 5 */ 6 #include <linux/init.h> 7 #include <linux/interconnect.h> 8 #include <linux/ioctl.h> 9 #include <linux/delay.h> 10 #include <linux/list.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/slab.h> 15 #include <linux/types.h> 16 #include <linux/pm_runtime.h> 17 #include <media/videobuf2-v4l2.h> 18 #include <media/v4l2-mem2mem.h> 19 #include <media/v4l2-ioctl.h> 20 21 #include "core.h" 22 #include "firmware.h" 23 #include "pm_helpers.h" 24 25 static void venus_event_notify(struct venus_core *core, u32 event) 26 { 27 struct venus_inst *inst; 28 29 switch (event) { 30 case EVT_SYS_WATCHDOG_TIMEOUT: 31 case EVT_SYS_ERROR: 32 break; 33 default: 34 return; 35 } 36 37 mutex_lock(&core->lock); 38 core->sys_error = true; 39 list_for_each_entry(inst, &core->instances, list) 40 inst->ops->event_notify(inst, EVT_SESSION_ERROR, NULL); 41 mutex_unlock(&core->lock); 42 43 disable_irq_nosync(core->irq); 44 schedule_delayed_work(&core->work, msecs_to_jiffies(10)); 45 } 46 47 static const struct hfi_core_ops venus_core_ops = { 48 .event_notify = venus_event_notify, 49 }; 50 51 static void venus_sys_error_handler(struct work_struct *work) 52 { 53 struct venus_core *core = 54 container_of(work, struct venus_core, work.work); 55 int ret = 0; 56 57 pm_runtime_get_sync(core->dev); 58 59 hfi_core_deinit(core, true); 60 61 dev_warn(core->dev, "system error has occurred, starting recovery!\n"); 62 63 mutex_lock(&core->lock); 64 65 while (pm_runtime_active(core->dev_dec) || pm_runtime_active(core->dev_enc)) 66 msleep(10); 67 68 venus_shutdown(core); 69 70 pm_runtime_put_sync(core->dev); 71 72 while (core->pmdomains[0] && pm_runtime_active(core->pmdomains[0])) 73 usleep_range(1000, 1500); 74 75 hfi_reinit(core); 76 77 pm_runtime_get_sync(core->dev); 78 79 ret |= venus_boot(core); 80 ret |= hfi_core_resume(core, true); 81 82 enable_irq(core->irq); 83 84 mutex_unlock(&core->lock); 85 86 ret |= hfi_core_init(core); 87 88 pm_runtime_put_sync(core->dev); 89 90 if (ret) { 91 disable_irq_nosync(core->irq); 92 dev_warn(core->dev, "recovery failed (%d)\n", ret); 93 schedule_delayed_work(&core->work, msecs_to_jiffies(10)); 94 return; 95 } 96 97 mutex_lock(&core->lock); 98 core->sys_error = false; 99 mutex_unlock(&core->lock); 100 } 101 102 static u32 to_v4l2_codec_type(u32 codec) 103 { 104 switch (codec) { 105 case HFI_VIDEO_CODEC_H264: 106 return V4L2_PIX_FMT_H264; 107 case HFI_VIDEO_CODEC_H263: 108 return V4L2_PIX_FMT_H263; 109 case HFI_VIDEO_CODEC_MPEG1: 110 return V4L2_PIX_FMT_MPEG1; 111 case HFI_VIDEO_CODEC_MPEG2: 112 return V4L2_PIX_FMT_MPEG2; 113 case HFI_VIDEO_CODEC_MPEG4: 114 return V4L2_PIX_FMT_MPEG4; 115 case HFI_VIDEO_CODEC_VC1: 116 return V4L2_PIX_FMT_VC1_ANNEX_G; 117 case HFI_VIDEO_CODEC_VP8: 118 return V4L2_PIX_FMT_VP8; 119 case HFI_VIDEO_CODEC_VP9: 120 return V4L2_PIX_FMT_VP9; 121 case HFI_VIDEO_CODEC_DIVX: 122 case HFI_VIDEO_CODEC_DIVX_311: 123 return V4L2_PIX_FMT_XVID; 124 default: 125 return 0; 126 } 127 } 128 129 static int venus_enumerate_codecs(struct venus_core *core, u32 type) 130 { 131 const struct hfi_inst_ops dummy_ops = {}; 132 struct venus_inst *inst; 133 u32 codec, codecs; 134 unsigned int i; 135 int ret; 136 137 if (core->res->hfi_version != HFI_VERSION_1XX) 138 return 0; 139 140 inst = kzalloc(sizeof(*inst), GFP_KERNEL); 141 if (!inst) 142 return -ENOMEM; 143 144 mutex_init(&inst->lock); 145 inst->core = core; 146 inst->session_type = type; 147 if (type == VIDC_SESSION_TYPE_DEC) 148 codecs = core->dec_codecs; 149 else 150 codecs = core->enc_codecs; 151 152 ret = hfi_session_create(inst, &dummy_ops); 153 if (ret) 154 goto err; 155 156 for (i = 0; i < MAX_CODEC_NUM; i++) { 157 codec = (1UL << i) & codecs; 158 if (!codec) 159 continue; 160 161 ret = hfi_session_init(inst, to_v4l2_codec_type(codec)); 162 if (ret) 163 goto done; 164 165 ret = hfi_session_deinit(inst); 166 if (ret) 167 goto done; 168 } 169 170 done: 171 hfi_session_destroy(inst); 172 err: 173 mutex_destroy(&inst->lock); 174 kfree(inst); 175 176 return ret; 177 } 178 179 static int venus_probe(struct platform_device *pdev) 180 { 181 struct device *dev = &pdev->dev; 182 struct venus_core *core; 183 struct resource *r; 184 int ret; 185 186 core = devm_kzalloc(dev, sizeof(*core), GFP_KERNEL); 187 if (!core) 188 return -ENOMEM; 189 190 core->dev = dev; 191 platform_set_drvdata(pdev, core); 192 193 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 194 core->base = devm_ioremap_resource(dev, r); 195 if (IS_ERR(core->base)) 196 return PTR_ERR(core->base); 197 198 core->video_path = of_icc_get(dev, "video-mem"); 199 if (IS_ERR(core->video_path)) 200 return PTR_ERR(core->video_path); 201 202 core->cpucfg_path = of_icc_get(dev, "cpu-cfg"); 203 if (IS_ERR(core->cpucfg_path)) 204 return PTR_ERR(core->cpucfg_path); 205 206 core->irq = platform_get_irq(pdev, 0); 207 if (core->irq < 0) 208 return core->irq; 209 210 core->res = of_device_get_match_data(dev); 211 if (!core->res) 212 return -ENODEV; 213 214 mutex_init(&core->pm_lock); 215 216 core->pm_ops = venus_pm_get(core->res->hfi_version); 217 if (!core->pm_ops) 218 return -ENODEV; 219 220 if (core->pm_ops->core_get) { 221 ret = core->pm_ops->core_get(dev); 222 if (ret) 223 return ret; 224 } 225 226 ret = dma_set_mask_and_coherent(dev, core->res->dma_mask); 227 if (ret) 228 goto err_core_put; 229 230 dma_set_max_seg_size(dev, UINT_MAX); 231 232 INIT_LIST_HEAD(&core->instances); 233 mutex_init(&core->lock); 234 INIT_DELAYED_WORK(&core->work, venus_sys_error_handler); 235 236 ret = devm_request_threaded_irq(dev, core->irq, hfi_isr, hfi_isr_thread, 237 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 238 "venus", core); 239 if (ret) 240 goto err_core_put; 241 242 ret = hfi_create(core, &venus_core_ops); 243 if (ret) 244 goto err_core_put; 245 246 pm_runtime_enable(dev); 247 248 ret = pm_runtime_get_sync(dev); 249 if (ret < 0) 250 goto err_runtime_disable; 251 252 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 253 if (ret) 254 goto err_runtime_disable; 255 256 ret = venus_firmware_init(core); 257 if (ret) 258 goto err_runtime_disable; 259 260 ret = venus_boot(core); 261 if (ret) 262 goto err_runtime_disable; 263 264 ret = hfi_core_resume(core, true); 265 if (ret) 266 goto err_venus_shutdown; 267 268 ret = hfi_core_init(core); 269 if (ret) 270 goto err_venus_shutdown; 271 272 ret = venus_enumerate_codecs(core, VIDC_SESSION_TYPE_DEC); 273 if (ret) 274 goto err_venus_shutdown; 275 276 ret = venus_enumerate_codecs(core, VIDC_SESSION_TYPE_ENC); 277 if (ret) 278 goto err_venus_shutdown; 279 280 ret = v4l2_device_register(dev, &core->v4l2_dev); 281 if (ret) 282 goto err_core_deinit; 283 284 ret = pm_runtime_put_sync(dev); 285 if (ret) { 286 pm_runtime_get_noresume(dev); 287 goto err_dev_unregister; 288 } 289 290 venus_dbgfs_init(core); 291 292 return 0; 293 294 err_dev_unregister: 295 v4l2_device_unregister(&core->v4l2_dev); 296 err_core_deinit: 297 hfi_core_deinit(core, false); 298 err_venus_shutdown: 299 venus_shutdown(core); 300 err_runtime_disable: 301 pm_runtime_put_noidle(dev); 302 pm_runtime_set_suspended(dev); 303 pm_runtime_disable(dev); 304 hfi_destroy(core); 305 err_core_put: 306 if (core->pm_ops->core_put) 307 core->pm_ops->core_put(dev); 308 return ret; 309 } 310 311 static int venus_remove(struct platform_device *pdev) 312 { 313 struct venus_core *core = platform_get_drvdata(pdev); 314 const struct venus_pm_ops *pm_ops = core->pm_ops; 315 struct device *dev = core->dev; 316 int ret; 317 318 ret = pm_runtime_get_sync(dev); 319 WARN_ON(ret < 0); 320 321 ret = hfi_core_deinit(core, true); 322 WARN_ON(ret); 323 324 venus_shutdown(core); 325 of_platform_depopulate(dev); 326 327 venus_firmware_deinit(core); 328 329 pm_runtime_put_sync(dev); 330 pm_runtime_disable(dev); 331 332 if (pm_ops->core_put) 333 pm_ops->core_put(dev); 334 335 hfi_destroy(core); 336 337 icc_put(core->video_path); 338 icc_put(core->cpucfg_path); 339 340 v4l2_device_unregister(&core->v4l2_dev); 341 mutex_destroy(&core->pm_lock); 342 mutex_destroy(&core->lock); 343 venus_dbgfs_deinit(core); 344 345 return ret; 346 } 347 348 static __maybe_unused int venus_runtime_suspend(struct device *dev) 349 { 350 struct venus_core *core = dev_get_drvdata(dev); 351 const struct venus_pm_ops *pm_ops = core->pm_ops; 352 int ret; 353 354 ret = hfi_core_suspend(core); 355 if (ret) 356 return ret; 357 358 ret = icc_set_bw(core->cpucfg_path, 0, 0); 359 if (ret) 360 return ret; 361 362 if (pm_ops->core_power) 363 ret = pm_ops->core_power(dev, POWER_OFF); 364 365 return ret; 366 } 367 368 static __maybe_unused int venus_runtime_resume(struct device *dev) 369 { 370 struct venus_core *core = dev_get_drvdata(dev); 371 const struct venus_pm_ops *pm_ops = core->pm_ops; 372 int ret; 373 374 if (pm_ops->core_power) { 375 ret = pm_ops->core_power(dev, POWER_ON); 376 if (ret) 377 return ret; 378 } 379 380 ret = icc_set_bw(core->cpucfg_path, 0, kbps_to_icc(1000)); 381 if (ret) 382 return ret; 383 384 return hfi_core_resume(core, false); 385 } 386 387 static const struct dev_pm_ops venus_pm_ops = { 388 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 389 pm_runtime_force_resume) 390 SET_RUNTIME_PM_OPS(venus_runtime_suspend, venus_runtime_resume, NULL) 391 }; 392 393 static const struct freq_tbl msm8916_freq_table[] = { 394 { 352800, 228570000 }, /* 1920x1088 @ 30 + 1280x720 @ 30 */ 395 { 244800, 160000000 }, /* 1920x1088 @ 30 */ 396 { 108000, 100000000 }, /* 1280x720 @ 30 */ 397 }; 398 399 static const struct reg_val msm8916_reg_preset[] = { 400 { 0xe0020, 0x05555556 }, 401 { 0xe0024, 0x05555556 }, 402 { 0x80124, 0x00000003 }, 403 }; 404 405 static const struct venus_resources msm8916_res = { 406 .freq_tbl = msm8916_freq_table, 407 .freq_tbl_size = ARRAY_SIZE(msm8916_freq_table), 408 .reg_tbl = msm8916_reg_preset, 409 .reg_tbl_size = ARRAY_SIZE(msm8916_reg_preset), 410 .clks = { "core", "iface", "bus", }, 411 .clks_num = 3, 412 .max_load = 352800, /* 720p@30 + 1080p@30 */ 413 .hfi_version = HFI_VERSION_1XX, 414 .vmem_id = VIDC_RESOURCE_NONE, 415 .vmem_size = 0, 416 .vmem_addr = 0, 417 .dma_mask = 0xddc00000 - 1, 418 .fwname = "qcom/venus-1.8/venus.mdt", 419 }; 420 421 static const struct freq_tbl msm8996_freq_table[] = { 422 { 1944000, 520000000 }, /* 4k UHD @ 60 (decode only) */ 423 { 972000, 520000000 }, /* 4k UHD @ 30 */ 424 { 489600, 346666667 }, /* 1080p @ 60 */ 425 { 244800, 150000000 }, /* 1080p @ 30 */ 426 { 108000, 75000000 }, /* 720p @ 30 */ 427 }; 428 429 static const struct reg_val msm8996_reg_preset[] = { 430 { 0x80010, 0xffffffff }, 431 { 0x80018, 0x00001556 }, 432 { 0x8001C, 0x00001556 }, 433 }; 434 435 static const struct venus_resources msm8996_res = { 436 .freq_tbl = msm8996_freq_table, 437 .freq_tbl_size = ARRAY_SIZE(msm8996_freq_table), 438 .reg_tbl = msm8996_reg_preset, 439 .reg_tbl_size = ARRAY_SIZE(msm8996_reg_preset), 440 .clks = {"core", "iface", "bus", "mbus" }, 441 .clks_num = 4, 442 .vcodec0_clks = { "core" }, 443 .vcodec1_clks = { "core" }, 444 .vcodec_clks_num = 1, 445 .max_load = 2563200, 446 .hfi_version = HFI_VERSION_3XX, 447 .vmem_id = VIDC_RESOURCE_NONE, 448 .vmem_size = 0, 449 .vmem_addr = 0, 450 .dma_mask = 0xddc00000 - 1, 451 .fwname = "qcom/venus-4.2/venus.mdt", 452 }; 453 454 static const struct freq_tbl sdm845_freq_table[] = { 455 { 3110400, 533000000 }, /* 4096x2160@90 */ 456 { 2073600, 444000000 }, /* 4096x2160@60 */ 457 { 1944000, 404000000 }, /* 3840x2160@60 */ 458 { 972000, 330000000 }, /* 3840x2160@30 */ 459 { 489600, 200000000 }, /* 1920x1080@60 */ 460 { 244800, 100000000 }, /* 1920x1080@30 */ 461 }; 462 463 static const struct codec_freq_data sdm845_codec_freq_data[] = { 464 { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_ENC, 675, 10 }, 465 { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_ENC, 675, 10 }, 466 { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_ENC, 675, 10 }, 467 { V4L2_PIX_FMT_MPEG2, VIDC_SESSION_TYPE_DEC, 200, 10 }, 468 { V4L2_PIX_FMT_H264, VIDC_SESSION_TYPE_DEC, 200, 10 }, 469 { V4L2_PIX_FMT_HEVC, VIDC_SESSION_TYPE_DEC, 200, 10 }, 470 { V4L2_PIX_FMT_VP8, VIDC_SESSION_TYPE_DEC, 200, 10 }, 471 { V4L2_PIX_FMT_VP9, VIDC_SESSION_TYPE_DEC, 200, 10 }, 472 }; 473 474 static const struct bw_tbl sdm845_bw_table_enc[] = { 475 { 1944000, 1612000, 0, 2416000, 0 }, /* 3840x2160@60 */ 476 { 972000, 951000, 0, 1434000, 0 }, /* 3840x2160@30 */ 477 { 489600, 723000, 0, 973000, 0 }, /* 1920x1080@60 */ 478 { 244800, 370000, 0, 495000, 0 }, /* 1920x1080@30 */ 479 }; 480 481 static const struct bw_tbl sdm845_bw_table_dec[] = { 482 { 2073600, 3929000, 0, 5551000, 0 }, /* 4096x2160@60 */ 483 { 1036800, 1987000, 0, 2797000, 0 }, /* 4096x2160@30 */ 484 { 489600, 1040000, 0, 1298000, 0 }, /* 1920x1080@60 */ 485 { 244800, 530000, 0, 659000, 0 }, /* 1920x1080@30 */ 486 }; 487 488 static const struct venus_resources sdm845_res = { 489 .freq_tbl = sdm845_freq_table, 490 .freq_tbl_size = ARRAY_SIZE(sdm845_freq_table), 491 .bw_tbl_enc = sdm845_bw_table_enc, 492 .bw_tbl_enc_size = ARRAY_SIZE(sdm845_bw_table_enc), 493 .bw_tbl_dec = sdm845_bw_table_dec, 494 .bw_tbl_dec_size = ARRAY_SIZE(sdm845_bw_table_dec), 495 .codec_freq_data = sdm845_codec_freq_data, 496 .codec_freq_data_size = ARRAY_SIZE(sdm845_codec_freq_data), 497 .clks = {"core", "iface", "bus" }, 498 .clks_num = 3, 499 .vcodec0_clks = { "core", "bus" }, 500 .vcodec1_clks = { "core", "bus" }, 501 .vcodec_clks_num = 2, 502 .max_load = 3110400, /* 4096x2160@90 */ 503 .hfi_version = HFI_VERSION_4XX, 504 .vmem_id = VIDC_RESOURCE_NONE, 505 .vmem_size = 0, 506 .vmem_addr = 0, 507 .dma_mask = 0xe0000000 - 1, 508 .fwname = "qcom/venus-5.2/venus.mdt", 509 }; 510 511 static const struct venus_resources sdm845_res_v2 = { 512 .freq_tbl = sdm845_freq_table, 513 .freq_tbl_size = ARRAY_SIZE(sdm845_freq_table), 514 .bw_tbl_enc = sdm845_bw_table_enc, 515 .bw_tbl_enc_size = ARRAY_SIZE(sdm845_bw_table_enc), 516 .bw_tbl_dec = sdm845_bw_table_dec, 517 .bw_tbl_dec_size = ARRAY_SIZE(sdm845_bw_table_dec), 518 .codec_freq_data = sdm845_codec_freq_data, 519 .codec_freq_data_size = ARRAY_SIZE(sdm845_codec_freq_data), 520 .clks = {"core", "iface", "bus" }, 521 .clks_num = 3, 522 .vcodec0_clks = { "vcodec0_core", "vcodec0_bus" }, 523 .vcodec1_clks = { "vcodec1_core", "vcodec1_bus" }, 524 .vcodec_clks_num = 2, 525 .vcodec_pmdomains = { "venus", "vcodec0", "vcodec1" }, 526 .vcodec_pmdomains_num = 3, 527 .opp_pmdomain = (const char *[]) { "cx", NULL }, 528 .vcodec_num = 2, 529 .max_load = 3110400, /* 4096x2160@90 */ 530 .hfi_version = HFI_VERSION_4XX, 531 .vmem_id = VIDC_RESOURCE_NONE, 532 .vmem_size = 0, 533 .vmem_addr = 0, 534 .dma_mask = 0xe0000000 - 1, 535 .cp_start = 0, 536 .cp_size = 0x70800000, 537 .cp_nonpixel_start = 0x1000000, 538 .cp_nonpixel_size = 0x24800000, 539 .fwname = "qcom/venus-5.2/venus.mdt", 540 }; 541 542 static const struct freq_tbl sc7180_freq_table[] = { 543 { 0, 500000000 }, 544 { 0, 434000000 }, 545 { 0, 340000000 }, 546 { 0, 270000000 }, 547 { 0, 150000000 }, 548 }; 549 550 static const struct bw_tbl sc7180_bw_table_enc[] = { 551 { 972000, 750000, 0, 0, 0 }, /* 3840x2160@30 */ 552 { 489600, 451000, 0, 0, 0 }, /* 1920x1080@60 */ 553 { 244800, 234000, 0, 0, 0 }, /* 1920x1080@30 */ 554 }; 555 556 static const struct bw_tbl sc7180_bw_table_dec[] = { 557 { 1036800, 1386000, 0, 1875000, 0 }, /* 4096x2160@30 */ 558 { 489600, 865000, 0, 1146000, 0 }, /* 1920x1080@60 */ 559 { 244800, 530000, 0, 583000, 0 }, /* 1920x1080@30 */ 560 }; 561 562 static const struct venus_resources sc7180_res = { 563 .freq_tbl = sc7180_freq_table, 564 .freq_tbl_size = ARRAY_SIZE(sc7180_freq_table), 565 .bw_tbl_enc = sc7180_bw_table_enc, 566 .bw_tbl_enc_size = ARRAY_SIZE(sc7180_bw_table_enc), 567 .bw_tbl_dec = sc7180_bw_table_dec, 568 .bw_tbl_dec_size = ARRAY_SIZE(sc7180_bw_table_dec), 569 .codec_freq_data = sdm845_codec_freq_data, 570 .codec_freq_data_size = ARRAY_SIZE(sdm845_codec_freq_data), 571 .clks = {"core", "iface", "bus" }, 572 .clks_num = 3, 573 .vcodec0_clks = { "vcodec0_core", "vcodec0_bus" }, 574 .vcodec_clks_num = 2, 575 .vcodec_pmdomains = { "venus", "vcodec0" }, 576 .vcodec_pmdomains_num = 2, 577 .opp_pmdomain = (const char *[]) { "cx", NULL }, 578 .vcodec_num = 1, 579 .hfi_version = HFI_VERSION_4XX, 580 .vmem_id = VIDC_RESOURCE_NONE, 581 .vmem_size = 0, 582 .vmem_addr = 0, 583 .dma_mask = 0xe0000000 - 1, 584 .fwname = "qcom/venus-5.4/venus.mdt", 585 }; 586 587 static const struct of_device_id venus_dt_match[] = { 588 { .compatible = "qcom,msm8916-venus", .data = &msm8916_res, }, 589 { .compatible = "qcom,msm8996-venus", .data = &msm8996_res, }, 590 { .compatible = "qcom,sdm845-venus", .data = &sdm845_res, }, 591 { .compatible = "qcom,sdm845-venus-v2", .data = &sdm845_res_v2, }, 592 { .compatible = "qcom,sc7180-venus", .data = &sc7180_res, }, 593 { } 594 }; 595 MODULE_DEVICE_TABLE(of, venus_dt_match); 596 597 static struct platform_driver qcom_venus_driver = { 598 .probe = venus_probe, 599 .remove = venus_remove, 600 .driver = { 601 .name = "qcom-venus", 602 .of_match_table = venus_dt_match, 603 .pm = &venus_pm_ops, 604 }, 605 }; 606 module_platform_driver(qcom_venus_driver); 607 608 MODULE_ALIAS("platform:qcom-venus"); 609 MODULE_DESCRIPTION("Qualcomm Venus video encoder and decoder driver"); 610 MODULE_LICENSE("GPL v2"); 611