1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss.c 4 * 5 * Qualcomm MSM Camera Subsystem - Core 6 * 7 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/media-bus-format.h> 12 #include <linux/media.h> 13 #include <linux/module.h> 14 #include <linux/platform_device.h> 15 #include <linux/of.h> 16 #include <linux/of_graph.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/pm_domain.h> 19 #include <linux/slab.h> 20 #include <linux/videodev2.h> 21 22 #include <media/media-device.h> 23 #include <media/v4l2-async.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-mc.h> 26 #include <media/v4l2-fwnode.h> 27 28 #include "camss.h" 29 30 #define CAMSS_CLOCK_MARGIN_NUMERATOR 105 31 #define CAMSS_CLOCK_MARGIN_DENOMINATOR 100 32 33 static const struct resources csiphy_res_8x16[] = { 34 /* CSIPHY0 */ 35 { 36 .regulator = { NULL }, 37 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 38 .clock_rate = { { 0 }, 39 { 0 }, 40 { 0 }, 41 { 100000000, 200000000 } }, 42 .reg = { "csiphy0", "csiphy0_clk_mux" }, 43 .interrupt = { "csiphy0" } 44 }, 45 46 /* CSIPHY1 */ 47 { 48 .regulator = { NULL }, 49 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 50 .clock_rate = { { 0 }, 51 { 0 }, 52 { 0 }, 53 { 100000000, 200000000 } }, 54 .reg = { "csiphy1", "csiphy1_clk_mux" }, 55 .interrupt = { "csiphy1" } 56 } 57 }; 58 59 static const struct resources csid_res_8x16[] = { 60 /* CSID0 */ 61 { 62 .regulator = { "vdda" }, 63 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 64 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 65 .clock_rate = { { 0 }, 66 { 0 }, 67 { 0 }, 68 { 0 }, 69 { 100000000, 200000000 }, 70 { 0 }, 71 { 0 }, 72 { 0 } }, 73 .reg = { "csid0" }, 74 .interrupt = { "csid0" } 75 }, 76 77 /* CSID1 */ 78 { 79 .regulator = { "vdda" }, 80 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 81 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 82 .clock_rate = { { 0 }, 83 { 0 }, 84 { 0 }, 85 { 0 }, 86 { 100000000, 200000000 }, 87 { 0 }, 88 { 0 }, 89 { 0 } }, 90 .reg = { "csid1" }, 91 .interrupt = { "csid1" } 92 }, 93 }; 94 95 static const struct resources_ispif ispif_res_8x16 = { 96 /* ISPIF */ 97 .clock = { "top_ahb", "ahb", "ispif_ahb", 98 "csi0", "csi0_pix", "csi0_rdi", 99 "csi1", "csi1_pix", "csi1_rdi" }, 100 .clock_for_reset = { "vfe0", "csi_vfe0" }, 101 .reg = { "ispif", "csi_clk_mux" }, 102 .interrupt = "ispif" 103 104 }; 105 106 static const struct resources vfe_res_8x16[] = { 107 /* VFE0 */ 108 { 109 .regulator = { NULL }, 110 .clock = { "top_ahb", "vfe0", "csi_vfe0", 111 "vfe_ahb", "vfe_axi", "ahb" }, 112 .clock_rate = { { 0 }, 113 { 50000000, 80000000, 100000000, 160000000, 114 177780000, 200000000, 266670000, 320000000, 115 400000000, 465000000 }, 116 { 0 }, 117 { 0 }, 118 { 0 }, 119 { 0 }, 120 { 0 }, 121 { 0 }, 122 { 0 } }, 123 .reg = { "vfe0" }, 124 .interrupt = { "vfe0" } 125 } 126 }; 127 128 static const struct resources csiphy_res_8x96[] = { 129 /* CSIPHY0 */ 130 { 131 .regulator = { NULL }, 132 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, 133 .clock_rate = { { 0 }, 134 { 0 }, 135 { 0 }, 136 { 100000000, 200000000, 266666667 } }, 137 .reg = { "csiphy0", "csiphy0_clk_mux" }, 138 .interrupt = { "csiphy0" } 139 }, 140 141 /* CSIPHY1 */ 142 { 143 .regulator = { NULL }, 144 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, 145 .clock_rate = { { 0 }, 146 { 0 }, 147 { 0 }, 148 { 100000000, 200000000, 266666667 } }, 149 .reg = { "csiphy1", "csiphy1_clk_mux" }, 150 .interrupt = { "csiphy1" } 151 }, 152 153 /* CSIPHY2 */ 154 { 155 .regulator = { NULL }, 156 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" }, 157 .clock_rate = { { 0 }, 158 { 0 }, 159 { 0 }, 160 { 100000000, 200000000, 266666667 } }, 161 .reg = { "csiphy2", "csiphy2_clk_mux" }, 162 .interrupt = { "csiphy2" } 163 } 164 }; 165 166 static const struct resources csid_res_8x96[] = { 167 /* CSID0 */ 168 { 169 .regulator = { "vdda" }, 170 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 171 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, 172 .clock_rate = { { 0 }, 173 { 0 }, 174 { 0 }, 175 { 0 }, 176 { 100000000, 200000000, 266666667 }, 177 { 0 }, 178 { 0 }, 179 { 0 } }, 180 .reg = { "csid0" }, 181 .interrupt = { "csid0" } 182 }, 183 184 /* CSID1 */ 185 { 186 .regulator = { "vdda" }, 187 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 188 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, 189 .clock_rate = { { 0 }, 190 { 0 }, 191 { 0 }, 192 { 0 }, 193 { 100000000, 200000000, 266666667 }, 194 { 0 }, 195 { 0 }, 196 { 0 } }, 197 .reg = { "csid1" }, 198 .interrupt = { "csid1" } 199 }, 200 201 /* CSID2 */ 202 { 203 .regulator = { "vdda" }, 204 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 205 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, 206 .clock_rate = { { 0 }, 207 { 0 }, 208 { 0 }, 209 { 0 }, 210 { 100000000, 200000000, 266666667 }, 211 { 0 }, 212 { 0 }, 213 { 0 } }, 214 .reg = { "csid2" }, 215 .interrupt = { "csid2" } 216 }, 217 218 /* CSID3 */ 219 { 220 .regulator = { "vdda" }, 221 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 222 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" }, 223 .clock_rate = { { 0 }, 224 { 0 }, 225 { 0 }, 226 { 0 }, 227 { 100000000, 200000000, 266666667 }, 228 { 0 }, 229 { 0 }, 230 { 0 } }, 231 .reg = { "csid3" }, 232 .interrupt = { "csid3" } 233 } 234 }; 235 236 static const struct resources_ispif ispif_res_8x96 = { 237 /* ISPIF */ 238 .clock = { "top_ahb", "ahb", "ispif_ahb", 239 "csi0", "csi0_pix", "csi0_rdi", 240 "csi1", "csi1_pix", "csi1_rdi", 241 "csi2", "csi2_pix", "csi2_rdi", 242 "csi3", "csi3_pix", "csi3_rdi" }, 243 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" }, 244 .reg = { "ispif", "csi_clk_mux" }, 245 .interrupt = "ispif" 246 }; 247 248 static const struct resources vfe_res_8x96[] = { 249 /* VFE0 */ 250 { 251 .regulator = { NULL }, 252 .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb", 253 "vfe0_ahb", "vfe_axi", "vfe0_stream"}, 254 .clock_rate = { { 0 }, 255 { 0 }, 256 { 75000000, 100000000, 300000000, 257 320000000, 480000000, 600000000 }, 258 { 0 }, 259 { 0 }, 260 { 0 }, 261 { 0 }, 262 { 0 } }, 263 .reg = { "vfe0" }, 264 .interrupt = { "vfe0" } 265 }, 266 267 /* VFE1 */ 268 { 269 .regulator = { NULL }, 270 .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb", 271 "vfe1_ahb", "vfe_axi", "vfe1_stream"}, 272 .clock_rate = { { 0 }, 273 { 0 }, 274 { 75000000, 100000000, 300000000, 275 320000000, 480000000, 600000000 }, 276 { 0 }, 277 { 0 }, 278 { 0 }, 279 { 0 }, 280 { 0 } }, 281 .reg = { "vfe1" }, 282 .interrupt = { "vfe1" } 283 } 284 }; 285 286 static const struct resources csiphy_res_660[] = { 287 /* CSIPHY0 */ 288 { 289 .regulator = { NULL }, 290 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer", 291 "csi0_phy", "csiphy_ahb2crif" }, 292 .clock_rate = { { 0 }, 293 { 0 }, 294 { 0 }, 295 { 100000000, 200000000, 269333333 }, 296 { 0 } }, 297 .reg = { "csiphy0", "csiphy0_clk_mux" }, 298 .interrupt = { "csiphy0" } 299 }, 300 301 /* CSIPHY1 */ 302 { 303 .regulator = { NULL }, 304 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer", 305 "csi1_phy", "csiphy_ahb2crif" }, 306 .clock_rate = { { 0 }, 307 { 0 }, 308 { 0 }, 309 { 100000000, 200000000, 269333333 }, 310 { 0 } }, 311 .reg = { "csiphy1", "csiphy1_clk_mux" }, 312 .interrupt = { "csiphy1" } 313 }, 314 315 /* CSIPHY2 */ 316 { 317 .regulator = { NULL }, 318 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer", 319 "csi2_phy", "csiphy_ahb2crif" }, 320 .clock_rate = { { 0 }, 321 { 0 }, 322 { 0 }, 323 { 100000000, 200000000, 269333333 }, 324 { 0 } }, 325 .reg = { "csiphy2", "csiphy2_clk_mux" }, 326 .interrupt = { "csiphy2" } 327 } 328 }; 329 330 static const struct resources csid_res_660[] = { 331 /* CSID0 */ 332 { 333 .regulator = { "vdda", "vdd_sec" }, 334 .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", 335 "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", 336 "cphy_csid0" }, 337 .clock_rate = { { 0 }, 338 { 0 }, 339 { 0 }, 340 { 0 }, 341 { 100000000, 200000000, 310000000, 342 404000000, 465000000 }, 343 { 0 }, 344 { 0 }, 345 { 0 }, 346 { 0 } }, 347 .reg = { "csid0" }, 348 .interrupt = { "csid0" } 349 }, 350 351 /* CSID1 */ 352 { 353 .regulator = { "vdda", "vdd_sec" }, 354 .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", 355 "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", 356 "cphy_csid1" }, 357 .clock_rate = { { 0 }, 358 { 0 }, 359 { 0 }, 360 { 0 }, 361 { 100000000, 200000000, 310000000, 362 404000000, 465000000 }, 363 { 0 }, 364 { 0 }, 365 { 0 }, 366 { 0 } }, 367 .reg = { "csid1" }, 368 .interrupt = { "csid1" } 369 }, 370 371 /* CSID2 */ 372 { 373 .regulator = { "vdda", "vdd_sec" }, 374 .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", 375 "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", 376 "cphy_csid2" }, 377 .clock_rate = { { 0 }, 378 { 0 }, 379 { 0 }, 380 { 0 }, 381 { 100000000, 200000000, 310000000, 382 404000000, 465000000 }, 383 { 0 }, 384 { 0 }, 385 { 0 }, 386 { 0 } }, 387 .reg = { "csid2" }, 388 .interrupt = { "csid2" } 389 }, 390 391 /* CSID3 */ 392 { 393 .regulator = { "vdda", "vdd_sec" }, 394 .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", 395 "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", 396 "cphy_csid3" }, 397 .clock_rate = { { 0 }, 398 { 0 }, 399 { 0 }, 400 { 0 }, 401 { 100000000, 200000000, 310000000, 402 404000000, 465000000 }, 403 { 0 }, 404 { 0 }, 405 { 0 }, 406 { 0 } }, 407 .reg = { "csid3" }, 408 .interrupt = { "csid3" } 409 } 410 }; 411 412 static const struct resources_ispif ispif_res_660 = { 413 /* ISPIF */ 414 .clock = { "top_ahb", "ahb", "ispif_ahb", 415 "csi0", "csi0_pix", "csi0_rdi", 416 "csi1", "csi1_pix", "csi1_rdi", 417 "csi2", "csi2_pix", "csi2_rdi", 418 "csi3", "csi3_pix", "csi3_rdi" }, 419 .clock_for_reset = { "vfe0", "csi_vfe0", "vfe1", "csi_vfe1" }, 420 .reg = { "ispif", "csi_clk_mux" }, 421 .interrupt = "ispif" 422 }; 423 424 static const struct resources vfe_res_660[] = { 425 /* VFE0 */ 426 { 427 .regulator = { NULL }, 428 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0", 429 "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi", 430 "vfe0_stream"}, 431 .clock_rate = { { 0 }, 432 { 0 }, 433 { 0 }, 434 { 120000000, 200000000, 256000000, 435 300000000, 404000000, 480000000, 436 540000000, 576000000 }, 437 { 0 }, 438 { 0 }, 439 { 0 }, 440 { 0 }, 441 { 0 } }, 442 .reg = { "vfe0" }, 443 .interrupt = { "vfe0" } 444 }, 445 446 /* VFE1 */ 447 { 448 .regulator = { NULL }, 449 .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1", 450 "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi", 451 "vfe1_stream"}, 452 .clock_rate = { { 0 }, 453 { 0 }, 454 { 0 }, 455 { 120000000, 200000000, 256000000, 456 300000000, 404000000, 480000000, 457 540000000, 576000000 }, 458 { 0 }, 459 { 0 }, 460 { 0 }, 461 { 0 }, 462 { 0 } }, 463 .reg = { "vfe1" }, 464 .interrupt = { "vfe1" } 465 } 466 }; 467 468 /* 469 * camss_add_clock_margin - Add margin to clock frequency rate 470 * @rate: Clock frequency rate 471 * 472 * When making calculations with physical clock frequency values 473 * some safety margin must be added. Add it. 474 */ 475 inline void camss_add_clock_margin(u64 *rate) 476 { 477 *rate *= CAMSS_CLOCK_MARGIN_NUMERATOR; 478 *rate = div_u64(*rate, CAMSS_CLOCK_MARGIN_DENOMINATOR); 479 } 480 481 /* 482 * camss_enable_clocks - Enable multiple clocks 483 * @nclocks: Number of clocks in clock array 484 * @clock: Clock array 485 * @dev: Device 486 * 487 * Return 0 on success or a negative error code otherwise 488 */ 489 int camss_enable_clocks(int nclocks, struct camss_clock *clock, 490 struct device *dev) 491 { 492 int ret; 493 int i; 494 495 for (i = 0; i < nclocks; i++) { 496 ret = clk_prepare_enable(clock[i].clk); 497 if (ret) { 498 dev_err(dev, "clock enable failed: %d\n", ret); 499 goto error; 500 } 501 } 502 503 return 0; 504 505 error: 506 for (i--; i >= 0; i--) 507 clk_disable_unprepare(clock[i].clk); 508 509 return ret; 510 } 511 512 /* 513 * camss_disable_clocks - Disable multiple clocks 514 * @nclocks: Number of clocks in clock array 515 * @clock: Clock array 516 */ 517 void camss_disable_clocks(int nclocks, struct camss_clock *clock) 518 { 519 int i; 520 521 for (i = nclocks - 1; i >= 0; i--) 522 clk_disable_unprepare(clock[i].clk); 523 } 524 525 /* 526 * camss_find_sensor - Find a linked media entity which represents a sensor 527 * @entity: Media entity to start searching from 528 * 529 * Return a pointer to sensor media entity or NULL if not found 530 */ 531 struct media_entity *camss_find_sensor(struct media_entity *entity) 532 { 533 struct media_pad *pad; 534 535 while (1) { 536 pad = &entity->pads[0]; 537 if (!(pad->flags & MEDIA_PAD_FL_SINK)) 538 return NULL; 539 540 pad = media_entity_remote_pad(pad); 541 if (!pad || !is_media_entity_v4l2_subdev(pad->entity)) 542 return NULL; 543 544 entity = pad->entity; 545 546 if (entity->function == MEDIA_ENT_F_CAM_SENSOR) 547 return entity; 548 } 549 } 550 551 /** 552 * camss_get_link_freq - Get link frequency from sensor 553 * @entity: Media entity in the current pipeline 554 * @bpp: Number of bits per pixel for the current format 555 * @lanes: Number of lanes in the link to the sensor 556 * 557 * Return link frequency on success or a negative error code otherwise 558 */ 559 s64 camss_get_link_freq(struct media_entity *entity, unsigned int bpp, 560 unsigned int lanes) 561 { 562 struct media_entity *sensor; 563 struct v4l2_subdev *subdev; 564 565 sensor = camss_find_sensor(entity); 566 if (!sensor) 567 return -ENODEV; 568 569 subdev = media_entity_to_v4l2_subdev(sensor); 570 571 return v4l2_get_link_freq(subdev->ctrl_handler, bpp, 2 * lanes); 572 } 573 574 /* 575 * camss_get_pixel_clock - Get pixel clock rate from sensor 576 * @entity: Media entity in the current pipeline 577 * @pixel_clock: Received pixel clock value 578 * 579 * Return 0 on success or a negative error code otherwise 580 */ 581 int camss_get_pixel_clock(struct media_entity *entity, u64 *pixel_clock) 582 { 583 struct media_entity *sensor; 584 struct v4l2_subdev *subdev; 585 struct v4l2_ctrl *ctrl; 586 587 sensor = camss_find_sensor(entity); 588 if (!sensor) 589 return -ENODEV; 590 591 subdev = media_entity_to_v4l2_subdev(sensor); 592 593 ctrl = v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); 594 595 if (!ctrl) 596 return -EINVAL; 597 598 *pixel_clock = v4l2_ctrl_g_ctrl_int64(ctrl); 599 600 return 0; 601 } 602 603 int camss_pm_domain_on(struct camss *camss, int id) 604 { 605 if (camss->version == CAMSS_8x96 || 606 camss->version == CAMSS_660) { 607 camss->genpd_link[id] = device_link_add(camss->dev, 608 camss->genpd[id], DL_FLAG_STATELESS | 609 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 610 611 if (!camss->genpd_link[id]) 612 return -EINVAL; 613 } 614 615 return 0; 616 } 617 618 void camss_pm_domain_off(struct camss *camss, int id) 619 { 620 if (camss->version == CAMSS_8x96 || 621 camss->version == CAMSS_660) 622 device_link_del(camss->genpd_link[id]); 623 } 624 625 /* 626 * camss_of_parse_endpoint_node - Parse port endpoint node 627 * @dev: Device 628 * @node: Device node to be parsed 629 * @csd: Parsed data from port endpoint node 630 * 631 * Return 0 on success or a negative error code on failure 632 */ 633 static int camss_of_parse_endpoint_node(struct device *dev, 634 struct device_node *node, 635 struct camss_async_subdev *csd) 636 { 637 struct csiphy_lanes_cfg *lncfg = &csd->interface.csi2.lane_cfg; 638 struct v4l2_fwnode_bus_mipi_csi2 *mipi_csi2; 639 struct v4l2_fwnode_endpoint vep = { { 0 } }; 640 unsigned int i; 641 642 v4l2_fwnode_endpoint_parse(of_fwnode_handle(node), &vep); 643 644 csd->interface.csiphy_id = vep.base.port; 645 646 mipi_csi2 = &vep.bus.mipi_csi2; 647 lncfg->clk.pos = mipi_csi2->clock_lane; 648 lncfg->clk.pol = mipi_csi2->lane_polarities[0]; 649 lncfg->num_data = mipi_csi2->num_data_lanes; 650 651 lncfg->data = devm_kcalloc(dev, 652 lncfg->num_data, sizeof(*lncfg->data), 653 GFP_KERNEL); 654 if (!lncfg->data) 655 return -ENOMEM; 656 657 for (i = 0; i < lncfg->num_data; i++) { 658 lncfg->data[i].pos = mipi_csi2->data_lanes[i]; 659 lncfg->data[i].pol = mipi_csi2->lane_polarities[i + 1]; 660 } 661 662 return 0; 663 } 664 665 /* 666 * camss_of_parse_ports - Parse ports node 667 * @dev: Device 668 * @notifier: v4l2_device notifier data 669 * 670 * Return number of "port" nodes found in "ports" node 671 */ 672 static int camss_of_parse_ports(struct camss *camss) 673 { 674 struct device *dev = camss->dev; 675 struct device_node *node = NULL; 676 struct device_node *remote = NULL; 677 int ret, num_subdevs = 0; 678 679 for_each_endpoint_of_node(dev->of_node, node) { 680 struct camss_async_subdev *csd; 681 682 if (!of_device_is_available(node)) 683 continue; 684 685 remote = of_graph_get_remote_port_parent(node); 686 if (!remote) { 687 dev_err(dev, "Cannot get remote parent\n"); 688 ret = -EINVAL; 689 goto err_cleanup; 690 } 691 692 csd = v4l2_async_notifier_add_fwnode_subdev( 693 &camss->notifier, of_fwnode_handle(remote), 694 struct camss_async_subdev); 695 of_node_put(remote); 696 if (IS_ERR(csd)) { 697 ret = PTR_ERR(csd); 698 goto err_cleanup; 699 } 700 701 ret = camss_of_parse_endpoint_node(dev, node, csd); 702 if (ret < 0) 703 goto err_cleanup; 704 705 num_subdevs++; 706 } 707 708 return num_subdevs; 709 710 err_cleanup: 711 of_node_put(node); 712 return ret; 713 } 714 715 /* 716 * camss_init_subdevices - Initialize subdev structures and resources 717 * @camss: CAMSS device 718 * 719 * Return 0 on success or a negative error code on failure 720 */ 721 static int camss_init_subdevices(struct camss *camss) 722 { 723 const struct resources *csiphy_res; 724 const struct resources *csid_res; 725 const struct resources_ispif *ispif_res; 726 const struct resources *vfe_res; 727 unsigned int i; 728 int ret; 729 730 if (camss->version == CAMSS_8x16) { 731 csiphy_res = csiphy_res_8x16; 732 csid_res = csid_res_8x16; 733 ispif_res = &ispif_res_8x16; 734 vfe_res = vfe_res_8x16; 735 } else if (camss->version == CAMSS_8x96) { 736 csiphy_res = csiphy_res_8x96; 737 csid_res = csid_res_8x96; 738 ispif_res = &ispif_res_8x96; 739 vfe_res = vfe_res_8x96; 740 } else if (camss->version == CAMSS_660) { 741 csiphy_res = csiphy_res_660; 742 csid_res = csid_res_660; 743 ispif_res = &ispif_res_660; 744 vfe_res = vfe_res_660; 745 } else { 746 return -EINVAL; 747 } 748 749 for (i = 0; i < camss->csiphy_num; i++) { 750 ret = msm_csiphy_subdev_init(camss, &camss->csiphy[i], 751 &csiphy_res[i], i); 752 if (ret < 0) { 753 dev_err(camss->dev, 754 "Failed to init csiphy%d sub-device: %d\n", 755 i, ret); 756 return ret; 757 } 758 } 759 760 for (i = 0; i < camss->csid_num; i++) { 761 ret = msm_csid_subdev_init(camss, &camss->csid[i], 762 &csid_res[i], i); 763 if (ret < 0) { 764 dev_err(camss->dev, 765 "Failed to init csid%d sub-device: %d\n", 766 i, ret); 767 return ret; 768 } 769 } 770 771 ret = msm_ispif_subdev_init(&camss->ispif, ispif_res); 772 if (ret < 0) { 773 dev_err(camss->dev, "Failed to init ispif sub-device: %d\n", 774 ret); 775 return ret; 776 } 777 778 for (i = 0; i < camss->vfe_num; i++) { 779 ret = msm_vfe_subdev_init(camss, &camss->vfe[i], 780 &vfe_res[i], i); 781 if (ret < 0) { 782 dev_err(camss->dev, 783 "Fail to init vfe%d sub-device: %d\n", i, ret); 784 return ret; 785 } 786 } 787 788 return 0; 789 } 790 791 /* 792 * camss_register_entities - Register subdev nodes and create links 793 * @camss: CAMSS device 794 * 795 * Return 0 on success or a negative error code on failure 796 */ 797 static int camss_register_entities(struct camss *camss) 798 { 799 int i, j, k; 800 int ret; 801 802 for (i = 0; i < camss->csiphy_num; i++) { 803 ret = msm_csiphy_register_entity(&camss->csiphy[i], 804 &camss->v4l2_dev); 805 if (ret < 0) { 806 dev_err(camss->dev, 807 "Failed to register csiphy%d entity: %d\n", 808 i, ret); 809 goto err_reg_csiphy; 810 } 811 } 812 813 for (i = 0; i < camss->csid_num; i++) { 814 ret = msm_csid_register_entity(&camss->csid[i], 815 &camss->v4l2_dev); 816 if (ret < 0) { 817 dev_err(camss->dev, 818 "Failed to register csid%d entity: %d\n", 819 i, ret); 820 goto err_reg_csid; 821 } 822 } 823 824 ret = msm_ispif_register_entities(&camss->ispif, &camss->v4l2_dev); 825 if (ret < 0) { 826 dev_err(camss->dev, "Failed to register ispif entities: %d\n", 827 ret); 828 goto err_reg_ispif; 829 } 830 831 for (i = 0; i < camss->vfe_num; i++) { 832 ret = msm_vfe_register_entities(&camss->vfe[i], 833 &camss->v4l2_dev); 834 if (ret < 0) { 835 dev_err(camss->dev, 836 "Failed to register vfe%d entities: %d\n", 837 i, ret); 838 goto err_reg_vfe; 839 } 840 } 841 842 for (i = 0; i < camss->csiphy_num; i++) { 843 for (j = 0; j < camss->csid_num; j++) { 844 ret = media_create_pad_link( 845 &camss->csiphy[i].subdev.entity, 846 MSM_CSIPHY_PAD_SRC, 847 &camss->csid[j].subdev.entity, 848 MSM_CSID_PAD_SINK, 849 0); 850 if (ret < 0) { 851 dev_err(camss->dev, 852 "Failed to link %s->%s entities: %d\n", 853 camss->csiphy[i].subdev.entity.name, 854 camss->csid[j].subdev.entity.name, 855 ret); 856 goto err_link; 857 } 858 } 859 } 860 861 for (i = 0; i < camss->csid_num; i++) { 862 for (j = 0; j < camss->ispif.line_num; j++) { 863 ret = media_create_pad_link( 864 &camss->csid[i].subdev.entity, 865 MSM_CSID_PAD_SRC, 866 &camss->ispif.line[j].subdev.entity, 867 MSM_ISPIF_PAD_SINK, 868 0); 869 if (ret < 0) { 870 dev_err(camss->dev, 871 "Failed to link %s->%s entities: %d\n", 872 camss->csid[i].subdev.entity.name, 873 camss->ispif.line[j].subdev.entity.name, 874 ret); 875 goto err_link; 876 } 877 } 878 } 879 880 for (i = 0; i < camss->ispif.line_num; i++) 881 for (k = 0; k < camss->vfe_num; k++) 882 for (j = 0; j < ARRAY_SIZE(camss->vfe[k].line); j++) { 883 ret = media_create_pad_link( 884 &camss->ispif.line[i].subdev.entity, 885 MSM_ISPIF_PAD_SRC, 886 &camss->vfe[k].line[j].subdev.entity, 887 MSM_VFE_PAD_SINK, 888 0); 889 if (ret < 0) { 890 dev_err(camss->dev, 891 "Failed to link %s->%s entities: %d\n", 892 camss->ispif.line[i].subdev.entity.name, 893 camss->vfe[k].line[j].subdev.entity.name, 894 ret); 895 goto err_link; 896 } 897 } 898 899 return 0; 900 901 err_link: 902 i = camss->vfe_num; 903 err_reg_vfe: 904 for (i--; i >= 0; i--) 905 msm_vfe_unregister_entities(&camss->vfe[i]); 906 907 msm_ispif_unregister_entities(&camss->ispif); 908 err_reg_ispif: 909 910 i = camss->csid_num; 911 err_reg_csid: 912 for (i--; i >= 0; i--) 913 msm_csid_unregister_entity(&camss->csid[i]); 914 915 i = camss->csiphy_num; 916 err_reg_csiphy: 917 for (i--; i >= 0; i--) 918 msm_csiphy_unregister_entity(&camss->csiphy[i]); 919 920 return ret; 921 } 922 923 /* 924 * camss_unregister_entities - Unregister subdev nodes 925 * @camss: CAMSS device 926 * 927 * Return 0 on success or a negative error code on failure 928 */ 929 static void camss_unregister_entities(struct camss *camss) 930 { 931 unsigned int i; 932 933 for (i = 0; i < camss->csiphy_num; i++) 934 msm_csiphy_unregister_entity(&camss->csiphy[i]); 935 936 for (i = 0; i < camss->csid_num; i++) 937 msm_csid_unregister_entity(&camss->csid[i]); 938 939 msm_ispif_unregister_entities(&camss->ispif); 940 941 for (i = 0; i < camss->vfe_num; i++) 942 msm_vfe_unregister_entities(&camss->vfe[i]); 943 } 944 945 static int camss_subdev_notifier_bound(struct v4l2_async_notifier *async, 946 struct v4l2_subdev *subdev, 947 struct v4l2_async_subdev *asd) 948 { 949 struct camss *camss = container_of(async, struct camss, notifier); 950 struct camss_async_subdev *csd = 951 container_of(asd, struct camss_async_subdev, asd); 952 u8 id = csd->interface.csiphy_id; 953 struct csiphy_device *csiphy = &camss->csiphy[id]; 954 955 csiphy->cfg.csi2 = &csd->interface.csi2; 956 subdev->host_priv = csiphy; 957 958 return 0; 959 } 960 961 static int camss_subdev_notifier_complete(struct v4l2_async_notifier *async) 962 { 963 struct camss *camss = container_of(async, struct camss, notifier); 964 struct v4l2_device *v4l2_dev = &camss->v4l2_dev; 965 struct v4l2_subdev *sd; 966 int ret; 967 968 list_for_each_entry(sd, &v4l2_dev->subdevs, list) { 969 if (sd->host_priv) { 970 struct media_entity *sensor = &sd->entity; 971 struct csiphy_device *csiphy = 972 (struct csiphy_device *) sd->host_priv; 973 struct media_entity *input = &csiphy->subdev.entity; 974 unsigned int i; 975 976 for (i = 0; i < sensor->num_pads; i++) { 977 if (sensor->pads[i].flags & MEDIA_PAD_FL_SOURCE) 978 break; 979 } 980 if (i == sensor->num_pads) { 981 dev_err(camss->dev, 982 "No source pad in external entity\n"); 983 return -EINVAL; 984 } 985 986 ret = media_create_pad_link(sensor, i, 987 input, MSM_CSIPHY_PAD_SINK, 988 MEDIA_LNK_FL_IMMUTABLE | MEDIA_LNK_FL_ENABLED); 989 if (ret < 0) { 990 dev_err(camss->dev, 991 "Failed to link %s->%s entities: %d\n", 992 sensor->name, input->name, ret); 993 return ret; 994 } 995 } 996 } 997 998 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev); 999 if (ret < 0) 1000 return ret; 1001 1002 return media_device_register(&camss->media_dev); 1003 } 1004 1005 static const struct v4l2_async_notifier_operations camss_subdev_notifier_ops = { 1006 .bound = camss_subdev_notifier_bound, 1007 .complete = camss_subdev_notifier_complete, 1008 }; 1009 1010 static const struct media_device_ops camss_media_ops = { 1011 .link_notify = v4l2_pipeline_link_notify, 1012 }; 1013 1014 /* 1015 * camss_probe - Probe CAMSS platform device 1016 * @pdev: Pointer to CAMSS platform device 1017 * 1018 * Return 0 on success or a negative error code on failure 1019 */ 1020 static int camss_probe(struct platform_device *pdev) 1021 { 1022 struct device *dev = &pdev->dev; 1023 struct camss *camss; 1024 int num_subdevs, ret; 1025 1026 camss = kzalloc(sizeof(*camss), GFP_KERNEL); 1027 if (!camss) 1028 return -ENOMEM; 1029 1030 atomic_set(&camss->ref_count, 0); 1031 camss->dev = dev; 1032 platform_set_drvdata(pdev, camss); 1033 1034 if (of_device_is_compatible(dev->of_node, "qcom,msm8916-camss")) { 1035 camss->version = CAMSS_8x16; 1036 camss->csiphy_num = 2; 1037 camss->csid_num = 2; 1038 camss->vfe_num = 1; 1039 } else if (of_device_is_compatible(dev->of_node, 1040 "qcom,msm8996-camss")) { 1041 camss->version = CAMSS_8x96; 1042 camss->csiphy_num = 3; 1043 camss->csid_num = 4; 1044 camss->vfe_num = 2; 1045 } else if (of_device_is_compatible(dev->of_node, 1046 "qcom,sdm660-camss")) { 1047 camss->version = CAMSS_660; 1048 camss->csiphy_num = 3; 1049 camss->csid_num = 4; 1050 camss->vfe_num = 2; 1051 } else { 1052 ret = -EINVAL; 1053 goto err_free; 1054 } 1055 1056 camss->csiphy = devm_kcalloc(dev, camss->csiphy_num, 1057 sizeof(*camss->csiphy), GFP_KERNEL); 1058 if (!camss->csiphy) { 1059 ret = -ENOMEM; 1060 goto err_free; 1061 } 1062 1063 camss->csid = devm_kcalloc(dev, camss->csid_num, sizeof(*camss->csid), 1064 GFP_KERNEL); 1065 if (!camss->csid) { 1066 ret = -ENOMEM; 1067 goto err_free; 1068 } 1069 1070 camss->vfe = devm_kcalloc(dev, camss->vfe_num, sizeof(*camss->vfe), 1071 GFP_KERNEL); 1072 if (!camss->vfe) { 1073 ret = -ENOMEM; 1074 goto err_free; 1075 } 1076 1077 v4l2_async_notifier_init(&camss->notifier); 1078 1079 num_subdevs = camss_of_parse_ports(camss); 1080 if (num_subdevs < 0) { 1081 ret = num_subdevs; 1082 goto err_cleanup; 1083 } 1084 1085 ret = camss_init_subdevices(camss); 1086 if (ret < 0) 1087 goto err_cleanup; 1088 1089 ret = dma_set_mask_and_coherent(dev, 0xffffffff); 1090 if (ret) 1091 goto err_cleanup; 1092 1093 camss->media_dev.dev = camss->dev; 1094 strscpy(camss->media_dev.model, "Qualcomm Camera Subsystem", 1095 sizeof(camss->media_dev.model)); 1096 camss->media_dev.ops = &camss_media_ops; 1097 media_device_init(&camss->media_dev); 1098 1099 camss->v4l2_dev.mdev = &camss->media_dev; 1100 ret = v4l2_device_register(camss->dev, &camss->v4l2_dev); 1101 if (ret < 0) { 1102 dev_err(dev, "Failed to register V4L2 device: %d\n", ret); 1103 goto err_cleanup; 1104 } 1105 1106 ret = camss_register_entities(camss); 1107 if (ret < 0) 1108 goto err_register_entities; 1109 1110 if (num_subdevs) { 1111 camss->notifier.ops = &camss_subdev_notifier_ops; 1112 1113 ret = v4l2_async_notifier_register(&camss->v4l2_dev, 1114 &camss->notifier); 1115 if (ret) { 1116 dev_err(dev, 1117 "Failed to register async subdev nodes: %d\n", 1118 ret); 1119 goto err_register_subdevs; 1120 } 1121 } else { 1122 ret = v4l2_device_register_subdev_nodes(&camss->v4l2_dev); 1123 if (ret < 0) { 1124 dev_err(dev, "Failed to register subdev nodes: %d\n", 1125 ret); 1126 goto err_register_subdevs; 1127 } 1128 1129 ret = media_device_register(&camss->media_dev); 1130 if (ret < 0) { 1131 dev_err(dev, "Failed to register media device: %d\n", 1132 ret); 1133 goto err_register_subdevs; 1134 } 1135 } 1136 1137 if (camss->version == CAMSS_8x96 || 1138 camss->version == CAMSS_660) { 1139 camss->genpd[PM_DOMAIN_VFE0] = dev_pm_domain_attach_by_id( 1140 camss->dev, PM_DOMAIN_VFE0); 1141 if (IS_ERR(camss->genpd[PM_DOMAIN_VFE0])) 1142 return PTR_ERR(camss->genpd[PM_DOMAIN_VFE0]); 1143 1144 camss->genpd[PM_DOMAIN_VFE1] = dev_pm_domain_attach_by_id( 1145 camss->dev, PM_DOMAIN_VFE1); 1146 if (IS_ERR(camss->genpd[PM_DOMAIN_VFE1])) { 1147 dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0], 1148 true); 1149 return PTR_ERR(camss->genpd[PM_DOMAIN_VFE1]); 1150 } 1151 } 1152 1153 pm_runtime_enable(dev); 1154 1155 return 0; 1156 1157 err_register_subdevs: 1158 camss_unregister_entities(camss); 1159 err_register_entities: 1160 v4l2_device_unregister(&camss->v4l2_dev); 1161 err_cleanup: 1162 v4l2_async_notifier_cleanup(&camss->notifier); 1163 err_free: 1164 kfree(camss); 1165 1166 return ret; 1167 } 1168 1169 void camss_delete(struct camss *camss) 1170 { 1171 v4l2_device_unregister(&camss->v4l2_dev); 1172 media_device_unregister(&camss->media_dev); 1173 media_device_cleanup(&camss->media_dev); 1174 1175 pm_runtime_disable(camss->dev); 1176 1177 if (camss->version == CAMSS_8x96 || 1178 camss->version == CAMSS_660) { 1179 dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE0], true); 1180 dev_pm_domain_detach(camss->genpd[PM_DOMAIN_VFE1], true); 1181 } 1182 1183 kfree(camss); 1184 } 1185 1186 /* 1187 * camss_remove - Remove CAMSS platform device 1188 * @pdev: Pointer to CAMSS platform device 1189 * 1190 * Always returns 0. 1191 */ 1192 static int camss_remove(struct platform_device *pdev) 1193 { 1194 struct camss *camss = platform_get_drvdata(pdev); 1195 1196 v4l2_async_notifier_unregister(&camss->notifier); 1197 v4l2_async_notifier_cleanup(&camss->notifier); 1198 camss_unregister_entities(camss); 1199 1200 if (atomic_read(&camss->ref_count) == 0) 1201 camss_delete(camss); 1202 1203 return 0; 1204 } 1205 1206 static const struct of_device_id camss_dt_match[] = { 1207 { .compatible = "qcom,msm8916-camss" }, 1208 { .compatible = "qcom,msm8996-camss" }, 1209 { .compatible = "qcom,sdm660-camss" }, 1210 { } 1211 }; 1212 1213 MODULE_DEVICE_TABLE(of, camss_dt_match); 1214 1215 static int __maybe_unused camss_runtime_suspend(struct device *dev) 1216 { 1217 return 0; 1218 } 1219 1220 static int __maybe_unused camss_runtime_resume(struct device *dev) 1221 { 1222 return 0; 1223 } 1224 1225 static const struct dev_pm_ops camss_pm_ops = { 1226 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1227 pm_runtime_force_resume) 1228 SET_RUNTIME_PM_OPS(camss_runtime_suspend, camss_runtime_resume, NULL) 1229 }; 1230 1231 static struct platform_driver qcom_camss_driver = { 1232 .probe = camss_probe, 1233 .remove = camss_remove, 1234 .driver = { 1235 .name = "qcom-camss", 1236 .of_match_table = camss_dt_match, 1237 .pm = &camss_pm_ops, 1238 }, 1239 }; 1240 1241 module_platform_driver(qcom_camss_driver); 1242 1243 MODULE_ALIAS("platform:qcom-camss"); 1244 MODULE_DESCRIPTION("Qualcomm Camera Subsystem driver"); 1245 MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>"); 1246 MODULE_LICENSE("GPL v2"); 1247