1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-8.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.8 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2021 Linaro Ltd. 9 */ 10 11 #include <linux/device.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 16 #include "camss.h" 17 #include "camss-vfe.h" 18 #include "camss-vfe-gen1.h" 19 20 #define VFE_0_HW_VERSION 0x000 21 22 #define VFE_0_GLOBAL_RESET_CMD 0x018 23 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 24 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 25 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 26 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 27 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 28 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(5) 29 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(6) 30 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(7) 31 #define VFE_0_GLOBAL_RESET_CMD_DSP BIT(8) 32 #define VFE_0_GLOBAL_RESET_CMD_IDLE_CGC BIT(9) 33 34 #define VFE_0_MODULE_LENS_EN 0x040 35 #define VFE_0_MODULE_LENS_EN_DEMUX BIT(2) 36 #define VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE BIT(3) 37 38 #define VFE_0_MODULE_ZOOM_EN 0x04c 39 #define VFE_0_MODULE_ZOOM_EN_SCALE_ENC BIT(1) 40 #define VFE_0_MODULE_ZOOM_EN_CROP_ENC BIT(2) 41 #define VFE_0_MODULE_ZOOM_EN_REALIGN_BUF BIT(9) 42 43 #define VFE_0_CORE_CFG 0x050 44 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 45 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 46 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 47 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 48 #define VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN BIT(4) 49 50 #define VFE_0_IRQ_CMD 0x058 51 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 52 53 #define VFE_0_IRQ_MASK_0 0x05c 54 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 55 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 56 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 57 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 58 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 59 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 60 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 61 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 62 #define VFE_0_IRQ_MASK_1 0x060 63 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 64 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 65 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 66 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 67 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 68 69 #define VFE_0_IRQ_CLEAR_0 0x064 70 #define VFE_0_IRQ_CLEAR_1 0x068 71 72 #define VFE_0_IRQ_STATUS_0 0x06c 73 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 74 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 75 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 76 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 77 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 78 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 79 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 80 #define VFE_0_IRQ_STATUS_1 0x070 81 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 82 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 83 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 84 85 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x074 86 #define VFE_0_VIOLATION_STATUS 0x07c 87 88 #define VFE_0_BUS_CMD 0x80 89 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 90 91 #define VFE_0_BUS_CFG 0x084 92 93 #define VFE_0_BUS_XBAR_CFG_x(x) (0x90 + 0x4 * ((x) / 2)) 94 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(2) 95 #define VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN BIT(3) 96 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA (0x1 << 4) 97 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER (0x2 << 4) 98 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 99 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 100 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0x0 101 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 0xc 102 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 0xd 103 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 0xe 104 105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x0a0 + 0x2c * (n)) 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x0a4 + 0x2c * (n)) 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x0ac + 0x2c * (n)) 109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x0b4 + 0x2c * (n)) 110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT 1 111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 112 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x0b8 + 0x2c * (n)) 114 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 115 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x0bc + 0x2c * (n)) 116 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x0c0 + 0x2c * (n)) 117 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 118 (0x0c4 + 0x2c * (n)) 119 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 120 (0x0c8 + 0x2c * (n)) 121 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 122 123 #define VFE_0_BUS_PING_PONG_STATUS 0x338 124 125 #define VFE_0_BUS_BDG_CMD 0x400 126 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 127 128 #define VFE_0_BUS_BDG_QOS_CFG_0 0x404 129 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 130 #define VFE_0_BUS_BDG_QOS_CFG_1 0x408 131 #define VFE_0_BUS_BDG_QOS_CFG_2 0x40c 132 #define VFE_0_BUS_BDG_QOS_CFG_3 0x410 133 #define VFE_0_BUS_BDG_QOS_CFG_3_CFG 0xaa55aaa5 134 #define VFE_0_BUS_BDG_QOS_CFG_4 0x414 135 #define VFE_0_BUS_BDG_QOS_CFG_4_CFG 0xaa55aa55 136 #define VFE_0_BUS_BDG_QOS_CFG_5 0x418 137 #define VFE_0_BUS_BDG_QOS_CFG_6 0x41c 138 #define VFE_0_BUS_BDG_QOS_CFG_7 0x420 139 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0005aa55 140 141 #define VFE_0_BUS_BDG_DS_CFG_0 0x424 142 #define VFE_0_BUS_BDG_DS_CFG_0_CFG 0xcccc1111 143 #define VFE_0_BUS_BDG_DS_CFG_1 0x428 144 #define VFE_0_BUS_BDG_DS_CFG_2 0x42c 145 #define VFE_0_BUS_BDG_DS_CFG_3 0x430 146 #define VFE_0_BUS_BDG_DS_CFG_4 0x434 147 #define VFE_0_BUS_BDG_DS_CFG_5 0x438 148 #define VFE_0_BUS_BDG_DS_CFG_6 0x43c 149 #define VFE_0_BUS_BDG_DS_CFG_7 0x440 150 #define VFE_0_BUS_BDG_DS_CFG_8 0x444 151 #define VFE_0_BUS_BDG_DS_CFG_9 0x448 152 #define VFE_0_BUS_BDG_DS_CFG_10 0x44c 153 #define VFE_0_BUS_BDG_DS_CFG_11 0x450 154 #define VFE_0_BUS_BDG_DS_CFG_12 0x454 155 #define VFE_0_BUS_BDG_DS_CFG_13 0x458 156 #define VFE_0_BUS_BDG_DS_CFG_14 0x45c 157 #define VFE_0_BUS_BDG_DS_CFG_15 0x460 158 #define VFE_0_BUS_BDG_DS_CFG_16 0x464 159 #define VFE_0_BUS_BDG_DS_CFG_16_CFG 0x00000110 160 161 #define VFE_0_RDI_CFG_x(x) (0x46c + (0x4 * (x))) 162 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 163 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 164 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 165 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 166 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 167 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 168 169 #define VFE_0_CAMIF_CMD 0x478 170 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 171 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 172 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 173 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 174 #define VFE_0_CAMIF_CFG 0x47c 175 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 176 #define VFE_0_CAMIF_FRAME_CFG 0x484 177 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x488 178 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x48c 179 #define VFE_0_CAMIF_SUBSAMPLE_CFG 0x490 180 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN 0x498 181 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x49c 182 #define VFE_0_CAMIF_STATUS 0x4a4 183 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 184 185 #define VFE_0_REG_UPDATE 0x4ac 186 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 187 #define VFE_0_REG_UPDATE_line_n(n) \ 188 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 189 190 #define VFE_0_DEMUX_CFG 0x560 191 #define VFE_0_DEMUX_CFG_PERIOD 0x3 192 #define VFE_0_DEMUX_GAIN_0 0x564 193 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 194 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 195 #define VFE_0_DEMUX_GAIN_1 0x568 196 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 197 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 198 #define VFE_0_DEMUX_EVEN_CFG 0x574 199 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 200 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 201 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 202 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 203 #define VFE_0_DEMUX_ODD_CFG 0x578 204 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 205 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 206 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 207 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 208 209 #define VFE_0_SCALE_ENC_Y_CFG 0x91c 210 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x920 211 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x924 212 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x934 213 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x938 214 #define VFE_0_SCALE_ENC_CBCR_CFG 0x948 215 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x94c 216 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x950 217 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x960 218 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x964 219 220 #define VFE_0_CROP_ENC_Y_WIDTH 0x974 221 #define VFE_0_CROP_ENC_Y_HEIGHT 0x978 222 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x97c 223 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x980 224 225 #define VFE_0_CLAMP_ENC_MAX_CFG 0x984 226 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 227 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 228 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 229 #define VFE_0_CLAMP_ENC_MIN_CFG 0x988 230 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 231 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 232 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 233 234 #define VFE_0_REALIGN_BUF_CFG 0xaac 235 #define VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL BIT(2) 236 #define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3) 237 #define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4) 238 239 #define VFE_0_BUS_IMAGE_MASTER_CMD 0xcec 240 #define VFE_0_BUS_IMAGE_MASTER_n_SHIFT(x) (2 * (x)) 241 242 #define CAMIF_TIMEOUT_SLEEP_US 1000 243 #define CAMIF_TIMEOUT_ALL_US 1000000 244 245 #define MSM_VFE_VFE0_UB_SIZE 2047 246 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 247 #define MSM_VFE_VFE1_UB_SIZE 1535 248 #define MSM_VFE_VFE1_UB_SIZE_RDI (MSM_VFE_VFE1_UB_SIZE / 3) 249 250 static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 251 { 252 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 253 254 dev_err(dev, "VFE HW Version = 0x%08x\n", hw_version); 255 } 256 257 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 258 { 259 u32 bits = readl_relaxed(vfe->base + reg); 260 261 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 262 } 263 264 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 265 { 266 u32 bits = readl_relaxed(vfe->base + reg); 267 268 writel_relaxed(bits | set_bits, vfe->base + reg); 269 } 270 271 static void vfe_global_reset(struct vfe_device *vfe) 272 { 273 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_IDLE_CGC | 274 VFE_0_GLOBAL_RESET_CMD_DSP | 275 VFE_0_GLOBAL_RESET_CMD_TESTGEN | 276 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 277 VFE_0_GLOBAL_RESET_CMD_PM | 278 VFE_0_GLOBAL_RESET_CMD_REGISTER | 279 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 280 VFE_0_GLOBAL_RESET_CMD_BUS | 281 VFE_0_GLOBAL_RESET_CMD_CAMIF | 282 VFE_0_GLOBAL_RESET_CMD_CORE; 283 284 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); 285 286 /* Enforce barrier between IRQ mask setup and global reset */ 287 wmb(); 288 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 289 } 290 291 static void vfe_halt_request(struct vfe_device *vfe) 292 { 293 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 294 vfe->base + VFE_0_BUS_BDG_CMD); 295 } 296 297 static void vfe_halt_clear(struct vfe_device *vfe) 298 { 299 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 300 } 301 302 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 303 { 304 if (enable) 305 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 306 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 307 else 308 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 309 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 310 } 311 312 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 313 314 static int vfe_word_per_line_by_pixel(u32 format, u32 pixel_per_line) 315 { 316 int val = 0; 317 318 switch (format) { 319 case V4L2_PIX_FMT_NV12: 320 case V4L2_PIX_FMT_NV21: 321 case V4L2_PIX_FMT_NV16: 322 case V4L2_PIX_FMT_NV61: 323 val = CALC_WORD(pixel_per_line, 1, 8); 324 break; 325 case V4L2_PIX_FMT_YUYV: 326 case V4L2_PIX_FMT_YVYU: 327 case V4L2_PIX_FMT_UYVY: 328 case V4L2_PIX_FMT_VYUY: 329 val = CALC_WORD(pixel_per_line, 2, 8); 330 break; 331 } 332 333 return val; 334 } 335 336 static int vfe_word_per_line_by_bytes(u32 bytes_per_line) 337 { 338 return CALC_WORD(bytes_per_line, 1, 8); 339 } 340 341 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 342 u16 *width, u16 *height, u16 *bytesperline) 343 { 344 switch (pix->pixelformat) { 345 case V4L2_PIX_FMT_NV12: 346 case V4L2_PIX_FMT_NV21: 347 *width = pix->width; 348 *height = pix->height; 349 *bytesperline = pix->plane_fmt[0].bytesperline; 350 if (plane == 1) 351 *height /= 2; 352 break; 353 case V4L2_PIX_FMT_NV16: 354 case V4L2_PIX_FMT_NV61: 355 *width = pix->width; 356 *height = pix->height; 357 *bytesperline = pix->plane_fmt[0].bytesperline; 358 break; 359 case V4L2_PIX_FMT_YUYV: 360 case V4L2_PIX_FMT_YVYU: 361 case V4L2_PIX_FMT_VYUY: 362 case V4L2_PIX_FMT_UYVY: 363 *width = pix->width; 364 *height = pix->height; 365 *bytesperline = pix->plane_fmt[plane].bytesperline; 366 break; 367 } 368 } 369 370 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 371 struct v4l2_pix_format_mplane *pix, 372 u8 plane, u32 enable) 373 { 374 u32 reg; 375 376 if (enable) { 377 u16 width = 0, height = 0, bytesperline = 0, wpl; 378 379 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 380 381 wpl = vfe_word_per_line_by_pixel(pix->pixelformat, width); 382 383 reg = height - 1; 384 reg |= ((wpl + 3) / 4 - 1) << 16; 385 386 writel_relaxed(reg, vfe->base + 387 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 388 389 wpl = vfe_word_per_line_by_bytes(bytesperline); 390 391 reg = 0x3; 392 reg |= (height - 1) << 2; 393 reg |= ((wpl + 1) / 2) << 16; 394 395 writel_relaxed(reg, vfe->base + 396 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 397 } else { 398 writel_relaxed(0, vfe->base + 399 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 400 writel_relaxed(0, vfe->base + 401 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 402 } 403 } 404 405 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 406 { 407 u32 reg; 408 409 reg = readl_relaxed(vfe->base + 410 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 411 412 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 413 414 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 415 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 416 417 writel_relaxed(reg, 418 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 419 } 420 421 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 422 u32 pattern) 423 { 424 writel_relaxed(pattern, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 425 } 426 427 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 428 u16 offset, u16 depth) 429 { 430 u32 reg; 431 432 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 433 depth; 434 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 435 } 436 437 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 438 { 439 /* Enforce barrier between any outstanding register write */ 440 wmb(); 441 442 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 443 444 /* Use barrier to make sure bus reload is issued before anything else */ 445 wmb(); 446 } 447 448 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 449 { 450 writel_relaxed(addr, 451 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 452 } 453 454 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 455 { 456 writel_relaxed(addr, 457 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 458 } 459 460 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 461 { 462 u32 reg; 463 464 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 465 466 return (reg >> wm) & 0x1; 467 } 468 469 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 470 { 471 if (enable) 472 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); 473 else 474 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 475 } 476 477 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 478 enum vfe_line_id id) 479 { 480 u32 reg; 481 482 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 483 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 484 485 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 486 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 487 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 488 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 489 490 switch (id) { 491 case VFE_LINE_RDI0: 492 default: 493 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 494 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 495 break; 496 case VFE_LINE_RDI1: 497 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 498 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 499 break; 500 case VFE_LINE_RDI2: 501 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 502 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 503 break; 504 } 505 506 if (wm % 2 == 1) 507 reg <<= 16; 508 509 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 510 } 511 512 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 513 { 514 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 515 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 516 } 517 518 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 519 enum vfe_line_id id) 520 { 521 u32 reg; 522 523 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 524 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 525 526 switch (id) { 527 case VFE_LINE_RDI0: 528 default: 529 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 530 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 531 break; 532 case VFE_LINE_RDI1: 533 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 534 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 535 break; 536 case VFE_LINE_RDI2: 537 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 538 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 539 break; 540 } 541 542 if (wm % 2 == 1) 543 reg <<= 16; 544 545 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 546 } 547 548 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 549 u8 enable) 550 { 551 struct vfe_line *line = container_of(output, struct vfe_line, output); 552 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 553 u32 reg; 554 555 switch (p) { 556 case V4L2_PIX_FMT_NV12: 557 case V4L2_PIX_FMT_NV21: 558 case V4L2_PIX_FMT_NV16: 559 case V4L2_PIX_FMT_NV61: 560 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 561 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 562 563 if (output->wm_idx[0] % 2 == 1) 564 reg <<= 16; 565 566 if (enable) 567 vfe_reg_set(vfe, 568 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 569 reg); 570 else 571 vfe_reg_clr(vfe, 572 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 573 reg); 574 575 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 576 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 577 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 578 579 if (output->wm_idx[1] % 2 == 1) 580 reg <<= 16; 581 582 if (enable) 583 vfe_reg_set(vfe, 584 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 585 reg); 586 else 587 vfe_reg_clr(vfe, 588 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 589 reg); 590 break; 591 case V4L2_PIX_FMT_YUYV: 592 case V4L2_PIX_FMT_YVYU: 593 case V4L2_PIX_FMT_VYUY: 594 case V4L2_PIX_FMT_UYVY: 595 reg = VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN; 596 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 597 598 if (p == V4L2_PIX_FMT_YUYV || p == V4L2_PIX_FMT_YVYU) 599 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 600 601 if (output->wm_idx[0] % 2 == 1) 602 reg <<= 16; 603 604 if (enable) 605 vfe_reg_set(vfe, 606 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 607 reg); 608 else 609 vfe_reg_clr(vfe, 610 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 611 reg); 612 break; 613 default: 614 break; 615 } 616 } 617 618 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 619 u8 enable) 620 { 621 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 622 u32 val = VFE_0_MODULE_ZOOM_EN_REALIGN_BUF; 623 624 if (p != V4L2_PIX_FMT_YUYV && p != V4L2_PIX_FMT_YVYU && 625 p != V4L2_PIX_FMT_VYUY && p != V4L2_PIX_FMT_UYVY) 626 return; 627 628 if (enable) { 629 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val); 630 } else { 631 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val); 632 return; 633 } 634 635 val = VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE; 636 637 if (p == V4L2_PIX_FMT_UYVY || p == V4L2_PIX_FMT_YUYV) 638 val |= VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL; 639 else 640 val |= VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL; 641 642 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); 643 } 644 645 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 646 { 647 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 648 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 649 650 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 651 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 652 } 653 654 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 655 { 656 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 657 658 /* Enforce barrier between line update and commit */ 659 wmb(); 660 661 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 662 663 /* Make sure register update is issued before further reg writes */ 664 wmb(); 665 } 666 667 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 668 enum vfe_line_id line_id) 669 { 670 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 671 } 672 673 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 674 enum vfe_line_id line_id, u8 enable) 675 { 676 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 677 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 678 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 679 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 680 681 if (enable) { 682 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 683 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 684 } else { 685 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 686 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 687 } 688 } 689 690 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 691 enum vfe_line_id line_id, u8 enable) 692 { 693 struct vfe_output *output = &vfe->line[line_id].output; 694 unsigned int i; 695 u32 irq_en0; 696 u32 irq_en1; 697 u32 comp_mask = 0; 698 699 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 700 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 701 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 702 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 703 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 704 for (i = 0; i < output->wm_num; i++) { 705 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(output->wm_idx[i]); 706 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 707 } 708 709 if (enable) { 710 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 711 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 712 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 713 } else { 714 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 715 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 716 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 717 } 718 } 719 720 static void vfe_enable_irq_common(struct vfe_device *vfe) 721 { 722 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 723 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 724 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 725 726 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 727 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 728 } 729 730 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 731 { 732 u32 val, even_cfg, odd_cfg; 733 734 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 735 736 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 737 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 738 739 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 740 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 741 742 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 743 case MEDIA_BUS_FMT_YUYV8_2X8: 744 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 745 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 746 break; 747 case MEDIA_BUS_FMT_YVYU8_2X8: 748 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 749 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 750 break; 751 case MEDIA_BUS_FMT_UYVY8_2X8: 752 default: 753 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 754 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 755 break; 756 case MEDIA_BUS_FMT_VYUY8_2X8: 757 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 758 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 759 break; 760 } 761 762 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 763 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 764 } 765 766 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 767 { 768 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 769 u32 reg; 770 u16 input, output; 771 u8 interp_reso; 772 u32 phase_mult; 773 774 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 775 776 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 777 output = line->compose.width - 1; 778 reg = (output << 16) | input; 779 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 780 781 interp_reso = vfe_calc_interp_reso(input, output); 782 phase_mult = input * (1 << (14 + interp_reso)) / output; 783 reg = (interp_reso << 28) | phase_mult; 784 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 785 786 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 787 output = line->compose.height - 1; 788 reg = (output << 16) | input; 789 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 790 791 interp_reso = vfe_calc_interp_reso(input, output); 792 phase_mult = input * (1 << (14 + interp_reso)) / output; 793 reg = (interp_reso << 28) | phase_mult; 794 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 795 796 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 797 798 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 799 output = line->compose.width / 2 - 1; 800 reg = (output << 16) | input; 801 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 802 803 interp_reso = vfe_calc_interp_reso(input, output); 804 phase_mult = input * (1 << (14 + interp_reso)) / output; 805 reg = (interp_reso << 28) | phase_mult; 806 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 807 808 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 809 output = line->compose.height - 1; 810 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 811 output = line->compose.height / 2 - 1; 812 reg = (output << 16) | input; 813 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 814 815 interp_reso = vfe_calc_interp_reso(input, output); 816 phase_mult = input * (1 << (14 + interp_reso)) / output; 817 reg = (interp_reso << 28) | phase_mult; 818 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 819 } 820 821 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 822 { 823 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 824 u32 reg; 825 u16 first, last; 826 827 first = line->crop.left; 828 last = line->crop.left + line->crop.width - 1; 829 reg = (first << 16) | last; 830 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 831 832 first = line->crop.top; 833 last = line->crop.top + line->crop.height - 1; 834 reg = (first << 16) | last; 835 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 836 837 first = line->crop.left / 2; 838 last = line->crop.left / 2 + line->crop.width / 2 - 1; 839 reg = (first << 16) | last; 840 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 841 842 first = line->crop.top; 843 last = line->crop.top + line->crop.height - 1; 844 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 845 first = line->crop.top / 2; 846 last = line->crop.top / 2 + line->crop.height / 2 - 1; 847 } 848 reg = (first << 16) | last; 849 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 850 } 851 852 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 853 { 854 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 855 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 856 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 857 858 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 859 860 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 861 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 862 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 863 864 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 865 } 866 867 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 868 { 869 /* empty */ 870 } 871 872 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 873 { 874 u32 val; 875 876 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 877 case MEDIA_BUS_FMT_YUYV8_2X8: 878 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 879 break; 880 case MEDIA_BUS_FMT_YVYU8_2X8: 881 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 882 break; 883 case MEDIA_BUS_FMT_UYVY8_2X8: 884 default: 885 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 886 break; 887 case MEDIA_BUS_FMT_VYUY8_2X8: 888 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 889 break; 890 } 891 892 val |= VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN; 893 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 894 895 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 896 val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; 897 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 898 899 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 900 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 901 902 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 903 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 904 905 val = 0xffffffff; 906 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); 907 908 val = 0xffffffff; 909 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); 910 911 val = 0xffffffff; 912 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 913 914 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 915 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 916 917 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 918 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 919 } 920 921 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 922 { 923 u32 cmd; 924 925 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 926 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 927 928 /* Make sure camif command is issued written before it is changed again */ 929 wmb(); 930 931 if (enable) 932 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 933 else 934 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 935 936 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 937 } 938 939 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 940 { 941 u32 val_lens = VFE_0_MODULE_LENS_EN_DEMUX | 942 VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE; 943 u32 val_zoom = VFE_0_MODULE_ZOOM_EN_SCALE_ENC | 944 VFE_0_MODULE_ZOOM_EN_CROP_ENC; 945 946 if (enable) { 947 vfe_reg_set(vfe, VFE_0_MODULE_LENS_EN, val_lens); 948 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 949 } else { 950 vfe_reg_clr(vfe, VFE_0_MODULE_LENS_EN, val_lens); 951 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 952 } 953 } 954 955 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 956 { 957 u32 val; 958 int ret; 959 960 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 961 val, 962 (val & VFE_0_CAMIF_STATUS_HALT), 963 CAMIF_TIMEOUT_SLEEP_US, 964 CAMIF_TIMEOUT_ALL_US); 965 if (ret < 0) 966 dev_err(dev, "%s: camif stop timeout\n", __func__); 967 968 return ret; 969 } 970 971 /* 972 * vfe_isr - VFE module interrupt handler 973 * @irq: Interrupt line 974 * @dev: VFE device 975 * 976 * Return IRQ_HANDLED on success 977 */ 978 static irqreturn_t vfe_isr(int irq, void *dev) 979 { 980 struct vfe_device *vfe = dev; 981 u32 value0, value1; 982 int i, j; 983 984 vfe->ops->isr_read(vfe, &value0, &value1); 985 986 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", 987 value0, value1); 988 989 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 990 vfe->isr_ops.reset_ack(vfe); 991 992 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 993 vfe->ops->violation_read(vfe); 994 995 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 996 vfe->isr_ops.halt_ack(vfe); 997 998 for (i = VFE_LINE_RDI0; i < vfe->line_num; i++) 999 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 1000 vfe->isr_ops.reg_update(vfe, i); 1001 1002 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 1003 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 1004 1005 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 1006 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 1007 vfe->isr_ops.sof(vfe, i); 1008 1009 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 1010 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 1011 vfe->isr_ops.comp_done(vfe, i); 1012 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 1013 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 1014 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 1015 } 1016 1017 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 1018 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 1019 vfe->isr_ops.wm_done(vfe, i); 1020 1021 return IRQ_HANDLED; 1022 } 1023 1024 static u16 vfe_get_ub_size(u8 vfe_id) 1025 { 1026 /* On VFE4.8 the ub-size is the same on both instances */ 1027 return MSM_VFE_VFE0_UB_SIZE_RDI; 1028 } 1029 1030 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 1031 { 1032 if (enable) 1033 writel_relaxed(2 << VFE_0_BUS_IMAGE_MASTER_n_SHIFT(wm), 1034 vfe->base + VFE_0_BUS_IMAGE_MASTER_CMD); 1035 else 1036 writel_relaxed(1 << VFE_0_BUS_IMAGE_MASTER_n_SHIFT(wm), 1037 vfe->base + VFE_0_BUS_IMAGE_MASTER_CMD); 1038 1039 /* The WM must be enabled before sending other commands */ 1040 wmb(); 1041 } 1042 1043 static void vfe_set_qos(struct vfe_device *vfe) 1044 { 1045 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 1046 u32 val3 = VFE_0_BUS_BDG_QOS_CFG_3_CFG; 1047 u32 val4 = VFE_0_BUS_BDG_QOS_CFG_4_CFG; 1048 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 1049 1050 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 1051 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 1052 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 1053 writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 1054 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 1055 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 1056 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 1057 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 1058 } 1059 1060 static void vfe_set_ds(struct vfe_device *vfe) 1061 { 1062 u32 val = VFE_0_BUS_BDG_DS_CFG_0_CFG; 1063 u32 val16 = VFE_0_BUS_BDG_DS_CFG_16_CFG; 1064 1065 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); 1066 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); 1067 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); 1068 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); 1069 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); 1070 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); 1071 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); 1072 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); 1073 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); 1074 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); 1075 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); 1076 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); 1077 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); 1078 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); 1079 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); 1080 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); 1081 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); 1082 } 1083 1084 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 1085 { 1086 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 1087 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 1088 1089 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 1090 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 1091 1092 /* Enforce barrier between local & global IRQ clear */ 1093 wmb(); 1094 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 1095 } 1096 1097 /* 1098 * vfe_pm_domain_off - Disable power domains specific to this VFE. 1099 * @vfe: VFE Device 1100 */ 1101 static void vfe_pm_domain_off(struct vfe_device *vfe) 1102 { 1103 struct camss *camss = vfe->camss; 1104 1105 device_link_del(camss->genpd_link[vfe->id]); 1106 } 1107 1108 /* 1109 * vfe_pm_domain_on - Enable power domains specific to this VFE. 1110 * @vfe: VFE Device 1111 */ 1112 static int vfe_pm_domain_on(struct vfe_device *vfe) 1113 { 1114 struct camss *camss = vfe->camss; 1115 enum vfe_line_id id = vfe->id; 1116 1117 camss->genpd_link[id] = device_link_add(camss->dev, camss->genpd[id], DL_FLAG_STATELESS | 1118 DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE); 1119 1120 if (!camss->genpd_link[id]) { 1121 dev_err(vfe->camss->dev, "Failed to add VFE#%d to power domain\n", id); 1122 return -EINVAL; 1123 } 1124 1125 return 0; 1126 } 1127 1128 static void vfe_violation_read(struct vfe_device *vfe) 1129 { 1130 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 1131 1132 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 1133 } 1134 1135 static const struct vfe_hw_ops_gen1 vfe_ops_gen1_4_8 = { 1136 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 1137 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 1138 .bus_enable_wr_if = vfe_bus_enable_wr_if, 1139 .bus_reload_wm = vfe_bus_reload_wm, 1140 .camif_wait_for_stop = vfe_camif_wait_for_stop, 1141 .enable_irq_common = vfe_enable_irq_common, 1142 .enable_irq_pix_line = vfe_enable_irq_pix_line, 1143 .enable_irq_wm_line = vfe_enable_irq_wm_line, 1144 .get_ub_size = vfe_get_ub_size, 1145 .halt_clear = vfe_halt_clear, 1146 .halt_request = vfe_halt_request, 1147 .set_camif_cfg = vfe_set_camif_cfg, 1148 .set_camif_cmd = vfe_set_camif_cmd, 1149 .set_cgc_override = vfe_set_cgc_override, 1150 .set_clamp_cfg = vfe_set_clamp_cfg, 1151 .set_crop_cfg = vfe_set_crop_cfg, 1152 .set_demux_cfg = vfe_set_demux_cfg, 1153 .set_ds = vfe_set_ds, 1154 .set_module_cfg = vfe_set_module_cfg, 1155 .set_qos = vfe_set_qos, 1156 .set_rdi_cid = vfe_set_rdi_cid, 1157 .set_realign_cfg = vfe_set_realign_cfg, 1158 .set_scale_cfg = vfe_set_scale_cfg, 1159 .set_xbar_cfg = vfe_set_xbar_cfg, 1160 .wm_enable = vfe_wm_enable, 1161 .wm_frame_based = vfe_wm_frame_based, 1162 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 1163 .wm_line_based = vfe_wm_line_based, 1164 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 1165 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 1166 .wm_set_ping_addr = vfe_wm_set_ping_addr, 1167 .wm_set_pong_addr = vfe_wm_set_pong_addr, 1168 .wm_set_subsample = vfe_wm_set_subsample, 1169 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 1170 }; 1171 1172 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 1173 { 1174 vfe->isr_ops = vfe_isr_ops_gen1; 1175 vfe->ops_gen1 = &vfe_ops_gen1_4_8; 1176 vfe->video_ops = vfe_video_ops_gen1; 1177 1178 vfe->line_num = VFE_LINE_NUM_GEN1; 1179 } 1180 1181 const struct vfe_hw_ops vfe_ops_4_8 = { 1182 .global_reset = vfe_global_reset, 1183 .hw_version_read = vfe_hw_version_read, 1184 .isr_read = vfe_isr_read, 1185 .isr = vfe_isr, 1186 .pm_domain_off = vfe_pm_domain_off, 1187 .pm_domain_on = vfe_pm_domain_on, 1188 .reg_update_clear = vfe_reg_update_clear, 1189 .reg_update = vfe_reg_update, 1190 .subdev_init = vfe_subdev_init, 1191 .vfe_disable = vfe_gen1_disable, 1192 .vfe_enable = vfe_gen1_enable, 1193 .vfe_halt = vfe_gen1_halt, 1194 .violation_read = vfe_violation_read, 1195 }; 1196