1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-7.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.7 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/iopoll.h> 13 14 #include "camss-vfe.h" 15 16 #define VFE_0_HW_VERSION 0x000 17 18 #define VFE_0_GLOBAL_RESET_CMD 0x018 19 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 20 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 21 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 22 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 23 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 24 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(5) 25 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(6) 26 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(7) 27 #define VFE_0_GLOBAL_RESET_CMD_DSP BIT(8) 28 #define VFE_0_GLOBAL_RESET_CMD_IDLE_CGC BIT(9) 29 30 #define VFE_0_MODULE_LENS_EN 0x040 31 #define VFE_0_MODULE_LENS_EN_DEMUX BIT(2) 32 #define VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE BIT(3) 33 34 #define VFE_0_MODULE_ZOOM_EN 0x04c 35 #define VFE_0_MODULE_ZOOM_EN_SCALE_ENC BIT(1) 36 #define VFE_0_MODULE_ZOOM_EN_CROP_ENC BIT(2) 37 #define VFE_0_MODULE_ZOOM_EN_REALIGN_BUF BIT(9) 38 39 #define VFE_0_CORE_CFG 0x050 40 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 43 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 44 #define VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN BIT(4) 45 46 #define VFE_0_IRQ_CMD 0x058 47 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 48 49 #define VFE_0_IRQ_MASK_0 0x05c 50 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 51 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 52 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 53 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 54 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 55 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 56 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 57 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 58 #define VFE_0_IRQ_MASK_1 0x060 59 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 60 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 61 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 62 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 63 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 64 65 #define VFE_0_IRQ_CLEAR_0 0x064 66 #define VFE_0_IRQ_CLEAR_1 0x068 67 68 #define VFE_0_IRQ_STATUS_0 0x06c 69 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 70 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 71 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 72 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 73 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 74 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 75 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 76 #define VFE_0_IRQ_STATUS_1 0x070 77 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 78 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 79 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 80 81 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x074 82 #define VFE_0_VIOLATION_STATUS 0x07c 83 84 #define VFE_0_BUS_CMD 0x80 85 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 86 87 #define VFE_0_BUS_CFG 0x084 88 89 #define VFE_0_BUS_XBAR_CFG_x(x) (0x90 + 0x4 * ((x) / 2)) 90 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(2) 91 #define VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN BIT(3) 92 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA (0x1 << 4) 93 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER (0x2 << 4) 94 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 95 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 96 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0x0 97 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 0xc 98 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 0xd 99 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 0xe 100 101 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x0a0 + 0x2c * (n)) 102 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x0a4 + 0x2c * (n)) 104 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x0ac + 0x2c * (n)) 105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x0b4 + 0x2c * (n)) 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT 1 107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x0b8 + 0x2c * (n)) 110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x0bc + 0x2c * (n)) 112 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x0c0 + 0x2c * (n)) 113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 114 (0x0c4 + 0x2c * (n)) 115 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 116 (0x0c8 + 0x2c * (n)) 117 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 118 119 #define VFE_0_BUS_PING_PONG_STATUS 0x338 120 121 #define VFE_0_BUS_BDG_CMD 0x400 122 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 123 124 #define VFE_0_BUS_BDG_QOS_CFG_0 0x404 125 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa9aaa9 126 #define VFE_0_BUS_BDG_QOS_CFG_1 0x408 127 #define VFE_0_BUS_BDG_QOS_CFG_2 0x40c 128 #define VFE_0_BUS_BDG_QOS_CFG_3 0x410 129 #define VFE_0_BUS_BDG_QOS_CFG_4 0x414 130 #define VFE_0_BUS_BDG_QOS_CFG_5 0x418 131 #define VFE_0_BUS_BDG_QOS_CFG_6 0x41c 132 #define VFE_0_BUS_BDG_QOS_CFG_7 0x420 133 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa9 134 135 #define VFE_0_BUS_BDG_DS_CFG_0 0x424 136 #define VFE_0_BUS_BDG_DS_CFG_0_CFG 0xcccc0011 137 #define VFE_0_BUS_BDG_DS_CFG_1 0x428 138 #define VFE_0_BUS_BDG_DS_CFG_2 0x42c 139 #define VFE_0_BUS_BDG_DS_CFG_3 0x430 140 #define VFE_0_BUS_BDG_DS_CFG_4 0x434 141 #define VFE_0_BUS_BDG_DS_CFG_5 0x438 142 #define VFE_0_BUS_BDG_DS_CFG_6 0x43c 143 #define VFE_0_BUS_BDG_DS_CFG_7 0x440 144 #define VFE_0_BUS_BDG_DS_CFG_8 0x444 145 #define VFE_0_BUS_BDG_DS_CFG_9 0x448 146 #define VFE_0_BUS_BDG_DS_CFG_10 0x44c 147 #define VFE_0_BUS_BDG_DS_CFG_11 0x450 148 #define VFE_0_BUS_BDG_DS_CFG_12 0x454 149 #define VFE_0_BUS_BDG_DS_CFG_13 0x458 150 #define VFE_0_BUS_BDG_DS_CFG_14 0x45c 151 #define VFE_0_BUS_BDG_DS_CFG_15 0x460 152 #define VFE_0_BUS_BDG_DS_CFG_16 0x464 153 #define VFE_0_BUS_BDG_DS_CFG_16_CFG 0x40000103 154 155 #define VFE_0_RDI_CFG_x(x) (0x46c + (0x4 * (x))) 156 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 157 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 158 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 159 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 160 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 161 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 162 163 #define VFE_0_CAMIF_CMD 0x478 164 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 165 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 166 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 167 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 168 #define VFE_0_CAMIF_CFG 0x47c 169 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 170 #define VFE_0_CAMIF_FRAME_CFG 0x484 171 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x488 172 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x48c 173 #define VFE_0_CAMIF_SUBSAMPLE_CFG 0x490 174 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN 0x498 175 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x49c 176 #define VFE_0_CAMIF_STATUS 0x4a4 177 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 178 179 #define VFE_0_REG_UPDATE 0x4ac 180 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 181 #define VFE_0_REG_UPDATE_line_n(n) \ 182 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 183 184 #define VFE_0_DEMUX_CFG 0x560 185 #define VFE_0_DEMUX_CFG_PERIOD 0x3 186 #define VFE_0_DEMUX_GAIN_0 0x564 187 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 188 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 189 #define VFE_0_DEMUX_GAIN_1 0x568 190 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 191 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 192 #define VFE_0_DEMUX_EVEN_CFG 0x574 193 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 194 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 195 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 196 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 197 #define VFE_0_DEMUX_ODD_CFG 0x578 198 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 199 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 200 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 201 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 202 203 #define VFE_0_SCALE_ENC_Y_CFG 0x91c 204 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x920 205 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x924 206 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x934 207 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x938 208 #define VFE_0_SCALE_ENC_CBCR_CFG 0x948 209 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x94c 210 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x950 211 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x960 212 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x964 213 214 #define VFE_0_CROP_ENC_Y_WIDTH 0x974 215 #define VFE_0_CROP_ENC_Y_HEIGHT 0x978 216 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x97c 217 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x980 218 219 #define VFE_0_CLAMP_ENC_MAX_CFG 0x984 220 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 221 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 222 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 223 #define VFE_0_CLAMP_ENC_MIN_CFG 0x988 224 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 225 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 226 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 227 228 #define VFE_0_REALIGN_BUF_CFG 0xaac 229 #define VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL BIT(2) 230 #define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3) 231 #define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4) 232 233 #define CAMIF_TIMEOUT_SLEEP_US 1000 234 #define CAMIF_TIMEOUT_ALL_US 1000000 235 236 #define MSM_VFE_VFE0_UB_SIZE 2047 237 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 238 #define MSM_VFE_VFE1_UB_SIZE 1535 239 #define MSM_VFE_VFE1_UB_SIZE_RDI (MSM_VFE_VFE1_UB_SIZE / 3) 240 241 static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 242 { 243 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 244 245 dev_err(dev, "VFE HW Version = 0x%08x\n", hw_version); 246 } 247 248 static u16 vfe_get_ub_size(u8 vfe_id) 249 { 250 if (vfe_id == 0) 251 return MSM_VFE_VFE0_UB_SIZE_RDI; 252 else if (vfe_id == 1) 253 return MSM_VFE_VFE1_UB_SIZE_RDI; 254 255 return 0; 256 } 257 258 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 259 { 260 u32 bits = readl_relaxed(vfe->base + reg); 261 262 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 263 } 264 265 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 266 { 267 u32 bits = readl_relaxed(vfe->base + reg); 268 269 writel_relaxed(bits | set_bits, vfe->base + reg); 270 } 271 272 static void vfe_global_reset(struct vfe_device *vfe) 273 { 274 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_IDLE_CGC | 275 VFE_0_GLOBAL_RESET_CMD_DSP | 276 VFE_0_GLOBAL_RESET_CMD_TESTGEN | 277 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 278 VFE_0_GLOBAL_RESET_CMD_PM | 279 VFE_0_GLOBAL_RESET_CMD_REGISTER | 280 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 281 VFE_0_GLOBAL_RESET_CMD_BUS | 282 VFE_0_GLOBAL_RESET_CMD_CAMIF | 283 VFE_0_GLOBAL_RESET_CMD_CORE; 284 285 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); 286 wmb(); 287 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 288 } 289 290 static void vfe_halt_request(struct vfe_device *vfe) 291 { 292 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 293 vfe->base + VFE_0_BUS_BDG_CMD); 294 } 295 296 static void vfe_halt_clear(struct vfe_device *vfe) 297 { 298 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 299 } 300 301 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 302 { 303 if (enable) 304 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 305 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 306 else 307 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 308 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 309 } 310 311 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 312 { 313 if (enable) 314 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 315 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 316 else 317 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 318 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 319 } 320 321 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 322 323 static int vfe_word_per_line_by_pixel(u32 format, u32 pixel_per_line) 324 { 325 int val = 0; 326 327 switch (format) { 328 case V4L2_PIX_FMT_NV12: 329 case V4L2_PIX_FMT_NV21: 330 case V4L2_PIX_FMT_NV16: 331 case V4L2_PIX_FMT_NV61: 332 val = CALC_WORD(pixel_per_line, 1, 8); 333 break; 334 case V4L2_PIX_FMT_YUYV: 335 case V4L2_PIX_FMT_YVYU: 336 case V4L2_PIX_FMT_UYVY: 337 case V4L2_PIX_FMT_VYUY: 338 val = CALC_WORD(pixel_per_line, 2, 8); 339 break; 340 } 341 342 return val; 343 } 344 345 static int vfe_word_per_line_by_bytes(u32 bytes_per_line) 346 { 347 return CALC_WORD(bytes_per_line, 1, 8); 348 } 349 350 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 351 u16 *width, u16 *height, u16 *bytesperline) 352 { 353 switch (pix->pixelformat) { 354 case V4L2_PIX_FMT_NV12: 355 case V4L2_PIX_FMT_NV21: 356 *width = pix->width; 357 *height = pix->height; 358 *bytesperline = pix->plane_fmt[0].bytesperline; 359 if (plane == 1) 360 *height /= 2; 361 break; 362 case V4L2_PIX_FMT_NV16: 363 case V4L2_PIX_FMT_NV61: 364 *width = pix->width; 365 *height = pix->height; 366 *bytesperline = pix->plane_fmt[0].bytesperline; 367 break; 368 case V4L2_PIX_FMT_YUYV: 369 case V4L2_PIX_FMT_YVYU: 370 case V4L2_PIX_FMT_VYUY: 371 case V4L2_PIX_FMT_UYVY: 372 *width = pix->width; 373 *height = pix->height; 374 *bytesperline = pix->plane_fmt[plane].bytesperline; 375 break; 376 377 } 378 } 379 380 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 381 struct v4l2_pix_format_mplane *pix, 382 u8 plane, u32 enable) 383 { 384 u32 reg; 385 386 if (enable) { 387 u16 width = 0, height = 0, bytesperline = 0, wpl; 388 389 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 390 391 wpl = vfe_word_per_line_by_pixel(pix->pixelformat, width); 392 393 reg = height - 1; 394 reg |= ((wpl + 3) / 4 - 1) << 16; 395 396 writel_relaxed(reg, vfe->base + 397 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 398 399 wpl = vfe_word_per_line_by_bytes(bytesperline); 400 401 reg = 0x3; 402 reg |= (height - 1) << 2; 403 reg |= ((wpl + 1) / 2) << 16; 404 405 writel_relaxed(reg, vfe->base + 406 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 407 } else { 408 writel_relaxed(0, vfe->base + 409 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 410 writel_relaxed(0, vfe->base + 411 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 412 } 413 } 414 415 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 416 { 417 u32 reg; 418 419 reg = readl_relaxed(vfe->base + 420 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 421 422 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 423 424 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 425 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 426 427 writel_relaxed(reg, 428 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 429 } 430 431 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 432 u32 pattern) 433 { 434 writel_relaxed(pattern, 435 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 436 } 437 438 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 439 u16 offset, u16 depth) 440 { 441 u32 reg; 442 443 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 444 depth; 445 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 446 } 447 448 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 449 { 450 wmb(); 451 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 452 wmb(); 453 } 454 455 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 456 { 457 writel_relaxed(addr, 458 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 459 } 460 461 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 462 { 463 writel_relaxed(addr, 464 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 465 } 466 467 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 468 { 469 u32 reg; 470 471 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 472 473 return (reg >> wm) & 0x1; 474 } 475 476 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 477 { 478 if (enable) 479 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); 480 else 481 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 482 } 483 484 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 485 enum vfe_line_id id) 486 { 487 u32 reg; 488 489 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 490 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 491 492 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 493 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 494 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 495 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 496 497 switch (id) { 498 case VFE_LINE_RDI0: 499 default: 500 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 501 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 502 break; 503 case VFE_LINE_RDI1: 504 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 505 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 506 break; 507 case VFE_LINE_RDI2: 508 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 509 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 510 break; 511 } 512 513 if (wm % 2 == 1) 514 reg <<= 16; 515 516 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 517 } 518 519 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 520 { 521 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 522 vfe->base + 523 VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 524 } 525 526 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 527 enum vfe_line_id id) 528 { 529 u32 reg; 530 531 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 532 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 533 534 switch (id) { 535 case VFE_LINE_RDI0: 536 default: 537 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 538 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 539 break; 540 case VFE_LINE_RDI1: 541 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 542 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 543 break; 544 case VFE_LINE_RDI2: 545 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 546 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 547 break; 548 } 549 550 if (wm % 2 == 1) 551 reg <<= 16; 552 553 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 554 } 555 556 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 557 u8 enable) 558 { 559 struct vfe_line *line = container_of(output, struct vfe_line, output); 560 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 561 u32 reg; 562 563 switch (p) { 564 case V4L2_PIX_FMT_NV12: 565 case V4L2_PIX_FMT_NV21: 566 case V4L2_PIX_FMT_NV16: 567 case V4L2_PIX_FMT_NV61: 568 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 569 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 570 571 if (output->wm_idx[0] % 2 == 1) 572 reg <<= 16; 573 574 if (enable) 575 vfe_reg_set(vfe, 576 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 577 reg); 578 else 579 vfe_reg_clr(vfe, 580 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 581 reg); 582 583 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 584 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 585 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 586 587 if (output->wm_idx[1] % 2 == 1) 588 reg <<= 16; 589 590 if (enable) 591 vfe_reg_set(vfe, 592 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 593 reg); 594 else 595 vfe_reg_clr(vfe, 596 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 597 reg); 598 break; 599 case V4L2_PIX_FMT_YUYV: 600 case V4L2_PIX_FMT_YVYU: 601 case V4L2_PIX_FMT_VYUY: 602 case V4L2_PIX_FMT_UYVY: 603 reg = VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN; 604 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 605 606 if (p == V4L2_PIX_FMT_YUYV || p == V4L2_PIX_FMT_YVYU) 607 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 608 609 if (output->wm_idx[0] % 2 == 1) 610 reg <<= 16; 611 612 if (enable) 613 vfe_reg_set(vfe, 614 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 615 reg); 616 else 617 vfe_reg_clr(vfe, 618 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 619 reg); 620 break; 621 default: 622 break; 623 } 624 } 625 626 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 627 u8 enable) 628 { 629 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 630 u32 val = VFE_0_MODULE_ZOOM_EN_REALIGN_BUF; 631 632 if (p != V4L2_PIX_FMT_YUYV && p != V4L2_PIX_FMT_YVYU && 633 p != V4L2_PIX_FMT_VYUY && p != V4L2_PIX_FMT_UYVY) 634 return; 635 636 if (enable) { 637 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val); 638 } else { 639 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val); 640 return; 641 } 642 643 val = VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE; 644 645 if (p == V4L2_PIX_FMT_UYVY || p == V4L2_PIX_FMT_YUYV) 646 val |= VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL; 647 else 648 val |= VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL; 649 650 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); 651 } 652 653 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 654 { 655 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 656 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 657 658 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 659 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 660 } 661 662 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 663 { 664 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 665 wmb(); 666 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 667 wmb(); 668 } 669 670 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 671 enum vfe_line_id line_id) 672 { 673 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 674 } 675 676 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 677 enum vfe_line_id line_id, u8 enable) 678 { 679 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 680 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 681 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 682 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 683 684 if (enable) { 685 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 686 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 687 } else { 688 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 689 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 690 } 691 } 692 693 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 694 enum vfe_line_id line_id, u8 enable) 695 { 696 struct vfe_output *output = &vfe->line[line_id].output; 697 unsigned int i; 698 u32 irq_en0; 699 u32 irq_en1; 700 u32 comp_mask = 0; 701 702 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 703 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 704 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 705 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 706 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 707 for (i = 0; i < output->wm_num; i++) { 708 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 709 output->wm_idx[i]); 710 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 711 } 712 713 if (enable) { 714 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 715 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 716 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 717 } else { 718 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 719 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 720 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 721 } 722 } 723 724 static void vfe_enable_irq_common(struct vfe_device *vfe) 725 { 726 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 727 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 728 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 729 730 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 731 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 732 } 733 734 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 735 { 736 u32 val, even_cfg, odd_cfg; 737 738 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 739 740 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 741 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 742 743 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 744 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 745 746 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 747 case MEDIA_BUS_FMT_YUYV8_2X8: 748 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 749 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 750 break; 751 case MEDIA_BUS_FMT_YVYU8_2X8: 752 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 753 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 754 break; 755 case MEDIA_BUS_FMT_UYVY8_2X8: 756 default: 757 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 758 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 759 break; 760 case MEDIA_BUS_FMT_VYUY8_2X8: 761 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 762 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 763 break; 764 } 765 766 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 767 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 768 } 769 770 static inline u8 vfe_calc_interp_reso(u16 input, u16 output) 771 { 772 if (input / output >= 16) 773 return 0; 774 775 if (input / output >= 8) 776 return 1; 777 778 if (input / output >= 4) 779 return 2; 780 781 return 3; 782 } 783 784 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 785 { 786 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 787 u32 reg; 788 u16 input, output; 789 u8 interp_reso; 790 u32 phase_mult; 791 792 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 793 794 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 795 output = line->compose.width - 1; 796 reg = (output << 16) | input; 797 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 798 799 interp_reso = vfe_calc_interp_reso(input, output); 800 phase_mult = input * (1 << (14 + interp_reso)) / output; 801 reg = (interp_reso << 28) | phase_mult; 802 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 803 804 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 805 output = line->compose.height - 1; 806 reg = (output << 16) | input; 807 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 808 809 interp_reso = vfe_calc_interp_reso(input, output); 810 phase_mult = input * (1 << (14 + interp_reso)) / output; 811 reg = (interp_reso << 28) | phase_mult; 812 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 813 814 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 815 816 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 817 output = line->compose.width / 2 - 1; 818 reg = (output << 16) | input; 819 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 820 821 interp_reso = vfe_calc_interp_reso(input, output); 822 phase_mult = input * (1 << (14 + interp_reso)) / output; 823 reg = (interp_reso << 28) | phase_mult; 824 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 825 826 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 827 output = line->compose.height - 1; 828 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 829 output = line->compose.height / 2 - 1; 830 reg = (output << 16) | input; 831 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 832 833 interp_reso = vfe_calc_interp_reso(input, output); 834 phase_mult = input * (1 << (14 + interp_reso)) / output; 835 reg = (interp_reso << 28) | phase_mult; 836 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 837 } 838 839 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 840 { 841 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 842 u32 reg; 843 u16 first, last; 844 845 first = line->crop.left; 846 last = line->crop.left + line->crop.width - 1; 847 reg = (first << 16) | last; 848 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 849 850 first = line->crop.top; 851 last = line->crop.top + line->crop.height - 1; 852 reg = (first << 16) | last; 853 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 854 855 first = line->crop.left / 2; 856 last = line->crop.left / 2 + line->crop.width / 2 - 1; 857 reg = (first << 16) | last; 858 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 859 860 first = line->crop.top; 861 last = line->crop.top + line->crop.height - 1; 862 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 863 first = line->crop.top / 2; 864 last = line->crop.top / 2 + line->crop.height / 2 - 1; 865 } 866 reg = (first << 16) | last; 867 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 868 } 869 870 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 871 { 872 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 873 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 874 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 875 876 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 877 878 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 879 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 880 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 881 882 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 883 } 884 885 static void vfe_set_qos(struct vfe_device *vfe) 886 { 887 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 888 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 889 890 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 891 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 892 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 893 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 894 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 895 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 896 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 897 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 898 } 899 900 static void vfe_set_ds(struct vfe_device *vfe) 901 { 902 u32 val = VFE_0_BUS_BDG_DS_CFG_0_CFG; 903 u32 val16 = VFE_0_BUS_BDG_DS_CFG_16_CFG; 904 905 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); 906 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); 907 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); 908 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); 909 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); 910 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); 911 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); 912 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); 913 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); 914 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); 915 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); 916 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); 917 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); 918 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); 919 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); 920 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); 921 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); 922 } 923 924 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 925 { 926 /* empty */ 927 } 928 929 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 930 { 931 u32 val; 932 933 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 934 case MEDIA_BUS_FMT_YUYV8_2X8: 935 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 936 break; 937 case MEDIA_BUS_FMT_YVYU8_2X8: 938 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 939 break; 940 case MEDIA_BUS_FMT_UYVY8_2X8: 941 default: 942 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 943 break; 944 case MEDIA_BUS_FMT_VYUY8_2X8: 945 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 946 break; 947 } 948 949 val |= VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN; 950 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 951 952 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 953 val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; 954 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 955 956 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 957 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 958 959 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 960 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 961 962 val = 0xffffffff; 963 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); 964 965 val = 0xffffffff; 966 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); 967 968 val = 0xffffffff; 969 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 970 971 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 972 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 973 974 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 975 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 976 } 977 978 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 979 { 980 u32 cmd; 981 982 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 983 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 984 wmb(); 985 986 if (enable) 987 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 988 else 989 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 990 991 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 992 } 993 994 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 995 { 996 u32 val_lens = VFE_0_MODULE_LENS_EN_DEMUX | 997 VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE; 998 u32 val_zoom = VFE_0_MODULE_ZOOM_EN_SCALE_ENC | 999 VFE_0_MODULE_ZOOM_EN_CROP_ENC; 1000 1001 if (enable) { 1002 vfe_reg_set(vfe, VFE_0_MODULE_LENS_EN, val_lens); 1003 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 1004 } else { 1005 vfe_reg_clr(vfe, VFE_0_MODULE_LENS_EN, val_lens); 1006 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 1007 } 1008 } 1009 1010 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 1011 { 1012 u32 val; 1013 int ret; 1014 1015 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 1016 val, 1017 (val & VFE_0_CAMIF_STATUS_HALT), 1018 CAMIF_TIMEOUT_SLEEP_US, 1019 CAMIF_TIMEOUT_ALL_US); 1020 if (ret < 0) 1021 dev_err(dev, "%s: camif stop timeout\n", __func__); 1022 1023 return ret; 1024 } 1025 1026 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 1027 { 1028 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 1029 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 1030 1031 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 1032 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 1033 1034 wmb(); 1035 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 1036 } 1037 1038 static void vfe_violation_read(struct vfe_device *vfe) 1039 { 1040 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 1041 1042 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 1043 } 1044 1045 /* 1046 * vfe_isr - ISPIF module interrupt handler 1047 * @irq: Interrupt line 1048 * @dev: VFE device 1049 * 1050 * Return IRQ_HANDLED on success 1051 */ 1052 static irqreturn_t vfe_isr(int irq, void *dev) 1053 { 1054 struct vfe_device *vfe = dev; 1055 u32 value0, value1; 1056 int i, j; 1057 1058 vfe->ops->isr_read(vfe, &value0, &value1); 1059 1060 trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n", 1061 value0, value1); 1062 1063 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 1064 vfe->isr_ops.reset_ack(vfe); 1065 1066 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 1067 vfe->ops->violation_read(vfe); 1068 1069 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 1070 vfe->isr_ops.halt_ack(vfe); 1071 1072 for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 1073 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 1074 vfe->isr_ops.reg_update(vfe, i); 1075 1076 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 1077 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 1078 1079 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 1080 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 1081 vfe->isr_ops.sof(vfe, i); 1082 1083 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 1084 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 1085 vfe->isr_ops.comp_done(vfe, i); 1086 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 1087 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 1088 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 1089 } 1090 1091 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 1092 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 1093 vfe->isr_ops.wm_done(vfe, i); 1094 1095 return IRQ_HANDLED; 1096 } 1097 1098 const struct vfe_hw_ops vfe_ops_4_7 = { 1099 .hw_version_read = vfe_hw_version_read, 1100 .get_ub_size = vfe_get_ub_size, 1101 .global_reset = vfe_global_reset, 1102 .halt_request = vfe_halt_request, 1103 .halt_clear = vfe_halt_clear, 1104 .wm_enable = vfe_wm_enable, 1105 .wm_frame_based = vfe_wm_frame_based, 1106 .wm_line_based = vfe_wm_line_based, 1107 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 1108 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 1109 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 1110 .bus_reload_wm = vfe_bus_reload_wm, 1111 .wm_set_ping_addr = vfe_wm_set_ping_addr, 1112 .wm_set_pong_addr = vfe_wm_set_pong_addr, 1113 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 1114 .bus_enable_wr_if = vfe_bus_enable_wr_if, 1115 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 1116 .wm_set_subsample = vfe_wm_set_subsample, 1117 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 1118 .set_xbar_cfg = vfe_set_xbar_cfg, 1119 .set_realign_cfg = vfe_set_realign_cfg, 1120 .set_rdi_cid = vfe_set_rdi_cid, 1121 .reg_update = vfe_reg_update, 1122 .reg_update_clear = vfe_reg_update_clear, 1123 .enable_irq_wm_line = vfe_enable_irq_wm_line, 1124 .enable_irq_pix_line = vfe_enable_irq_pix_line, 1125 .enable_irq_common = vfe_enable_irq_common, 1126 .set_demux_cfg = vfe_set_demux_cfg, 1127 .set_scale_cfg = vfe_set_scale_cfg, 1128 .set_crop_cfg = vfe_set_crop_cfg, 1129 .set_clamp_cfg = vfe_set_clamp_cfg, 1130 .set_qos = vfe_set_qos, 1131 .set_ds = vfe_set_ds, 1132 .set_cgc_override = vfe_set_cgc_override, 1133 .set_camif_cfg = vfe_set_camif_cfg, 1134 .set_camif_cmd = vfe_set_camif_cmd, 1135 .set_module_cfg = vfe_set_module_cfg, 1136 .camif_wait_for_stop = vfe_camif_wait_for_stop, 1137 .isr_read = vfe_isr_read, 1138 .violation_read = vfe_violation_read, 1139 .isr = vfe_isr, 1140 }; 1141