1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-7.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.7 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 15 #include "camss-vfe.h" 16 17 #define VFE_0_HW_VERSION 0x000 18 19 #define VFE_0_GLOBAL_RESET_CMD 0x018 20 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 21 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 22 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 23 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 24 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 25 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(5) 26 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(6) 27 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(7) 28 #define VFE_0_GLOBAL_RESET_CMD_DSP BIT(8) 29 #define VFE_0_GLOBAL_RESET_CMD_IDLE_CGC BIT(9) 30 31 #define VFE_0_MODULE_LENS_EN 0x040 32 #define VFE_0_MODULE_LENS_EN_DEMUX BIT(2) 33 #define VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE BIT(3) 34 35 #define VFE_0_MODULE_ZOOM_EN 0x04c 36 #define VFE_0_MODULE_ZOOM_EN_SCALE_ENC BIT(1) 37 #define VFE_0_MODULE_ZOOM_EN_CROP_ENC BIT(2) 38 #define VFE_0_MODULE_ZOOM_EN_REALIGN_BUF BIT(9) 39 40 #define VFE_0_CORE_CFG 0x050 41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 43 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 44 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 45 #define VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN BIT(4) 46 47 #define VFE_0_IRQ_CMD 0x058 48 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 49 50 #define VFE_0_IRQ_MASK_0 0x05c 51 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 52 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 53 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 54 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 55 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 56 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 57 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 58 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 59 #define VFE_0_IRQ_MASK_1 0x060 60 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 61 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 62 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 63 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 64 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 65 66 #define VFE_0_IRQ_CLEAR_0 0x064 67 #define VFE_0_IRQ_CLEAR_1 0x068 68 69 #define VFE_0_IRQ_STATUS_0 0x06c 70 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 71 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 72 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 73 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 74 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 75 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 76 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 77 #define VFE_0_IRQ_STATUS_1 0x070 78 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 79 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 80 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 81 82 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x074 83 #define VFE_0_VIOLATION_STATUS 0x07c 84 85 #define VFE_0_BUS_CMD 0x80 86 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 87 88 #define VFE_0_BUS_CFG 0x084 89 90 #define VFE_0_BUS_XBAR_CFG_x(x) (0x90 + 0x4 * ((x) / 2)) 91 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(2) 92 #define VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN BIT(3) 93 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA (0x1 << 4) 94 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER (0x2 << 4) 95 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 96 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 97 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0x0 98 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 0xc 99 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 0xd 100 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 0xe 101 102 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x0a0 + 0x2c * (n)) 103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 104 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x0a4 + 0x2c * (n)) 105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x0ac + 0x2c * (n)) 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x0b4 + 0x2c * (n)) 107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT 1 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x0b8 + 0x2c * (n)) 111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 112 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x0bc + 0x2c * (n)) 113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x0c0 + 0x2c * (n)) 114 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 115 (0x0c4 + 0x2c * (n)) 116 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 117 (0x0c8 + 0x2c * (n)) 118 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 119 120 #define VFE_0_BUS_PING_PONG_STATUS 0x338 121 122 #define VFE_0_BUS_BDG_CMD 0x400 123 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 124 125 #define VFE_0_BUS_BDG_QOS_CFG_0 0x404 126 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa9aaa9 127 #define VFE_0_BUS_BDG_QOS_CFG_1 0x408 128 #define VFE_0_BUS_BDG_QOS_CFG_2 0x40c 129 #define VFE_0_BUS_BDG_QOS_CFG_3 0x410 130 #define VFE_0_BUS_BDG_QOS_CFG_4 0x414 131 #define VFE_0_BUS_BDG_QOS_CFG_5 0x418 132 #define VFE_0_BUS_BDG_QOS_CFG_6 0x41c 133 #define VFE_0_BUS_BDG_QOS_CFG_7 0x420 134 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa9 135 136 #define VFE48_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 137 #define VFE48_0_BUS_BDG_QOS_CFG_3_CFG 0xaa55aaa5 138 #define VFE48_0_BUS_BDG_QOS_CFG_4_CFG 0xaa55aa55 139 #define VFE48_0_BUS_BDG_QOS_CFG_7_CFG 0x0005aa55 140 141 #define VFE_0_BUS_BDG_DS_CFG_0 0x424 142 #define VFE_0_BUS_BDG_DS_CFG_0_CFG 0xcccc0011 143 #define VFE_0_BUS_BDG_DS_CFG_1 0x428 144 #define VFE_0_BUS_BDG_DS_CFG_2 0x42c 145 #define VFE_0_BUS_BDG_DS_CFG_3 0x430 146 #define VFE_0_BUS_BDG_DS_CFG_4 0x434 147 #define VFE_0_BUS_BDG_DS_CFG_5 0x438 148 #define VFE_0_BUS_BDG_DS_CFG_6 0x43c 149 #define VFE_0_BUS_BDG_DS_CFG_7 0x440 150 #define VFE_0_BUS_BDG_DS_CFG_8 0x444 151 #define VFE_0_BUS_BDG_DS_CFG_9 0x448 152 #define VFE_0_BUS_BDG_DS_CFG_10 0x44c 153 #define VFE_0_BUS_BDG_DS_CFG_11 0x450 154 #define VFE_0_BUS_BDG_DS_CFG_12 0x454 155 #define VFE_0_BUS_BDG_DS_CFG_13 0x458 156 #define VFE_0_BUS_BDG_DS_CFG_14 0x45c 157 #define VFE_0_BUS_BDG_DS_CFG_15 0x460 158 #define VFE_0_BUS_BDG_DS_CFG_16 0x464 159 #define VFE_0_BUS_BDG_DS_CFG_16_CFG 0x40000103 160 161 #define VFE48_0_BUS_BDG_DS_CFG_0_CFG 0xcccc1111 162 #define VFE48_0_BUS_BDG_DS_CFG_16_CFG 0x00000110 163 164 #define VFE_0_RDI_CFG_x(x) (0x46c + (0x4 * (x))) 165 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 166 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 167 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 168 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 169 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 170 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 171 172 #define VFE_0_CAMIF_CMD 0x478 173 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 174 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 175 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 176 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 177 #define VFE_0_CAMIF_CFG 0x47c 178 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 179 #define VFE_0_CAMIF_FRAME_CFG 0x484 180 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x488 181 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x48c 182 #define VFE_0_CAMIF_SUBSAMPLE_CFG 0x490 183 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN 0x498 184 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x49c 185 #define VFE_0_CAMIF_STATUS 0x4a4 186 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 187 188 #define VFE_0_REG_UPDATE 0x4ac 189 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 190 #define VFE_0_REG_UPDATE_line_n(n) \ 191 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 192 193 #define VFE_0_DEMUX_CFG 0x560 194 #define VFE_0_DEMUX_CFG_PERIOD 0x3 195 #define VFE_0_DEMUX_GAIN_0 0x564 196 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 197 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 198 #define VFE_0_DEMUX_GAIN_1 0x568 199 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 200 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 201 #define VFE_0_DEMUX_EVEN_CFG 0x574 202 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 203 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 204 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 205 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 206 #define VFE_0_DEMUX_ODD_CFG 0x578 207 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 208 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 209 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 210 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 211 212 #define VFE_0_SCALE_ENC_Y_CFG 0x91c 213 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x920 214 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x924 215 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x934 216 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x938 217 #define VFE_0_SCALE_ENC_CBCR_CFG 0x948 218 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x94c 219 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x950 220 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x960 221 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x964 222 223 #define VFE_0_CROP_ENC_Y_WIDTH 0x974 224 #define VFE_0_CROP_ENC_Y_HEIGHT 0x978 225 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x97c 226 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x980 227 228 #define VFE_0_CLAMP_ENC_MAX_CFG 0x984 229 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 230 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 231 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 232 #define VFE_0_CLAMP_ENC_MIN_CFG 0x988 233 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 234 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 235 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 236 237 #define VFE_0_REALIGN_BUF_CFG 0xaac 238 #define VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL BIT(2) 239 #define VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL BIT(3) 240 #define VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE BIT(4) 241 242 #define VFE48_0_BUS_IMAGE_MASTER_CMD 0xcec 243 #define VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(x) (2 * (x)) 244 245 #define CAMIF_TIMEOUT_SLEEP_US 1000 246 #define CAMIF_TIMEOUT_ALL_US 1000000 247 248 #define MSM_VFE_VFE0_UB_SIZE 2047 249 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 250 #define MSM_VFE_VFE1_UB_SIZE 1535 251 #define MSM_VFE_VFE1_UB_SIZE_RDI (MSM_VFE_VFE1_UB_SIZE / 3) 252 253 static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 254 { 255 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 256 257 dev_err(dev, "VFE HW Version = 0x%08x\n", hw_version); 258 } 259 260 static u16 vfe47_get_ub_size(u8 vfe_id) 261 { 262 if (vfe_id == 0) 263 return MSM_VFE_VFE0_UB_SIZE_RDI; 264 else if (vfe_id == 1) 265 return MSM_VFE_VFE1_UB_SIZE_RDI; 266 267 return 0; 268 } 269 270 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 271 { 272 u32 bits = readl_relaxed(vfe->base + reg); 273 274 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 275 } 276 277 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 278 { 279 u32 bits = readl_relaxed(vfe->base + reg); 280 281 writel_relaxed(bits | set_bits, vfe->base + reg); 282 } 283 284 static void vfe_global_reset(struct vfe_device *vfe) 285 { 286 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_IDLE_CGC | 287 VFE_0_GLOBAL_RESET_CMD_DSP | 288 VFE_0_GLOBAL_RESET_CMD_TESTGEN | 289 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 290 VFE_0_GLOBAL_RESET_CMD_PM | 291 VFE_0_GLOBAL_RESET_CMD_REGISTER | 292 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 293 VFE_0_GLOBAL_RESET_CMD_BUS | 294 VFE_0_GLOBAL_RESET_CMD_CAMIF | 295 VFE_0_GLOBAL_RESET_CMD_CORE; 296 297 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); 298 wmb(); 299 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 300 } 301 302 static void vfe_halt_request(struct vfe_device *vfe) 303 { 304 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 305 vfe->base + VFE_0_BUS_BDG_CMD); 306 } 307 308 static void vfe_halt_clear(struct vfe_device *vfe) 309 { 310 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 311 } 312 313 static void vfe47_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 314 { 315 if (enable) 316 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 317 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 318 else 319 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 320 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 321 } 322 323 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 324 { 325 if (enable) 326 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 327 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 328 else 329 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), 330 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_BASED_SHIFT); 331 } 332 333 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 334 335 static int vfe_word_per_line_by_pixel(u32 format, u32 pixel_per_line) 336 { 337 int val = 0; 338 339 switch (format) { 340 case V4L2_PIX_FMT_NV12: 341 case V4L2_PIX_FMT_NV21: 342 case V4L2_PIX_FMT_NV16: 343 case V4L2_PIX_FMT_NV61: 344 val = CALC_WORD(pixel_per_line, 1, 8); 345 break; 346 case V4L2_PIX_FMT_YUYV: 347 case V4L2_PIX_FMT_YVYU: 348 case V4L2_PIX_FMT_UYVY: 349 case V4L2_PIX_FMT_VYUY: 350 val = CALC_WORD(pixel_per_line, 2, 8); 351 break; 352 } 353 354 return val; 355 } 356 357 static int vfe_word_per_line_by_bytes(u32 bytes_per_line) 358 { 359 return CALC_WORD(bytes_per_line, 1, 8); 360 } 361 362 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 363 u16 *width, u16 *height, u16 *bytesperline) 364 { 365 switch (pix->pixelformat) { 366 case V4L2_PIX_FMT_NV12: 367 case V4L2_PIX_FMT_NV21: 368 *width = pix->width; 369 *height = pix->height; 370 *bytesperline = pix->plane_fmt[0].bytesperline; 371 if (plane == 1) 372 *height /= 2; 373 break; 374 case V4L2_PIX_FMT_NV16: 375 case V4L2_PIX_FMT_NV61: 376 *width = pix->width; 377 *height = pix->height; 378 *bytesperline = pix->plane_fmt[0].bytesperline; 379 break; 380 case V4L2_PIX_FMT_YUYV: 381 case V4L2_PIX_FMT_YVYU: 382 case V4L2_PIX_FMT_VYUY: 383 case V4L2_PIX_FMT_UYVY: 384 *width = pix->width; 385 *height = pix->height; 386 *bytesperline = pix->plane_fmt[plane].bytesperline; 387 break; 388 389 } 390 } 391 392 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 393 struct v4l2_pix_format_mplane *pix, 394 u8 plane, u32 enable) 395 { 396 u32 reg; 397 398 if (enable) { 399 u16 width = 0, height = 0, bytesperline = 0, wpl; 400 401 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 402 403 wpl = vfe_word_per_line_by_pixel(pix->pixelformat, width); 404 405 reg = height - 1; 406 reg |= ((wpl + 3) / 4 - 1) << 16; 407 408 writel_relaxed(reg, vfe->base + 409 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 410 411 wpl = vfe_word_per_line_by_bytes(bytesperline); 412 413 reg = 0x3; 414 reg |= (height - 1) << 2; 415 reg |= ((wpl + 1) / 2) << 16; 416 417 writel_relaxed(reg, vfe->base + 418 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 419 } else { 420 writel_relaxed(0, vfe->base + 421 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 422 writel_relaxed(0, vfe->base + 423 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 424 } 425 } 426 427 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 428 { 429 u32 reg; 430 431 reg = readl_relaxed(vfe->base + 432 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 433 434 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 435 436 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 437 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 438 439 writel_relaxed(reg, 440 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 441 } 442 443 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 444 u32 pattern) 445 { 446 writel_relaxed(pattern, 447 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 448 } 449 450 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 451 u16 offset, u16 depth) 452 { 453 u32 reg; 454 455 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 456 depth; 457 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 458 } 459 460 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 461 { 462 wmb(); 463 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 464 wmb(); 465 } 466 467 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 468 { 469 writel_relaxed(addr, 470 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 471 } 472 473 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 474 { 475 writel_relaxed(addr, 476 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 477 } 478 479 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 480 { 481 u32 reg; 482 483 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 484 485 return (reg >> wm) & 0x1; 486 } 487 488 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 489 { 490 if (enable) 491 writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG); 492 else 493 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 494 } 495 496 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 497 enum vfe_line_id id) 498 { 499 u32 reg; 500 501 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 502 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 503 504 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 505 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 506 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 507 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 508 509 switch (id) { 510 case VFE_LINE_RDI0: 511 default: 512 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 513 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 514 break; 515 case VFE_LINE_RDI1: 516 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 517 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 518 break; 519 case VFE_LINE_RDI2: 520 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 521 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 522 break; 523 } 524 525 if (wm % 2 == 1) 526 reg <<= 16; 527 528 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 529 } 530 531 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 532 { 533 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 534 vfe->base + 535 VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 536 } 537 538 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 539 enum vfe_line_id id) 540 { 541 u32 reg; 542 543 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 544 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 545 546 switch (id) { 547 case VFE_LINE_RDI0: 548 default: 549 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 550 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 551 break; 552 case VFE_LINE_RDI1: 553 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 554 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 555 break; 556 case VFE_LINE_RDI2: 557 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 558 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 559 break; 560 } 561 562 if (wm % 2 == 1) 563 reg <<= 16; 564 565 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 566 } 567 568 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 569 u8 enable) 570 { 571 struct vfe_line *line = container_of(output, struct vfe_line, output); 572 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 573 u32 reg; 574 575 switch (p) { 576 case V4L2_PIX_FMT_NV12: 577 case V4L2_PIX_FMT_NV21: 578 case V4L2_PIX_FMT_NV16: 579 case V4L2_PIX_FMT_NV61: 580 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 581 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 582 583 if (output->wm_idx[0] % 2 == 1) 584 reg <<= 16; 585 586 if (enable) 587 vfe_reg_set(vfe, 588 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 589 reg); 590 else 591 vfe_reg_clr(vfe, 592 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 593 reg); 594 595 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 596 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 597 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 598 599 if (output->wm_idx[1] % 2 == 1) 600 reg <<= 16; 601 602 if (enable) 603 vfe_reg_set(vfe, 604 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 605 reg); 606 else 607 vfe_reg_clr(vfe, 608 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[1]), 609 reg); 610 break; 611 case V4L2_PIX_FMT_YUYV: 612 case V4L2_PIX_FMT_YVYU: 613 case V4L2_PIX_FMT_VYUY: 614 case V4L2_PIX_FMT_UYVY: 615 reg = VFE_0_BUS_XBAR_CFG_x_M_REALIGN_BUF_EN; 616 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 617 618 if (p == V4L2_PIX_FMT_YUYV || p == V4L2_PIX_FMT_YVYU) 619 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 620 621 if (output->wm_idx[0] % 2 == 1) 622 reg <<= 16; 623 624 if (enable) 625 vfe_reg_set(vfe, 626 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 627 reg); 628 else 629 vfe_reg_clr(vfe, 630 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]), 631 reg); 632 break; 633 default: 634 break; 635 } 636 } 637 638 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 639 u8 enable) 640 { 641 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 642 u32 val = VFE_0_MODULE_ZOOM_EN_REALIGN_BUF; 643 644 if (p != V4L2_PIX_FMT_YUYV && p != V4L2_PIX_FMT_YVYU && 645 p != V4L2_PIX_FMT_VYUY && p != V4L2_PIX_FMT_UYVY) 646 return; 647 648 if (enable) { 649 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val); 650 } else { 651 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val); 652 return; 653 } 654 655 val = VFE_0_REALIGN_BUF_CFG_HSUB_ENABLE; 656 657 if (p == V4L2_PIX_FMT_UYVY || p == V4L2_PIX_FMT_YUYV) 658 val |= VFE_0_REALIGN_BUF_CFG_CR_ODD_PIXEL; 659 else 660 val |= VFE_0_REALIGN_BUF_CFG_CB_ODD_PIXEL; 661 662 writel_relaxed(val, vfe->base + VFE_0_REALIGN_BUF_CFG); 663 } 664 665 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 666 { 667 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 668 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 669 670 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 671 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 672 } 673 674 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 675 { 676 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 677 wmb(); 678 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 679 wmb(); 680 } 681 682 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 683 enum vfe_line_id line_id) 684 { 685 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 686 } 687 688 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 689 enum vfe_line_id line_id, u8 enable) 690 { 691 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 692 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 693 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 694 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 695 696 if (enable) { 697 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 698 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 699 } else { 700 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 701 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 702 } 703 } 704 705 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 706 enum vfe_line_id line_id, u8 enable) 707 { 708 struct vfe_output *output = &vfe->line[line_id].output; 709 unsigned int i; 710 u32 irq_en0; 711 u32 irq_en1; 712 u32 comp_mask = 0; 713 714 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 715 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 716 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 717 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 718 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 719 for (i = 0; i < output->wm_num; i++) { 720 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 721 output->wm_idx[i]); 722 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 723 } 724 725 if (enable) { 726 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 727 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 728 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 729 } else { 730 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 731 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 732 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 733 } 734 } 735 736 static void vfe_enable_irq_common(struct vfe_device *vfe) 737 { 738 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 739 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 740 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 741 742 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 743 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 744 } 745 746 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 747 { 748 u32 val, even_cfg, odd_cfg; 749 750 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 751 752 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 753 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 754 755 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 756 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 757 758 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 759 case MEDIA_BUS_FMT_YUYV8_2X8: 760 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 761 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 762 break; 763 case MEDIA_BUS_FMT_YVYU8_2X8: 764 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 765 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 766 break; 767 case MEDIA_BUS_FMT_UYVY8_2X8: 768 default: 769 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 770 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 771 break; 772 case MEDIA_BUS_FMT_VYUY8_2X8: 773 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 774 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 775 break; 776 } 777 778 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 779 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 780 } 781 782 static inline u8 vfe_calc_interp_reso(u16 input, u16 output) 783 { 784 if (input / output >= 16) 785 return 0; 786 787 if (input / output >= 8) 788 return 1; 789 790 if (input / output >= 4) 791 return 2; 792 793 return 3; 794 } 795 796 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 797 { 798 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 799 u32 reg; 800 u16 input, output; 801 u8 interp_reso; 802 u32 phase_mult; 803 804 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 805 806 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 807 output = line->compose.width - 1; 808 reg = (output << 16) | input; 809 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 810 811 interp_reso = vfe_calc_interp_reso(input, output); 812 phase_mult = input * (1 << (14 + interp_reso)) / output; 813 reg = (interp_reso << 28) | phase_mult; 814 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 815 816 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 817 output = line->compose.height - 1; 818 reg = (output << 16) | input; 819 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 820 821 interp_reso = vfe_calc_interp_reso(input, output); 822 phase_mult = input * (1 << (14 + interp_reso)) / output; 823 reg = (interp_reso << 28) | phase_mult; 824 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 825 826 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 827 828 input = line->fmt[MSM_VFE_PAD_SINK].width - 1; 829 output = line->compose.width / 2 - 1; 830 reg = (output << 16) | input; 831 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 832 833 interp_reso = vfe_calc_interp_reso(input, output); 834 phase_mult = input * (1 << (14 + interp_reso)) / output; 835 reg = (interp_reso << 28) | phase_mult; 836 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 837 838 input = line->fmt[MSM_VFE_PAD_SINK].height - 1; 839 output = line->compose.height - 1; 840 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 841 output = line->compose.height / 2 - 1; 842 reg = (output << 16) | input; 843 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 844 845 interp_reso = vfe_calc_interp_reso(input, output); 846 phase_mult = input * (1 << (14 + interp_reso)) / output; 847 reg = (interp_reso << 28) | phase_mult; 848 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 849 } 850 851 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 852 { 853 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 854 u32 reg; 855 u16 first, last; 856 857 first = line->crop.left; 858 last = line->crop.left + line->crop.width - 1; 859 reg = (first << 16) | last; 860 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 861 862 first = line->crop.top; 863 last = line->crop.top + line->crop.height - 1; 864 reg = (first << 16) | last; 865 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 866 867 first = line->crop.left / 2; 868 last = line->crop.left / 2 + line->crop.width / 2 - 1; 869 reg = (first << 16) | last; 870 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 871 872 first = line->crop.top; 873 last = line->crop.top + line->crop.height - 1; 874 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 875 first = line->crop.top / 2; 876 last = line->crop.top / 2 + line->crop.height / 2 - 1; 877 } 878 reg = (first << 16) | last; 879 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 880 } 881 882 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 883 { 884 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 885 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 886 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 887 888 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 889 890 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 891 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 892 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 893 894 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 895 } 896 897 static void vfe47_set_qos(struct vfe_device *vfe) 898 { 899 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 900 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 901 902 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 903 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 904 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 905 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 906 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 907 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 908 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 909 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 910 } 911 912 static void vfe47_set_ds(struct vfe_device *vfe) 913 { 914 u32 val = VFE_0_BUS_BDG_DS_CFG_0_CFG; 915 u32 val16 = VFE_0_BUS_BDG_DS_CFG_16_CFG; 916 917 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); 918 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); 919 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); 920 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); 921 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); 922 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); 923 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); 924 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); 925 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); 926 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); 927 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); 928 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); 929 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); 930 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); 931 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); 932 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); 933 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); 934 } 935 936 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 937 { 938 /* empty */ 939 } 940 941 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 942 { 943 u32 val; 944 945 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 946 case MEDIA_BUS_FMT_YUYV8_2X8: 947 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 948 break; 949 case MEDIA_BUS_FMT_YVYU8_2X8: 950 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 951 break; 952 case MEDIA_BUS_FMT_UYVY8_2X8: 953 default: 954 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 955 break; 956 case MEDIA_BUS_FMT_VYUY8_2X8: 957 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 958 break; 959 } 960 961 val |= VFE_0_CORE_CFG_COMPOSITE_REG_UPDATE_EN; 962 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 963 964 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 965 val |= (line->fmt[MSM_VFE_PAD_SINK].height - 1) << 16; 966 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 967 968 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 969 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 970 971 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 972 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 973 974 val = 0xffffffff; 975 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG); 976 977 val = 0xffffffff; 978 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN); 979 980 val = 0xffffffff; 981 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 982 983 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 984 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 985 986 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 987 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 988 } 989 990 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 991 { 992 u32 cmd; 993 994 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 995 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 996 wmb(); 997 998 if (enable) 999 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 1000 else 1001 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 1002 1003 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 1004 } 1005 1006 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 1007 { 1008 u32 val_lens = VFE_0_MODULE_LENS_EN_DEMUX | 1009 VFE_0_MODULE_LENS_EN_CHROMA_UPSAMPLE; 1010 u32 val_zoom = VFE_0_MODULE_ZOOM_EN_SCALE_ENC | 1011 VFE_0_MODULE_ZOOM_EN_CROP_ENC; 1012 1013 if (enable) { 1014 vfe_reg_set(vfe, VFE_0_MODULE_LENS_EN, val_lens); 1015 vfe_reg_set(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 1016 } else { 1017 vfe_reg_clr(vfe, VFE_0_MODULE_LENS_EN, val_lens); 1018 vfe_reg_clr(vfe, VFE_0_MODULE_ZOOM_EN, val_zoom); 1019 } 1020 } 1021 1022 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 1023 { 1024 u32 val; 1025 int ret; 1026 1027 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 1028 val, 1029 (val & VFE_0_CAMIF_STATUS_HALT), 1030 CAMIF_TIMEOUT_SLEEP_US, 1031 CAMIF_TIMEOUT_ALL_US); 1032 if (ret < 0) 1033 dev_err(dev, "%s: camif stop timeout\n", __func__); 1034 1035 return ret; 1036 } 1037 1038 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 1039 { 1040 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 1041 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 1042 1043 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 1044 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 1045 1046 wmb(); 1047 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 1048 } 1049 1050 static void vfe_violation_read(struct vfe_device *vfe) 1051 { 1052 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 1053 1054 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 1055 } 1056 1057 /* 1058 * vfe_isr - ISPIF module interrupt handler 1059 * @irq: Interrupt line 1060 * @dev: VFE device 1061 * 1062 * Return IRQ_HANDLED on success 1063 */ 1064 static irqreturn_t vfe_isr(int irq, void *dev) 1065 { 1066 struct vfe_device *vfe = dev; 1067 u32 value0, value1; 1068 int i, j; 1069 1070 vfe->ops->isr_read(vfe, &value0, &value1); 1071 1072 trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n", 1073 value0, value1); 1074 1075 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 1076 vfe->isr_ops.reset_ack(vfe); 1077 1078 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 1079 vfe->ops->violation_read(vfe); 1080 1081 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 1082 vfe->isr_ops.halt_ack(vfe); 1083 1084 for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 1085 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 1086 vfe->isr_ops.reg_update(vfe, i); 1087 1088 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 1089 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 1090 1091 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 1092 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 1093 vfe->isr_ops.sof(vfe, i); 1094 1095 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 1096 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 1097 vfe->isr_ops.comp_done(vfe, i); 1098 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 1099 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 1100 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 1101 } 1102 1103 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 1104 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 1105 vfe->isr_ops.wm_done(vfe, i); 1106 1107 return IRQ_HANDLED; 1108 } 1109 1110 const struct vfe_hw_ops vfe_ops_4_7 = { 1111 .hw_version_read = vfe_hw_version_read, 1112 .get_ub_size = vfe47_get_ub_size, 1113 .global_reset = vfe_global_reset, 1114 .halt_request = vfe_halt_request, 1115 .halt_clear = vfe_halt_clear, 1116 .wm_enable = vfe47_wm_enable, 1117 .wm_frame_based = vfe_wm_frame_based, 1118 .wm_line_based = vfe_wm_line_based, 1119 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 1120 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 1121 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 1122 .bus_reload_wm = vfe_bus_reload_wm, 1123 .wm_set_ping_addr = vfe_wm_set_ping_addr, 1124 .wm_set_pong_addr = vfe_wm_set_pong_addr, 1125 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 1126 .bus_enable_wr_if = vfe_bus_enable_wr_if, 1127 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 1128 .wm_set_subsample = vfe_wm_set_subsample, 1129 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 1130 .set_xbar_cfg = vfe_set_xbar_cfg, 1131 .set_realign_cfg = vfe_set_realign_cfg, 1132 .set_rdi_cid = vfe_set_rdi_cid, 1133 .reg_update = vfe_reg_update, 1134 .reg_update_clear = vfe_reg_update_clear, 1135 .enable_irq_wm_line = vfe_enable_irq_wm_line, 1136 .enable_irq_pix_line = vfe_enable_irq_pix_line, 1137 .enable_irq_common = vfe_enable_irq_common, 1138 .set_demux_cfg = vfe_set_demux_cfg, 1139 .set_scale_cfg = vfe_set_scale_cfg, 1140 .set_crop_cfg = vfe_set_crop_cfg, 1141 .set_clamp_cfg = vfe_set_clamp_cfg, 1142 .set_qos = vfe47_set_qos, 1143 .set_ds = vfe47_set_ds, 1144 .set_cgc_override = vfe_set_cgc_override, 1145 .set_camif_cfg = vfe_set_camif_cfg, 1146 .set_camif_cmd = vfe_set_camif_cmd, 1147 .set_module_cfg = vfe_set_module_cfg, 1148 .camif_wait_for_stop = vfe_camif_wait_for_stop, 1149 .isr_read = vfe_isr_read, 1150 .violation_read = vfe_violation_read, 1151 .isr = vfe_isr, 1152 }; 1153 1154 static u16 vfe48_get_ub_size(u8 vfe_id) 1155 { 1156 /* On VFE4.8 the ub-size is the same on both instances */ 1157 return MSM_VFE_VFE0_UB_SIZE_RDI; 1158 } 1159 1160 static void vfe48_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 1161 { 1162 if (enable) 1163 writel_relaxed(2 << VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(wm), 1164 vfe->base + VFE48_0_BUS_IMAGE_MASTER_CMD); 1165 else 1166 writel_relaxed(1 << VFE48_0_BUS_IMAGE_MASTER_n_SHIFT(wm), 1167 vfe->base + VFE48_0_BUS_IMAGE_MASTER_CMD); 1168 1169 /* The WM must be enabled before sending other commands */ 1170 wmb(); 1171 } 1172 1173 static void vfe48_set_qos(struct vfe_device *vfe) 1174 { 1175 u32 val = VFE48_0_BUS_BDG_QOS_CFG_0_CFG; 1176 u32 val3 = VFE48_0_BUS_BDG_QOS_CFG_3_CFG; 1177 u32 val4 = VFE48_0_BUS_BDG_QOS_CFG_4_CFG; 1178 u32 val7 = VFE48_0_BUS_BDG_QOS_CFG_7_CFG; 1179 1180 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 1181 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 1182 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 1183 writel_relaxed(val3, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 1184 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 1185 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 1186 writel_relaxed(val4, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 1187 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 1188 } 1189 1190 static void vfe48_set_ds(struct vfe_device *vfe) 1191 { 1192 u32 val = VFE48_0_BUS_BDG_DS_CFG_0_CFG; 1193 u32 val16 = VFE48_0_BUS_BDG_DS_CFG_16_CFG; 1194 1195 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_0); 1196 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_1); 1197 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_2); 1198 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_3); 1199 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_4); 1200 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_5); 1201 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_6); 1202 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_7); 1203 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_8); 1204 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_9); 1205 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_10); 1206 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_11); 1207 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_12); 1208 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_13); 1209 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_14); 1210 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_DS_CFG_15); 1211 writel_relaxed(val16, vfe->base + VFE_0_BUS_BDG_DS_CFG_16); 1212 } 1213 1214 const struct vfe_hw_ops vfe_ops_4_8 = { 1215 .hw_version_read = vfe_hw_version_read, 1216 .get_ub_size = vfe48_get_ub_size, 1217 .global_reset = vfe_global_reset, 1218 .halt_request = vfe_halt_request, 1219 .halt_clear = vfe_halt_clear, 1220 .wm_enable = vfe48_wm_enable, 1221 .wm_frame_based = vfe_wm_frame_based, 1222 .wm_line_based = vfe_wm_line_based, 1223 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 1224 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 1225 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 1226 .bus_reload_wm = vfe_bus_reload_wm, 1227 .wm_set_ping_addr = vfe_wm_set_ping_addr, 1228 .wm_set_pong_addr = vfe_wm_set_pong_addr, 1229 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 1230 .bus_enable_wr_if = vfe_bus_enable_wr_if, 1231 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 1232 .wm_set_subsample = vfe_wm_set_subsample, 1233 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 1234 .set_xbar_cfg = vfe_set_xbar_cfg, 1235 .set_realign_cfg = vfe_set_realign_cfg, 1236 .set_rdi_cid = vfe_set_rdi_cid, 1237 .reg_update = vfe_reg_update, 1238 .reg_update_clear = vfe_reg_update_clear, 1239 .enable_irq_wm_line = vfe_enable_irq_wm_line, 1240 .enable_irq_pix_line = vfe_enable_irq_pix_line, 1241 .enable_irq_common = vfe_enable_irq_common, 1242 .set_demux_cfg = vfe_set_demux_cfg, 1243 .set_scale_cfg = vfe_set_scale_cfg, 1244 .set_crop_cfg = vfe_set_crop_cfg, 1245 .set_clamp_cfg = vfe_set_clamp_cfg, 1246 .set_qos = vfe48_set_qos, 1247 .set_ds = vfe48_set_ds, 1248 .set_cgc_override = vfe_set_cgc_override, 1249 .set_camif_cfg = vfe_set_camif_cfg, 1250 .set_camif_cmd = vfe_set_camif_cmd, 1251 .set_module_cfg = vfe_set_module_cfg, 1252 .camif_wait_for_stop = vfe_camif_wait_for_stop, 1253 .isr_read = vfe_isr_read, 1254 .violation_read = vfe_violation_read, 1255 .isr = vfe_isr, 1256 }; 1257