1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-1.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/iopoll.h> 13 14 #include "camss-vfe.h" 15 16 #define VFE_0_HW_VERSION 0x000 17 18 #define VFE_0_GLOBAL_RESET_CMD 0x00c 19 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 20 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 21 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 22 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 23 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 24 #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) 25 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) 26 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) 27 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) 28 29 #define VFE_0_MODULE_CFG 0x018 30 #define VFE_0_MODULE_CFG_DEMUX BIT(2) 31 #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) 32 #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) 33 #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) 34 35 #define VFE_0_CORE_CFG 0x01c 36 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 37 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 38 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 39 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 40 41 #define VFE_0_IRQ_CMD 0x024 42 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 43 44 #define VFE_0_IRQ_MASK_0 0x028 45 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 46 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 47 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 48 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 49 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 50 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 51 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 52 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 53 #define VFE_0_IRQ_MASK_1 0x02c 54 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 55 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 56 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 57 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 58 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 59 60 #define VFE_0_IRQ_CLEAR_0 0x030 61 #define VFE_0_IRQ_CLEAR_1 0x034 62 63 #define VFE_0_IRQ_STATUS_0 0x038 64 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 65 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 66 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 67 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 68 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 69 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 70 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 71 #define VFE_0_IRQ_STATUS_1 0x03c 72 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 73 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 74 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 75 76 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x40 77 #define VFE_0_VIOLATION_STATUS 0x48 78 79 #define VFE_0_BUS_CMD 0x4c 80 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 81 82 #define VFE_0_BUS_CFG 0x050 83 84 #define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2)) 85 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) 86 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 87 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 88 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0 89 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5 90 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6 91 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7 92 93 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n)) 94 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 95 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1 96 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n)) 97 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n)) 98 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n)) 99 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 100 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 101 102 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n)) 103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 104 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n)) 105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n)) 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 107 (0x088 + 0x24 * (n)) 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 109 (0x08c + 0x24 * (n)) 110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 111 112 #define VFE_0_BUS_PING_PONG_STATUS 0x268 113 114 #define VFE_0_BUS_BDG_CMD 0x2c0 115 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 116 117 #define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4 118 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 119 #define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8 120 #define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc 121 #define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0 122 #define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4 123 #define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8 124 #define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc 125 #define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0 126 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5 127 128 #define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x))) 129 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 130 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 131 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 132 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 133 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 134 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 135 #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) 136 137 #define VFE_0_CAMIF_CMD 0x2f4 138 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 139 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 140 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 141 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 142 #define VFE_0_CAMIF_CFG 0x2f8 143 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 144 #define VFE_0_CAMIF_FRAME_CFG 0x300 145 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304 146 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308 147 #define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c 148 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314 149 #define VFE_0_CAMIF_STATUS 0x31c 150 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 151 152 #define VFE_0_REG_UPDATE 0x378 153 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 154 #define VFE_0_REG_UPDATE_line_n(n) \ 155 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 156 157 #define VFE_0_DEMUX_CFG 0x424 158 #define VFE_0_DEMUX_CFG_PERIOD 0x3 159 #define VFE_0_DEMUX_GAIN_0 0x428 160 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 161 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 162 #define VFE_0_DEMUX_GAIN_1 0x42c 163 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 164 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 165 #define VFE_0_DEMUX_EVEN_CFG 0x438 166 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 167 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 168 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 169 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 170 #define VFE_0_DEMUX_ODD_CFG 0x43c 171 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 172 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 173 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 174 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 175 176 #define VFE_0_SCALE_ENC_Y_CFG 0x75c 177 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760 178 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x764 179 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c 180 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x770 181 #define VFE_0_SCALE_ENC_CBCR_CFG 0x778 182 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c 183 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 184 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 185 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 186 187 #define VFE_0_CROP_ENC_Y_WIDTH 0x854 188 #define VFE_0_CROP_ENC_Y_HEIGHT 0x858 189 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c 190 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860 191 192 #define VFE_0_CLAMP_ENC_MAX_CFG 0x874 193 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 194 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 195 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 196 #define VFE_0_CLAMP_ENC_MIN_CFG 0x878 197 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 198 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 199 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 200 201 #define VFE_0_CGC_OVERRIDE_1 0x974 202 #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) 203 204 #define CAMIF_TIMEOUT_SLEEP_US 1000 205 #define CAMIF_TIMEOUT_ALL_US 1000000 206 207 #define MSM_VFE_VFE0_UB_SIZE 1023 208 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 209 210 static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 211 { 212 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 213 214 dev_dbg(dev, "VFE HW Version = 0x%08x\n", hw_version); 215 } 216 217 static u16 vfe_get_ub_size(u8 vfe_id) 218 { 219 if (vfe_id == 0) 220 return MSM_VFE_VFE0_UB_SIZE_RDI; 221 222 return 0; 223 } 224 225 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 226 { 227 u32 bits = readl_relaxed(vfe->base + reg); 228 229 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 230 } 231 232 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 233 { 234 u32 bits = readl_relaxed(vfe->base + reg); 235 236 writel_relaxed(bits | set_bits, vfe->base + reg); 237 } 238 239 static void vfe_global_reset(struct vfe_device *vfe) 240 { 241 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN | 242 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 243 VFE_0_GLOBAL_RESET_CMD_PM | 244 VFE_0_GLOBAL_RESET_CMD_TIMER | 245 VFE_0_GLOBAL_RESET_CMD_REGISTER | 246 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 247 VFE_0_GLOBAL_RESET_CMD_BUS | 248 VFE_0_GLOBAL_RESET_CMD_CAMIF | 249 VFE_0_GLOBAL_RESET_CMD_CORE; 250 251 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 252 } 253 254 static void vfe_halt_request(struct vfe_device *vfe) 255 { 256 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 257 vfe->base + VFE_0_BUS_BDG_CMD); 258 } 259 260 static void vfe_halt_clear(struct vfe_device *vfe) 261 { 262 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 263 } 264 265 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 266 { 267 if (enable) 268 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 269 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 270 else 271 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 272 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 273 } 274 275 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 276 { 277 if (enable) 278 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 279 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 280 else 281 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 282 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 283 } 284 285 #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 286 287 static int vfe_word_per_line(u32 format, u32 pixel_per_line) 288 { 289 int val = 0; 290 291 switch (format) { 292 case V4L2_PIX_FMT_NV12: 293 case V4L2_PIX_FMT_NV21: 294 case V4L2_PIX_FMT_NV16: 295 case V4L2_PIX_FMT_NV61: 296 val = CALC_WORD(pixel_per_line, 1, 8); 297 break; 298 case V4L2_PIX_FMT_YUYV: 299 case V4L2_PIX_FMT_YVYU: 300 case V4L2_PIX_FMT_UYVY: 301 case V4L2_PIX_FMT_VYUY: 302 val = CALC_WORD(pixel_per_line, 2, 8); 303 break; 304 } 305 306 return val; 307 } 308 309 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 310 u16 *width, u16 *height, u16 *bytesperline) 311 { 312 switch (pix->pixelformat) { 313 case V4L2_PIX_FMT_NV12: 314 case V4L2_PIX_FMT_NV21: 315 *width = pix->width; 316 *height = pix->height; 317 *bytesperline = pix->plane_fmt[0].bytesperline; 318 if (plane == 1) 319 *height /= 2; 320 break; 321 case V4L2_PIX_FMT_NV16: 322 case V4L2_PIX_FMT_NV61: 323 *width = pix->width; 324 *height = pix->height; 325 *bytesperline = pix->plane_fmt[0].bytesperline; 326 break; 327 } 328 } 329 330 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 331 struct v4l2_pix_format_mplane *pix, 332 u8 plane, u32 enable) 333 { 334 u32 reg; 335 336 if (enable) { 337 u16 width = 0, height = 0, bytesperline = 0, wpl; 338 339 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 340 341 wpl = vfe_word_per_line(pix->pixelformat, width); 342 343 reg = height - 1; 344 reg |= ((wpl + 1) / 2 - 1) << 16; 345 346 writel_relaxed(reg, vfe->base + 347 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 348 349 wpl = vfe_word_per_line(pix->pixelformat, bytesperline); 350 351 reg = 0x3; 352 reg |= (height - 1) << 4; 353 reg |= wpl << 16; 354 355 writel_relaxed(reg, vfe->base + 356 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 357 } else { 358 writel_relaxed(0, vfe->base + 359 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 360 writel_relaxed(0, vfe->base + 361 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 362 } 363 } 364 365 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 366 { 367 u32 reg; 368 369 reg = readl_relaxed(vfe->base + 370 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 371 372 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 373 374 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 375 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 376 377 writel_relaxed(reg, 378 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 379 } 380 381 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 382 u32 pattern) 383 { 384 writel_relaxed(pattern, 385 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 386 } 387 388 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 389 u16 offset, u16 depth) 390 { 391 u32 reg; 392 393 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 394 depth; 395 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 396 } 397 398 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 399 { 400 wmb(); 401 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 402 wmb(); 403 } 404 405 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 406 { 407 writel_relaxed(addr, 408 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 409 } 410 411 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 412 { 413 writel_relaxed(addr, 414 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 415 } 416 417 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 418 { 419 u32 reg; 420 421 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 422 423 return (reg >> wm) & 0x1; 424 } 425 426 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 427 { 428 if (enable) 429 writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); 430 else 431 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 432 } 433 434 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 435 enum vfe_line_id id) 436 { 437 u32 reg; 438 439 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 440 reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 441 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 442 443 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 444 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 445 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 446 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 447 448 switch (id) { 449 case VFE_LINE_RDI0: 450 default: 451 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 452 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 453 break; 454 case VFE_LINE_RDI1: 455 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 456 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 457 break; 458 case VFE_LINE_RDI2: 459 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 460 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 461 break; 462 } 463 464 if (wm % 2 == 1) 465 reg <<= 16; 466 467 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 468 } 469 470 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 471 { 472 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 473 vfe->base + 474 VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 475 } 476 477 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 478 enum vfe_line_id id) 479 { 480 u32 reg; 481 482 reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 483 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); 484 485 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 486 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 487 488 switch (id) { 489 case VFE_LINE_RDI0: 490 default: 491 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 492 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 493 break; 494 case VFE_LINE_RDI1: 495 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 496 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 497 break; 498 case VFE_LINE_RDI2: 499 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 500 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 501 break; 502 } 503 504 if (wm % 2 == 1) 505 reg <<= 16; 506 507 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 508 } 509 510 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 511 u8 enable) 512 { 513 struct vfe_line *line = container_of(output, struct vfe_line, output); 514 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 515 u32 reg; 516 unsigned int i; 517 518 for (i = 0; i < output->wm_num; i++) { 519 if (i == 0) { 520 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 521 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 522 } else if (i == 1) { 523 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 524 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 525 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 526 } else { 527 /* On current devices output->wm_num is always <= 2 */ 528 break; 529 } 530 531 if (output->wm_idx[i] % 2 == 1) 532 reg <<= 16; 533 534 if (enable) 535 vfe_reg_set(vfe, 536 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 537 reg); 538 else 539 vfe_reg_clr(vfe, 540 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 541 reg); 542 } 543 } 544 545 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 546 u8 enable) 547 { 548 /* empty */ 549 } 550 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 551 { 552 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 553 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 554 555 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 556 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 557 } 558 559 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 560 { 561 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 562 wmb(); 563 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 564 wmb(); 565 } 566 567 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 568 enum vfe_line_id line_id) 569 { 570 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 571 } 572 573 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 574 enum vfe_line_id line_id, u8 enable) 575 { 576 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 577 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 578 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 579 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 580 581 if (enable) { 582 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 583 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 584 } else { 585 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 586 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 587 } 588 } 589 590 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 591 enum vfe_line_id line_id, u8 enable) 592 { 593 struct vfe_output *output = &vfe->line[line_id].output; 594 unsigned int i; 595 u32 irq_en0; 596 u32 irq_en1; 597 u32 comp_mask = 0; 598 599 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 600 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 601 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 602 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 603 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 604 for (i = 0; i < output->wm_num; i++) { 605 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 606 output->wm_idx[i]); 607 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 608 } 609 610 if (enable) { 611 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 612 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 613 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 614 } else { 615 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 616 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 617 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 618 } 619 } 620 621 static void vfe_enable_irq_common(struct vfe_device *vfe) 622 { 623 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 624 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 625 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 626 627 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 628 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 629 } 630 631 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 632 { 633 u32 val, even_cfg, odd_cfg; 634 635 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 636 637 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 638 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 639 640 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 641 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 642 643 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 644 case MEDIA_BUS_FMT_YUYV8_2X8: 645 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 646 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 647 break; 648 case MEDIA_BUS_FMT_YVYU8_2X8: 649 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 650 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 651 break; 652 case MEDIA_BUS_FMT_UYVY8_2X8: 653 default: 654 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 655 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 656 break; 657 case MEDIA_BUS_FMT_VYUY8_2X8: 658 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 659 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 660 break; 661 } 662 663 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 664 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 665 } 666 667 static inline u8 vfe_calc_interp_reso(u16 input, u16 output) 668 { 669 if (input / output >= 16) 670 return 0; 671 672 if (input / output >= 8) 673 return 1; 674 675 if (input / output >= 4) 676 return 2; 677 678 return 3; 679 } 680 681 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 682 { 683 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 684 u32 reg; 685 u16 input, output; 686 u8 interp_reso; 687 u32 phase_mult; 688 689 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 690 691 input = line->fmt[MSM_VFE_PAD_SINK].width; 692 output = line->compose.width; 693 reg = (output << 16) | input; 694 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 695 696 interp_reso = vfe_calc_interp_reso(input, output); 697 phase_mult = input * (1 << (13 + interp_reso)) / output; 698 reg = (interp_reso << 20) | phase_mult; 699 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 700 701 input = line->fmt[MSM_VFE_PAD_SINK].height; 702 output = line->compose.height; 703 reg = (output << 16) | input; 704 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 705 706 interp_reso = vfe_calc_interp_reso(input, output); 707 phase_mult = input * (1 << (13 + interp_reso)) / output; 708 reg = (interp_reso << 20) | phase_mult; 709 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 710 711 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 712 713 input = line->fmt[MSM_VFE_PAD_SINK].width; 714 output = line->compose.width / 2; 715 reg = (output << 16) | input; 716 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 717 718 interp_reso = vfe_calc_interp_reso(input, output); 719 phase_mult = input * (1 << (13 + interp_reso)) / output; 720 reg = (interp_reso << 20) | phase_mult; 721 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 722 723 input = line->fmt[MSM_VFE_PAD_SINK].height; 724 output = line->compose.height; 725 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 726 output = line->compose.height / 2; 727 reg = (output << 16) | input; 728 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 729 730 interp_reso = vfe_calc_interp_reso(input, output); 731 phase_mult = input * (1 << (13 + interp_reso)) / output; 732 reg = (interp_reso << 20) | phase_mult; 733 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 734 } 735 736 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 737 { 738 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 739 u32 reg; 740 u16 first, last; 741 742 first = line->crop.left; 743 last = line->crop.left + line->crop.width - 1; 744 reg = (first << 16) | last; 745 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 746 747 first = line->crop.top; 748 last = line->crop.top + line->crop.height - 1; 749 reg = (first << 16) | last; 750 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 751 752 first = line->crop.left / 2; 753 last = line->crop.left / 2 + line->crop.width / 2 - 1; 754 reg = (first << 16) | last; 755 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 756 757 first = line->crop.top; 758 last = line->crop.top + line->crop.height - 1; 759 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 760 first = line->crop.top / 2; 761 last = line->crop.top / 2 + line->crop.height / 2 - 1; 762 } 763 reg = (first << 16) | last; 764 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 765 } 766 767 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 768 { 769 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 770 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 771 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 772 773 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 774 775 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 776 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 777 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 778 779 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 780 } 781 782 static void vfe_set_qos(struct vfe_device *vfe) 783 { 784 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 785 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 786 787 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 788 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 789 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 790 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 791 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 792 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 793 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 794 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 795 } 796 797 static void vfe_set_ds(struct vfe_device *vfe) 798 { 799 /* empty */ 800 } 801 802 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 803 { 804 u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); 805 806 if (enable) 807 vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); 808 else 809 vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); 810 811 wmb(); 812 } 813 814 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 815 { 816 u32 val; 817 818 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 819 case MEDIA_BUS_FMT_YUYV8_2X8: 820 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 821 break; 822 case MEDIA_BUS_FMT_YVYU8_2X8: 823 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 824 break; 825 case MEDIA_BUS_FMT_UYVY8_2X8: 826 default: 827 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 828 break; 829 case MEDIA_BUS_FMT_VYUY8_2X8: 830 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 831 break; 832 } 833 834 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 835 836 val = line->fmt[MSM_VFE_PAD_SINK].width * 2; 837 val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; 838 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 839 840 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 841 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 842 843 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 844 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 845 846 val = 0xffffffff; 847 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); 848 849 val = 0xffffffff; 850 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 851 852 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 853 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 854 855 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 856 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 857 } 858 859 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 860 { 861 u32 cmd; 862 863 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 864 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 865 wmb(); 866 867 if (enable) 868 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 869 else 870 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 871 872 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 873 } 874 875 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 876 { 877 u32 val = VFE_0_MODULE_CFG_DEMUX | 878 VFE_0_MODULE_CFG_CHROMA_UPSAMPLE | 879 VFE_0_MODULE_CFG_SCALE_ENC | 880 VFE_0_MODULE_CFG_CROP_ENC; 881 882 if (enable) 883 writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); 884 else 885 writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); 886 } 887 888 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 889 { 890 u32 val; 891 int ret; 892 893 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 894 val, 895 (val & VFE_0_CAMIF_STATUS_HALT), 896 CAMIF_TIMEOUT_SLEEP_US, 897 CAMIF_TIMEOUT_ALL_US); 898 if (ret < 0) 899 dev_err(dev, "%s: camif stop timeout\n", __func__); 900 901 return ret; 902 } 903 904 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 905 { 906 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 907 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 908 909 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 910 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 911 912 wmb(); 913 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 914 } 915 916 static void vfe_violation_read(struct vfe_device *vfe) 917 { 918 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 919 920 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 921 } 922 923 /* 924 * vfe_isr - ISPIF module interrupt handler 925 * @irq: Interrupt line 926 * @dev: VFE device 927 * 928 * Return IRQ_HANDLED on success 929 */ 930 static irqreturn_t vfe_isr(int irq, void *dev) 931 { 932 struct vfe_device *vfe = dev; 933 u32 value0, value1; 934 int i, j; 935 936 vfe->ops->isr_read(vfe, &value0, &value1); 937 938 trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n", 939 value0, value1); 940 941 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 942 vfe->isr_ops.reset_ack(vfe); 943 944 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 945 vfe->ops->violation_read(vfe); 946 947 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 948 vfe->isr_ops.halt_ack(vfe); 949 950 for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 951 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 952 vfe->isr_ops.reg_update(vfe, i); 953 954 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 955 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 956 957 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 958 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 959 vfe->isr_ops.sof(vfe, i); 960 961 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 962 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 963 vfe->isr_ops.comp_done(vfe, i); 964 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 965 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 966 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 967 } 968 969 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 970 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 971 vfe->isr_ops.wm_done(vfe, i); 972 973 return IRQ_HANDLED; 974 } 975 976 const struct vfe_hw_ops vfe_ops_4_1 = { 977 .hw_version_read = vfe_hw_version_read, 978 .get_ub_size = vfe_get_ub_size, 979 .global_reset = vfe_global_reset, 980 .halt_request = vfe_halt_request, 981 .halt_clear = vfe_halt_clear, 982 .wm_enable = vfe_wm_enable, 983 .wm_frame_based = vfe_wm_frame_based, 984 .wm_line_based = vfe_wm_line_based, 985 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 986 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 987 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 988 .bus_reload_wm = vfe_bus_reload_wm, 989 .wm_set_ping_addr = vfe_wm_set_ping_addr, 990 .wm_set_pong_addr = vfe_wm_set_pong_addr, 991 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 992 .bus_enable_wr_if = vfe_bus_enable_wr_if, 993 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 994 .wm_set_subsample = vfe_wm_set_subsample, 995 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 996 .set_xbar_cfg = vfe_set_xbar_cfg, 997 .set_realign_cfg = vfe_set_realign_cfg, 998 .set_rdi_cid = vfe_set_rdi_cid, 999 .reg_update = vfe_reg_update, 1000 .reg_update_clear = vfe_reg_update_clear, 1001 .enable_irq_wm_line = vfe_enable_irq_wm_line, 1002 .enable_irq_pix_line = vfe_enable_irq_pix_line, 1003 .enable_irq_common = vfe_enable_irq_common, 1004 .set_demux_cfg = vfe_set_demux_cfg, 1005 .set_scale_cfg = vfe_set_scale_cfg, 1006 .set_crop_cfg = vfe_set_crop_cfg, 1007 .set_clamp_cfg = vfe_set_clamp_cfg, 1008 .set_qos = vfe_set_qos, 1009 .set_ds = vfe_set_ds, 1010 .set_cgc_override = vfe_set_cgc_override, 1011 .set_camif_cfg = vfe_set_camif_cfg, 1012 .set_camif_cmd = vfe_set_camif_cmd, 1013 .set_module_cfg = vfe_set_module_cfg, 1014 .camif_wait_for_stop = vfe_camif_wait_for_stop, 1015 .isr_read = vfe_isr_read, 1016 .violation_read = vfe_violation_read, 1017 .isr = vfe_isr, 1018 }; 1019