1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-vfe-4-1.c 4 * 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 15 #include "camss.h" 16 #include "camss-vfe.h" 17 #include "camss-vfe-gen1.h" 18 19 #define VFE_0_HW_VERSION 0x000 20 21 #define VFE_0_GLOBAL_RESET_CMD 0x00c 22 #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 23 #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 24 #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 25 #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 26 #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 27 #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) 28 #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) 29 #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) 30 #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) 31 32 #define VFE_0_MODULE_CFG 0x018 33 #define VFE_0_MODULE_CFG_DEMUX BIT(2) 34 #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) 35 #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) 36 #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) 37 38 #define VFE_0_CORE_CFG 0x01c 39 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 40 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 41 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 43 44 #define VFE_0_IRQ_CMD 0x024 45 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 46 47 #define VFE_0_IRQ_MASK_0 0x028 48 #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 49 #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 50 #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 51 #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 52 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 53 #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 54 #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 55 #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 56 #define VFE_0_IRQ_MASK_1 0x02c 57 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 58 #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 59 #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 60 #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 61 #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 62 63 #define VFE_0_IRQ_CLEAR_0 0x030 64 #define VFE_0_IRQ_CLEAR_1 0x034 65 66 #define VFE_0_IRQ_STATUS_0 0x038 67 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 68 #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 69 #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 70 ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 71 #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 72 #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 73 #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 74 #define VFE_0_IRQ_STATUS_1 0x03c 75 #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 76 #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 77 #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 78 79 #define VFE_0_IRQ_COMPOSITE_MASK_0 0x40 80 #define VFE_0_VIOLATION_STATUS 0x48 81 82 #define VFE_0_BUS_CMD 0x4c 83 #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 84 85 #define VFE_0_BUS_CFG 0x050 86 87 #define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2)) 88 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) 89 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 90 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 91 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0 92 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5 93 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6 94 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7 95 96 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n)) 97 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 98 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1 99 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n)) 100 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n)) 101 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n)) 102 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 104 105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n)) 106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n)) 108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n)) 109 #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 110 (0x088 + 0x24 * (n)) 111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 112 (0x08c + 0x24 * (n)) 113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 114 115 #define VFE_0_BUS_PING_PONG_STATUS 0x268 116 117 #define VFE_0_BUS_BDG_CMD 0x2c0 118 #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 119 120 #define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4 121 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 122 #define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8 123 #define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc 124 #define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0 125 #define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4 126 #define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8 127 #define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc 128 #define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0 129 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5 130 131 #define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x))) 132 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 133 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 134 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 135 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 136 #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 137 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 138 #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) 139 140 #define VFE_0_CAMIF_CMD 0x2f4 141 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 142 #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 143 #define VFE_0_CAMIF_CMD_NO_CHANGE 3 144 #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 145 #define VFE_0_CAMIF_CFG 0x2f8 146 #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 147 #define VFE_0_CAMIF_FRAME_CFG 0x300 148 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304 149 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308 150 #define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c 151 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314 152 #define VFE_0_CAMIF_STATUS 0x31c 153 #define VFE_0_CAMIF_STATUS_HALT BIT(31) 154 155 #define VFE_0_REG_UPDATE 0x378 156 #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 157 #define VFE_0_REG_UPDATE_line_n(n) \ 158 ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 159 160 #define VFE_0_DEMUX_CFG 0x424 161 #define VFE_0_DEMUX_CFG_PERIOD 0x3 162 #define VFE_0_DEMUX_GAIN_0 0x428 163 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 164 #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 165 #define VFE_0_DEMUX_GAIN_1 0x42c 166 #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 167 #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 168 #define VFE_0_DEMUX_EVEN_CFG 0x438 169 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 170 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 171 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 172 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 173 #define VFE_0_DEMUX_ODD_CFG 0x43c 174 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 175 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 176 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 177 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 178 179 #define VFE_0_SCALE_ENC_Y_CFG 0x75c 180 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760 181 #define VFE_0_SCALE_ENC_Y_H_PHASE 0x764 182 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c 183 #define VFE_0_SCALE_ENC_Y_V_PHASE 0x770 184 #define VFE_0_SCALE_ENC_CBCR_CFG 0x778 185 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c 186 #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 187 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 188 #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 189 190 #define VFE_0_CROP_ENC_Y_WIDTH 0x854 191 #define VFE_0_CROP_ENC_Y_HEIGHT 0x858 192 #define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c 193 #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860 194 195 #define VFE_0_CLAMP_ENC_MAX_CFG 0x874 196 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 197 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 198 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 199 #define VFE_0_CLAMP_ENC_MIN_CFG 0x878 200 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 201 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 202 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 203 204 #define VFE_0_CGC_OVERRIDE_1 0x974 205 #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) 206 207 #define CAMIF_TIMEOUT_SLEEP_US 1000 208 #define CAMIF_TIMEOUT_ALL_US 1000000 209 210 #define MSM_VFE_VFE0_UB_SIZE 1023 211 #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 212 213 static u32 vfe_hw_version(struct vfe_device *vfe) 214 { 215 u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 216 217 dev_dbg(vfe->camss->dev, "VFE HW Version = 0x%08x\n", hw_version); 218 219 return hw_version; 220 } 221 222 static u16 vfe_get_ub_size(u8 vfe_id) 223 { 224 if (vfe_id == 0) 225 return MSM_VFE_VFE0_UB_SIZE_RDI; 226 227 return 0; 228 } 229 230 static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 231 { 232 u32 bits = readl_relaxed(vfe->base + reg); 233 234 writel_relaxed(bits & ~clr_bits, vfe->base + reg); 235 } 236 237 static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 238 { 239 u32 bits = readl_relaxed(vfe->base + reg); 240 241 writel_relaxed(bits | set_bits, vfe->base + reg); 242 } 243 244 static void vfe_global_reset(struct vfe_device *vfe) 245 { 246 u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN | 247 VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 248 VFE_0_GLOBAL_RESET_CMD_PM | 249 VFE_0_GLOBAL_RESET_CMD_TIMER | 250 VFE_0_GLOBAL_RESET_CMD_REGISTER | 251 VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 252 VFE_0_GLOBAL_RESET_CMD_BUS | 253 VFE_0_GLOBAL_RESET_CMD_CAMIF | 254 VFE_0_GLOBAL_RESET_CMD_CORE; 255 256 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 257 } 258 259 static void vfe_halt_request(struct vfe_device *vfe) 260 { 261 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 262 vfe->base + VFE_0_BUS_BDG_CMD); 263 } 264 265 static void vfe_halt_clear(struct vfe_device *vfe) 266 { 267 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 268 } 269 270 static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 271 { 272 if (enable) 273 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 274 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 275 else 276 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 277 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 278 } 279 280 static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 281 { 282 if (enable) 283 vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 284 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 285 else 286 vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 287 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 288 } 289 290 static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 291 u16 *width, u16 *height, u16 *bytesperline) 292 { 293 switch (pix->pixelformat) { 294 case V4L2_PIX_FMT_NV12: 295 case V4L2_PIX_FMT_NV21: 296 *width = pix->width; 297 *height = pix->height; 298 *bytesperline = pix->plane_fmt[0].bytesperline; 299 if (plane == 1) 300 *height /= 2; 301 break; 302 case V4L2_PIX_FMT_NV16: 303 case V4L2_PIX_FMT_NV61: 304 *width = pix->width; 305 *height = pix->height; 306 *bytesperline = pix->plane_fmt[0].bytesperline; 307 break; 308 } 309 } 310 311 static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 312 struct v4l2_pix_format_mplane *pix, 313 u8 plane, u32 enable) 314 { 315 u32 reg; 316 317 if (enable) { 318 u16 width = 0, height = 0, bytesperline = 0, wpl; 319 320 vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 321 322 wpl = vfe_word_per_line(pix->pixelformat, width); 323 324 reg = height - 1; 325 reg |= ((wpl + 1) / 2 - 1) << 16; 326 327 writel_relaxed(reg, vfe->base + 328 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 329 330 wpl = vfe_word_per_line(pix->pixelformat, bytesperline); 331 332 reg = 0x3; 333 reg |= (height - 1) << 4; 334 reg |= wpl << 16; 335 336 writel_relaxed(reg, vfe->base + 337 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 338 } else { 339 writel_relaxed(0, vfe->base + 340 VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 341 writel_relaxed(0, vfe->base + 342 VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 343 } 344 } 345 346 static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 347 { 348 u32 reg; 349 350 reg = readl_relaxed(vfe->base + 351 VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 352 353 reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 354 355 reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 356 & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 357 358 writel_relaxed(reg, 359 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 360 } 361 362 static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 363 u32 pattern) 364 { 365 writel_relaxed(pattern, 366 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 367 } 368 369 static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 370 u16 offset, u16 depth) 371 { 372 u32 reg; 373 374 reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 375 depth; 376 writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 377 } 378 379 static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 380 { 381 wmb(); 382 writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 383 wmb(); 384 } 385 386 static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 387 { 388 writel_relaxed(addr, 389 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 390 } 391 392 static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 393 { 394 writel_relaxed(addr, 395 vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 396 } 397 398 static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 399 { 400 u32 reg; 401 402 reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 403 404 return (reg >> wm) & 0x1; 405 } 406 407 static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 408 { 409 if (enable) 410 writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); 411 else 412 writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 413 } 414 415 static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 416 enum vfe_line_id id) 417 { 418 u32 reg; 419 420 reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 421 reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 422 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 423 424 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 425 reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 426 VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 427 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 428 429 switch (id) { 430 case VFE_LINE_RDI0: 431 default: 432 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 433 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 434 break; 435 case VFE_LINE_RDI1: 436 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 437 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 438 break; 439 case VFE_LINE_RDI2: 440 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 441 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 442 break; 443 } 444 445 if (wm % 2 == 1) 446 reg <<= 16; 447 448 vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 449 } 450 451 static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 452 { 453 writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 454 vfe->base + 455 VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 456 } 457 458 static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 459 enum vfe_line_id id) 460 { 461 u32 reg; 462 463 reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 464 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); 465 466 reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 467 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 468 469 switch (id) { 470 case VFE_LINE_RDI0: 471 default: 472 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 473 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 474 break; 475 case VFE_LINE_RDI1: 476 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 477 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 478 break; 479 case VFE_LINE_RDI2: 480 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 481 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 482 break; 483 } 484 485 if (wm % 2 == 1) 486 reg <<= 16; 487 488 vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 489 } 490 491 static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 492 u8 enable) 493 { 494 struct vfe_line *line = container_of(output, struct vfe_line, output); 495 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 496 u32 reg; 497 unsigned int i; 498 499 for (i = 0; i < output->wm_num; i++) { 500 if (i == 0) { 501 reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 502 VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 503 } else if (i == 1) { 504 reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 505 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 506 reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 507 } else { 508 /* On current devices output->wm_num is always <= 2 */ 509 break; 510 } 511 512 if (output->wm_idx[i] % 2 == 1) 513 reg <<= 16; 514 515 if (enable) 516 vfe_reg_set(vfe, 517 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 518 reg); 519 else 520 vfe_reg_clr(vfe, 521 VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 522 reg); 523 } 524 } 525 526 static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 527 u8 enable) 528 { 529 /* empty */ 530 } 531 static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 532 { 533 vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 534 VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 535 536 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 537 cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 538 } 539 540 static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 541 { 542 vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 543 wmb(); 544 writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 545 wmb(); 546 } 547 548 static inline void vfe_reg_update_clear(struct vfe_device *vfe, 549 enum vfe_line_id line_id) 550 { 551 vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 552 } 553 554 static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 555 enum vfe_line_id line_id, u8 enable) 556 { 557 u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 558 VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 559 u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 560 VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 561 562 if (enable) { 563 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 564 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 565 } else { 566 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 567 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 568 } 569 } 570 571 static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 572 enum vfe_line_id line_id, u8 enable) 573 { 574 struct vfe_output *output = &vfe->line[line_id].output; 575 unsigned int i; 576 u32 irq_en0; 577 u32 irq_en1; 578 u32 comp_mask = 0; 579 580 irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 581 irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 582 irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 583 irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 584 irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 585 for (i = 0; i < output->wm_num; i++) { 586 irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 587 output->wm_idx[i]); 588 comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 589 } 590 591 if (enable) { 592 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 593 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 594 vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 595 } else { 596 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 597 vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 598 vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 599 } 600 } 601 602 static void vfe_enable_irq_common(struct vfe_device *vfe) 603 { 604 u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 605 u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 606 VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 607 608 vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 609 vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 610 } 611 612 static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 613 { 614 u32 val, even_cfg, odd_cfg; 615 616 writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 617 618 val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 619 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 620 621 val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 622 writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 623 624 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 625 case MEDIA_BUS_FMT_YUYV8_2X8: 626 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 627 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 628 break; 629 case MEDIA_BUS_FMT_YVYU8_2X8: 630 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 631 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 632 break; 633 case MEDIA_BUS_FMT_UYVY8_2X8: 634 default: 635 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 636 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 637 break; 638 case MEDIA_BUS_FMT_VYUY8_2X8: 639 even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 640 odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 641 break; 642 } 643 644 writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 645 writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 646 } 647 648 static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 649 { 650 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 651 u32 reg; 652 u16 input, output; 653 u8 interp_reso; 654 u32 phase_mult; 655 656 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 657 658 input = line->fmt[MSM_VFE_PAD_SINK].width; 659 output = line->compose.width; 660 reg = (output << 16) | input; 661 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 662 663 interp_reso = vfe_calc_interp_reso(input, output); 664 phase_mult = input * (1 << (13 + interp_reso)) / output; 665 reg = (interp_reso << 20) | phase_mult; 666 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 667 668 input = line->fmt[MSM_VFE_PAD_SINK].height; 669 output = line->compose.height; 670 reg = (output << 16) | input; 671 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 672 673 interp_reso = vfe_calc_interp_reso(input, output); 674 phase_mult = input * (1 << (13 + interp_reso)) / output; 675 reg = (interp_reso << 20) | phase_mult; 676 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 677 678 writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 679 680 input = line->fmt[MSM_VFE_PAD_SINK].width; 681 output = line->compose.width / 2; 682 reg = (output << 16) | input; 683 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 684 685 interp_reso = vfe_calc_interp_reso(input, output); 686 phase_mult = input * (1 << (13 + interp_reso)) / output; 687 reg = (interp_reso << 20) | phase_mult; 688 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 689 690 input = line->fmt[MSM_VFE_PAD_SINK].height; 691 output = line->compose.height; 692 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 693 output = line->compose.height / 2; 694 reg = (output << 16) | input; 695 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 696 697 interp_reso = vfe_calc_interp_reso(input, output); 698 phase_mult = input * (1 << (13 + interp_reso)) / output; 699 reg = (interp_reso << 20) | phase_mult; 700 writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 701 } 702 703 static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 704 { 705 u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 706 u32 reg; 707 u16 first, last; 708 709 first = line->crop.left; 710 last = line->crop.left + line->crop.width - 1; 711 reg = (first << 16) | last; 712 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 713 714 first = line->crop.top; 715 last = line->crop.top + line->crop.height - 1; 716 reg = (first << 16) | last; 717 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 718 719 first = line->crop.left / 2; 720 last = line->crop.left / 2 + line->crop.width / 2 - 1; 721 reg = (first << 16) | last; 722 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 723 724 first = line->crop.top; 725 last = line->crop.top + line->crop.height - 1; 726 if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 727 first = line->crop.top / 2; 728 last = line->crop.top / 2 + line->crop.height / 2 - 1; 729 } 730 reg = (first << 16) | last; 731 writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 732 } 733 734 static void vfe_set_clamp_cfg(struct vfe_device *vfe) 735 { 736 u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 737 VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 738 VFE_0_CLAMP_ENC_MAX_CFG_CH2; 739 740 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 741 742 val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 743 VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 744 VFE_0_CLAMP_ENC_MIN_CFG_CH2; 745 746 writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 747 } 748 749 static void vfe_set_qos(struct vfe_device *vfe) 750 { 751 u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 752 u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 753 754 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 755 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 756 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 757 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 758 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 759 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 760 writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 761 writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 762 } 763 764 static void vfe_set_ds(struct vfe_device *vfe) 765 { 766 /* empty */ 767 } 768 769 static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 770 { 771 u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); 772 773 if (enable) 774 vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); 775 else 776 vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); 777 778 wmb(); 779 } 780 781 static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 782 { 783 u32 val; 784 785 switch (line->fmt[MSM_VFE_PAD_SINK].code) { 786 case MEDIA_BUS_FMT_YUYV8_2X8: 787 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 788 break; 789 case MEDIA_BUS_FMT_YVYU8_2X8: 790 val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 791 break; 792 case MEDIA_BUS_FMT_UYVY8_2X8: 793 default: 794 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 795 break; 796 case MEDIA_BUS_FMT_VYUY8_2X8: 797 val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 798 break; 799 } 800 801 writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 802 803 val = line->fmt[MSM_VFE_PAD_SINK].width * 2; 804 val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; 805 writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 806 807 val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 808 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 809 810 val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 811 writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 812 813 val = 0xffffffff; 814 writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); 815 816 val = 0xffffffff; 817 writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 818 819 val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 820 vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 821 822 val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 823 writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 824 } 825 826 static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 827 { 828 u32 cmd; 829 830 cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 831 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 832 wmb(); 833 834 if (enable) 835 cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 836 else 837 cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 838 839 writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 840 } 841 842 static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 843 { 844 u32 val = VFE_0_MODULE_CFG_DEMUX | 845 VFE_0_MODULE_CFG_CHROMA_UPSAMPLE | 846 VFE_0_MODULE_CFG_SCALE_ENC | 847 VFE_0_MODULE_CFG_CROP_ENC; 848 849 if (enable) 850 writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); 851 else 852 writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); 853 } 854 855 static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 856 { 857 u32 val; 858 int ret; 859 860 ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 861 val, 862 (val & VFE_0_CAMIF_STATUS_HALT), 863 CAMIF_TIMEOUT_SLEEP_US, 864 CAMIF_TIMEOUT_ALL_US); 865 if (ret < 0) 866 dev_err(dev, "%s: camif stop timeout\n", __func__); 867 868 return ret; 869 } 870 871 static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 872 { 873 *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 874 *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 875 876 writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 877 writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 878 879 wmb(); 880 writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 881 } 882 883 static void vfe_violation_read(struct vfe_device *vfe) 884 { 885 u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 886 887 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 888 } 889 890 /* 891 * vfe_isr - VFE module interrupt handler 892 * @irq: Interrupt line 893 * @dev: VFE device 894 * 895 * Return IRQ_HANDLED on success 896 */ 897 static irqreturn_t vfe_isr(int irq, void *dev) 898 { 899 struct vfe_device *vfe = dev; 900 u32 value0, value1; 901 int i, j; 902 903 vfe->ops->isr_read(vfe, &value0, &value1); 904 905 dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", 906 value0, value1); 907 908 if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 909 vfe->isr_ops.reset_ack(vfe); 910 911 if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 912 vfe->ops->violation_read(vfe); 913 914 if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 915 vfe->isr_ops.halt_ack(vfe); 916 917 for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 918 if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 919 vfe->isr_ops.reg_update(vfe, i); 920 921 if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 922 vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 923 924 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 925 if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 926 vfe->isr_ops.sof(vfe, i); 927 928 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 929 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 930 vfe->isr_ops.comp_done(vfe, i); 931 for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 932 if (vfe->wm_output_map[j] == VFE_LINE_PIX) 933 value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 934 } 935 936 for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 937 if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 938 vfe->isr_ops.wm_done(vfe, i); 939 940 return IRQ_HANDLED; 941 } 942 943 /* 944 * vfe_pm_domain_off - Disable power domains specific to this VFE. 945 * @vfe: VFE Device 946 */ 947 static void vfe_pm_domain_off(struct vfe_device *vfe) 948 { 949 /* nop */ 950 } 951 952 /* 953 * vfe_pm_domain_on - Enable power domains specific to this VFE. 954 * @vfe: VFE Device 955 */ 956 static int vfe_pm_domain_on(struct vfe_device *vfe) 957 { 958 return 0; 959 } 960 961 static const struct vfe_hw_ops_gen1 vfe_ops_gen1_4_1 = { 962 .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 963 .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 964 .bus_enable_wr_if = vfe_bus_enable_wr_if, 965 .bus_reload_wm = vfe_bus_reload_wm, 966 .camif_wait_for_stop = vfe_camif_wait_for_stop, 967 .enable_irq_common = vfe_enable_irq_common, 968 .enable_irq_pix_line = vfe_enable_irq_pix_line, 969 .enable_irq_wm_line = vfe_enable_irq_wm_line, 970 .get_ub_size = vfe_get_ub_size, 971 .halt_clear = vfe_halt_clear, 972 .halt_request = vfe_halt_request, 973 .set_camif_cfg = vfe_set_camif_cfg, 974 .set_camif_cmd = vfe_set_camif_cmd, 975 .set_cgc_override = vfe_set_cgc_override, 976 .set_clamp_cfg = vfe_set_clamp_cfg, 977 .set_crop_cfg = vfe_set_crop_cfg, 978 .set_demux_cfg = vfe_set_demux_cfg, 979 .set_ds = vfe_set_ds, 980 .set_module_cfg = vfe_set_module_cfg, 981 .set_qos = vfe_set_qos, 982 .set_rdi_cid = vfe_set_rdi_cid, 983 .set_realign_cfg = vfe_set_realign_cfg, 984 .set_scale_cfg = vfe_set_scale_cfg, 985 .set_xbar_cfg = vfe_set_xbar_cfg, 986 .wm_enable = vfe_wm_enable, 987 .wm_frame_based = vfe_wm_frame_based, 988 .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 989 .wm_line_based = vfe_wm_line_based, 990 .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 991 .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 992 .wm_set_ping_addr = vfe_wm_set_ping_addr, 993 .wm_set_pong_addr = vfe_wm_set_pong_addr, 994 .wm_set_subsample = vfe_wm_set_subsample, 995 .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 996 }; 997 998 static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 999 { 1000 vfe->isr_ops = vfe_isr_ops_gen1; 1001 vfe->ops_gen1 = &vfe_ops_gen1_4_1; 1002 vfe->video_ops = vfe_video_ops_gen1; 1003 1004 vfe->line_num = VFE_LINE_NUM_GEN1; 1005 } 1006 1007 const struct vfe_hw_ops vfe_ops_4_1 = { 1008 .global_reset = vfe_global_reset, 1009 .hw_version = vfe_hw_version, 1010 .isr_read = vfe_isr_read, 1011 .isr = vfe_isr, 1012 .pm_domain_off = vfe_pm_domain_off, 1013 .pm_domain_on = vfe_pm_domain_on, 1014 .reg_update_clear = vfe_reg_update_clear, 1015 .reg_update = vfe_reg_update, 1016 .subdev_init = vfe_subdev_init, 1017 .vfe_disable = vfe_gen1_disable, 1018 .vfe_enable = vfe_gen1_enable, 1019 .vfe_halt = vfe_gen1_halt, 1020 .violation_read = vfe_violation_read, 1021 }; 1022