1051a01acSTodor Tomov // SPDX-License-Identifier: GPL-2.0 2051a01acSTodor Tomov /* 3051a01acSTodor Tomov * camss-vfe-4-1.c 4051a01acSTodor Tomov * 5051a01acSTodor Tomov * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1 6051a01acSTodor Tomov * 7051a01acSTodor Tomov * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8051a01acSTodor Tomov * Copyright (C) 2015-2018 Linaro Ltd. 9051a01acSTodor Tomov */ 10051a01acSTodor Tomov 11051a01acSTodor Tomov #include <linux/interrupt.h> 123799eca5SArnd Bergmann #include <linux/io.h> 13051a01acSTodor Tomov #include <linux/iopoll.h> 14051a01acSTodor Tomov 15*c3177cb0SRobert Foss #include "camss.h" 16051a01acSTodor Tomov #include "camss-vfe.h" 17051a01acSTodor Tomov 18051a01acSTodor Tomov #define VFE_0_HW_VERSION 0x000 19051a01acSTodor Tomov 20051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD 0x00c 21051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 22051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 23051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 24051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 25051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 26051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) 27051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) 28051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) 29051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) 30051a01acSTodor Tomov 31051a01acSTodor Tomov #define VFE_0_MODULE_CFG 0x018 32051a01acSTodor Tomov #define VFE_0_MODULE_CFG_DEMUX BIT(2) 33051a01acSTodor Tomov #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) 34051a01acSTodor Tomov #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) 35051a01acSTodor Tomov #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) 36051a01acSTodor Tomov 37051a01acSTodor Tomov #define VFE_0_CORE_CFG 0x01c 38051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 39051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 40051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 41051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 42051a01acSTodor Tomov 43051a01acSTodor Tomov #define VFE_0_IRQ_CMD 0x024 44051a01acSTodor Tomov #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 45051a01acSTodor Tomov 46051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0 0x028 47051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 48051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 49051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 50051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 51051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 52051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 53051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 54051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 55051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1 0x02c 56051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 57051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 58051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 59051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 60051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 61051a01acSTodor Tomov 62051a01acSTodor Tomov #define VFE_0_IRQ_CLEAR_0 0x030 63051a01acSTodor Tomov #define VFE_0_IRQ_CLEAR_1 0x034 64051a01acSTodor Tomov 65051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0 0x038 66051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 67051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 68051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 69051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 70051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 71051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 72051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 73051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1 0x03c 74051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 75051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 76051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 77051a01acSTodor Tomov 78051a01acSTodor Tomov #define VFE_0_IRQ_COMPOSITE_MASK_0 0x40 79051a01acSTodor Tomov #define VFE_0_VIOLATION_STATUS 0x48 80051a01acSTodor Tomov 81051a01acSTodor Tomov #define VFE_0_BUS_CMD 0x4c 82051a01acSTodor Tomov #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 83051a01acSTodor Tomov 84051a01acSTodor Tomov #define VFE_0_BUS_CFG 0x050 85051a01acSTodor Tomov 86051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2)) 87051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) 88051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 89051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 90051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0 91051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5 92051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6 93051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7 94051a01acSTodor Tomov 95051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n)) 96051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 97051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1 98051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n)) 99051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n)) 100051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n)) 101051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 102051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 103051a01acSTodor Tomov 104051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n)) 105051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 106051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n)) 107051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n)) 108051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 109051a01acSTodor Tomov (0x088 + 0x24 * (n)) 110051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 111051a01acSTodor Tomov (0x08c + 0x24 * (n)) 112051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 113051a01acSTodor Tomov 114051a01acSTodor Tomov #define VFE_0_BUS_PING_PONG_STATUS 0x268 115051a01acSTodor Tomov 116051a01acSTodor Tomov #define VFE_0_BUS_BDG_CMD 0x2c0 117051a01acSTodor Tomov #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 118051a01acSTodor Tomov 119051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4 120051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 121051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8 122051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc 123051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0 124051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4 125051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8 126051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc 127051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0 128051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5 129051a01acSTodor Tomov 130051a01acSTodor Tomov #define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x))) 131051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 132051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 133051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 134051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 135051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 136051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 137051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) 138051a01acSTodor Tomov 139051a01acSTodor Tomov #define VFE_0_CAMIF_CMD 0x2f4 140051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 141051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 142051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_NO_CHANGE 3 143051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 144051a01acSTodor Tomov #define VFE_0_CAMIF_CFG 0x2f8 145051a01acSTodor Tomov #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 146051a01acSTodor Tomov #define VFE_0_CAMIF_FRAME_CFG 0x300 147051a01acSTodor Tomov #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304 148051a01acSTodor Tomov #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308 149051a01acSTodor Tomov #define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c 150051a01acSTodor Tomov #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314 151051a01acSTodor Tomov #define VFE_0_CAMIF_STATUS 0x31c 152051a01acSTodor Tomov #define VFE_0_CAMIF_STATUS_HALT BIT(31) 153051a01acSTodor Tomov 154051a01acSTodor Tomov #define VFE_0_REG_UPDATE 0x378 155051a01acSTodor Tomov #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 156051a01acSTodor Tomov #define VFE_0_REG_UPDATE_line_n(n) \ 157051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 158051a01acSTodor Tomov 159051a01acSTodor Tomov #define VFE_0_DEMUX_CFG 0x424 160051a01acSTodor Tomov #define VFE_0_DEMUX_CFG_PERIOD 0x3 161051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0 0x428 162051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 163051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 164051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1 0x42c 165051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 166051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 167051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG 0x438 168051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 169051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 170051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 171051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 172051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG 0x43c 173051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 174051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 175051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 176051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 177051a01acSTodor Tomov 178051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_CFG 0x75c 179051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760 180051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_H_PHASE 0x764 181051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c 182051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_V_PHASE 0x770 183051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_CFG 0x778 184051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c 185051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 186051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 187051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 188051a01acSTodor Tomov 189051a01acSTodor Tomov #define VFE_0_CROP_ENC_Y_WIDTH 0x854 190051a01acSTodor Tomov #define VFE_0_CROP_ENC_Y_HEIGHT 0x858 191051a01acSTodor Tomov #define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c 192051a01acSTodor Tomov #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860 193051a01acSTodor Tomov 194051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG 0x874 195051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 196051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 197051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 198051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG 0x878 199051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 200051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 201051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 202051a01acSTodor Tomov 203051a01acSTodor Tomov #define VFE_0_CGC_OVERRIDE_1 0x974 204051a01acSTodor Tomov #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) 205051a01acSTodor Tomov 206051a01acSTodor Tomov #define CAMIF_TIMEOUT_SLEEP_US 1000 207051a01acSTodor Tomov #define CAMIF_TIMEOUT_ALL_US 1000000 208051a01acSTodor Tomov 209051a01acSTodor Tomov #define MSM_VFE_VFE0_UB_SIZE 1023 210051a01acSTodor Tomov #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 211051a01acSTodor Tomov 212051a01acSTodor Tomov static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 213051a01acSTodor Tomov { 214051a01acSTodor Tomov u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 215051a01acSTodor Tomov 216051a01acSTodor Tomov dev_dbg(dev, "VFE HW Version = 0x%08x\n", hw_version); 217051a01acSTodor Tomov } 218051a01acSTodor Tomov 219051a01acSTodor Tomov static u16 vfe_get_ub_size(u8 vfe_id) 220051a01acSTodor Tomov { 221051a01acSTodor Tomov if (vfe_id == 0) 222051a01acSTodor Tomov return MSM_VFE_VFE0_UB_SIZE_RDI; 223051a01acSTodor Tomov 224051a01acSTodor Tomov return 0; 225051a01acSTodor Tomov } 226051a01acSTodor Tomov 227051a01acSTodor Tomov static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 228051a01acSTodor Tomov { 229051a01acSTodor Tomov u32 bits = readl_relaxed(vfe->base + reg); 230051a01acSTodor Tomov 231051a01acSTodor Tomov writel_relaxed(bits & ~clr_bits, vfe->base + reg); 232051a01acSTodor Tomov } 233051a01acSTodor Tomov 234051a01acSTodor Tomov static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 235051a01acSTodor Tomov { 236051a01acSTodor Tomov u32 bits = readl_relaxed(vfe->base + reg); 237051a01acSTodor Tomov 238051a01acSTodor Tomov writel_relaxed(bits | set_bits, vfe->base + reg); 239051a01acSTodor Tomov } 240051a01acSTodor Tomov 241051a01acSTodor Tomov static void vfe_global_reset(struct vfe_device *vfe) 242051a01acSTodor Tomov { 243051a01acSTodor Tomov u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN | 244051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 245051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_PM | 246051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_TIMER | 247051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_REGISTER | 248051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 249051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS | 250051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_CAMIF | 251051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_CORE; 252051a01acSTodor Tomov 253051a01acSTodor Tomov writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 254051a01acSTodor Tomov } 255051a01acSTodor Tomov 256051a01acSTodor Tomov static void vfe_halt_request(struct vfe_device *vfe) 257051a01acSTodor Tomov { 258051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 259051a01acSTodor Tomov vfe->base + VFE_0_BUS_BDG_CMD); 260051a01acSTodor Tomov } 261051a01acSTodor Tomov 262051a01acSTodor Tomov static void vfe_halt_clear(struct vfe_device *vfe) 263051a01acSTodor Tomov { 264051a01acSTodor Tomov writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 265051a01acSTodor Tomov } 266051a01acSTodor Tomov 267051a01acSTodor Tomov static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 268051a01acSTodor Tomov { 269051a01acSTodor Tomov if (enable) 270051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 271051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 272051a01acSTodor Tomov else 273051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 274051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 275051a01acSTodor Tomov } 276051a01acSTodor Tomov 277051a01acSTodor Tomov static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 278051a01acSTodor Tomov { 279051a01acSTodor Tomov if (enable) 280051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 281051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 282051a01acSTodor Tomov else 283051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 284051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 285051a01acSTodor Tomov } 286051a01acSTodor Tomov 287051a01acSTodor Tomov #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 288051a01acSTodor Tomov 289051a01acSTodor Tomov static int vfe_word_per_line(u32 format, u32 pixel_per_line) 290051a01acSTodor Tomov { 291051a01acSTodor Tomov int val = 0; 292051a01acSTodor Tomov 293051a01acSTodor Tomov switch (format) { 294051a01acSTodor Tomov case V4L2_PIX_FMT_NV12: 295051a01acSTodor Tomov case V4L2_PIX_FMT_NV21: 296051a01acSTodor Tomov case V4L2_PIX_FMT_NV16: 297051a01acSTodor Tomov case V4L2_PIX_FMT_NV61: 298051a01acSTodor Tomov val = CALC_WORD(pixel_per_line, 1, 8); 299051a01acSTodor Tomov break; 300051a01acSTodor Tomov case V4L2_PIX_FMT_YUYV: 301051a01acSTodor Tomov case V4L2_PIX_FMT_YVYU: 302051a01acSTodor Tomov case V4L2_PIX_FMT_UYVY: 303051a01acSTodor Tomov case V4L2_PIX_FMT_VYUY: 304051a01acSTodor Tomov val = CALC_WORD(pixel_per_line, 2, 8); 305051a01acSTodor Tomov break; 306051a01acSTodor Tomov } 307051a01acSTodor Tomov 308051a01acSTodor Tomov return val; 309051a01acSTodor Tomov } 310051a01acSTodor Tomov 311051a01acSTodor Tomov static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 312051a01acSTodor Tomov u16 *width, u16 *height, u16 *bytesperline) 313051a01acSTodor Tomov { 314051a01acSTodor Tomov switch (pix->pixelformat) { 315051a01acSTodor Tomov case V4L2_PIX_FMT_NV12: 316051a01acSTodor Tomov case V4L2_PIX_FMT_NV21: 317051a01acSTodor Tomov *width = pix->width; 318051a01acSTodor Tomov *height = pix->height; 319051a01acSTodor Tomov *bytesperline = pix->plane_fmt[0].bytesperline; 320051a01acSTodor Tomov if (plane == 1) 321051a01acSTodor Tomov *height /= 2; 322051a01acSTodor Tomov break; 323051a01acSTodor Tomov case V4L2_PIX_FMT_NV16: 324051a01acSTodor Tomov case V4L2_PIX_FMT_NV61: 325051a01acSTodor Tomov *width = pix->width; 326051a01acSTodor Tomov *height = pix->height; 327051a01acSTodor Tomov *bytesperline = pix->plane_fmt[0].bytesperline; 328051a01acSTodor Tomov break; 329051a01acSTodor Tomov } 330051a01acSTodor Tomov } 331051a01acSTodor Tomov 332051a01acSTodor Tomov static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 333051a01acSTodor Tomov struct v4l2_pix_format_mplane *pix, 334051a01acSTodor Tomov u8 plane, u32 enable) 335051a01acSTodor Tomov { 336051a01acSTodor Tomov u32 reg; 337051a01acSTodor Tomov 338051a01acSTodor Tomov if (enable) { 339051a01acSTodor Tomov u16 width = 0, height = 0, bytesperline = 0, wpl; 340051a01acSTodor Tomov 341051a01acSTodor Tomov vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 342051a01acSTodor Tomov 343051a01acSTodor Tomov wpl = vfe_word_per_line(pix->pixelformat, width); 344051a01acSTodor Tomov 345051a01acSTodor Tomov reg = height - 1; 346051a01acSTodor Tomov reg |= ((wpl + 1) / 2 - 1) << 16; 347051a01acSTodor Tomov 348051a01acSTodor Tomov writel_relaxed(reg, vfe->base + 349051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 350051a01acSTodor Tomov 351051a01acSTodor Tomov wpl = vfe_word_per_line(pix->pixelformat, bytesperline); 352051a01acSTodor Tomov 353051a01acSTodor Tomov reg = 0x3; 354051a01acSTodor Tomov reg |= (height - 1) << 4; 355051a01acSTodor Tomov reg |= wpl << 16; 356051a01acSTodor Tomov 357051a01acSTodor Tomov writel_relaxed(reg, vfe->base + 358051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 359051a01acSTodor Tomov } else { 360051a01acSTodor Tomov writel_relaxed(0, vfe->base + 361051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 362051a01acSTodor Tomov writel_relaxed(0, vfe->base + 363051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 364051a01acSTodor Tomov } 365051a01acSTodor Tomov } 366051a01acSTodor Tomov 367051a01acSTodor Tomov static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 368051a01acSTodor Tomov { 369051a01acSTodor Tomov u32 reg; 370051a01acSTodor Tomov 371051a01acSTodor Tomov reg = readl_relaxed(vfe->base + 372051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 373051a01acSTodor Tomov 374051a01acSTodor Tomov reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 375051a01acSTodor Tomov 376051a01acSTodor Tomov reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 377051a01acSTodor Tomov & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 378051a01acSTodor Tomov 379051a01acSTodor Tomov writel_relaxed(reg, 380051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 381051a01acSTodor Tomov } 382051a01acSTodor Tomov 383051a01acSTodor Tomov static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 384051a01acSTodor Tomov u32 pattern) 385051a01acSTodor Tomov { 386051a01acSTodor Tomov writel_relaxed(pattern, 387051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 388051a01acSTodor Tomov } 389051a01acSTodor Tomov 390051a01acSTodor Tomov static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 391051a01acSTodor Tomov u16 offset, u16 depth) 392051a01acSTodor Tomov { 393051a01acSTodor Tomov u32 reg; 394051a01acSTodor Tomov 395051a01acSTodor Tomov reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 396051a01acSTodor Tomov depth; 397051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 398051a01acSTodor Tomov } 399051a01acSTodor Tomov 400051a01acSTodor Tomov static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 401051a01acSTodor Tomov { 402051a01acSTodor Tomov wmb(); 403051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 404051a01acSTodor Tomov wmb(); 405051a01acSTodor Tomov } 406051a01acSTodor Tomov 407051a01acSTodor Tomov static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 408051a01acSTodor Tomov { 409051a01acSTodor Tomov writel_relaxed(addr, 410051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 411051a01acSTodor Tomov } 412051a01acSTodor Tomov 413051a01acSTodor Tomov static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 414051a01acSTodor Tomov { 415051a01acSTodor Tomov writel_relaxed(addr, 416051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 417051a01acSTodor Tomov } 418051a01acSTodor Tomov 419051a01acSTodor Tomov static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 420051a01acSTodor Tomov { 421051a01acSTodor Tomov u32 reg; 422051a01acSTodor Tomov 423051a01acSTodor Tomov reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 424051a01acSTodor Tomov 425051a01acSTodor Tomov return (reg >> wm) & 0x1; 426051a01acSTodor Tomov } 427051a01acSTodor Tomov 428051a01acSTodor Tomov static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 429051a01acSTodor Tomov { 430051a01acSTodor Tomov if (enable) 431051a01acSTodor Tomov writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); 432051a01acSTodor Tomov else 433051a01acSTodor Tomov writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 434051a01acSTodor Tomov } 435051a01acSTodor Tomov 436051a01acSTodor Tomov static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 437051a01acSTodor Tomov enum vfe_line_id id) 438051a01acSTodor Tomov { 439051a01acSTodor Tomov u32 reg; 440051a01acSTodor Tomov 441051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 442051a01acSTodor Tomov reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 443051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 444051a01acSTodor Tomov 445051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 446051a01acSTodor Tomov reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 447051a01acSTodor Tomov VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 448051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 449051a01acSTodor Tomov 450051a01acSTodor Tomov switch (id) { 451051a01acSTodor Tomov case VFE_LINE_RDI0: 452051a01acSTodor Tomov default: 453051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 454051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 455051a01acSTodor Tomov break; 456051a01acSTodor Tomov case VFE_LINE_RDI1: 457051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 458051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 459051a01acSTodor Tomov break; 460051a01acSTodor Tomov case VFE_LINE_RDI2: 461051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 462051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 463051a01acSTodor Tomov break; 464051a01acSTodor Tomov } 465051a01acSTodor Tomov 466051a01acSTodor Tomov if (wm % 2 == 1) 467051a01acSTodor Tomov reg <<= 16; 468051a01acSTodor Tomov 469051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 470051a01acSTodor Tomov } 471051a01acSTodor Tomov 472051a01acSTodor Tomov static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 473051a01acSTodor Tomov { 474051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 475051a01acSTodor Tomov vfe->base + 476051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 477051a01acSTodor Tomov } 478051a01acSTodor Tomov 479051a01acSTodor Tomov static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 480051a01acSTodor Tomov enum vfe_line_id id) 481051a01acSTodor Tomov { 482051a01acSTodor Tomov u32 reg; 483051a01acSTodor Tomov 484051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 485051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); 486051a01acSTodor Tomov 487051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 488051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 489051a01acSTodor Tomov 490051a01acSTodor Tomov switch (id) { 491051a01acSTodor Tomov case VFE_LINE_RDI0: 492051a01acSTodor Tomov default: 493051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 494051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 495051a01acSTodor Tomov break; 496051a01acSTodor Tomov case VFE_LINE_RDI1: 497051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 498051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 499051a01acSTodor Tomov break; 500051a01acSTodor Tomov case VFE_LINE_RDI2: 501051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 502051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 503051a01acSTodor Tomov break; 504051a01acSTodor Tomov } 505051a01acSTodor Tomov 506051a01acSTodor Tomov if (wm % 2 == 1) 507051a01acSTodor Tomov reg <<= 16; 508051a01acSTodor Tomov 509051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 510051a01acSTodor Tomov } 511051a01acSTodor Tomov 512051a01acSTodor Tomov static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 513051a01acSTodor Tomov u8 enable) 514051a01acSTodor Tomov { 515051a01acSTodor Tomov struct vfe_line *line = container_of(output, struct vfe_line, output); 516051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 517051a01acSTodor Tomov u32 reg; 518051a01acSTodor Tomov unsigned int i; 519051a01acSTodor Tomov 520051a01acSTodor Tomov for (i = 0; i < output->wm_num; i++) { 521051a01acSTodor Tomov if (i == 0) { 522051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 523051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 524051a01acSTodor Tomov } else if (i == 1) { 525051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 526051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 527051a01acSTodor Tomov reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 528051a01acSTodor Tomov } else { 529051a01acSTodor Tomov /* On current devices output->wm_num is always <= 2 */ 530051a01acSTodor Tomov break; 531051a01acSTodor Tomov } 532051a01acSTodor Tomov 533051a01acSTodor Tomov if (output->wm_idx[i] % 2 == 1) 534051a01acSTodor Tomov reg <<= 16; 535051a01acSTodor Tomov 536051a01acSTodor Tomov if (enable) 537051a01acSTodor Tomov vfe_reg_set(vfe, 538051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 539051a01acSTodor Tomov reg); 540051a01acSTodor Tomov else 541051a01acSTodor Tomov vfe_reg_clr(vfe, 542051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 543051a01acSTodor Tomov reg); 544051a01acSTodor Tomov } 545051a01acSTodor Tomov } 546051a01acSTodor Tomov 547312e1c85STodor Tomov static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 548312e1c85STodor Tomov u8 enable) 549312e1c85STodor Tomov { 550312e1c85STodor Tomov /* empty */ 551312e1c85STodor Tomov } 552051a01acSTodor Tomov static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 553051a01acSTodor Tomov { 554051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 555051a01acSTodor Tomov VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 556051a01acSTodor Tomov 557051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 558051a01acSTodor Tomov cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 559051a01acSTodor Tomov } 560051a01acSTodor Tomov 561051a01acSTodor Tomov static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 562051a01acSTodor Tomov { 563051a01acSTodor Tomov vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 564051a01acSTodor Tomov wmb(); 565051a01acSTodor Tomov writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 566051a01acSTodor Tomov wmb(); 567051a01acSTodor Tomov } 568051a01acSTodor Tomov 569051a01acSTodor Tomov static inline void vfe_reg_update_clear(struct vfe_device *vfe, 570051a01acSTodor Tomov enum vfe_line_id line_id) 571051a01acSTodor Tomov { 572051a01acSTodor Tomov vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 573051a01acSTodor Tomov } 574051a01acSTodor Tomov 575051a01acSTodor Tomov static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 576051a01acSTodor Tomov enum vfe_line_id line_id, u8 enable) 577051a01acSTodor Tomov { 578051a01acSTodor Tomov u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 579051a01acSTodor Tomov VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 580051a01acSTodor Tomov u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 581051a01acSTodor Tomov VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 582051a01acSTodor Tomov 583051a01acSTodor Tomov if (enable) { 584051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 585051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 586051a01acSTodor Tomov } else { 587051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 588051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 589051a01acSTodor Tomov } 590051a01acSTodor Tomov } 591051a01acSTodor Tomov 592051a01acSTodor Tomov static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 593051a01acSTodor Tomov enum vfe_line_id line_id, u8 enable) 594051a01acSTodor Tomov { 595051a01acSTodor Tomov struct vfe_output *output = &vfe->line[line_id].output; 596051a01acSTodor Tomov unsigned int i; 597051a01acSTodor Tomov u32 irq_en0; 598051a01acSTodor Tomov u32 irq_en1; 599051a01acSTodor Tomov u32 comp_mask = 0; 600051a01acSTodor Tomov 601051a01acSTodor Tomov irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 602051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 603051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 604051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 605051a01acSTodor Tomov irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 606051a01acSTodor Tomov for (i = 0; i < output->wm_num; i++) { 607051a01acSTodor Tomov irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 608051a01acSTodor Tomov output->wm_idx[i]); 609051a01acSTodor Tomov comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 610051a01acSTodor Tomov } 611051a01acSTodor Tomov 612051a01acSTodor Tomov if (enable) { 613051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 614051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 615051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 616051a01acSTodor Tomov } else { 617051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 618051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 619051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 620051a01acSTodor Tomov } 621051a01acSTodor Tomov } 622051a01acSTodor Tomov 623051a01acSTodor Tomov static void vfe_enable_irq_common(struct vfe_device *vfe) 624051a01acSTodor Tomov { 625051a01acSTodor Tomov u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 626051a01acSTodor Tomov u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 627051a01acSTodor Tomov VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 628051a01acSTodor Tomov 629051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 630051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 631051a01acSTodor Tomov } 632051a01acSTodor Tomov 633051a01acSTodor Tomov static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 634051a01acSTodor Tomov { 635051a01acSTodor Tomov u32 val, even_cfg, odd_cfg; 636051a01acSTodor Tomov 637051a01acSTodor Tomov writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 638051a01acSTodor Tomov 639051a01acSTodor Tomov val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 640051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 641051a01acSTodor Tomov 642051a01acSTodor Tomov val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 643051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 644051a01acSTodor Tomov 645051a01acSTodor Tomov switch (line->fmt[MSM_VFE_PAD_SINK].code) { 646051a01acSTodor Tomov case MEDIA_BUS_FMT_YUYV8_2X8: 647051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 648051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 649051a01acSTodor Tomov break; 650051a01acSTodor Tomov case MEDIA_BUS_FMT_YVYU8_2X8: 651051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 652051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 653051a01acSTodor Tomov break; 654051a01acSTodor Tomov case MEDIA_BUS_FMT_UYVY8_2X8: 655051a01acSTodor Tomov default: 656051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 657051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 658051a01acSTodor Tomov break; 659051a01acSTodor Tomov case MEDIA_BUS_FMT_VYUY8_2X8: 660051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 661051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 662051a01acSTodor Tomov break; 663051a01acSTodor Tomov } 664051a01acSTodor Tomov 665051a01acSTodor Tomov writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 666051a01acSTodor Tomov writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 667051a01acSTodor Tomov } 668051a01acSTodor Tomov 669051a01acSTodor Tomov static inline u8 vfe_calc_interp_reso(u16 input, u16 output) 670051a01acSTodor Tomov { 671051a01acSTodor Tomov if (input / output >= 16) 672051a01acSTodor Tomov return 0; 673051a01acSTodor Tomov 674051a01acSTodor Tomov if (input / output >= 8) 675051a01acSTodor Tomov return 1; 676051a01acSTodor Tomov 677051a01acSTodor Tomov if (input / output >= 4) 678051a01acSTodor Tomov return 2; 679051a01acSTodor Tomov 680051a01acSTodor Tomov return 3; 681051a01acSTodor Tomov } 682051a01acSTodor Tomov 683051a01acSTodor Tomov static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 684051a01acSTodor Tomov { 685051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 686051a01acSTodor Tomov u32 reg; 687051a01acSTodor Tomov u16 input, output; 688051a01acSTodor Tomov u8 interp_reso; 689051a01acSTodor Tomov u32 phase_mult; 690051a01acSTodor Tomov 691051a01acSTodor Tomov writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 692051a01acSTodor Tomov 693051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].width; 694051a01acSTodor Tomov output = line->compose.width; 695051a01acSTodor Tomov reg = (output << 16) | input; 696051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 697051a01acSTodor Tomov 698051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 699051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 700051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 701051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 702051a01acSTodor Tomov 703051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].height; 704051a01acSTodor Tomov output = line->compose.height; 705051a01acSTodor Tomov reg = (output << 16) | input; 706051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 707051a01acSTodor Tomov 708051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 709051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 710051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 711051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 712051a01acSTodor Tomov 713051a01acSTodor Tomov writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 714051a01acSTodor Tomov 715051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].width; 716051a01acSTodor Tomov output = line->compose.width / 2; 717051a01acSTodor Tomov reg = (output << 16) | input; 718051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 719051a01acSTodor Tomov 720051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 721051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 722051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 723051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 724051a01acSTodor Tomov 725051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].height; 726051a01acSTodor Tomov output = line->compose.height; 727051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 728051a01acSTodor Tomov output = line->compose.height / 2; 729051a01acSTodor Tomov reg = (output << 16) | input; 730051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 731051a01acSTodor Tomov 732051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 733051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 734051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 735051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 736051a01acSTodor Tomov } 737051a01acSTodor Tomov 738051a01acSTodor Tomov static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 739051a01acSTodor Tomov { 740051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 741051a01acSTodor Tomov u32 reg; 742051a01acSTodor Tomov u16 first, last; 743051a01acSTodor Tomov 744051a01acSTodor Tomov first = line->crop.left; 745051a01acSTodor Tomov last = line->crop.left + line->crop.width - 1; 746051a01acSTodor Tomov reg = (first << 16) | last; 747051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 748051a01acSTodor Tomov 749051a01acSTodor Tomov first = line->crop.top; 750051a01acSTodor Tomov last = line->crop.top + line->crop.height - 1; 751051a01acSTodor Tomov reg = (first << 16) | last; 752051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 753051a01acSTodor Tomov 754051a01acSTodor Tomov first = line->crop.left / 2; 755051a01acSTodor Tomov last = line->crop.left / 2 + line->crop.width / 2 - 1; 756051a01acSTodor Tomov reg = (first << 16) | last; 757051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 758051a01acSTodor Tomov 759051a01acSTodor Tomov first = line->crop.top; 760051a01acSTodor Tomov last = line->crop.top + line->crop.height - 1; 761051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 762051a01acSTodor Tomov first = line->crop.top / 2; 763051a01acSTodor Tomov last = line->crop.top / 2 + line->crop.height / 2 - 1; 764051a01acSTodor Tomov } 765051a01acSTodor Tomov reg = (first << 16) | last; 766051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 767051a01acSTodor Tomov } 768051a01acSTodor Tomov 769051a01acSTodor Tomov static void vfe_set_clamp_cfg(struct vfe_device *vfe) 770051a01acSTodor Tomov { 771051a01acSTodor Tomov u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 772051a01acSTodor Tomov VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 773051a01acSTodor Tomov VFE_0_CLAMP_ENC_MAX_CFG_CH2; 774051a01acSTodor Tomov 775051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 776051a01acSTodor Tomov 777051a01acSTodor Tomov val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 778051a01acSTodor Tomov VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 779051a01acSTodor Tomov VFE_0_CLAMP_ENC_MIN_CFG_CH2; 780051a01acSTodor Tomov 781051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 782051a01acSTodor Tomov } 783051a01acSTodor Tomov 784051a01acSTodor Tomov static void vfe_set_qos(struct vfe_device *vfe) 785051a01acSTodor Tomov { 786051a01acSTodor Tomov u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 787051a01acSTodor Tomov u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 788051a01acSTodor Tomov 789051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 790051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 791051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 792051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 793051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 794051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 795051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 796051a01acSTodor Tomov writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 797051a01acSTodor Tomov } 798051a01acSTodor Tomov 7994e1abf66STodor Tomov static void vfe_set_ds(struct vfe_device *vfe) 8004e1abf66STodor Tomov { 8014e1abf66STodor Tomov /* empty */ 8024e1abf66STodor Tomov } 8034e1abf66STodor Tomov 804051a01acSTodor Tomov static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 805051a01acSTodor Tomov { 806051a01acSTodor Tomov u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); 807051a01acSTodor Tomov 808051a01acSTodor Tomov if (enable) 809051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); 810051a01acSTodor Tomov else 811051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); 812051a01acSTodor Tomov 813051a01acSTodor Tomov wmb(); 814051a01acSTodor Tomov } 815051a01acSTodor Tomov 816051a01acSTodor Tomov static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 817051a01acSTodor Tomov { 818051a01acSTodor Tomov u32 val; 819051a01acSTodor Tomov 820051a01acSTodor Tomov switch (line->fmt[MSM_VFE_PAD_SINK].code) { 821051a01acSTodor Tomov case MEDIA_BUS_FMT_YUYV8_2X8: 822051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 823051a01acSTodor Tomov break; 824051a01acSTodor Tomov case MEDIA_BUS_FMT_YVYU8_2X8: 825051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 826051a01acSTodor Tomov break; 827051a01acSTodor Tomov case MEDIA_BUS_FMT_UYVY8_2X8: 828051a01acSTodor Tomov default: 829051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 830051a01acSTodor Tomov break; 831051a01acSTodor Tomov case MEDIA_BUS_FMT_VYUY8_2X8: 832051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 833051a01acSTodor Tomov break; 834051a01acSTodor Tomov } 835051a01acSTodor Tomov 836051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 837051a01acSTodor Tomov 838051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].width * 2; 839051a01acSTodor Tomov val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; 840051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 841051a01acSTodor Tomov 842051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 843051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 844051a01acSTodor Tomov 845051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 846051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 847051a01acSTodor Tomov 848051a01acSTodor Tomov val = 0xffffffff; 849051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); 850051a01acSTodor Tomov 851051a01acSTodor Tomov val = 0xffffffff; 852051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 853051a01acSTodor Tomov 854051a01acSTodor Tomov val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 855051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 856051a01acSTodor Tomov 857051a01acSTodor Tomov val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 858051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 859051a01acSTodor Tomov } 860051a01acSTodor Tomov 861051a01acSTodor Tomov static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 862051a01acSTodor Tomov { 863051a01acSTodor Tomov u32 cmd; 864051a01acSTodor Tomov 865051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 866051a01acSTodor Tomov writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 867051a01acSTodor Tomov wmb(); 868051a01acSTodor Tomov 869051a01acSTodor Tomov if (enable) 870051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 871051a01acSTodor Tomov else 872051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 873051a01acSTodor Tomov 874051a01acSTodor Tomov writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 875051a01acSTodor Tomov } 876051a01acSTodor Tomov 877051a01acSTodor Tomov static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 878051a01acSTodor Tomov { 879051a01acSTodor Tomov u32 val = VFE_0_MODULE_CFG_DEMUX | 880051a01acSTodor Tomov VFE_0_MODULE_CFG_CHROMA_UPSAMPLE | 881051a01acSTodor Tomov VFE_0_MODULE_CFG_SCALE_ENC | 882051a01acSTodor Tomov VFE_0_MODULE_CFG_CROP_ENC; 883051a01acSTodor Tomov 884051a01acSTodor Tomov if (enable) 885051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); 886051a01acSTodor Tomov else 887051a01acSTodor Tomov writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); 888051a01acSTodor Tomov } 889051a01acSTodor Tomov 890051a01acSTodor Tomov static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 891051a01acSTodor Tomov { 892051a01acSTodor Tomov u32 val; 893051a01acSTodor Tomov int ret; 894051a01acSTodor Tomov 895051a01acSTodor Tomov ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 896051a01acSTodor Tomov val, 897051a01acSTodor Tomov (val & VFE_0_CAMIF_STATUS_HALT), 898051a01acSTodor Tomov CAMIF_TIMEOUT_SLEEP_US, 899051a01acSTodor Tomov CAMIF_TIMEOUT_ALL_US); 900051a01acSTodor Tomov if (ret < 0) 901051a01acSTodor Tomov dev_err(dev, "%s: camif stop timeout\n", __func__); 902051a01acSTodor Tomov 903051a01acSTodor Tomov return ret; 904051a01acSTodor Tomov } 905051a01acSTodor Tomov 906051a01acSTodor Tomov static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 907051a01acSTodor Tomov { 908051a01acSTodor Tomov *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 909051a01acSTodor Tomov *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 910051a01acSTodor Tomov 911051a01acSTodor Tomov writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 912051a01acSTodor Tomov writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 913051a01acSTodor Tomov 914051a01acSTodor Tomov wmb(); 915051a01acSTodor Tomov writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 916051a01acSTodor Tomov } 917051a01acSTodor Tomov 918051a01acSTodor Tomov static void vfe_violation_read(struct vfe_device *vfe) 919051a01acSTodor Tomov { 920051a01acSTodor Tomov u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 921051a01acSTodor Tomov 922051a01acSTodor Tomov pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 923051a01acSTodor Tomov } 924051a01acSTodor Tomov 925051a01acSTodor Tomov /* 926ad46e1a8SRobert Foss * vfe_isr - VFE module interrupt handler 927051a01acSTodor Tomov * @irq: Interrupt line 928051a01acSTodor Tomov * @dev: VFE device 929051a01acSTodor Tomov * 930051a01acSTodor Tomov * Return IRQ_HANDLED on success 931051a01acSTodor Tomov */ 932051a01acSTodor Tomov static irqreturn_t vfe_isr(int irq, void *dev) 933051a01acSTodor Tomov { 934051a01acSTodor Tomov struct vfe_device *vfe = dev; 935051a01acSTodor Tomov u32 value0, value1; 936051a01acSTodor Tomov int i, j; 937051a01acSTodor Tomov 938051a01acSTodor Tomov vfe->ops->isr_read(vfe, &value0, &value1); 939051a01acSTodor Tomov 940*c3177cb0SRobert Foss dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", 941051a01acSTodor Tomov value0, value1); 942051a01acSTodor Tomov 943051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 944051a01acSTodor Tomov vfe->isr_ops.reset_ack(vfe); 945051a01acSTodor Tomov 946051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 947051a01acSTodor Tomov vfe->ops->violation_read(vfe); 948051a01acSTodor Tomov 949051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 950051a01acSTodor Tomov vfe->isr_ops.halt_ack(vfe); 951051a01acSTodor Tomov 952051a01acSTodor Tomov for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 953051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 954051a01acSTodor Tomov vfe->isr_ops.reg_update(vfe, i); 955051a01acSTodor Tomov 956051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 957051a01acSTodor Tomov vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 958051a01acSTodor Tomov 959051a01acSTodor Tomov for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 960051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 961051a01acSTodor Tomov vfe->isr_ops.sof(vfe, i); 962051a01acSTodor Tomov 963051a01acSTodor Tomov for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 964051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 965051a01acSTodor Tomov vfe->isr_ops.comp_done(vfe, i); 966051a01acSTodor Tomov for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 967051a01acSTodor Tomov if (vfe->wm_output_map[j] == VFE_LINE_PIX) 968051a01acSTodor Tomov value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 969051a01acSTodor Tomov } 970051a01acSTodor Tomov 971051a01acSTodor Tomov for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 972051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 973051a01acSTodor Tomov vfe->isr_ops.wm_done(vfe, i); 974051a01acSTodor Tomov 975051a01acSTodor Tomov return IRQ_HANDLED; 976051a01acSTodor Tomov } 977051a01acSTodor Tomov 978051a01acSTodor Tomov const struct vfe_hw_ops vfe_ops_4_1 = { 979051a01acSTodor Tomov .hw_version_read = vfe_hw_version_read, 980051a01acSTodor Tomov .get_ub_size = vfe_get_ub_size, 981051a01acSTodor Tomov .global_reset = vfe_global_reset, 982051a01acSTodor Tomov .halt_request = vfe_halt_request, 983051a01acSTodor Tomov .halt_clear = vfe_halt_clear, 984051a01acSTodor Tomov .wm_enable = vfe_wm_enable, 985051a01acSTodor Tomov .wm_frame_based = vfe_wm_frame_based, 986051a01acSTodor Tomov .wm_line_based = vfe_wm_line_based, 987051a01acSTodor Tomov .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 988051a01acSTodor Tomov .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 989051a01acSTodor Tomov .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 990051a01acSTodor Tomov .bus_reload_wm = vfe_bus_reload_wm, 991051a01acSTodor Tomov .wm_set_ping_addr = vfe_wm_set_ping_addr, 992051a01acSTodor Tomov .wm_set_pong_addr = vfe_wm_set_pong_addr, 993051a01acSTodor Tomov .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 994051a01acSTodor Tomov .bus_enable_wr_if = vfe_bus_enable_wr_if, 995051a01acSTodor Tomov .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 996051a01acSTodor Tomov .wm_set_subsample = vfe_wm_set_subsample, 997051a01acSTodor Tomov .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 998051a01acSTodor Tomov .set_xbar_cfg = vfe_set_xbar_cfg, 999312e1c85STodor Tomov .set_realign_cfg = vfe_set_realign_cfg, 1000051a01acSTodor Tomov .set_rdi_cid = vfe_set_rdi_cid, 1001051a01acSTodor Tomov .reg_update = vfe_reg_update, 1002051a01acSTodor Tomov .reg_update_clear = vfe_reg_update_clear, 1003051a01acSTodor Tomov .enable_irq_wm_line = vfe_enable_irq_wm_line, 1004051a01acSTodor Tomov .enable_irq_pix_line = vfe_enable_irq_pix_line, 1005051a01acSTodor Tomov .enable_irq_common = vfe_enable_irq_common, 1006051a01acSTodor Tomov .set_demux_cfg = vfe_set_demux_cfg, 1007051a01acSTodor Tomov .set_scale_cfg = vfe_set_scale_cfg, 1008051a01acSTodor Tomov .set_crop_cfg = vfe_set_crop_cfg, 1009051a01acSTodor Tomov .set_clamp_cfg = vfe_set_clamp_cfg, 1010051a01acSTodor Tomov .set_qos = vfe_set_qos, 10114e1abf66STodor Tomov .set_ds = vfe_set_ds, 1012051a01acSTodor Tomov .set_cgc_override = vfe_set_cgc_override, 1013051a01acSTodor Tomov .set_camif_cfg = vfe_set_camif_cfg, 1014051a01acSTodor Tomov .set_camif_cmd = vfe_set_camif_cmd, 1015051a01acSTodor Tomov .set_module_cfg = vfe_set_module_cfg, 1016051a01acSTodor Tomov .camif_wait_for_stop = vfe_camif_wait_for_stop, 1017051a01acSTodor Tomov .isr_read = vfe_isr_read, 1018051a01acSTodor Tomov .violation_read = vfe_violation_read, 1019051a01acSTodor Tomov .isr = vfe_isr, 1020051a01acSTodor Tomov }; 1021