1051a01acSTodor Tomov // SPDX-License-Identifier: GPL-2.0 2051a01acSTodor Tomov /* 3051a01acSTodor Tomov * camss-vfe-4-1.c 4051a01acSTodor Tomov * 5051a01acSTodor Tomov * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1 6051a01acSTodor Tomov * 7051a01acSTodor Tomov * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8051a01acSTodor Tomov * Copyright (C) 2015-2018 Linaro Ltd. 9051a01acSTodor Tomov */ 10051a01acSTodor Tomov 11051a01acSTodor Tomov #include <linux/interrupt.h> 123799eca5SArnd Bergmann #include <linux/io.h> 13051a01acSTodor Tomov #include <linux/iopoll.h> 14051a01acSTodor Tomov 15c3177cb0SRobert Foss #include "camss.h" 16051a01acSTodor Tomov #include "camss-vfe.h" 17*633b388fSRobert Foss #include "camss-vfe-gen1.h" 18051a01acSTodor Tomov 19051a01acSTodor Tomov #define VFE_0_HW_VERSION 0x000 20051a01acSTodor Tomov 21051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD 0x00c 22051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 23051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 24051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 25051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 26051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 27051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) 28051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) 29051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) 30051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) 31051a01acSTodor Tomov 32051a01acSTodor Tomov #define VFE_0_MODULE_CFG 0x018 33051a01acSTodor Tomov #define VFE_0_MODULE_CFG_DEMUX BIT(2) 34051a01acSTodor Tomov #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) 35051a01acSTodor Tomov #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) 36051a01acSTodor Tomov #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) 37051a01acSTodor Tomov 38051a01acSTodor Tomov #define VFE_0_CORE_CFG 0x01c 39051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 40051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 41051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 42051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 43051a01acSTodor Tomov 44051a01acSTodor Tomov #define VFE_0_IRQ_CMD 0x024 45051a01acSTodor Tomov #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 46051a01acSTodor Tomov 47051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0 0x028 48051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 49051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 50051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 51051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 52051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 53051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 54051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 55051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 56051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1 0x02c 57051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 58051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 59051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 60051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 61051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 62051a01acSTodor Tomov 63051a01acSTodor Tomov #define VFE_0_IRQ_CLEAR_0 0x030 64051a01acSTodor Tomov #define VFE_0_IRQ_CLEAR_1 0x034 65051a01acSTodor Tomov 66051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0 0x038 67051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 68051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 69051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 70051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 71051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 72051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 73051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 74051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1 0x03c 75051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 76051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 77051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 78051a01acSTodor Tomov 79051a01acSTodor Tomov #define VFE_0_IRQ_COMPOSITE_MASK_0 0x40 80051a01acSTodor Tomov #define VFE_0_VIOLATION_STATUS 0x48 81051a01acSTodor Tomov 82051a01acSTodor Tomov #define VFE_0_BUS_CMD 0x4c 83051a01acSTodor Tomov #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 84051a01acSTodor Tomov 85051a01acSTodor Tomov #define VFE_0_BUS_CFG 0x050 86051a01acSTodor Tomov 87051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2)) 88051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) 89051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 90051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 91051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0 92051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5 93051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6 94051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7 95051a01acSTodor Tomov 96051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n)) 97051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 98051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1 99051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n)) 100051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n)) 101051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n)) 102051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 103051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 104051a01acSTodor Tomov 105051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n)) 106051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 107051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n)) 108051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n)) 109051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 110051a01acSTodor Tomov (0x088 + 0x24 * (n)) 111051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 112051a01acSTodor Tomov (0x08c + 0x24 * (n)) 113051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 114051a01acSTodor Tomov 115051a01acSTodor Tomov #define VFE_0_BUS_PING_PONG_STATUS 0x268 116051a01acSTodor Tomov 117051a01acSTodor Tomov #define VFE_0_BUS_BDG_CMD 0x2c0 118051a01acSTodor Tomov #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 119051a01acSTodor Tomov 120051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4 121051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 122051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8 123051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc 124051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0 125051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4 126051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8 127051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc 128051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0 129051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5 130051a01acSTodor Tomov 131051a01acSTodor Tomov #define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x))) 132051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 133051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 134051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 135051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 136051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 137051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 138051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) 139051a01acSTodor Tomov 140051a01acSTodor Tomov #define VFE_0_CAMIF_CMD 0x2f4 141051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 142051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 143051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_NO_CHANGE 3 144051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 145051a01acSTodor Tomov #define VFE_0_CAMIF_CFG 0x2f8 146051a01acSTodor Tomov #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 147051a01acSTodor Tomov #define VFE_0_CAMIF_FRAME_CFG 0x300 148051a01acSTodor Tomov #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304 149051a01acSTodor Tomov #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308 150051a01acSTodor Tomov #define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c 151051a01acSTodor Tomov #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314 152051a01acSTodor Tomov #define VFE_0_CAMIF_STATUS 0x31c 153051a01acSTodor Tomov #define VFE_0_CAMIF_STATUS_HALT BIT(31) 154051a01acSTodor Tomov 155051a01acSTodor Tomov #define VFE_0_REG_UPDATE 0x378 156051a01acSTodor Tomov #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 157051a01acSTodor Tomov #define VFE_0_REG_UPDATE_line_n(n) \ 158051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 159051a01acSTodor Tomov 160051a01acSTodor Tomov #define VFE_0_DEMUX_CFG 0x424 161051a01acSTodor Tomov #define VFE_0_DEMUX_CFG_PERIOD 0x3 162051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0 0x428 163051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 164051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 165051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1 0x42c 166051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 167051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 168051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG 0x438 169051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 170051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 171051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 172051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 173051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG 0x43c 174051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 175051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 176051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 177051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 178051a01acSTodor Tomov 179051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_CFG 0x75c 180051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760 181051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_H_PHASE 0x764 182051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c 183051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_V_PHASE 0x770 184051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_CFG 0x778 185051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c 186051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 187051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 188051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 189051a01acSTodor Tomov 190051a01acSTodor Tomov #define VFE_0_CROP_ENC_Y_WIDTH 0x854 191051a01acSTodor Tomov #define VFE_0_CROP_ENC_Y_HEIGHT 0x858 192051a01acSTodor Tomov #define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c 193051a01acSTodor Tomov #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860 194051a01acSTodor Tomov 195051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG 0x874 196051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 197051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 198051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 199051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG 0x878 200051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 201051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 202051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 203051a01acSTodor Tomov 204051a01acSTodor Tomov #define VFE_0_CGC_OVERRIDE_1 0x974 205051a01acSTodor Tomov #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) 206051a01acSTodor Tomov 207051a01acSTodor Tomov #define CAMIF_TIMEOUT_SLEEP_US 1000 208051a01acSTodor Tomov #define CAMIF_TIMEOUT_ALL_US 1000000 209051a01acSTodor Tomov 210051a01acSTodor Tomov #define MSM_VFE_VFE0_UB_SIZE 1023 211051a01acSTodor Tomov #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 212051a01acSTodor Tomov 213051a01acSTodor Tomov static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 214051a01acSTodor Tomov { 215051a01acSTodor Tomov u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 216051a01acSTodor Tomov 217051a01acSTodor Tomov dev_dbg(dev, "VFE HW Version = 0x%08x\n", hw_version); 218051a01acSTodor Tomov } 219051a01acSTodor Tomov 220051a01acSTodor Tomov static u16 vfe_get_ub_size(u8 vfe_id) 221051a01acSTodor Tomov { 222051a01acSTodor Tomov if (vfe_id == 0) 223051a01acSTodor Tomov return MSM_VFE_VFE0_UB_SIZE_RDI; 224051a01acSTodor Tomov 225051a01acSTodor Tomov return 0; 226051a01acSTodor Tomov } 227051a01acSTodor Tomov 228051a01acSTodor Tomov static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 229051a01acSTodor Tomov { 230051a01acSTodor Tomov u32 bits = readl_relaxed(vfe->base + reg); 231051a01acSTodor Tomov 232051a01acSTodor Tomov writel_relaxed(bits & ~clr_bits, vfe->base + reg); 233051a01acSTodor Tomov } 234051a01acSTodor Tomov 235051a01acSTodor Tomov static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 236051a01acSTodor Tomov { 237051a01acSTodor Tomov u32 bits = readl_relaxed(vfe->base + reg); 238051a01acSTodor Tomov 239051a01acSTodor Tomov writel_relaxed(bits | set_bits, vfe->base + reg); 240051a01acSTodor Tomov } 241051a01acSTodor Tomov 242051a01acSTodor Tomov static void vfe_global_reset(struct vfe_device *vfe) 243051a01acSTodor Tomov { 244051a01acSTodor Tomov u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN | 245051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 246051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_PM | 247051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_TIMER | 248051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_REGISTER | 249051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 250051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS | 251051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_CAMIF | 252051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_CORE; 253051a01acSTodor Tomov 254051a01acSTodor Tomov writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 255051a01acSTodor Tomov } 256051a01acSTodor Tomov 257051a01acSTodor Tomov static void vfe_halt_request(struct vfe_device *vfe) 258051a01acSTodor Tomov { 259051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 260051a01acSTodor Tomov vfe->base + VFE_0_BUS_BDG_CMD); 261051a01acSTodor Tomov } 262051a01acSTodor Tomov 263051a01acSTodor Tomov static void vfe_halt_clear(struct vfe_device *vfe) 264051a01acSTodor Tomov { 265051a01acSTodor Tomov writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 266051a01acSTodor Tomov } 267051a01acSTodor Tomov 268051a01acSTodor Tomov static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 269051a01acSTodor Tomov { 270051a01acSTodor Tomov if (enable) 271051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 272051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 273051a01acSTodor Tomov else 274051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 275051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 276051a01acSTodor Tomov } 277051a01acSTodor Tomov 278051a01acSTodor Tomov static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 279051a01acSTodor Tomov { 280051a01acSTodor Tomov if (enable) 281051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 282051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 283051a01acSTodor Tomov else 284051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 285051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 286051a01acSTodor Tomov } 287051a01acSTodor Tomov 288051a01acSTodor Tomov static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 289051a01acSTodor Tomov u16 *width, u16 *height, u16 *bytesperline) 290051a01acSTodor Tomov { 291051a01acSTodor Tomov switch (pix->pixelformat) { 292051a01acSTodor Tomov case V4L2_PIX_FMT_NV12: 293051a01acSTodor Tomov case V4L2_PIX_FMT_NV21: 294051a01acSTodor Tomov *width = pix->width; 295051a01acSTodor Tomov *height = pix->height; 296051a01acSTodor Tomov *bytesperline = pix->plane_fmt[0].bytesperline; 297051a01acSTodor Tomov if (plane == 1) 298051a01acSTodor Tomov *height /= 2; 299051a01acSTodor Tomov break; 300051a01acSTodor Tomov case V4L2_PIX_FMT_NV16: 301051a01acSTodor Tomov case V4L2_PIX_FMT_NV61: 302051a01acSTodor Tomov *width = pix->width; 303051a01acSTodor Tomov *height = pix->height; 304051a01acSTodor Tomov *bytesperline = pix->plane_fmt[0].bytesperline; 305051a01acSTodor Tomov break; 306051a01acSTodor Tomov } 307051a01acSTodor Tomov } 308051a01acSTodor Tomov 309051a01acSTodor Tomov static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 310051a01acSTodor Tomov struct v4l2_pix_format_mplane *pix, 311051a01acSTodor Tomov u8 plane, u32 enable) 312051a01acSTodor Tomov { 313051a01acSTodor Tomov u32 reg; 314051a01acSTodor Tomov 315051a01acSTodor Tomov if (enable) { 316051a01acSTodor Tomov u16 width = 0, height = 0, bytesperline = 0, wpl; 317051a01acSTodor Tomov 318051a01acSTodor Tomov vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 319051a01acSTodor Tomov 320051a01acSTodor Tomov wpl = vfe_word_per_line(pix->pixelformat, width); 321051a01acSTodor Tomov 322051a01acSTodor Tomov reg = height - 1; 323051a01acSTodor Tomov reg |= ((wpl + 1) / 2 - 1) << 16; 324051a01acSTodor Tomov 325051a01acSTodor Tomov writel_relaxed(reg, vfe->base + 326051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 327051a01acSTodor Tomov 328051a01acSTodor Tomov wpl = vfe_word_per_line(pix->pixelformat, bytesperline); 329051a01acSTodor Tomov 330051a01acSTodor Tomov reg = 0x3; 331051a01acSTodor Tomov reg |= (height - 1) << 4; 332051a01acSTodor Tomov reg |= wpl << 16; 333051a01acSTodor Tomov 334051a01acSTodor Tomov writel_relaxed(reg, vfe->base + 335051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 336051a01acSTodor Tomov } else { 337051a01acSTodor Tomov writel_relaxed(0, vfe->base + 338051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 339051a01acSTodor Tomov writel_relaxed(0, vfe->base + 340051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 341051a01acSTodor Tomov } 342051a01acSTodor Tomov } 343051a01acSTodor Tomov 344051a01acSTodor Tomov static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 345051a01acSTodor Tomov { 346051a01acSTodor Tomov u32 reg; 347051a01acSTodor Tomov 348051a01acSTodor Tomov reg = readl_relaxed(vfe->base + 349051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 350051a01acSTodor Tomov 351051a01acSTodor Tomov reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 352051a01acSTodor Tomov 353051a01acSTodor Tomov reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 354051a01acSTodor Tomov & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 355051a01acSTodor Tomov 356051a01acSTodor Tomov writel_relaxed(reg, 357051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 358051a01acSTodor Tomov } 359051a01acSTodor Tomov 360051a01acSTodor Tomov static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 361051a01acSTodor Tomov u32 pattern) 362051a01acSTodor Tomov { 363051a01acSTodor Tomov writel_relaxed(pattern, 364051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 365051a01acSTodor Tomov } 366051a01acSTodor Tomov 367051a01acSTodor Tomov static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 368051a01acSTodor Tomov u16 offset, u16 depth) 369051a01acSTodor Tomov { 370051a01acSTodor Tomov u32 reg; 371051a01acSTodor Tomov 372051a01acSTodor Tomov reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 373051a01acSTodor Tomov depth; 374051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 375051a01acSTodor Tomov } 376051a01acSTodor Tomov 377051a01acSTodor Tomov static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 378051a01acSTodor Tomov { 379051a01acSTodor Tomov wmb(); 380051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 381051a01acSTodor Tomov wmb(); 382051a01acSTodor Tomov } 383051a01acSTodor Tomov 384051a01acSTodor Tomov static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 385051a01acSTodor Tomov { 386051a01acSTodor Tomov writel_relaxed(addr, 387051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 388051a01acSTodor Tomov } 389051a01acSTodor Tomov 390051a01acSTodor Tomov static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 391051a01acSTodor Tomov { 392051a01acSTodor Tomov writel_relaxed(addr, 393051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 394051a01acSTodor Tomov } 395051a01acSTodor Tomov 396051a01acSTodor Tomov static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 397051a01acSTodor Tomov { 398051a01acSTodor Tomov u32 reg; 399051a01acSTodor Tomov 400051a01acSTodor Tomov reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 401051a01acSTodor Tomov 402051a01acSTodor Tomov return (reg >> wm) & 0x1; 403051a01acSTodor Tomov } 404051a01acSTodor Tomov 405051a01acSTodor Tomov static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 406051a01acSTodor Tomov { 407051a01acSTodor Tomov if (enable) 408051a01acSTodor Tomov writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); 409051a01acSTodor Tomov else 410051a01acSTodor Tomov writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 411051a01acSTodor Tomov } 412051a01acSTodor Tomov 413051a01acSTodor Tomov static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 414051a01acSTodor Tomov enum vfe_line_id id) 415051a01acSTodor Tomov { 416051a01acSTodor Tomov u32 reg; 417051a01acSTodor Tomov 418051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 419051a01acSTodor Tomov reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 420051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 421051a01acSTodor Tomov 422051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 423051a01acSTodor Tomov reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 424051a01acSTodor Tomov VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 425051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 426051a01acSTodor Tomov 427051a01acSTodor Tomov switch (id) { 428051a01acSTodor Tomov case VFE_LINE_RDI0: 429051a01acSTodor Tomov default: 430051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 431051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 432051a01acSTodor Tomov break; 433051a01acSTodor Tomov case VFE_LINE_RDI1: 434051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 435051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 436051a01acSTodor Tomov break; 437051a01acSTodor Tomov case VFE_LINE_RDI2: 438051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 439051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 440051a01acSTodor Tomov break; 441051a01acSTodor Tomov } 442051a01acSTodor Tomov 443051a01acSTodor Tomov if (wm % 2 == 1) 444051a01acSTodor Tomov reg <<= 16; 445051a01acSTodor Tomov 446051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 447051a01acSTodor Tomov } 448051a01acSTodor Tomov 449051a01acSTodor Tomov static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 450051a01acSTodor Tomov { 451051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 452051a01acSTodor Tomov vfe->base + 453051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 454051a01acSTodor Tomov } 455051a01acSTodor Tomov 456051a01acSTodor Tomov static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 457051a01acSTodor Tomov enum vfe_line_id id) 458051a01acSTodor Tomov { 459051a01acSTodor Tomov u32 reg; 460051a01acSTodor Tomov 461051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 462051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); 463051a01acSTodor Tomov 464051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 465051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 466051a01acSTodor Tomov 467051a01acSTodor Tomov switch (id) { 468051a01acSTodor Tomov case VFE_LINE_RDI0: 469051a01acSTodor Tomov default: 470051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 471051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 472051a01acSTodor Tomov break; 473051a01acSTodor Tomov case VFE_LINE_RDI1: 474051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 475051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 476051a01acSTodor Tomov break; 477051a01acSTodor Tomov case VFE_LINE_RDI2: 478051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 479051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 480051a01acSTodor Tomov break; 481051a01acSTodor Tomov } 482051a01acSTodor Tomov 483051a01acSTodor Tomov if (wm % 2 == 1) 484051a01acSTodor Tomov reg <<= 16; 485051a01acSTodor Tomov 486051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 487051a01acSTodor Tomov } 488051a01acSTodor Tomov 489051a01acSTodor Tomov static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 490051a01acSTodor Tomov u8 enable) 491051a01acSTodor Tomov { 492051a01acSTodor Tomov struct vfe_line *line = container_of(output, struct vfe_line, output); 493051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 494051a01acSTodor Tomov u32 reg; 495051a01acSTodor Tomov unsigned int i; 496051a01acSTodor Tomov 497051a01acSTodor Tomov for (i = 0; i < output->wm_num; i++) { 498051a01acSTodor Tomov if (i == 0) { 499051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 500051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 501051a01acSTodor Tomov } else if (i == 1) { 502051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 503051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 504051a01acSTodor Tomov reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 505051a01acSTodor Tomov } else { 506051a01acSTodor Tomov /* On current devices output->wm_num is always <= 2 */ 507051a01acSTodor Tomov break; 508051a01acSTodor Tomov } 509051a01acSTodor Tomov 510051a01acSTodor Tomov if (output->wm_idx[i] % 2 == 1) 511051a01acSTodor Tomov reg <<= 16; 512051a01acSTodor Tomov 513051a01acSTodor Tomov if (enable) 514051a01acSTodor Tomov vfe_reg_set(vfe, 515051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 516051a01acSTodor Tomov reg); 517051a01acSTodor Tomov else 518051a01acSTodor Tomov vfe_reg_clr(vfe, 519051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 520051a01acSTodor Tomov reg); 521051a01acSTodor Tomov } 522051a01acSTodor Tomov } 523051a01acSTodor Tomov 524312e1c85STodor Tomov static void vfe_set_realign_cfg(struct vfe_device *vfe, struct vfe_line *line, 525312e1c85STodor Tomov u8 enable) 526312e1c85STodor Tomov { 527312e1c85STodor Tomov /* empty */ 528312e1c85STodor Tomov } 529051a01acSTodor Tomov static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 530051a01acSTodor Tomov { 531051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 532051a01acSTodor Tomov VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 533051a01acSTodor Tomov 534051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 535051a01acSTodor Tomov cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 536051a01acSTodor Tomov } 537051a01acSTodor Tomov 538051a01acSTodor Tomov static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 539051a01acSTodor Tomov { 540051a01acSTodor Tomov vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 541051a01acSTodor Tomov wmb(); 542051a01acSTodor Tomov writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 543051a01acSTodor Tomov wmb(); 544051a01acSTodor Tomov } 545051a01acSTodor Tomov 546051a01acSTodor Tomov static inline void vfe_reg_update_clear(struct vfe_device *vfe, 547051a01acSTodor Tomov enum vfe_line_id line_id) 548051a01acSTodor Tomov { 549051a01acSTodor Tomov vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 550051a01acSTodor Tomov } 551051a01acSTodor Tomov 552051a01acSTodor Tomov static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 553051a01acSTodor Tomov enum vfe_line_id line_id, u8 enable) 554051a01acSTodor Tomov { 555051a01acSTodor Tomov u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 556051a01acSTodor Tomov VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 557051a01acSTodor Tomov u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 558051a01acSTodor Tomov VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 559051a01acSTodor Tomov 560051a01acSTodor Tomov if (enable) { 561051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 562051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 563051a01acSTodor Tomov } else { 564051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 565051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 566051a01acSTodor Tomov } 567051a01acSTodor Tomov } 568051a01acSTodor Tomov 569051a01acSTodor Tomov static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 570051a01acSTodor Tomov enum vfe_line_id line_id, u8 enable) 571051a01acSTodor Tomov { 572051a01acSTodor Tomov struct vfe_output *output = &vfe->line[line_id].output; 573051a01acSTodor Tomov unsigned int i; 574051a01acSTodor Tomov u32 irq_en0; 575051a01acSTodor Tomov u32 irq_en1; 576051a01acSTodor Tomov u32 comp_mask = 0; 577051a01acSTodor Tomov 578051a01acSTodor Tomov irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 579051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 580051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 581051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 582051a01acSTodor Tomov irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 583051a01acSTodor Tomov for (i = 0; i < output->wm_num; i++) { 584051a01acSTodor Tomov irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 585051a01acSTodor Tomov output->wm_idx[i]); 586051a01acSTodor Tomov comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 587051a01acSTodor Tomov } 588051a01acSTodor Tomov 589051a01acSTodor Tomov if (enable) { 590051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 591051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 592051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 593051a01acSTodor Tomov } else { 594051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 595051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 596051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 597051a01acSTodor Tomov } 598051a01acSTodor Tomov } 599051a01acSTodor Tomov 600051a01acSTodor Tomov static void vfe_enable_irq_common(struct vfe_device *vfe) 601051a01acSTodor Tomov { 602051a01acSTodor Tomov u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 603051a01acSTodor Tomov u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 604051a01acSTodor Tomov VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 605051a01acSTodor Tomov 606051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 607051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 608051a01acSTodor Tomov } 609051a01acSTodor Tomov 610051a01acSTodor Tomov static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 611051a01acSTodor Tomov { 612051a01acSTodor Tomov u32 val, even_cfg, odd_cfg; 613051a01acSTodor Tomov 614051a01acSTodor Tomov writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 615051a01acSTodor Tomov 616051a01acSTodor Tomov val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 617051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 618051a01acSTodor Tomov 619051a01acSTodor Tomov val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 620051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 621051a01acSTodor Tomov 622051a01acSTodor Tomov switch (line->fmt[MSM_VFE_PAD_SINK].code) { 623051a01acSTodor Tomov case MEDIA_BUS_FMT_YUYV8_2X8: 624051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 625051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 626051a01acSTodor Tomov break; 627051a01acSTodor Tomov case MEDIA_BUS_FMT_YVYU8_2X8: 628051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 629051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 630051a01acSTodor Tomov break; 631051a01acSTodor Tomov case MEDIA_BUS_FMT_UYVY8_2X8: 632051a01acSTodor Tomov default: 633051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 634051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 635051a01acSTodor Tomov break; 636051a01acSTodor Tomov case MEDIA_BUS_FMT_VYUY8_2X8: 637051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 638051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 639051a01acSTodor Tomov break; 640051a01acSTodor Tomov } 641051a01acSTodor Tomov 642051a01acSTodor Tomov writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 643051a01acSTodor Tomov writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 644051a01acSTodor Tomov } 645051a01acSTodor Tomov 646051a01acSTodor Tomov static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 647051a01acSTodor Tomov { 648051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 649051a01acSTodor Tomov u32 reg; 650051a01acSTodor Tomov u16 input, output; 651051a01acSTodor Tomov u8 interp_reso; 652051a01acSTodor Tomov u32 phase_mult; 653051a01acSTodor Tomov 654051a01acSTodor Tomov writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 655051a01acSTodor Tomov 656051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].width; 657051a01acSTodor Tomov output = line->compose.width; 658051a01acSTodor Tomov reg = (output << 16) | input; 659051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 660051a01acSTodor Tomov 661051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 662051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 663051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 664051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 665051a01acSTodor Tomov 666051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].height; 667051a01acSTodor Tomov output = line->compose.height; 668051a01acSTodor Tomov reg = (output << 16) | input; 669051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 670051a01acSTodor Tomov 671051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 672051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 673051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 674051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 675051a01acSTodor Tomov 676051a01acSTodor Tomov writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 677051a01acSTodor Tomov 678051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].width; 679051a01acSTodor Tomov output = line->compose.width / 2; 680051a01acSTodor Tomov reg = (output << 16) | input; 681051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 682051a01acSTodor Tomov 683051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 684051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 685051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 686051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 687051a01acSTodor Tomov 688051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].height; 689051a01acSTodor Tomov output = line->compose.height; 690051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 691051a01acSTodor Tomov output = line->compose.height / 2; 692051a01acSTodor Tomov reg = (output << 16) | input; 693051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 694051a01acSTodor Tomov 695051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 696051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 697051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 698051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 699051a01acSTodor Tomov } 700051a01acSTodor Tomov 701051a01acSTodor Tomov static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 702051a01acSTodor Tomov { 703051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 704051a01acSTodor Tomov u32 reg; 705051a01acSTodor Tomov u16 first, last; 706051a01acSTodor Tomov 707051a01acSTodor Tomov first = line->crop.left; 708051a01acSTodor Tomov last = line->crop.left + line->crop.width - 1; 709051a01acSTodor Tomov reg = (first << 16) | last; 710051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 711051a01acSTodor Tomov 712051a01acSTodor Tomov first = line->crop.top; 713051a01acSTodor Tomov last = line->crop.top + line->crop.height - 1; 714051a01acSTodor Tomov reg = (first << 16) | last; 715051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 716051a01acSTodor Tomov 717051a01acSTodor Tomov first = line->crop.left / 2; 718051a01acSTodor Tomov last = line->crop.left / 2 + line->crop.width / 2 - 1; 719051a01acSTodor Tomov reg = (first << 16) | last; 720051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 721051a01acSTodor Tomov 722051a01acSTodor Tomov first = line->crop.top; 723051a01acSTodor Tomov last = line->crop.top + line->crop.height - 1; 724051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 725051a01acSTodor Tomov first = line->crop.top / 2; 726051a01acSTodor Tomov last = line->crop.top / 2 + line->crop.height / 2 - 1; 727051a01acSTodor Tomov } 728051a01acSTodor Tomov reg = (first << 16) | last; 729051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 730051a01acSTodor Tomov } 731051a01acSTodor Tomov 732051a01acSTodor Tomov static void vfe_set_clamp_cfg(struct vfe_device *vfe) 733051a01acSTodor Tomov { 734051a01acSTodor Tomov u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 735051a01acSTodor Tomov VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 736051a01acSTodor Tomov VFE_0_CLAMP_ENC_MAX_CFG_CH2; 737051a01acSTodor Tomov 738051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 739051a01acSTodor Tomov 740051a01acSTodor Tomov val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 741051a01acSTodor Tomov VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 742051a01acSTodor Tomov VFE_0_CLAMP_ENC_MIN_CFG_CH2; 743051a01acSTodor Tomov 744051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 745051a01acSTodor Tomov } 746051a01acSTodor Tomov 747051a01acSTodor Tomov static void vfe_set_qos(struct vfe_device *vfe) 748051a01acSTodor Tomov { 749051a01acSTodor Tomov u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 750051a01acSTodor Tomov u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 751051a01acSTodor Tomov 752051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 753051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 754051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 755051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 756051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 757051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 758051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 759051a01acSTodor Tomov writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 760051a01acSTodor Tomov } 761051a01acSTodor Tomov 7624e1abf66STodor Tomov static void vfe_set_ds(struct vfe_device *vfe) 7634e1abf66STodor Tomov { 7644e1abf66STodor Tomov /* empty */ 7654e1abf66STodor Tomov } 7664e1abf66STodor Tomov 767051a01acSTodor Tomov static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 768051a01acSTodor Tomov { 769051a01acSTodor Tomov u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); 770051a01acSTodor Tomov 771051a01acSTodor Tomov if (enable) 772051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); 773051a01acSTodor Tomov else 774051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); 775051a01acSTodor Tomov 776051a01acSTodor Tomov wmb(); 777051a01acSTodor Tomov } 778051a01acSTodor Tomov 779051a01acSTodor Tomov static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 780051a01acSTodor Tomov { 781051a01acSTodor Tomov u32 val; 782051a01acSTodor Tomov 783051a01acSTodor Tomov switch (line->fmt[MSM_VFE_PAD_SINK].code) { 784051a01acSTodor Tomov case MEDIA_BUS_FMT_YUYV8_2X8: 785051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 786051a01acSTodor Tomov break; 787051a01acSTodor Tomov case MEDIA_BUS_FMT_YVYU8_2X8: 788051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 789051a01acSTodor Tomov break; 790051a01acSTodor Tomov case MEDIA_BUS_FMT_UYVY8_2X8: 791051a01acSTodor Tomov default: 792051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 793051a01acSTodor Tomov break; 794051a01acSTodor Tomov case MEDIA_BUS_FMT_VYUY8_2X8: 795051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 796051a01acSTodor Tomov break; 797051a01acSTodor Tomov } 798051a01acSTodor Tomov 799051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 800051a01acSTodor Tomov 801051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].width * 2; 802051a01acSTodor Tomov val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; 803051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 804051a01acSTodor Tomov 805051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 806051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 807051a01acSTodor Tomov 808051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 809051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 810051a01acSTodor Tomov 811051a01acSTodor Tomov val = 0xffffffff; 812051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); 813051a01acSTodor Tomov 814051a01acSTodor Tomov val = 0xffffffff; 815051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 816051a01acSTodor Tomov 817051a01acSTodor Tomov val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 818051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 819051a01acSTodor Tomov 820051a01acSTodor Tomov val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 821051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 822051a01acSTodor Tomov } 823051a01acSTodor Tomov 824051a01acSTodor Tomov static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 825051a01acSTodor Tomov { 826051a01acSTodor Tomov u32 cmd; 827051a01acSTodor Tomov 828051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 829051a01acSTodor Tomov writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 830051a01acSTodor Tomov wmb(); 831051a01acSTodor Tomov 832051a01acSTodor Tomov if (enable) 833051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 834051a01acSTodor Tomov else 835051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 836051a01acSTodor Tomov 837051a01acSTodor Tomov writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 838051a01acSTodor Tomov } 839051a01acSTodor Tomov 840051a01acSTodor Tomov static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 841051a01acSTodor Tomov { 842051a01acSTodor Tomov u32 val = VFE_0_MODULE_CFG_DEMUX | 843051a01acSTodor Tomov VFE_0_MODULE_CFG_CHROMA_UPSAMPLE | 844051a01acSTodor Tomov VFE_0_MODULE_CFG_SCALE_ENC | 845051a01acSTodor Tomov VFE_0_MODULE_CFG_CROP_ENC; 846051a01acSTodor Tomov 847051a01acSTodor Tomov if (enable) 848051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); 849051a01acSTodor Tomov else 850051a01acSTodor Tomov writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); 851051a01acSTodor Tomov } 852051a01acSTodor Tomov 853051a01acSTodor Tomov static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 854051a01acSTodor Tomov { 855051a01acSTodor Tomov u32 val; 856051a01acSTodor Tomov int ret; 857051a01acSTodor Tomov 858051a01acSTodor Tomov ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 859051a01acSTodor Tomov val, 860051a01acSTodor Tomov (val & VFE_0_CAMIF_STATUS_HALT), 861051a01acSTodor Tomov CAMIF_TIMEOUT_SLEEP_US, 862051a01acSTodor Tomov CAMIF_TIMEOUT_ALL_US); 863051a01acSTodor Tomov if (ret < 0) 864051a01acSTodor Tomov dev_err(dev, "%s: camif stop timeout\n", __func__); 865051a01acSTodor Tomov 866051a01acSTodor Tomov return ret; 867051a01acSTodor Tomov } 868051a01acSTodor Tomov 869051a01acSTodor Tomov static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 870051a01acSTodor Tomov { 871051a01acSTodor Tomov *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 872051a01acSTodor Tomov *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 873051a01acSTodor Tomov 874051a01acSTodor Tomov writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 875051a01acSTodor Tomov writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 876051a01acSTodor Tomov 877051a01acSTodor Tomov wmb(); 878051a01acSTodor Tomov writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 879051a01acSTodor Tomov } 880051a01acSTodor Tomov 881051a01acSTodor Tomov static void vfe_violation_read(struct vfe_device *vfe) 882051a01acSTodor Tomov { 883051a01acSTodor Tomov u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 884051a01acSTodor Tomov 885051a01acSTodor Tomov pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 886051a01acSTodor Tomov } 887051a01acSTodor Tomov 888051a01acSTodor Tomov /* 889ad46e1a8SRobert Foss * vfe_isr - VFE module interrupt handler 890051a01acSTodor Tomov * @irq: Interrupt line 891051a01acSTodor Tomov * @dev: VFE device 892051a01acSTodor Tomov * 893051a01acSTodor Tomov * Return IRQ_HANDLED on success 894051a01acSTodor Tomov */ 895051a01acSTodor Tomov static irqreturn_t vfe_isr(int irq, void *dev) 896051a01acSTodor Tomov { 897051a01acSTodor Tomov struct vfe_device *vfe = dev; 898051a01acSTodor Tomov u32 value0, value1; 899051a01acSTodor Tomov int i, j; 900051a01acSTodor Tomov 901051a01acSTodor Tomov vfe->ops->isr_read(vfe, &value0, &value1); 902051a01acSTodor Tomov 903c3177cb0SRobert Foss dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n", 904051a01acSTodor Tomov value0, value1); 905051a01acSTodor Tomov 906051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 907051a01acSTodor Tomov vfe->isr_ops.reset_ack(vfe); 908051a01acSTodor Tomov 909051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 910051a01acSTodor Tomov vfe->ops->violation_read(vfe); 911051a01acSTodor Tomov 912051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 913051a01acSTodor Tomov vfe->isr_ops.halt_ack(vfe); 914051a01acSTodor Tomov 915051a01acSTodor Tomov for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 916051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 917051a01acSTodor Tomov vfe->isr_ops.reg_update(vfe, i); 918051a01acSTodor Tomov 919051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 920051a01acSTodor Tomov vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 921051a01acSTodor Tomov 922051a01acSTodor Tomov for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 923051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 924051a01acSTodor Tomov vfe->isr_ops.sof(vfe, i); 925051a01acSTodor Tomov 926051a01acSTodor Tomov for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 927051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 928051a01acSTodor Tomov vfe->isr_ops.comp_done(vfe, i); 929051a01acSTodor Tomov for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 930051a01acSTodor Tomov if (vfe->wm_output_map[j] == VFE_LINE_PIX) 931051a01acSTodor Tomov value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 932051a01acSTodor Tomov } 933051a01acSTodor Tomov 934051a01acSTodor Tomov for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 935051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 936051a01acSTodor Tomov vfe->isr_ops.wm_done(vfe, i); 937051a01acSTodor Tomov 938051a01acSTodor Tomov return IRQ_HANDLED; 939051a01acSTodor Tomov } 940051a01acSTodor Tomov 941*633b388fSRobert Foss static const struct vfe_hw_ops_gen1 vfe_ops_gen1_4_1 = { 942051a01acSTodor Tomov .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 943051a01acSTodor Tomov .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 944*633b388fSRobert Foss .bus_enable_wr_if = vfe_bus_enable_wr_if, 945*633b388fSRobert Foss .bus_reload_wm = vfe_bus_reload_wm, 946*633b388fSRobert Foss .camif_wait_for_stop = vfe_camif_wait_for_stop, 947051a01acSTodor Tomov .enable_irq_common = vfe_enable_irq_common, 948*633b388fSRobert Foss .enable_irq_pix_line = vfe_enable_irq_pix_line, 949*633b388fSRobert Foss .enable_irq_wm_line = vfe_enable_irq_wm_line, 950*633b388fSRobert Foss .get_ub_size = vfe_get_ub_size, 951*633b388fSRobert Foss .halt_clear = vfe_halt_clear, 952*633b388fSRobert Foss .halt_request = vfe_halt_request, 953051a01acSTodor Tomov .set_camif_cfg = vfe_set_camif_cfg, 954051a01acSTodor Tomov .set_camif_cmd = vfe_set_camif_cmd, 955*633b388fSRobert Foss .set_cgc_override = vfe_set_cgc_override, 956*633b388fSRobert Foss .set_clamp_cfg = vfe_set_clamp_cfg, 957*633b388fSRobert Foss .set_crop_cfg = vfe_set_crop_cfg, 958*633b388fSRobert Foss .set_demux_cfg = vfe_set_demux_cfg, 959*633b388fSRobert Foss .set_ds = vfe_set_ds, 960051a01acSTodor Tomov .set_module_cfg = vfe_set_module_cfg, 961*633b388fSRobert Foss .set_qos = vfe_set_qos, 962*633b388fSRobert Foss .set_rdi_cid = vfe_set_rdi_cid, 963*633b388fSRobert Foss .set_realign_cfg = vfe_set_realign_cfg, 964*633b388fSRobert Foss .set_scale_cfg = vfe_set_scale_cfg, 965*633b388fSRobert Foss .set_xbar_cfg = vfe_set_xbar_cfg, 966*633b388fSRobert Foss .wm_enable = vfe_wm_enable, 967*633b388fSRobert Foss .wm_frame_based = vfe_wm_frame_based, 968*633b388fSRobert Foss .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 969*633b388fSRobert Foss .wm_line_based = vfe_wm_line_based, 970*633b388fSRobert Foss .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 971*633b388fSRobert Foss .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 972*633b388fSRobert Foss .wm_set_ping_addr = vfe_wm_set_ping_addr, 973*633b388fSRobert Foss .wm_set_pong_addr = vfe_wm_set_pong_addr, 974*633b388fSRobert Foss .wm_set_subsample = vfe_wm_set_subsample, 975*633b388fSRobert Foss .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 976*633b388fSRobert Foss }; 977*633b388fSRobert Foss 978*633b388fSRobert Foss static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe) 979*633b388fSRobert Foss { 980*633b388fSRobert Foss vfe->isr_ops = vfe_isr_ops_gen1; 981*633b388fSRobert Foss vfe->ops_gen1 = &vfe_ops_gen1_4_1; 982*633b388fSRobert Foss vfe->video_ops = vfe_video_ops_gen1; 983*633b388fSRobert Foss 984*633b388fSRobert Foss vfe->line_num = VFE_LINE_NUM_GEN1; 985*633b388fSRobert Foss } 986*633b388fSRobert Foss 987*633b388fSRobert Foss const struct vfe_hw_ops vfe_ops_4_1 = { 988*633b388fSRobert Foss .global_reset = vfe_global_reset, 989*633b388fSRobert Foss .hw_version_read = vfe_hw_version_read, 990051a01acSTodor Tomov .isr_read = vfe_isr_read, 991051a01acSTodor Tomov .isr = vfe_isr, 992*633b388fSRobert Foss .reg_update_clear = vfe_reg_update_clear, 993*633b388fSRobert Foss .reg_update = vfe_reg_update, 994*633b388fSRobert Foss .subdev_init = vfe_subdev_init, 995*633b388fSRobert Foss .vfe_disable = vfe_gen1_disable, 996*633b388fSRobert Foss .vfe_enable = vfe_gen1_enable, 997*633b388fSRobert Foss .vfe_halt = vfe_gen1_halt, 998*633b388fSRobert Foss .violation_read = vfe_violation_read, 999051a01acSTodor Tomov }; 1000