1051a01acSTodor Tomov // SPDX-License-Identifier: GPL-2.0 2051a01acSTodor Tomov /* 3051a01acSTodor Tomov * camss-vfe-4-1.c 4051a01acSTodor Tomov * 5051a01acSTodor Tomov * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module v4.1 6051a01acSTodor Tomov * 7051a01acSTodor Tomov * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8051a01acSTodor Tomov * Copyright (C) 2015-2018 Linaro Ltd. 9051a01acSTodor Tomov */ 10051a01acSTodor Tomov 11051a01acSTodor Tomov #include <linux/interrupt.h> 12051a01acSTodor Tomov #include <linux/iopoll.h> 13051a01acSTodor Tomov 14051a01acSTodor Tomov #include "camss-vfe.h" 15051a01acSTodor Tomov 16051a01acSTodor Tomov #define VFE_0_HW_VERSION 0x000 17051a01acSTodor Tomov 18051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD 0x00c 19051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_CORE BIT(0) 20051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_CAMIF BIT(1) 21051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS BIT(2) 22051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS_BDG BIT(3) 23051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_REGISTER BIT(4) 24051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_TIMER BIT(5) 25051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_PM BIT(6) 26051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_BUS_MISR BIT(7) 27051a01acSTodor Tomov #define VFE_0_GLOBAL_RESET_CMD_TESTGEN BIT(8) 28051a01acSTodor Tomov 29051a01acSTodor Tomov #define VFE_0_MODULE_CFG 0x018 30051a01acSTodor Tomov #define VFE_0_MODULE_CFG_DEMUX BIT(2) 31051a01acSTodor Tomov #define VFE_0_MODULE_CFG_CHROMA_UPSAMPLE BIT(3) 32051a01acSTodor Tomov #define VFE_0_MODULE_CFG_SCALE_ENC BIT(23) 33051a01acSTodor Tomov #define VFE_0_MODULE_CFG_CROP_ENC BIT(27) 34051a01acSTodor Tomov 35051a01acSTodor Tomov #define VFE_0_CORE_CFG 0x01c 36051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR 0x4 37051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB 0x5 38051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY 0x6 39051a01acSTodor Tomov #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY 0x7 40051a01acSTodor Tomov 41051a01acSTodor Tomov #define VFE_0_IRQ_CMD 0x024 42051a01acSTodor Tomov #define VFE_0_IRQ_CMD_GLOBAL_CLEAR BIT(0) 43051a01acSTodor Tomov 44051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0 0x028 45051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_CAMIF_SOF BIT(0) 46051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_CAMIF_EOF BIT(1) 47051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 48051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(n) \ 49051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_MASK_0_RDIn_REG_UPDATE(n)) 50051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 51051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 52051a01acSTodor Tomov #define VFE_0_IRQ_MASK_0_RESET_ACK BIT(31) 53051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1 0x02c 54051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_CAMIF_ERROR BIT(0) 55051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_VIOLATION BIT(7) 56051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK BIT(8) 57051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9) 58051a01acSTodor Tomov #define VFE_0_IRQ_MASK_1_RDIn_SOF(n) BIT((n) + 29) 59051a01acSTodor Tomov 60051a01acSTodor Tomov #define VFE_0_IRQ_CLEAR_0 0x030 61051a01acSTodor Tomov #define VFE_0_IRQ_CLEAR_1 0x034 62051a01acSTodor Tomov 63051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0 0x038 64051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_CAMIF_SOF BIT(0) 65051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n) BIT((n) + 5) 66051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(n) \ 67051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? BIT(4) : VFE_0_IRQ_STATUS_0_RDIn_REG_UPDATE(n)) 68051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8) 69051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25) 70051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_0_RESET_ACK BIT(31) 71051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1 0x03c 72051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_VIOLATION BIT(7) 73051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK BIT(8) 74051a01acSTodor Tomov #define VFE_0_IRQ_STATUS_1_RDIn_SOF(n) BIT((n) + 29) 75051a01acSTodor Tomov 76051a01acSTodor Tomov #define VFE_0_IRQ_COMPOSITE_MASK_0 0x40 77051a01acSTodor Tomov #define VFE_0_VIOLATION_STATUS 0x48 78051a01acSTodor Tomov 79051a01acSTodor Tomov #define VFE_0_BUS_CMD 0x4c 80051a01acSTodor Tomov #define VFE_0_BUS_CMD_Mx_RLD_CMD(x) BIT(x) 81051a01acSTodor Tomov 82051a01acSTodor Tomov #define VFE_0_BUS_CFG 0x050 83051a01acSTodor Tomov 84051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x(x) (0x58 + 0x4 * ((x) / 2)) 85051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN BIT(1) 86051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA (0x3 << 4) 87051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT 8 88051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA 0 89051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 5 90051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 6 91051a01acSTodor Tomov #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 7 92051a01acSTodor Tomov 93051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n) (0x06c + 0x24 * (n)) 94051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT 0 95051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT 1 96051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n) (0x070 + 0x24 * (n)) 97051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n) (0x074 + 0x24 * (n)) 98051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n) (0x078 + 0x24 * (n)) 99051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT 2 100051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK (0x1f << 2) 101051a01acSTodor Tomov 102051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n) (0x07c + 0x24 * (n)) 103051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT 16 104051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n) (0x080 + 0x24 * (n)) 105051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n) (0x084 + 0x24 * (n)) 106051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(n) \ 107051a01acSTodor Tomov (0x088 + 0x24 * (n)) 108051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(n) \ 109051a01acSTodor Tomov (0x08c + 0x24 * (n)) 110051a01acSTodor Tomov #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF 0xffffffff 111051a01acSTodor Tomov 112051a01acSTodor Tomov #define VFE_0_BUS_PING_PONG_STATUS 0x268 113051a01acSTodor Tomov 114051a01acSTodor Tomov #define VFE_0_BUS_BDG_CMD 0x2c0 115051a01acSTodor Tomov #define VFE_0_BUS_BDG_CMD_HALT_REQ 1 116051a01acSTodor Tomov 117051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_0 0x2c4 118051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_0_CFG 0xaaa5aaa5 119051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_1 0x2c8 120051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_2 0x2cc 121051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_3 0x2d0 122051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_4 0x2d4 123051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_5 0x2d8 124051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_6 0x2dc 125051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_7 0x2e0 126051a01acSTodor Tomov #define VFE_0_BUS_BDG_QOS_CFG_7_CFG 0x0001aaa5 127051a01acSTodor Tomov 128051a01acSTodor Tomov #define VFE_0_RDI_CFG_x(x) (0x2e8 + (0x4 * (x))) 129051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT 28 130051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK (0xf << 28) 131051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT 4 132051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK (0xf << 4) 133051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_EN_BIT BIT(2) 134051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_MIPI_EN_BITS 0x3 135051a01acSTodor Tomov #define VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(r) BIT(16 + (r)) 136051a01acSTodor Tomov 137051a01acSTodor Tomov #define VFE_0_CAMIF_CMD 0x2f4 138051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY 0 139051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY 1 140051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_NO_CHANGE 3 141051a01acSTodor Tomov #define VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS BIT(2) 142051a01acSTodor Tomov #define VFE_0_CAMIF_CFG 0x2f8 143051a01acSTodor Tomov #define VFE_0_CAMIF_CFG_VFE_OUTPUT_EN BIT(6) 144051a01acSTodor Tomov #define VFE_0_CAMIF_FRAME_CFG 0x300 145051a01acSTodor Tomov #define VFE_0_CAMIF_WINDOW_WIDTH_CFG 0x304 146051a01acSTodor Tomov #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG 0x308 147051a01acSTodor Tomov #define VFE_0_CAMIF_SUBSAMPLE_CFG_0 0x30c 148051a01acSTodor Tomov #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN 0x314 149051a01acSTodor Tomov #define VFE_0_CAMIF_STATUS 0x31c 150051a01acSTodor Tomov #define VFE_0_CAMIF_STATUS_HALT BIT(31) 151051a01acSTodor Tomov 152051a01acSTodor Tomov #define VFE_0_REG_UPDATE 0x378 153051a01acSTodor Tomov #define VFE_0_REG_UPDATE_RDIn(n) BIT(1 + (n)) 154051a01acSTodor Tomov #define VFE_0_REG_UPDATE_line_n(n) \ 155051a01acSTodor Tomov ((n) == VFE_LINE_PIX ? 1 : VFE_0_REG_UPDATE_RDIn(n)) 156051a01acSTodor Tomov 157051a01acSTodor Tomov #define VFE_0_DEMUX_CFG 0x424 158051a01acSTodor Tomov #define VFE_0_DEMUX_CFG_PERIOD 0x3 159051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0 0x428 160051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0_CH0_EVEN (0x80 << 0) 161051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_0_CH0_ODD (0x80 << 16) 162051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1 0x42c 163051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1_CH1 (0x80 << 0) 164051a01acSTodor Tomov #define VFE_0_DEMUX_GAIN_1_CH2 (0x80 << 16) 165051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG 0x438 166051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV 0x9cac 167051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU 0xac9c 168051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY 0xc9ca 169051a01acSTodor Tomov #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY 0xcac9 170051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG 0x43c 171051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV 0x9cac 172051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU 0xac9c 173051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY 0xc9ca 174051a01acSTodor Tomov #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY 0xcac9 175051a01acSTodor Tomov 176051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_CFG 0x75c 177051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE 0x760 178051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_H_PHASE 0x764 179051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE 0x76c 180051a01acSTodor Tomov #define VFE_0_SCALE_ENC_Y_V_PHASE 0x770 181051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_CFG 0x778 182051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE 0x77c 183051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_H_PHASE 0x780 184051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE 0x790 185051a01acSTodor Tomov #define VFE_0_SCALE_ENC_CBCR_V_PHASE 0x794 186051a01acSTodor Tomov 187051a01acSTodor Tomov #define VFE_0_CROP_ENC_Y_WIDTH 0x854 188051a01acSTodor Tomov #define VFE_0_CROP_ENC_Y_HEIGHT 0x858 189051a01acSTodor Tomov #define VFE_0_CROP_ENC_CBCR_WIDTH 0x85c 190051a01acSTodor Tomov #define VFE_0_CROP_ENC_CBCR_HEIGHT 0x860 191051a01acSTodor Tomov 192051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG 0x874 193051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH0 (0xff << 0) 194051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH1 (0xff << 8) 195051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MAX_CFG_CH2 (0xff << 16) 196051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG 0x878 197051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH0 (0x0 << 0) 198051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH1 (0x0 << 8) 199051a01acSTodor Tomov #define VFE_0_CLAMP_ENC_MIN_CFG_CH2 (0x0 << 16) 200051a01acSTodor Tomov 201051a01acSTodor Tomov #define VFE_0_CGC_OVERRIDE_1 0x974 202051a01acSTodor Tomov #define VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(x) BIT(x) 203051a01acSTodor Tomov 204051a01acSTodor Tomov #define CAMIF_TIMEOUT_SLEEP_US 1000 205051a01acSTodor Tomov #define CAMIF_TIMEOUT_ALL_US 1000000 206051a01acSTodor Tomov 207051a01acSTodor Tomov #define MSM_VFE_VFE0_UB_SIZE 1023 208051a01acSTodor Tomov #define MSM_VFE_VFE0_UB_SIZE_RDI (MSM_VFE_VFE0_UB_SIZE / 3) 209051a01acSTodor Tomov 210051a01acSTodor Tomov static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev) 211051a01acSTodor Tomov { 212051a01acSTodor Tomov u32 hw_version = readl_relaxed(vfe->base + VFE_0_HW_VERSION); 213051a01acSTodor Tomov 214051a01acSTodor Tomov dev_dbg(dev, "VFE HW Version = 0x%08x\n", hw_version); 215051a01acSTodor Tomov } 216051a01acSTodor Tomov 217051a01acSTodor Tomov static u16 vfe_get_ub_size(u8 vfe_id) 218051a01acSTodor Tomov { 219051a01acSTodor Tomov if (vfe_id == 0) 220051a01acSTodor Tomov return MSM_VFE_VFE0_UB_SIZE_RDI; 221051a01acSTodor Tomov 222051a01acSTodor Tomov return 0; 223051a01acSTodor Tomov } 224051a01acSTodor Tomov 225051a01acSTodor Tomov static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits) 226051a01acSTodor Tomov { 227051a01acSTodor Tomov u32 bits = readl_relaxed(vfe->base + reg); 228051a01acSTodor Tomov 229051a01acSTodor Tomov writel_relaxed(bits & ~clr_bits, vfe->base + reg); 230051a01acSTodor Tomov } 231051a01acSTodor Tomov 232051a01acSTodor Tomov static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits) 233051a01acSTodor Tomov { 234051a01acSTodor Tomov u32 bits = readl_relaxed(vfe->base + reg); 235051a01acSTodor Tomov 236051a01acSTodor Tomov writel_relaxed(bits | set_bits, vfe->base + reg); 237051a01acSTodor Tomov } 238051a01acSTodor Tomov 239051a01acSTodor Tomov static void vfe_global_reset(struct vfe_device *vfe) 240051a01acSTodor Tomov { 241051a01acSTodor Tomov u32 reset_bits = VFE_0_GLOBAL_RESET_CMD_TESTGEN | 242051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS_MISR | 243051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_PM | 244051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_TIMER | 245051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_REGISTER | 246051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS_BDG | 247051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_BUS | 248051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_CAMIF | 249051a01acSTodor Tomov VFE_0_GLOBAL_RESET_CMD_CORE; 250051a01acSTodor Tomov 251051a01acSTodor Tomov writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); 252051a01acSTodor Tomov } 253051a01acSTodor Tomov 254051a01acSTodor Tomov static void vfe_halt_request(struct vfe_device *vfe) 255051a01acSTodor Tomov { 256051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, 257051a01acSTodor Tomov vfe->base + VFE_0_BUS_BDG_CMD); 258051a01acSTodor Tomov } 259051a01acSTodor Tomov 260051a01acSTodor Tomov static void vfe_halt_clear(struct vfe_device *vfe) 261051a01acSTodor Tomov { 262051a01acSTodor Tomov writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); 263051a01acSTodor Tomov } 264051a01acSTodor Tomov 265051a01acSTodor Tomov static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) 266051a01acSTodor Tomov { 267051a01acSTodor Tomov if (enable) 268051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 269051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 270051a01acSTodor Tomov else 271051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 272051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT); 273051a01acSTodor Tomov } 274051a01acSTodor Tomov 275051a01acSTodor Tomov static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) 276051a01acSTodor Tomov { 277051a01acSTodor Tomov if (enable) 278051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 279051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 280051a01acSTodor Tomov else 281051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), 282051a01acSTodor Tomov 1 << VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_FRM_BASED_SHIFT); 283051a01acSTodor Tomov } 284051a01acSTodor Tomov 285051a01acSTodor Tomov #define CALC_WORD(width, M, N) (((width) * (M) + (N) - 1) / (N)) 286051a01acSTodor Tomov 287051a01acSTodor Tomov static int vfe_word_per_line(u32 format, u32 pixel_per_line) 288051a01acSTodor Tomov { 289051a01acSTodor Tomov int val = 0; 290051a01acSTodor Tomov 291051a01acSTodor Tomov switch (format) { 292051a01acSTodor Tomov case V4L2_PIX_FMT_NV12: 293051a01acSTodor Tomov case V4L2_PIX_FMT_NV21: 294051a01acSTodor Tomov case V4L2_PIX_FMT_NV16: 295051a01acSTodor Tomov case V4L2_PIX_FMT_NV61: 296051a01acSTodor Tomov val = CALC_WORD(pixel_per_line, 1, 8); 297051a01acSTodor Tomov break; 298051a01acSTodor Tomov case V4L2_PIX_FMT_YUYV: 299051a01acSTodor Tomov case V4L2_PIX_FMT_YVYU: 300051a01acSTodor Tomov case V4L2_PIX_FMT_UYVY: 301051a01acSTodor Tomov case V4L2_PIX_FMT_VYUY: 302051a01acSTodor Tomov val = CALC_WORD(pixel_per_line, 2, 8); 303051a01acSTodor Tomov break; 304051a01acSTodor Tomov } 305051a01acSTodor Tomov 306051a01acSTodor Tomov return val; 307051a01acSTodor Tomov } 308051a01acSTodor Tomov 309051a01acSTodor Tomov static void vfe_get_wm_sizes(struct v4l2_pix_format_mplane *pix, u8 plane, 310051a01acSTodor Tomov u16 *width, u16 *height, u16 *bytesperline) 311051a01acSTodor Tomov { 312051a01acSTodor Tomov switch (pix->pixelformat) { 313051a01acSTodor Tomov case V4L2_PIX_FMT_NV12: 314051a01acSTodor Tomov case V4L2_PIX_FMT_NV21: 315051a01acSTodor Tomov *width = pix->width; 316051a01acSTodor Tomov *height = pix->height; 317051a01acSTodor Tomov *bytesperline = pix->plane_fmt[0].bytesperline; 318051a01acSTodor Tomov if (plane == 1) 319051a01acSTodor Tomov *height /= 2; 320051a01acSTodor Tomov break; 321051a01acSTodor Tomov case V4L2_PIX_FMT_NV16: 322051a01acSTodor Tomov case V4L2_PIX_FMT_NV61: 323051a01acSTodor Tomov *width = pix->width; 324051a01acSTodor Tomov *height = pix->height; 325051a01acSTodor Tomov *bytesperline = pix->plane_fmt[0].bytesperline; 326051a01acSTodor Tomov break; 327051a01acSTodor Tomov } 328051a01acSTodor Tomov } 329051a01acSTodor Tomov 330051a01acSTodor Tomov static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, 331051a01acSTodor Tomov struct v4l2_pix_format_mplane *pix, 332051a01acSTodor Tomov u8 plane, u32 enable) 333051a01acSTodor Tomov { 334051a01acSTodor Tomov u32 reg; 335051a01acSTodor Tomov 336051a01acSTodor Tomov if (enable) { 337051a01acSTodor Tomov u16 width = 0, height = 0, bytesperline = 0, wpl; 338051a01acSTodor Tomov 339051a01acSTodor Tomov vfe_get_wm_sizes(pix, plane, &width, &height, &bytesperline); 340051a01acSTodor Tomov 341051a01acSTodor Tomov wpl = vfe_word_per_line(pix->pixelformat, width); 342051a01acSTodor Tomov 343051a01acSTodor Tomov reg = height - 1; 344051a01acSTodor Tomov reg |= ((wpl + 1) / 2 - 1) << 16; 345051a01acSTodor Tomov 346051a01acSTodor Tomov writel_relaxed(reg, vfe->base + 347051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 348051a01acSTodor Tomov 349051a01acSTodor Tomov wpl = vfe_word_per_line(pix->pixelformat, bytesperline); 350051a01acSTodor Tomov 351051a01acSTodor Tomov reg = 0x3; 352051a01acSTodor Tomov reg |= (height - 1) << 4; 353051a01acSTodor Tomov reg |= wpl << 16; 354051a01acSTodor Tomov 355051a01acSTodor Tomov writel_relaxed(reg, vfe->base + 356051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 357051a01acSTodor Tomov } else { 358051a01acSTodor Tomov writel_relaxed(0, vfe->base + 359051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); 360051a01acSTodor Tomov writel_relaxed(0, vfe->base + 361051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); 362051a01acSTodor Tomov } 363051a01acSTodor Tomov } 364051a01acSTodor Tomov 365051a01acSTodor Tomov static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) 366051a01acSTodor Tomov { 367051a01acSTodor Tomov u32 reg; 368051a01acSTodor Tomov 369051a01acSTodor Tomov reg = readl_relaxed(vfe->base + 370051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 371051a01acSTodor Tomov 372051a01acSTodor Tomov reg &= ~(VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK); 373051a01acSTodor Tomov 374051a01acSTodor Tomov reg |= (per << VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_SHIFT) 375051a01acSTodor Tomov & VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK; 376051a01acSTodor Tomov 377051a01acSTodor Tomov writel_relaxed(reg, 378051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); 379051a01acSTodor Tomov } 380051a01acSTodor Tomov 381051a01acSTodor Tomov static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, 382051a01acSTodor Tomov u32 pattern) 383051a01acSTodor Tomov { 384051a01acSTodor Tomov writel_relaxed(pattern, 385051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); 386051a01acSTodor Tomov } 387051a01acSTodor Tomov 388051a01acSTodor Tomov static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, 389051a01acSTodor Tomov u16 offset, u16 depth) 390051a01acSTodor Tomov { 391051a01acSTodor Tomov u32 reg; 392051a01acSTodor Tomov 393051a01acSTodor Tomov reg = (offset << VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG_OFFSET_SHIFT) | 394051a01acSTodor Tomov depth; 395051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); 396051a01acSTodor Tomov } 397051a01acSTodor Tomov 398051a01acSTodor Tomov static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) 399051a01acSTodor Tomov { 400051a01acSTodor Tomov wmb(); 401051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); 402051a01acSTodor Tomov wmb(); 403051a01acSTodor Tomov } 404051a01acSTodor Tomov 405051a01acSTodor Tomov static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) 406051a01acSTodor Tomov { 407051a01acSTodor Tomov writel_relaxed(addr, 408051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); 409051a01acSTodor Tomov } 410051a01acSTodor Tomov 411051a01acSTodor Tomov static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) 412051a01acSTodor Tomov { 413051a01acSTodor Tomov writel_relaxed(addr, 414051a01acSTodor Tomov vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); 415051a01acSTodor Tomov } 416051a01acSTodor Tomov 417051a01acSTodor Tomov static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) 418051a01acSTodor Tomov { 419051a01acSTodor Tomov u32 reg; 420051a01acSTodor Tomov 421051a01acSTodor Tomov reg = readl_relaxed(vfe->base + VFE_0_BUS_PING_PONG_STATUS); 422051a01acSTodor Tomov 423051a01acSTodor Tomov return (reg >> wm) & 0x1; 424051a01acSTodor Tomov } 425051a01acSTodor Tomov 426051a01acSTodor Tomov static void vfe_bus_enable_wr_if(struct vfe_device *vfe, u8 enable) 427051a01acSTodor Tomov { 428051a01acSTodor Tomov if (enable) 429051a01acSTodor Tomov writel_relaxed(0x10000009, vfe->base + VFE_0_BUS_CFG); 430051a01acSTodor Tomov else 431051a01acSTodor Tomov writel_relaxed(0, vfe->base + VFE_0_BUS_CFG); 432051a01acSTodor Tomov } 433051a01acSTodor Tomov 434051a01acSTodor Tomov static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, 435051a01acSTodor Tomov enum vfe_line_id id) 436051a01acSTodor Tomov { 437051a01acSTodor Tomov u32 reg; 438051a01acSTodor Tomov 439051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 440051a01acSTodor Tomov reg |= VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 441051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg); 442051a01acSTodor Tomov 443051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 444051a01acSTodor Tomov reg |= ((3 * id) << VFE_0_RDI_CFG_x_RDI_STREAM_SEL_SHIFT) & 445051a01acSTodor Tomov VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK; 446051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), reg); 447051a01acSTodor Tomov 448051a01acSTodor Tomov switch (id) { 449051a01acSTodor Tomov case VFE_LINE_RDI0: 450051a01acSTodor Tomov default: 451051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 452051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 453051a01acSTodor Tomov break; 454051a01acSTodor Tomov case VFE_LINE_RDI1: 455051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 456051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 457051a01acSTodor Tomov break; 458051a01acSTodor Tomov case VFE_LINE_RDI2: 459051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 460051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 461051a01acSTodor Tomov break; 462051a01acSTodor Tomov } 463051a01acSTodor Tomov 464051a01acSTodor Tomov if (wm % 2 == 1) 465051a01acSTodor Tomov reg <<= 16; 466051a01acSTodor Tomov 467051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 468051a01acSTodor Tomov } 469051a01acSTodor Tomov 470051a01acSTodor Tomov static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) 471051a01acSTodor Tomov { 472051a01acSTodor Tomov writel_relaxed(VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF, 473051a01acSTodor Tomov vfe->base + 474051a01acSTodor Tomov VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); 475051a01acSTodor Tomov } 476051a01acSTodor Tomov 477051a01acSTodor Tomov static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, 478051a01acSTodor Tomov enum vfe_line_id id) 479051a01acSTodor Tomov { 480051a01acSTodor Tomov u32 reg; 481051a01acSTodor Tomov 482051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_Mr_FRAME_BASED_EN(id); 483051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(0), reg); 484051a01acSTodor Tomov 485051a01acSTodor Tomov reg = VFE_0_RDI_CFG_x_RDI_EN_BIT; 486051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), reg); 487051a01acSTodor Tomov 488051a01acSTodor Tomov switch (id) { 489051a01acSTodor Tomov case VFE_LINE_RDI0: 490051a01acSTodor Tomov default: 491051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0 << 492051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 493051a01acSTodor Tomov break; 494051a01acSTodor Tomov case VFE_LINE_RDI1: 495051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1 << 496051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 497051a01acSTodor Tomov break; 498051a01acSTodor Tomov case VFE_LINE_RDI2: 499051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2 << 500051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 501051a01acSTodor Tomov break; 502051a01acSTodor Tomov } 503051a01acSTodor Tomov 504051a01acSTodor Tomov if (wm % 2 == 1) 505051a01acSTodor Tomov reg <<= 16; 506051a01acSTodor Tomov 507051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); 508051a01acSTodor Tomov } 509051a01acSTodor Tomov 510051a01acSTodor Tomov static void vfe_set_xbar_cfg(struct vfe_device *vfe, struct vfe_output *output, 511051a01acSTodor Tomov u8 enable) 512051a01acSTodor Tomov { 513051a01acSTodor Tomov struct vfe_line *line = container_of(output, struct vfe_line, output); 514051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 515051a01acSTodor Tomov u32 reg; 516051a01acSTodor Tomov unsigned int i; 517051a01acSTodor Tomov 518051a01acSTodor Tomov for (i = 0; i < output->wm_num; i++) { 519051a01acSTodor Tomov if (i == 0) { 520051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA << 521051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_SHIFT; 522051a01acSTodor Tomov } else if (i == 1) { 523051a01acSTodor Tomov reg = VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_EN; 524051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV16) 525051a01acSTodor Tomov reg |= VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA; 526051a01acSTodor Tomov } else { 527051a01acSTodor Tomov /* On current devices output->wm_num is always <= 2 */ 528051a01acSTodor Tomov break; 529051a01acSTodor Tomov } 530051a01acSTodor Tomov 531051a01acSTodor Tomov if (output->wm_idx[i] % 2 == 1) 532051a01acSTodor Tomov reg <<= 16; 533051a01acSTodor Tomov 534051a01acSTodor Tomov if (enable) 535051a01acSTodor Tomov vfe_reg_set(vfe, 536051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 537051a01acSTodor Tomov reg); 538051a01acSTodor Tomov else 539051a01acSTodor Tomov vfe_reg_clr(vfe, 540051a01acSTodor Tomov VFE_0_BUS_XBAR_CFG_x(output->wm_idx[i]), 541051a01acSTodor Tomov reg); 542051a01acSTodor Tomov } 543051a01acSTodor Tomov } 544051a01acSTodor Tomov 545051a01acSTodor Tomov static void vfe_set_rdi_cid(struct vfe_device *vfe, enum vfe_line_id id, u8 cid) 546051a01acSTodor Tomov { 547051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_RDI_CFG_x(id), 548051a01acSTodor Tomov VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK); 549051a01acSTodor Tomov 550051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(id), 551051a01acSTodor Tomov cid << VFE_0_RDI_CFG_x_RDI_M0_SEL_SHIFT); 552051a01acSTodor Tomov } 553051a01acSTodor Tomov 554051a01acSTodor Tomov static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id) 555051a01acSTodor Tomov { 556051a01acSTodor Tomov vfe->reg_update |= VFE_0_REG_UPDATE_line_n(line_id); 557051a01acSTodor Tomov wmb(); 558051a01acSTodor Tomov writel_relaxed(vfe->reg_update, vfe->base + VFE_0_REG_UPDATE); 559051a01acSTodor Tomov wmb(); 560051a01acSTodor Tomov } 561051a01acSTodor Tomov 562051a01acSTodor Tomov static inline void vfe_reg_update_clear(struct vfe_device *vfe, 563051a01acSTodor Tomov enum vfe_line_id line_id) 564051a01acSTodor Tomov { 565051a01acSTodor Tomov vfe->reg_update &= ~VFE_0_REG_UPDATE_line_n(line_id); 566051a01acSTodor Tomov } 567051a01acSTodor Tomov 568051a01acSTodor Tomov static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, 569051a01acSTodor Tomov enum vfe_line_id line_id, u8 enable) 570051a01acSTodor Tomov { 571051a01acSTodor Tomov u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | 572051a01acSTodor Tomov VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 573051a01acSTodor Tomov u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | 574051a01acSTodor Tomov VFE_0_IRQ_MASK_1_RDIn_SOF(line_id); 575051a01acSTodor Tomov 576051a01acSTodor Tomov if (enable) { 577051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 578051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 579051a01acSTodor Tomov } else { 580051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 581051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 582051a01acSTodor Tomov } 583051a01acSTodor Tomov } 584051a01acSTodor Tomov 585051a01acSTodor Tomov static void vfe_enable_irq_pix_line(struct vfe_device *vfe, u8 comp, 586051a01acSTodor Tomov enum vfe_line_id line_id, u8 enable) 587051a01acSTodor Tomov { 588051a01acSTodor Tomov struct vfe_output *output = &vfe->line[line_id].output; 589051a01acSTodor Tomov unsigned int i; 590051a01acSTodor Tomov u32 irq_en0; 591051a01acSTodor Tomov u32 irq_en1; 592051a01acSTodor Tomov u32 comp_mask = 0; 593051a01acSTodor Tomov 594051a01acSTodor Tomov irq_en0 = VFE_0_IRQ_MASK_0_CAMIF_SOF; 595051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_CAMIF_EOF; 596051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_IMAGE_COMPOSITE_DONE_n(comp); 597051a01acSTodor Tomov irq_en0 |= VFE_0_IRQ_MASK_0_line_n_REG_UPDATE(line_id); 598051a01acSTodor Tomov irq_en1 = VFE_0_IRQ_MASK_1_CAMIF_ERROR; 599051a01acSTodor Tomov for (i = 0; i < output->wm_num; i++) { 600051a01acSTodor Tomov irq_en1 |= VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW( 601051a01acSTodor Tomov output->wm_idx[i]); 602051a01acSTodor Tomov comp_mask |= (1 << output->wm_idx[i]) << comp * 8; 603051a01acSTodor Tomov } 604051a01acSTodor Tomov 605051a01acSTodor Tomov if (enable) { 606051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 607051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 608051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 609051a01acSTodor Tomov } else { 610051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_0, irq_en0); 611051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_MASK_1, irq_en1); 612051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_IRQ_COMPOSITE_MASK_0, comp_mask); 613051a01acSTodor Tomov } 614051a01acSTodor Tomov } 615051a01acSTodor Tomov 616051a01acSTodor Tomov static void vfe_enable_irq_common(struct vfe_device *vfe) 617051a01acSTodor Tomov { 618051a01acSTodor Tomov u32 irq_en0 = VFE_0_IRQ_MASK_0_RESET_ACK; 619051a01acSTodor Tomov u32 irq_en1 = VFE_0_IRQ_MASK_1_VIOLATION | 620051a01acSTodor Tomov VFE_0_IRQ_MASK_1_BUS_BDG_HALT_ACK; 621051a01acSTodor Tomov 622051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_0, irq_en0); 623051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_IRQ_MASK_1, irq_en1); 624051a01acSTodor Tomov } 625051a01acSTodor Tomov 626051a01acSTodor Tomov static void vfe_set_demux_cfg(struct vfe_device *vfe, struct vfe_line *line) 627051a01acSTodor Tomov { 628051a01acSTodor Tomov u32 val, even_cfg, odd_cfg; 629051a01acSTodor Tomov 630051a01acSTodor Tomov writel_relaxed(VFE_0_DEMUX_CFG_PERIOD, vfe->base + VFE_0_DEMUX_CFG); 631051a01acSTodor Tomov 632051a01acSTodor Tomov val = VFE_0_DEMUX_GAIN_0_CH0_EVEN | VFE_0_DEMUX_GAIN_0_CH0_ODD; 633051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_0); 634051a01acSTodor Tomov 635051a01acSTodor Tomov val = VFE_0_DEMUX_GAIN_1_CH1 | VFE_0_DEMUX_GAIN_1_CH2; 636051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_DEMUX_GAIN_1); 637051a01acSTodor Tomov 638051a01acSTodor Tomov switch (line->fmt[MSM_VFE_PAD_SINK].code) { 639051a01acSTodor Tomov case MEDIA_BUS_FMT_YUYV8_2X8: 640051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV; 641051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV; 642051a01acSTodor Tomov break; 643051a01acSTodor Tomov case MEDIA_BUS_FMT_YVYU8_2X8: 644051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU; 645051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU; 646051a01acSTodor Tomov break; 647051a01acSTodor Tomov case MEDIA_BUS_FMT_UYVY8_2X8: 648051a01acSTodor Tomov default: 649051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY; 650051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY; 651051a01acSTodor Tomov break; 652051a01acSTodor Tomov case MEDIA_BUS_FMT_VYUY8_2X8: 653051a01acSTodor Tomov even_cfg = VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY; 654051a01acSTodor Tomov odd_cfg = VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY; 655051a01acSTodor Tomov break; 656051a01acSTodor Tomov } 657051a01acSTodor Tomov 658051a01acSTodor Tomov writel_relaxed(even_cfg, vfe->base + VFE_0_DEMUX_EVEN_CFG); 659051a01acSTodor Tomov writel_relaxed(odd_cfg, vfe->base + VFE_0_DEMUX_ODD_CFG); 660051a01acSTodor Tomov } 661051a01acSTodor Tomov 662051a01acSTodor Tomov static inline u8 vfe_calc_interp_reso(u16 input, u16 output) 663051a01acSTodor Tomov { 664051a01acSTodor Tomov if (input / output >= 16) 665051a01acSTodor Tomov return 0; 666051a01acSTodor Tomov 667051a01acSTodor Tomov if (input / output >= 8) 668051a01acSTodor Tomov return 1; 669051a01acSTodor Tomov 670051a01acSTodor Tomov if (input / output >= 4) 671051a01acSTodor Tomov return 2; 672051a01acSTodor Tomov 673051a01acSTodor Tomov return 3; 674051a01acSTodor Tomov } 675051a01acSTodor Tomov 676051a01acSTodor Tomov static void vfe_set_scale_cfg(struct vfe_device *vfe, struct vfe_line *line) 677051a01acSTodor Tomov { 678051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 679051a01acSTodor Tomov u32 reg; 680051a01acSTodor Tomov u16 input, output; 681051a01acSTodor Tomov u8 interp_reso; 682051a01acSTodor Tomov u32 phase_mult; 683051a01acSTodor Tomov 684051a01acSTodor Tomov writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG); 685051a01acSTodor Tomov 686051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].width; 687051a01acSTodor Tomov output = line->compose.width; 688051a01acSTodor Tomov reg = (output << 16) | input; 689051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE); 690051a01acSTodor Tomov 691051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 692051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 693051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 694051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_H_PHASE); 695051a01acSTodor Tomov 696051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].height; 697051a01acSTodor Tomov output = line->compose.height; 698051a01acSTodor Tomov reg = (output << 16) | input; 699051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE); 700051a01acSTodor Tomov 701051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 702051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 703051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 704051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_Y_V_PHASE); 705051a01acSTodor Tomov 706051a01acSTodor Tomov writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG); 707051a01acSTodor Tomov 708051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].width; 709051a01acSTodor Tomov output = line->compose.width / 2; 710051a01acSTodor Tomov reg = (output << 16) | input; 711051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE); 712051a01acSTodor Tomov 713051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 714051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 715051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 716051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_H_PHASE); 717051a01acSTodor Tomov 718051a01acSTodor Tomov input = line->fmt[MSM_VFE_PAD_SINK].height; 719051a01acSTodor Tomov output = line->compose.height; 720051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) 721051a01acSTodor Tomov output = line->compose.height / 2; 722051a01acSTodor Tomov reg = (output << 16) | input; 723051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE); 724051a01acSTodor Tomov 725051a01acSTodor Tomov interp_reso = vfe_calc_interp_reso(input, output); 726051a01acSTodor Tomov phase_mult = input * (1 << (13 + interp_reso)) / output; 727051a01acSTodor Tomov reg = (interp_reso << 20) | phase_mult; 728051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_SCALE_ENC_CBCR_V_PHASE); 729051a01acSTodor Tomov } 730051a01acSTodor Tomov 731051a01acSTodor Tomov static void vfe_set_crop_cfg(struct vfe_device *vfe, struct vfe_line *line) 732051a01acSTodor Tomov { 733051a01acSTodor Tomov u32 p = line->video_out.active_fmt.fmt.pix_mp.pixelformat; 734051a01acSTodor Tomov u32 reg; 735051a01acSTodor Tomov u16 first, last; 736051a01acSTodor Tomov 737051a01acSTodor Tomov first = line->crop.left; 738051a01acSTodor Tomov last = line->crop.left + line->crop.width - 1; 739051a01acSTodor Tomov reg = (first << 16) | last; 740051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_WIDTH); 741051a01acSTodor Tomov 742051a01acSTodor Tomov first = line->crop.top; 743051a01acSTodor Tomov last = line->crop.top + line->crop.height - 1; 744051a01acSTodor Tomov reg = (first << 16) | last; 745051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_Y_HEIGHT); 746051a01acSTodor Tomov 747051a01acSTodor Tomov first = line->crop.left / 2; 748051a01acSTodor Tomov last = line->crop.left / 2 + line->crop.width / 2 - 1; 749051a01acSTodor Tomov reg = (first << 16) | last; 750051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_WIDTH); 751051a01acSTodor Tomov 752051a01acSTodor Tomov first = line->crop.top; 753051a01acSTodor Tomov last = line->crop.top + line->crop.height - 1; 754051a01acSTodor Tomov if (p == V4L2_PIX_FMT_NV12 || p == V4L2_PIX_FMT_NV21) { 755051a01acSTodor Tomov first = line->crop.top / 2; 756051a01acSTodor Tomov last = line->crop.top / 2 + line->crop.height / 2 - 1; 757051a01acSTodor Tomov } 758051a01acSTodor Tomov reg = (first << 16) | last; 759051a01acSTodor Tomov writel_relaxed(reg, vfe->base + VFE_0_CROP_ENC_CBCR_HEIGHT); 760051a01acSTodor Tomov } 761051a01acSTodor Tomov 762051a01acSTodor Tomov static void vfe_set_clamp_cfg(struct vfe_device *vfe) 763051a01acSTodor Tomov { 764051a01acSTodor Tomov u32 val = VFE_0_CLAMP_ENC_MAX_CFG_CH0 | 765051a01acSTodor Tomov VFE_0_CLAMP_ENC_MAX_CFG_CH1 | 766051a01acSTodor Tomov VFE_0_CLAMP_ENC_MAX_CFG_CH2; 767051a01acSTodor Tomov 768051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MAX_CFG); 769051a01acSTodor Tomov 770051a01acSTodor Tomov val = VFE_0_CLAMP_ENC_MIN_CFG_CH0 | 771051a01acSTodor Tomov VFE_0_CLAMP_ENC_MIN_CFG_CH1 | 772051a01acSTodor Tomov VFE_0_CLAMP_ENC_MIN_CFG_CH2; 773051a01acSTodor Tomov 774051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CLAMP_ENC_MIN_CFG); 775051a01acSTodor Tomov } 776051a01acSTodor Tomov 777051a01acSTodor Tomov static void vfe_set_qos(struct vfe_device *vfe) 778051a01acSTodor Tomov { 779051a01acSTodor Tomov u32 val = VFE_0_BUS_BDG_QOS_CFG_0_CFG; 780051a01acSTodor Tomov u32 val7 = VFE_0_BUS_BDG_QOS_CFG_7_CFG; 781051a01acSTodor Tomov 782051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_0); 783051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_1); 784051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_2); 785051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_3); 786051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_4); 787051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_5); 788051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_BUS_BDG_QOS_CFG_6); 789051a01acSTodor Tomov writel_relaxed(val7, vfe->base + VFE_0_BUS_BDG_QOS_CFG_7); 790051a01acSTodor Tomov } 791051a01acSTodor Tomov 792051a01acSTodor Tomov static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) 793051a01acSTodor Tomov { 794051a01acSTodor Tomov u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); 795051a01acSTodor Tomov 796051a01acSTodor Tomov if (enable) 797051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_CGC_OVERRIDE_1, val); 798051a01acSTodor Tomov else 799051a01acSTodor Tomov vfe_reg_clr(vfe, VFE_0_CGC_OVERRIDE_1, val); 800051a01acSTodor Tomov 801051a01acSTodor Tomov wmb(); 802051a01acSTodor Tomov } 803051a01acSTodor Tomov 804051a01acSTodor Tomov static void vfe_set_camif_cfg(struct vfe_device *vfe, struct vfe_line *line) 805051a01acSTodor Tomov { 806051a01acSTodor Tomov u32 val; 807051a01acSTodor Tomov 808051a01acSTodor Tomov switch (line->fmt[MSM_VFE_PAD_SINK].code) { 809051a01acSTodor Tomov case MEDIA_BUS_FMT_YUYV8_2X8: 810051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR; 811051a01acSTodor Tomov break; 812051a01acSTodor Tomov case MEDIA_BUS_FMT_YVYU8_2X8: 813051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB; 814051a01acSTodor Tomov break; 815051a01acSTodor Tomov case MEDIA_BUS_FMT_UYVY8_2X8: 816051a01acSTodor Tomov default: 817051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY; 818051a01acSTodor Tomov break; 819051a01acSTodor Tomov case MEDIA_BUS_FMT_VYUY8_2X8: 820051a01acSTodor Tomov val = VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY; 821051a01acSTodor Tomov break; 822051a01acSTodor Tomov } 823051a01acSTodor Tomov 824051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CORE_CFG); 825051a01acSTodor Tomov 826051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].width * 2; 827051a01acSTodor Tomov val |= line->fmt[MSM_VFE_PAD_SINK].height << 16; 828051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_FRAME_CFG); 829051a01acSTodor Tomov 830051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].width * 2 - 1; 831051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_WIDTH_CFG); 832051a01acSTodor Tomov 833051a01acSTodor Tomov val = line->fmt[MSM_VFE_PAD_SINK].height - 1; 834051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_WINDOW_HEIGHT_CFG); 835051a01acSTodor Tomov 836051a01acSTodor Tomov val = 0xffffffff; 837051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_SUBSAMPLE_CFG_0); 838051a01acSTodor Tomov 839051a01acSTodor Tomov val = 0xffffffff; 840051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN); 841051a01acSTodor Tomov 842051a01acSTodor Tomov val = VFE_0_RDI_CFG_x_MIPI_EN_BITS; 843051a01acSTodor Tomov vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val); 844051a01acSTodor Tomov 845051a01acSTodor Tomov val = VFE_0_CAMIF_CFG_VFE_OUTPUT_EN; 846051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_CAMIF_CFG); 847051a01acSTodor Tomov } 848051a01acSTodor Tomov 849051a01acSTodor Tomov static void vfe_set_camif_cmd(struct vfe_device *vfe, u8 enable) 850051a01acSTodor Tomov { 851051a01acSTodor Tomov u32 cmd; 852051a01acSTodor Tomov 853051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_CLEAR_CAMIF_STATUS | VFE_0_CAMIF_CMD_NO_CHANGE; 854051a01acSTodor Tomov writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 855051a01acSTodor Tomov wmb(); 856051a01acSTodor Tomov 857051a01acSTodor Tomov if (enable) 858051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_ENABLE_FRAME_BOUNDARY; 859051a01acSTodor Tomov else 860051a01acSTodor Tomov cmd = VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY; 861051a01acSTodor Tomov 862051a01acSTodor Tomov writel_relaxed(cmd, vfe->base + VFE_0_CAMIF_CMD); 863051a01acSTodor Tomov } 864051a01acSTodor Tomov 865051a01acSTodor Tomov static void vfe_set_module_cfg(struct vfe_device *vfe, u8 enable) 866051a01acSTodor Tomov { 867051a01acSTodor Tomov u32 val = VFE_0_MODULE_CFG_DEMUX | 868051a01acSTodor Tomov VFE_0_MODULE_CFG_CHROMA_UPSAMPLE | 869051a01acSTodor Tomov VFE_0_MODULE_CFG_SCALE_ENC | 870051a01acSTodor Tomov VFE_0_MODULE_CFG_CROP_ENC; 871051a01acSTodor Tomov 872051a01acSTodor Tomov if (enable) 873051a01acSTodor Tomov writel_relaxed(val, vfe->base + VFE_0_MODULE_CFG); 874051a01acSTodor Tomov else 875051a01acSTodor Tomov writel_relaxed(0x0, vfe->base + VFE_0_MODULE_CFG); 876051a01acSTodor Tomov } 877051a01acSTodor Tomov 878051a01acSTodor Tomov static int vfe_camif_wait_for_stop(struct vfe_device *vfe, struct device *dev) 879051a01acSTodor Tomov { 880051a01acSTodor Tomov u32 val; 881051a01acSTodor Tomov int ret; 882051a01acSTodor Tomov 883051a01acSTodor Tomov ret = readl_poll_timeout(vfe->base + VFE_0_CAMIF_STATUS, 884051a01acSTodor Tomov val, 885051a01acSTodor Tomov (val & VFE_0_CAMIF_STATUS_HALT), 886051a01acSTodor Tomov CAMIF_TIMEOUT_SLEEP_US, 887051a01acSTodor Tomov CAMIF_TIMEOUT_ALL_US); 888051a01acSTodor Tomov if (ret < 0) 889051a01acSTodor Tomov dev_err(dev, "%s: camif stop timeout\n", __func__); 890051a01acSTodor Tomov 891051a01acSTodor Tomov return ret; 892051a01acSTodor Tomov } 893051a01acSTodor Tomov 894051a01acSTodor Tomov static void vfe_isr_read(struct vfe_device *vfe, u32 *value0, u32 *value1) 895051a01acSTodor Tomov { 896051a01acSTodor Tomov *value0 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_0); 897051a01acSTodor Tomov *value1 = readl_relaxed(vfe->base + VFE_0_IRQ_STATUS_1); 898051a01acSTodor Tomov 899051a01acSTodor Tomov writel_relaxed(*value0, vfe->base + VFE_0_IRQ_CLEAR_0); 900051a01acSTodor Tomov writel_relaxed(*value1, vfe->base + VFE_0_IRQ_CLEAR_1); 901051a01acSTodor Tomov 902051a01acSTodor Tomov wmb(); 903051a01acSTodor Tomov writel_relaxed(VFE_0_IRQ_CMD_GLOBAL_CLEAR, vfe->base + VFE_0_IRQ_CMD); 904051a01acSTodor Tomov } 905051a01acSTodor Tomov 906051a01acSTodor Tomov static void vfe_violation_read(struct vfe_device *vfe) 907051a01acSTodor Tomov { 908051a01acSTodor Tomov u32 violation = readl_relaxed(vfe->base + VFE_0_VIOLATION_STATUS); 909051a01acSTodor Tomov 910051a01acSTodor Tomov pr_err_ratelimited("VFE: violation = 0x%08x\n", violation); 911051a01acSTodor Tomov } 912051a01acSTodor Tomov 913051a01acSTodor Tomov /* 914051a01acSTodor Tomov * vfe_isr - ISPIF module interrupt handler 915051a01acSTodor Tomov * @irq: Interrupt line 916051a01acSTodor Tomov * @dev: VFE device 917051a01acSTodor Tomov * 918051a01acSTodor Tomov * Return IRQ_HANDLED on success 919051a01acSTodor Tomov */ 920051a01acSTodor Tomov static irqreturn_t vfe_isr(int irq, void *dev) 921051a01acSTodor Tomov { 922051a01acSTodor Tomov struct vfe_device *vfe = dev; 923051a01acSTodor Tomov u32 value0, value1; 924051a01acSTodor Tomov int i, j; 925051a01acSTodor Tomov 926051a01acSTodor Tomov vfe->ops->isr_read(vfe, &value0, &value1); 927051a01acSTodor Tomov 928051a01acSTodor Tomov trace_printk("VFE: status0 = 0x%08x, status1 = 0x%08x\n", 929051a01acSTodor Tomov value0, value1); 930051a01acSTodor Tomov 931051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_RESET_ACK) 932051a01acSTodor Tomov vfe->isr_ops.reset_ack(vfe); 933051a01acSTodor Tomov 934051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_VIOLATION) 935051a01acSTodor Tomov vfe->ops->violation_read(vfe); 936051a01acSTodor Tomov 937051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_BUS_BDG_HALT_ACK) 938051a01acSTodor Tomov vfe->isr_ops.halt_ack(vfe); 939051a01acSTodor Tomov 940051a01acSTodor Tomov for (i = VFE_LINE_RDI0; i <= VFE_LINE_PIX; i++) 941051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_line_n_REG_UPDATE(i)) 942051a01acSTodor Tomov vfe->isr_ops.reg_update(vfe, i); 943051a01acSTodor Tomov 944051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_CAMIF_SOF) 945051a01acSTodor Tomov vfe->isr_ops.sof(vfe, VFE_LINE_PIX); 946051a01acSTodor Tomov 947051a01acSTodor Tomov for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) 948051a01acSTodor Tomov if (value1 & VFE_0_IRQ_STATUS_1_RDIn_SOF(i)) 949051a01acSTodor Tomov vfe->isr_ops.sof(vfe, i); 950051a01acSTodor Tomov 951051a01acSTodor Tomov for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++) 952051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_COMPOSITE_DONE_n(i)) { 953051a01acSTodor Tomov vfe->isr_ops.comp_done(vfe, i); 954051a01acSTodor Tomov for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++) 955051a01acSTodor Tomov if (vfe->wm_output_map[j] == VFE_LINE_PIX) 956051a01acSTodor Tomov value0 &= ~VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(j); 957051a01acSTodor Tomov } 958051a01acSTodor Tomov 959051a01acSTodor Tomov for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++) 960051a01acSTodor Tomov if (value0 & VFE_0_IRQ_STATUS_0_IMAGE_MASTER_n_PING_PONG(i)) 961051a01acSTodor Tomov vfe->isr_ops.wm_done(vfe, i); 962051a01acSTodor Tomov 963051a01acSTodor Tomov return IRQ_HANDLED; 964051a01acSTodor Tomov } 965051a01acSTodor Tomov 966051a01acSTodor Tomov const struct vfe_hw_ops vfe_ops_4_1 = { 967051a01acSTodor Tomov .hw_version_read = vfe_hw_version_read, 968051a01acSTodor Tomov .get_ub_size = vfe_get_ub_size, 969051a01acSTodor Tomov .global_reset = vfe_global_reset, 970051a01acSTodor Tomov .halt_request = vfe_halt_request, 971051a01acSTodor Tomov .halt_clear = vfe_halt_clear, 972051a01acSTodor Tomov .wm_enable = vfe_wm_enable, 973051a01acSTodor Tomov .wm_frame_based = vfe_wm_frame_based, 974051a01acSTodor Tomov .wm_line_based = vfe_wm_line_based, 975051a01acSTodor Tomov .wm_set_framedrop_period = vfe_wm_set_framedrop_period, 976051a01acSTodor Tomov .wm_set_framedrop_pattern = vfe_wm_set_framedrop_pattern, 977051a01acSTodor Tomov .wm_set_ub_cfg = vfe_wm_set_ub_cfg, 978051a01acSTodor Tomov .bus_reload_wm = vfe_bus_reload_wm, 979051a01acSTodor Tomov .wm_set_ping_addr = vfe_wm_set_ping_addr, 980051a01acSTodor Tomov .wm_set_pong_addr = vfe_wm_set_pong_addr, 981051a01acSTodor Tomov .wm_get_ping_pong_status = vfe_wm_get_ping_pong_status, 982051a01acSTodor Tomov .bus_enable_wr_if = vfe_bus_enable_wr_if, 983051a01acSTodor Tomov .bus_connect_wm_to_rdi = vfe_bus_connect_wm_to_rdi, 984051a01acSTodor Tomov .wm_set_subsample = vfe_wm_set_subsample, 985051a01acSTodor Tomov .bus_disconnect_wm_from_rdi = vfe_bus_disconnect_wm_from_rdi, 986051a01acSTodor Tomov .set_xbar_cfg = vfe_set_xbar_cfg, 987051a01acSTodor Tomov .set_rdi_cid = vfe_set_rdi_cid, 988051a01acSTodor Tomov .reg_update = vfe_reg_update, 989051a01acSTodor Tomov .reg_update_clear = vfe_reg_update_clear, 990051a01acSTodor Tomov .enable_irq_wm_line = vfe_enable_irq_wm_line, 991051a01acSTodor Tomov .enable_irq_pix_line = vfe_enable_irq_pix_line, 992051a01acSTodor Tomov .enable_irq_common = vfe_enable_irq_common, 993051a01acSTodor Tomov .set_demux_cfg = vfe_set_demux_cfg, 994051a01acSTodor Tomov .set_scale_cfg = vfe_set_scale_cfg, 995051a01acSTodor Tomov .set_crop_cfg = vfe_set_crop_cfg, 996051a01acSTodor Tomov .set_clamp_cfg = vfe_set_clamp_cfg, 997051a01acSTodor Tomov .set_qos = vfe_set_qos, 998051a01acSTodor Tomov .set_cgc_override = vfe_set_cgc_override, 999051a01acSTodor Tomov .set_camif_cfg = vfe_set_camif_cfg, 1000051a01acSTodor Tomov .set_camif_cmd = vfe_set_camif_cmd, 1001051a01acSTodor Tomov .set_module_cfg = vfe_set_module_cfg, 1002051a01acSTodor Tomov .camif_wait_for_stop = vfe_camif_wait_for_stop, 1003051a01acSTodor Tomov .isr_read = vfe_isr_read, 1004051a01acSTodor Tomov .violation_read = vfe_violation_read, 1005051a01acSTodor Tomov .isr = vfe_isr, 1006051a01acSTodor Tomov }; 1007