1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-ispif.c 4 * 5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/mutex.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <media/media-entity.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-subdev.h> 21 22 #include "camss-ispif.h" 23 #include "camss.h" 24 25 #define MSM_ISPIF_NAME "msm_ispif" 26 27 #define ISPIF_RST_CMD_0 0x008 28 #define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0) 29 #define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1) 30 #define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2) 31 #define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3) 32 #define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4) 33 #define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5) 34 #define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6) 35 #define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7) 36 #define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8) 37 #define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9) 38 #define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10) 39 #define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11) 40 #define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12) 41 #define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16) 42 #define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17) 43 #define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18) 44 #define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19) 45 #define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c 46 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m)) 47 #define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6) 48 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m)) 49 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249 50 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff 51 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000 52 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000 53 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m)) 54 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249 55 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff 56 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000 57 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000 58 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m)) 59 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249 60 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff 61 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m)) 62 #define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12) 63 #define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25) 64 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m)) 65 #define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12) 66 #define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25) 67 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m)) 68 #define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12) 69 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m)) 70 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m)) 71 #define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m)) 72 #define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m)) 73 #define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m)) 74 #define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m)) 75 #define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \ 76 (0x254 + 0x200 * (m) + 0x4 * (n)) 77 #define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \ 78 (0x264 + 0x200 * (m) + 0x4 * (n)) 79 /* PACK_CFG registers are 8x96 only */ 80 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \ 81 (0x270 + 0x200 * (m) + 0x4 * (n)) 82 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \ 83 (0x27c + 0x200 * (m) + 0x4 * (n)) 84 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \ 85 (1 << ((cid % 8) * 4)) 86 #define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \ 87 (0x2c0 + 0x200 * (m) + 0x4 * (n)) 88 #define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \ 89 (0x2d0 + 0x200 * (m) + 0x4 * (n)) 90 91 #define CSI_PIX_CLK_MUX_SEL 0x000 92 #define CSI_RDI_CLK_MUX_SEL 0x008 93 94 #define ISPIF_TIMEOUT_SLEEP_US 1000 95 #define ISPIF_TIMEOUT_ALL_US 1000000 96 #define ISPIF_RESET_TIMEOUT_MS 500 97 98 enum ispif_intf_cmd { 99 CMD_DISABLE_FRAME_BOUNDARY = 0x0, 100 CMD_ENABLE_FRAME_BOUNDARY = 0x1, 101 CMD_DISABLE_IMMEDIATELY = 0x2, 102 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa, 103 CMD_ALL_NO_CHANGE = 0xffffffff, 104 }; 105 106 static const u32 ispif_formats_8x16[] = { 107 MEDIA_BUS_FMT_UYVY8_2X8, 108 MEDIA_BUS_FMT_VYUY8_2X8, 109 MEDIA_BUS_FMT_YUYV8_2X8, 110 MEDIA_BUS_FMT_YVYU8_2X8, 111 MEDIA_BUS_FMT_SBGGR8_1X8, 112 MEDIA_BUS_FMT_SGBRG8_1X8, 113 MEDIA_BUS_FMT_SGRBG8_1X8, 114 MEDIA_BUS_FMT_SRGGB8_1X8, 115 MEDIA_BUS_FMT_SBGGR10_1X10, 116 MEDIA_BUS_FMT_SGBRG10_1X10, 117 MEDIA_BUS_FMT_SGRBG10_1X10, 118 MEDIA_BUS_FMT_SRGGB10_1X10, 119 MEDIA_BUS_FMT_SBGGR12_1X12, 120 MEDIA_BUS_FMT_SGBRG12_1X12, 121 MEDIA_BUS_FMT_SGRBG12_1X12, 122 MEDIA_BUS_FMT_SRGGB12_1X12, 123 MEDIA_BUS_FMT_Y10_1X10, 124 }; 125 126 static const u32 ispif_formats_8x96[] = { 127 MEDIA_BUS_FMT_UYVY8_2X8, 128 MEDIA_BUS_FMT_VYUY8_2X8, 129 MEDIA_BUS_FMT_YUYV8_2X8, 130 MEDIA_BUS_FMT_YVYU8_2X8, 131 MEDIA_BUS_FMT_SBGGR8_1X8, 132 MEDIA_BUS_FMT_SGBRG8_1X8, 133 MEDIA_BUS_FMT_SGRBG8_1X8, 134 MEDIA_BUS_FMT_SRGGB8_1X8, 135 MEDIA_BUS_FMT_SBGGR10_1X10, 136 MEDIA_BUS_FMT_SGBRG10_1X10, 137 MEDIA_BUS_FMT_SGRBG10_1X10, 138 MEDIA_BUS_FMT_SRGGB10_1X10, 139 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, 140 MEDIA_BUS_FMT_SBGGR12_1X12, 141 MEDIA_BUS_FMT_SGBRG12_1X12, 142 MEDIA_BUS_FMT_SGRBG12_1X12, 143 MEDIA_BUS_FMT_SRGGB12_1X12, 144 MEDIA_BUS_FMT_SBGGR14_1X14, 145 MEDIA_BUS_FMT_SGBRG14_1X14, 146 MEDIA_BUS_FMT_SGRBG14_1X14, 147 MEDIA_BUS_FMT_SRGGB14_1X14, 148 MEDIA_BUS_FMT_Y10_1X10, 149 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE, 150 }; 151 152 /* 153 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96 154 * @irq: Interrupt line 155 * @dev: ISPIF device 156 * 157 * Return IRQ_HANDLED on success 158 */ 159 static irqreturn_t ispif_isr_8x96(int irq, void *dev) 160 { 161 struct ispif_device *ispif = dev; 162 u32 value0, value1, value2, value3, value4, value5; 163 164 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); 165 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0)); 166 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); 167 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1)); 168 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1)); 169 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1)); 170 171 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); 172 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0)); 173 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); 174 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1)); 175 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1)); 176 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1)); 177 178 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); 179 180 if ((value0 >> 27) & 0x1) 181 complete(&ispif->reset_complete); 182 183 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) 184 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n"); 185 186 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) 187 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n"); 188 189 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW)) 190 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n"); 191 192 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW)) 193 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n"); 194 195 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) 196 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n"); 197 198 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) 199 dev_err_ratelimited(to_device(ispif), "VFE1 pix0 overflow\n"); 200 201 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) 202 dev_err_ratelimited(to_device(ispif), "VFE1 rdi0 overflow\n"); 203 204 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW)) 205 dev_err_ratelimited(to_device(ispif), "VFE1 pix1 overflow\n"); 206 207 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW)) 208 dev_err_ratelimited(to_device(ispif), "VFE1 rdi1 overflow\n"); 209 210 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) 211 dev_err_ratelimited(to_device(ispif), "VFE1 rdi2 overflow\n"); 212 213 return IRQ_HANDLED; 214 } 215 216 /* 217 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16 218 * @irq: Interrupt line 219 * @dev: ISPIF device 220 * 221 * Return IRQ_HANDLED on success 222 */ 223 static irqreturn_t ispif_isr_8x16(int irq, void *dev) 224 { 225 struct ispif_device *ispif = dev; 226 u32 value0, value1, value2; 227 228 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); 229 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0)); 230 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); 231 232 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); 233 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0)); 234 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); 235 236 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); 237 238 if ((value0 >> 27) & 0x1) 239 complete(&ispif->reset_complete); 240 241 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) 242 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n"); 243 244 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) 245 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n"); 246 247 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW)) 248 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n"); 249 250 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW)) 251 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n"); 252 253 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) 254 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n"); 255 256 return IRQ_HANDLED; 257 } 258 259 /* 260 * ispif_reset - Trigger reset on ISPIF module and wait to complete 261 * @ispif: ISPIF device 262 * 263 * Return 0 on success or a negative error code otherwise 264 */ 265 static int ispif_reset(struct ispif_device *ispif) 266 { 267 unsigned long time; 268 u32 val; 269 int ret; 270 271 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0); 272 if (ret < 0) 273 return ret; 274 275 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1); 276 if (ret < 0) 277 return ret; 278 279 ret = camss_enable_clocks(ispif->nclocks_for_reset, 280 ispif->clock_for_reset, 281 to_device(ispif)); 282 if (ret < 0) 283 return ret; 284 285 reinit_completion(&ispif->reset_complete); 286 287 val = ISPIF_RST_CMD_0_STROBED_RST_EN | 288 ISPIF_RST_CMD_0_MISC_LOGIC_RST | 289 ISPIF_RST_CMD_0_SW_REG_RST | 290 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST | 291 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST | 292 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST | 293 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST | 294 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST | 295 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST | 296 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST | 297 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST | 298 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST | 299 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST | 300 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST | 301 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST | 302 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST | 303 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST; 304 305 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0); 306 307 time = wait_for_completion_timeout(&ispif->reset_complete, 308 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS)); 309 if (!time) { 310 dev_err(to_device(ispif), "ISPIF reset timeout\n"); 311 ret = -EIO; 312 } 313 314 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset); 315 316 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE0); 317 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE1); 318 319 return ret; 320 } 321 322 /* 323 * ispif_set_power - Power on/off ISPIF module 324 * @sd: ISPIF V4L2 subdevice 325 * @on: Requested power state 326 * 327 * Return 0 on success or a negative error code otherwise 328 */ 329 static int ispif_set_power(struct v4l2_subdev *sd, int on) 330 { 331 struct ispif_line *line = v4l2_get_subdevdata(sd); 332 struct ispif_device *ispif = line->ispif; 333 struct device *dev = to_device(ispif); 334 int ret = 0; 335 336 mutex_lock(&ispif->power_lock); 337 338 if (on) { 339 if (ispif->power_count) { 340 /* Power is already on */ 341 ispif->power_count++; 342 goto exit; 343 } 344 345 ret = pm_runtime_get_sync(dev); 346 if (ret < 0) 347 goto exit; 348 349 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev); 350 if (ret < 0) { 351 pm_runtime_put_sync(dev); 352 goto exit; 353 } 354 355 ret = ispif_reset(ispif); 356 if (ret < 0) { 357 pm_runtime_put_sync(dev); 358 camss_disable_clocks(ispif->nclocks, ispif->clock); 359 goto exit; 360 } 361 362 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE; 363 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE; 364 365 ispif->power_count++; 366 } else { 367 if (ispif->power_count == 0) { 368 dev_err(dev, "ispif power off on power_count == 0\n"); 369 goto exit; 370 } else if (ispif->power_count == 1) { 371 camss_disable_clocks(ispif->nclocks, ispif->clock); 372 pm_runtime_put_sync(dev); 373 } 374 375 ispif->power_count--; 376 } 377 378 exit: 379 mutex_unlock(&ispif->power_lock); 380 381 return ret; 382 } 383 384 /* 385 * ispif_select_clk_mux - Select clock for PIX/RDI interface 386 * @ispif: ISPIF device 387 * @intf: VFE interface 388 * @csid: CSID HW module id 389 * @vfe: VFE HW module id 390 * @enable: enable or disable the selected clock 391 */ 392 static void ispif_select_clk_mux(struct ispif_device *ispif, 393 enum ispif_intf intf, u8 csid, 394 u8 vfe, u8 enable) 395 { 396 u32 val; 397 398 switch (intf) { 399 case PIX0: 400 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 401 val &= ~(0xf << (vfe * 8)); 402 if (enable) 403 val |= (csid << (vfe * 8)); 404 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 405 break; 406 407 case RDI0: 408 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 409 val &= ~(0xf << (vfe * 12)); 410 if (enable) 411 val |= (csid << (vfe * 12)); 412 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 413 break; 414 415 case PIX1: 416 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 417 val &= ~(0xf << (4 + (vfe * 8))); 418 if (enable) 419 val |= (csid << (4 + (vfe * 8))); 420 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 421 break; 422 423 case RDI1: 424 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 425 val &= ~(0xf << (4 + (vfe * 12))); 426 if (enable) 427 val |= (csid << (4 + (vfe * 12))); 428 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 429 break; 430 431 case RDI2: 432 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 433 val &= ~(0xf << (8 + (vfe * 12))); 434 if (enable) 435 val |= (csid << (8 + (vfe * 12))); 436 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 437 break; 438 } 439 440 mb(); 441 } 442 443 /* 444 * ispif_validate_intf_status - Validate current status of PIX/RDI interface 445 * @ispif: ISPIF device 446 * @intf: VFE interface 447 * @vfe: VFE HW module id 448 * 449 * Return 0 when interface is idle or -EBUSY otherwise 450 */ 451 static int ispif_validate_intf_status(struct ispif_device *ispif, 452 enum ispif_intf intf, u8 vfe) 453 { 454 int ret = 0; 455 u32 val = 0; 456 457 switch (intf) { 458 case PIX0: 459 val = readl_relaxed(ispif->base + 460 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0)); 461 break; 462 case RDI0: 463 val = readl_relaxed(ispif->base + 464 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0)); 465 break; 466 case PIX1: 467 val = readl_relaxed(ispif->base + 468 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1)); 469 break; 470 case RDI1: 471 val = readl_relaxed(ispif->base + 472 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1)); 473 break; 474 case RDI2: 475 val = readl_relaxed(ispif->base + 476 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2)); 477 break; 478 } 479 480 if ((val & 0xf) != 0xf) { 481 dev_err(to_device(ispif), "%s: ispif is busy: 0x%x\n", 482 __func__, val); 483 ret = -EBUSY; 484 } 485 486 return ret; 487 } 488 489 /* 490 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop 491 * @ispif: ISPIF device 492 * @intf: VFE interface 493 * @vfe: VFE HW module id 494 * 495 * Return 0 on success or a negative error code otherwise 496 */ 497 static int ispif_wait_for_stop(struct ispif_device *ispif, 498 enum ispif_intf intf, u8 vfe) 499 { 500 u32 addr = 0; 501 u32 stop_flag = 0; 502 int ret; 503 504 switch (intf) { 505 case PIX0: 506 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0); 507 break; 508 case RDI0: 509 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0); 510 break; 511 case PIX1: 512 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1); 513 break; 514 case RDI1: 515 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1); 516 break; 517 case RDI2: 518 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2); 519 break; 520 } 521 522 ret = readl_poll_timeout(ispif->base + addr, 523 stop_flag, 524 (stop_flag & 0xf) == 0xf, 525 ISPIF_TIMEOUT_SLEEP_US, 526 ISPIF_TIMEOUT_ALL_US); 527 if (ret < 0) 528 dev_err(to_device(ispif), "%s: ispif stop timeout\n", 529 __func__); 530 531 return ret; 532 } 533 534 /* 535 * ispif_select_csid - Select CSID HW module for input from 536 * @ispif: ISPIF device 537 * @intf: VFE interface 538 * @csid: CSID HW module id 539 * @vfe: VFE HW module id 540 * @enable: enable or disable the selected input 541 */ 542 static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf, 543 u8 csid, u8 vfe, u8 enable) 544 { 545 u32 val; 546 547 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); 548 switch (intf) { 549 case PIX0: 550 val &= ~(BIT(1) | BIT(0)); 551 if (enable) 552 val |= csid; 553 break; 554 case RDI0: 555 val &= ~(BIT(5) | BIT(4)); 556 if (enable) 557 val |= (csid << 4); 558 break; 559 case PIX1: 560 val &= ~(BIT(9) | BIT(8)); 561 if (enable) 562 val |= (csid << 8); 563 break; 564 case RDI1: 565 val &= ~(BIT(13) | BIT(12)); 566 if (enable) 567 val |= (csid << 12); 568 break; 569 case RDI2: 570 val &= ~(BIT(21) | BIT(20)); 571 if (enable) 572 val |= (csid << 20); 573 break; 574 } 575 576 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); 577 } 578 579 /* 580 * ispif_select_cid - Enable/disable desired CID 581 * @ispif: ISPIF device 582 * @intf: VFE interface 583 * @cid: desired CID to enable/disable 584 * @vfe: VFE HW module id 585 * @enable: enable or disable the desired CID 586 */ 587 static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf, 588 u8 cid, u8 vfe, u8 enable) 589 { 590 u32 cid_mask = 1 << cid; 591 u32 addr = 0; 592 u32 val; 593 594 switch (intf) { 595 case PIX0: 596 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0); 597 break; 598 case RDI0: 599 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0); 600 break; 601 case PIX1: 602 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1); 603 break; 604 case RDI1: 605 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1); 606 break; 607 case RDI2: 608 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2); 609 break; 610 } 611 612 val = readl_relaxed(ispif->base + addr); 613 if (enable) 614 val |= cid_mask; 615 else 616 val &= ~cid_mask; 617 618 writel(val, ispif->base + addr); 619 } 620 621 /* 622 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface 623 * @ispif: ISPIF device 624 * @intf: VFE interface 625 * @vfe: VFE HW module id 626 * @enable: enable or disable 627 */ 628 static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf, 629 u8 vfe, u8 enable) 630 { 631 u32 val; 632 633 switch (intf) { 634 case PIX0: 635 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 636 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK; 637 if (enable) 638 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE; 639 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 640 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE, 641 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); 642 break; 643 case RDI0: 644 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 645 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK; 646 if (enable) 647 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE; 648 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 649 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE, 650 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); 651 break; 652 case PIX1: 653 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 654 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK; 655 if (enable) 656 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE; 657 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 658 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE, 659 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); 660 break; 661 case RDI1: 662 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 663 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK; 664 if (enable) 665 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE; 666 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 667 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE, 668 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); 669 break; 670 case RDI2: 671 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); 672 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK; 673 if (enable) 674 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE; 675 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); 676 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE, 677 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe)); 678 break; 679 } 680 681 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); 682 } 683 684 /* 685 * ispif_config_pack - Config packing for PRDI mode 686 * @ispif: ISPIF device 687 * @code: media bus format code 688 * @intf: VFE interface 689 * @cid: desired CID to handle 690 * @vfe: VFE HW module id 691 * @enable: enable or disable 692 */ 693 static void ispif_config_pack(struct ispif_device *ispif, u32 code, 694 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable) 695 { 696 u32 addr, val; 697 698 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE && 699 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE) 700 return; 701 702 switch (intf) { 703 case RDI0: 704 if (cid < 8) 705 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0); 706 else 707 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0); 708 break; 709 case RDI1: 710 if (cid < 8) 711 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1); 712 else 713 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1); 714 break; 715 case RDI2: 716 if (cid < 8) 717 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2); 718 else 719 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2); 720 break; 721 default: 722 return; 723 } 724 725 if (enable) 726 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid); 727 else 728 val = 0; 729 730 writel_relaxed(val, ispif->base + addr); 731 } 732 733 /* 734 * ispif_set_intf_cmd - Set command to enable/disable interface 735 * @ispif: ISPIF device 736 * @cmd: interface command 737 * @intf: VFE interface 738 * @vfe: VFE HW module id 739 * @vc: virtual channel 740 */ 741 static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd, 742 enum ispif_intf intf, u8 vfe, u8 vc) 743 { 744 u32 *val; 745 746 if (intf == RDI2) { 747 val = &ispif->intf_cmd[vfe].cmd_1; 748 *val &= ~(0x3 << (vc * 2 + 8)); 749 *val |= (cmd << (vc * 2 + 8)); 750 wmb(); 751 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe)); 752 wmb(); 753 } else { 754 val = &ispif->intf_cmd[vfe].cmd_0; 755 *val &= ~(0x3 << (vc * 2 + intf * 8)); 756 *val |= (cmd << (vc * 2 + intf * 8)); 757 wmb(); 758 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe)); 759 wmb(); 760 } 761 } 762 763 /* 764 * ispif_set_stream - Enable/disable streaming on ISPIF module 765 * @sd: ISPIF V4L2 subdevice 766 * @enable: Requested streaming state 767 * 768 * Main configuration of ISPIF module is also done here. 769 * 770 * Return 0 on success or a negative error code otherwise 771 */ 772 static int ispif_set_stream(struct v4l2_subdev *sd, int enable) 773 { 774 struct ispif_line *line = v4l2_get_subdevdata(sd); 775 struct ispif_device *ispif = line->ispif; 776 enum ispif_intf intf = line->interface; 777 u8 csid = line->csid_id; 778 u8 vfe = line->vfe_id; 779 u8 vc = 0; /* Virtual Channel 0 */ 780 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */ 781 int ret; 782 783 if (enable) { 784 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK])) 785 return -ENOLINK; 786 787 /* Config */ 788 789 mutex_lock(&ispif->config_lock); 790 ispif_select_clk_mux(ispif, intf, csid, vfe, 1); 791 792 ret = ispif_validate_intf_status(ispif, intf, vfe); 793 if (ret < 0) { 794 mutex_unlock(&ispif->config_lock); 795 return ret; 796 } 797 798 ispif_select_csid(ispif, intf, csid, vfe, 1); 799 ispif_select_cid(ispif, intf, cid, vfe, 1); 800 ispif_config_irq(ispif, intf, vfe, 1); 801 if (to_camss(ispif)->version == CAMSS_8x96) 802 ispif_config_pack(ispif, 803 line->fmt[MSM_ISPIF_PAD_SINK].code, 804 intf, cid, vfe, 1); 805 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY, 806 intf, vfe, vc); 807 } else { 808 mutex_lock(&ispif->config_lock); 809 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY, 810 intf, vfe, vc); 811 mutex_unlock(&ispif->config_lock); 812 813 ret = ispif_wait_for_stop(ispif, intf, vfe); 814 if (ret < 0) 815 return ret; 816 817 mutex_lock(&ispif->config_lock); 818 if (to_camss(ispif)->version == CAMSS_8x96) 819 ispif_config_pack(ispif, 820 line->fmt[MSM_ISPIF_PAD_SINK].code, 821 intf, cid, vfe, 0); 822 ispif_config_irq(ispif, intf, vfe, 0); 823 ispif_select_cid(ispif, intf, cid, vfe, 0); 824 ispif_select_csid(ispif, intf, csid, vfe, 0); 825 ispif_select_clk_mux(ispif, intf, csid, vfe, 0); 826 } 827 828 mutex_unlock(&ispif->config_lock); 829 830 return 0; 831 } 832 833 /* 834 * __ispif_get_format - Get pointer to format structure 835 * @ispif: ISPIF line 836 * @cfg: V4L2 subdev pad configuration 837 * @pad: pad from which format is requested 838 * @which: TRY or ACTIVE format 839 * 840 * Return pointer to TRY or ACTIVE format structure 841 */ 842 static struct v4l2_mbus_framefmt * 843 __ispif_get_format(struct ispif_line *line, 844 struct v4l2_subdev_pad_config *cfg, 845 unsigned int pad, 846 enum v4l2_subdev_format_whence which) 847 { 848 if (which == V4L2_SUBDEV_FORMAT_TRY) 849 return v4l2_subdev_get_try_format(&line->subdev, cfg, pad); 850 851 return &line->fmt[pad]; 852 } 853 854 /* 855 * ispif_try_format - Handle try format by pad subdev method 856 * @ispif: ISPIF line 857 * @cfg: V4L2 subdev pad configuration 858 * @pad: pad on which format is requested 859 * @fmt: pointer to v4l2 format structure 860 * @which: wanted subdev format 861 */ 862 static void ispif_try_format(struct ispif_line *line, 863 struct v4l2_subdev_pad_config *cfg, 864 unsigned int pad, 865 struct v4l2_mbus_framefmt *fmt, 866 enum v4l2_subdev_format_whence which) 867 { 868 unsigned int i; 869 870 switch (pad) { 871 case MSM_ISPIF_PAD_SINK: 872 /* Set format on sink pad */ 873 874 for (i = 0; i < line->nformats; i++) 875 if (fmt->code == line->formats[i]) 876 break; 877 878 /* If not found, use UYVY as default */ 879 if (i >= line->nformats) 880 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 881 882 fmt->width = clamp_t(u32, fmt->width, 1, 8191); 883 fmt->height = clamp_t(u32, fmt->height, 1, 8191); 884 885 fmt->field = V4L2_FIELD_NONE; 886 fmt->colorspace = V4L2_COLORSPACE_SRGB; 887 888 break; 889 890 case MSM_ISPIF_PAD_SRC: 891 /* Set and return a format same as sink pad */ 892 893 *fmt = *__ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK, 894 which); 895 896 break; 897 } 898 899 fmt->colorspace = V4L2_COLORSPACE_SRGB; 900 } 901 902 /* 903 * ispif_enum_mbus_code - Handle pixel format enumeration 904 * @sd: ISPIF V4L2 subdevice 905 * @cfg: V4L2 subdev pad configuration 906 * @code: pointer to v4l2_subdev_mbus_code_enum structure 907 * return -EINVAL or zero on success 908 */ 909 static int ispif_enum_mbus_code(struct v4l2_subdev *sd, 910 struct v4l2_subdev_pad_config *cfg, 911 struct v4l2_subdev_mbus_code_enum *code) 912 { 913 struct ispif_line *line = v4l2_get_subdevdata(sd); 914 struct v4l2_mbus_framefmt *format; 915 916 if (code->pad == MSM_ISPIF_PAD_SINK) { 917 if (code->index >= line->nformats) 918 return -EINVAL; 919 920 code->code = line->formats[code->index]; 921 } else { 922 if (code->index > 0) 923 return -EINVAL; 924 925 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK, 926 code->which); 927 928 code->code = format->code; 929 } 930 931 return 0; 932 } 933 934 /* 935 * ispif_enum_frame_size - Handle frame size enumeration 936 * @sd: ISPIF V4L2 subdevice 937 * @cfg: V4L2 subdev pad configuration 938 * @fse: pointer to v4l2_subdev_frame_size_enum structure 939 * return -EINVAL or zero on success 940 */ 941 static int ispif_enum_frame_size(struct v4l2_subdev *sd, 942 struct v4l2_subdev_pad_config *cfg, 943 struct v4l2_subdev_frame_size_enum *fse) 944 { 945 struct ispif_line *line = v4l2_get_subdevdata(sd); 946 struct v4l2_mbus_framefmt format; 947 948 if (fse->index != 0) 949 return -EINVAL; 950 951 format.code = fse->code; 952 format.width = 1; 953 format.height = 1; 954 ispif_try_format(line, cfg, fse->pad, &format, fse->which); 955 fse->min_width = format.width; 956 fse->min_height = format.height; 957 958 if (format.code != fse->code) 959 return -EINVAL; 960 961 format.code = fse->code; 962 format.width = -1; 963 format.height = -1; 964 ispif_try_format(line, cfg, fse->pad, &format, fse->which); 965 fse->max_width = format.width; 966 fse->max_height = format.height; 967 968 return 0; 969 } 970 971 /* 972 * ispif_get_format - Handle get format by pads subdev method 973 * @sd: ISPIF V4L2 subdevice 974 * @cfg: V4L2 subdev pad configuration 975 * @fmt: pointer to v4l2 subdev format structure 976 * 977 * Return -EINVAL or zero on success 978 */ 979 static int ispif_get_format(struct v4l2_subdev *sd, 980 struct v4l2_subdev_pad_config *cfg, 981 struct v4l2_subdev_format *fmt) 982 { 983 struct ispif_line *line = v4l2_get_subdevdata(sd); 984 struct v4l2_mbus_framefmt *format; 985 986 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which); 987 if (format == NULL) 988 return -EINVAL; 989 990 fmt->format = *format; 991 992 return 0; 993 } 994 995 /* 996 * ispif_set_format - Handle set format by pads subdev method 997 * @sd: ISPIF V4L2 subdevice 998 * @cfg: V4L2 subdev pad configuration 999 * @fmt: pointer to v4l2 subdev format structure 1000 * 1001 * Return -EINVAL or zero on success 1002 */ 1003 static int ispif_set_format(struct v4l2_subdev *sd, 1004 struct v4l2_subdev_pad_config *cfg, 1005 struct v4l2_subdev_format *fmt) 1006 { 1007 struct ispif_line *line = v4l2_get_subdevdata(sd); 1008 struct v4l2_mbus_framefmt *format; 1009 1010 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which); 1011 if (format == NULL) 1012 return -EINVAL; 1013 1014 ispif_try_format(line, cfg, fmt->pad, &fmt->format, fmt->which); 1015 *format = fmt->format; 1016 1017 /* Propagate the format from sink to source */ 1018 if (fmt->pad == MSM_ISPIF_PAD_SINK) { 1019 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SRC, 1020 fmt->which); 1021 1022 *format = fmt->format; 1023 ispif_try_format(line, cfg, MSM_ISPIF_PAD_SRC, format, 1024 fmt->which); 1025 } 1026 1027 return 0; 1028 } 1029 1030 /* 1031 * ispif_init_formats - Initialize formats on all pads 1032 * @sd: ISPIF V4L2 subdevice 1033 * @fh: V4L2 subdev file handle 1034 * 1035 * Initialize all pad formats with default values. 1036 * 1037 * Return 0 on success or a negative error code otherwise 1038 */ 1039 static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1040 { 1041 struct v4l2_subdev_format format = { 1042 .pad = MSM_ISPIF_PAD_SINK, 1043 .which = fh ? V4L2_SUBDEV_FORMAT_TRY : 1044 V4L2_SUBDEV_FORMAT_ACTIVE, 1045 .format = { 1046 .code = MEDIA_BUS_FMT_UYVY8_2X8, 1047 .width = 1920, 1048 .height = 1080 1049 } 1050 }; 1051 1052 return ispif_set_format(sd, fh ? fh->pad : NULL, &format); 1053 } 1054 1055 /* 1056 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources 1057 * @ispif: ISPIF device 1058 * @res: ISPIF module resources table 1059 * 1060 * Return 0 on success or a negative error code otherwise 1061 */ 1062 int msm_ispif_subdev_init(struct ispif_device *ispif, 1063 const struct resources_ispif *res) 1064 { 1065 struct device *dev = to_device(ispif); 1066 struct platform_device *pdev = to_platform_device(dev); 1067 struct resource *r; 1068 int i; 1069 int ret; 1070 1071 /* Number of ISPIF lines - same as number of CSID hardware modules */ 1072 if (to_camss(ispif)->version == CAMSS_8x16) 1073 ispif->line_num = 2; 1074 else if (to_camss(ispif)->version == CAMSS_8x96) 1075 ispif->line_num = 4; 1076 else 1077 return -EINVAL; 1078 1079 ispif->line = kcalloc(ispif->line_num, sizeof(*ispif->line), 1080 GFP_KERNEL); 1081 if (!ispif->line) 1082 return -ENOMEM; 1083 1084 for (i = 0; i < ispif->line_num; i++) { 1085 ispif->line[i].ispif = ispif; 1086 ispif->line[i].id = i; 1087 1088 if (to_camss(ispif)->version == CAMSS_8x16) { 1089 ispif->line[i].formats = ispif_formats_8x16; 1090 ispif->line[i].nformats = 1091 ARRAY_SIZE(ispif_formats_8x16); 1092 } else if (to_camss(ispif)->version == CAMSS_8x96) { 1093 ispif->line[i].formats = ispif_formats_8x96; 1094 ispif->line[i].nformats = 1095 ARRAY_SIZE(ispif_formats_8x96); 1096 } else { 1097 return -EINVAL; 1098 } 1099 } 1100 1101 /* Memory */ 1102 1103 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); 1104 ispif->base = devm_ioremap_resource(dev, r); 1105 if (IS_ERR(ispif->base)) { 1106 dev_err(dev, "could not map memory\n"); 1107 return PTR_ERR(ispif->base); 1108 } 1109 1110 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]); 1111 ispif->base_clk_mux = devm_ioremap_resource(dev, r); 1112 if (IS_ERR(ispif->base_clk_mux)) { 1113 dev_err(dev, "could not map memory\n"); 1114 return PTR_ERR(ispif->base_clk_mux); 1115 } 1116 1117 /* Interrupt */ 1118 1119 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt); 1120 1121 if (!r) { 1122 dev_err(dev, "missing IRQ\n"); 1123 return -EINVAL; 1124 } 1125 1126 ispif->irq = r->start; 1127 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s", 1128 dev_name(dev), MSM_ISPIF_NAME); 1129 if (to_camss(ispif)->version == CAMSS_8x16) 1130 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16, 1131 IRQF_TRIGGER_RISING, ispif->irq_name, ispif); 1132 else if (to_camss(ispif)->version == CAMSS_8x96) 1133 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96, 1134 IRQF_TRIGGER_RISING, ispif->irq_name, ispif); 1135 else 1136 ret = -EINVAL; 1137 if (ret < 0) { 1138 dev_err(dev, "request_irq failed: %d\n", ret); 1139 return ret; 1140 } 1141 1142 /* Clocks */ 1143 1144 ispif->nclocks = 0; 1145 while (res->clock[ispif->nclocks]) 1146 ispif->nclocks++; 1147 1148 ispif->clock = devm_kcalloc(dev, 1149 ispif->nclocks, sizeof(*ispif->clock), 1150 GFP_KERNEL); 1151 if (!ispif->clock) 1152 return -ENOMEM; 1153 1154 for (i = 0; i < ispif->nclocks; i++) { 1155 struct camss_clock *clock = &ispif->clock[i]; 1156 1157 clock->clk = devm_clk_get(dev, res->clock[i]); 1158 if (IS_ERR(clock->clk)) 1159 return PTR_ERR(clock->clk); 1160 1161 clock->freq = NULL; 1162 clock->nfreqs = 0; 1163 } 1164 1165 ispif->nclocks_for_reset = 0; 1166 while (res->clock_for_reset[ispif->nclocks_for_reset]) 1167 ispif->nclocks_for_reset++; 1168 1169 ispif->clock_for_reset = devm_kcalloc(dev, 1170 ispif->nclocks_for_reset, 1171 sizeof(*ispif->clock_for_reset), 1172 GFP_KERNEL); 1173 if (!ispif->clock_for_reset) 1174 return -ENOMEM; 1175 1176 for (i = 0; i < ispif->nclocks_for_reset; i++) { 1177 struct camss_clock *clock = &ispif->clock_for_reset[i]; 1178 1179 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]); 1180 if (IS_ERR(clock->clk)) 1181 return PTR_ERR(clock->clk); 1182 1183 clock->freq = NULL; 1184 clock->nfreqs = 0; 1185 } 1186 1187 mutex_init(&ispif->power_lock); 1188 ispif->power_count = 0; 1189 1190 mutex_init(&ispif->config_lock); 1191 1192 init_completion(&ispif->reset_complete); 1193 1194 return 0; 1195 } 1196 1197 /* 1198 * ispif_get_intf - Get ISPIF interface to use by VFE line id 1199 * @line_id: VFE line id that the ISPIF line is connected to 1200 * 1201 * Return ISPIF interface to use 1202 */ 1203 static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id) 1204 { 1205 switch (line_id) { 1206 case (VFE_LINE_RDI0): 1207 return RDI0; 1208 case (VFE_LINE_RDI1): 1209 return RDI1; 1210 case (VFE_LINE_RDI2): 1211 return RDI2; 1212 case (VFE_LINE_PIX): 1213 return PIX0; 1214 default: 1215 return RDI0; 1216 } 1217 } 1218 1219 /* 1220 * ispif_link_setup - Setup ISPIF connections 1221 * @entity: Pointer to media entity structure 1222 * @local: Pointer to local pad 1223 * @remote: Pointer to remote pad 1224 * @flags: Link flags 1225 * 1226 * Return 0 on success 1227 */ 1228 static int ispif_link_setup(struct media_entity *entity, 1229 const struct media_pad *local, 1230 const struct media_pad *remote, u32 flags) 1231 { 1232 if (flags & MEDIA_LNK_FL_ENABLED) { 1233 if (media_entity_remote_pad(local)) 1234 return -EBUSY; 1235 1236 if (local->flags & MEDIA_PAD_FL_SINK) { 1237 struct v4l2_subdev *sd; 1238 struct ispif_line *line; 1239 1240 sd = media_entity_to_v4l2_subdev(entity); 1241 line = v4l2_get_subdevdata(sd); 1242 1243 msm_csid_get_csid_id(remote->entity, &line->csid_id); 1244 } else { /* MEDIA_PAD_FL_SOURCE */ 1245 struct v4l2_subdev *sd; 1246 struct ispif_line *line; 1247 enum vfe_line_id id; 1248 1249 sd = media_entity_to_v4l2_subdev(entity); 1250 line = v4l2_get_subdevdata(sd); 1251 1252 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id); 1253 msm_vfe_get_vfe_line_id(remote->entity, &id); 1254 line->interface = ispif_get_intf(id); 1255 } 1256 } 1257 1258 return 0; 1259 } 1260 1261 static const struct v4l2_subdev_core_ops ispif_core_ops = { 1262 .s_power = ispif_set_power, 1263 }; 1264 1265 static const struct v4l2_subdev_video_ops ispif_video_ops = { 1266 .s_stream = ispif_set_stream, 1267 }; 1268 1269 static const struct v4l2_subdev_pad_ops ispif_pad_ops = { 1270 .enum_mbus_code = ispif_enum_mbus_code, 1271 .enum_frame_size = ispif_enum_frame_size, 1272 .get_fmt = ispif_get_format, 1273 .set_fmt = ispif_set_format, 1274 }; 1275 1276 static const struct v4l2_subdev_ops ispif_v4l2_ops = { 1277 .core = &ispif_core_ops, 1278 .video = &ispif_video_ops, 1279 .pad = &ispif_pad_ops, 1280 }; 1281 1282 static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = { 1283 .open = ispif_init_formats, 1284 }; 1285 1286 static const struct media_entity_operations ispif_media_ops = { 1287 .link_setup = ispif_link_setup, 1288 .link_validate = v4l2_subdev_link_validate, 1289 }; 1290 1291 /* 1292 * msm_ispif_register_entities - Register subdev node for ISPIF module 1293 * @ispif: ISPIF device 1294 * @v4l2_dev: V4L2 device 1295 * 1296 * Return 0 on success or a negative error code otherwise 1297 */ 1298 int msm_ispif_register_entities(struct ispif_device *ispif, 1299 struct v4l2_device *v4l2_dev) 1300 { 1301 struct device *dev = to_device(ispif); 1302 int ret; 1303 int i; 1304 1305 for (i = 0; i < ispif->line_num; i++) { 1306 struct v4l2_subdev *sd = &ispif->line[i].subdev; 1307 struct media_pad *pads = ispif->line[i].pads; 1308 1309 v4l2_subdev_init(sd, &ispif_v4l2_ops); 1310 sd->internal_ops = &ispif_v4l2_internal_ops; 1311 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1312 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", 1313 MSM_ISPIF_NAME, i); 1314 v4l2_set_subdevdata(sd, &ispif->line[i]); 1315 1316 ret = ispif_init_formats(sd, NULL); 1317 if (ret < 0) { 1318 dev_err(dev, "Failed to init format: %d\n", ret); 1319 goto error; 1320 } 1321 1322 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 1323 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 1324 1325 sd->entity.function = MEDIA_ENT_F_IO_V4L; 1326 sd->entity.ops = &ispif_media_ops; 1327 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM, 1328 pads); 1329 if (ret < 0) { 1330 dev_err(dev, "Failed to init media entity: %d\n", ret); 1331 goto error; 1332 } 1333 1334 ret = v4l2_device_register_subdev(v4l2_dev, sd); 1335 if (ret < 0) { 1336 dev_err(dev, "Failed to register subdev: %d\n", ret); 1337 media_entity_cleanup(&sd->entity); 1338 goto error; 1339 } 1340 } 1341 1342 return 0; 1343 1344 error: 1345 for (i--; i >= 0; i--) { 1346 struct v4l2_subdev *sd = &ispif->line[i].subdev; 1347 1348 v4l2_device_unregister_subdev(sd); 1349 media_entity_cleanup(&sd->entity); 1350 } 1351 1352 return ret; 1353 } 1354 1355 /* 1356 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node 1357 * @ispif: ISPIF device 1358 */ 1359 void msm_ispif_unregister_entities(struct ispif_device *ispif) 1360 { 1361 int i; 1362 1363 mutex_destroy(&ispif->power_lock); 1364 mutex_destroy(&ispif->config_lock); 1365 1366 for (i = 0; i < ispif->line_num; i++) { 1367 struct v4l2_subdev *sd = &ispif->line[i].subdev; 1368 1369 v4l2_device_unregister_subdev(sd); 1370 media_entity_cleanup(&sd->entity); 1371 } 1372 } 1373