1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-ispif.c 4 * 5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module 6 * 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/completion.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/mutex.h> 17 #include <linux/platform_device.h> 18 #include <linux/pm_runtime.h> 19 #include <media/media-entity.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-subdev.h> 22 23 #include "camss-ispif.h" 24 #include "camss.h" 25 26 #define MSM_ISPIF_NAME "msm_ispif" 27 28 #define ISPIF_RST_CMD_0 0x008 29 #define ISPIF_RST_CMD_1 0x00c 30 #define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0) 31 #define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1) 32 #define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2) 33 #define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3) 34 #define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4) 35 #define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5) 36 #define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6) 37 #define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7) 38 #define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8) 39 #define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9) 40 #define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10) 41 #define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11) 42 #define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12) 43 #define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16) 44 #define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17) 45 #define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18) 46 #define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19) 47 #define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c 48 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m)) 49 #define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6) 50 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m)) 51 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249 52 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff 53 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000 54 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000 55 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m)) 56 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249 57 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff 58 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000 59 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000 60 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m)) 61 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249 62 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff 63 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m)) 64 #define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12) 65 #define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25) 66 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m)) 67 #define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12) 68 #define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25) 69 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m)) 70 #define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12) 71 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m)) 72 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m)) 73 #define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m)) 74 #define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m)) 75 #define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m)) 76 #define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m)) 77 #define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \ 78 (0x254 + 0x200 * (m) + 0x4 * (n)) 79 #define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \ 80 (0x264 + 0x200 * (m) + 0x4 * (n)) 81 /* PACK_CFG registers are 8x96 only */ 82 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \ 83 (0x270 + 0x200 * (m) + 0x4 * (n)) 84 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \ 85 (0x27c + 0x200 * (m) + 0x4 * (n)) 86 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \ 87 (1 << ((cid % 8) * 4)) 88 #define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \ 89 (0x2c0 + 0x200 * (m) + 0x4 * (n)) 90 #define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \ 91 (0x2d0 + 0x200 * (m) + 0x4 * (n)) 92 93 #define CSI_PIX_CLK_MUX_SEL 0x000 94 #define CSI_RDI_CLK_MUX_SEL 0x008 95 96 #define ISPIF_TIMEOUT_SLEEP_US 1000 97 #define ISPIF_TIMEOUT_ALL_US 1000000 98 #define ISPIF_RESET_TIMEOUT_MS 500 99 100 enum ispif_intf_cmd { 101 CMD_DISABLE_FRAME_BOUNDARY = 0x0, 102 CMD_ENABLE_FRAME_BOUNDARY = 0x1, 103 CMD_DISABLE_IMMEDIATELY = 0x2, 104 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa, 105 CMD_ALL_NO_CHANGE = 0xffffffff, 106 }; 107 108 static const u32 ispif_formats_8x16[] = { 109 MEDIA_BUS_FMT_UYVY8_2X8, 110 MEDIA_BUS_FMT_VYUY8_2X8, 111 MEDIA_BUS_FMT_YUYV8_2X8, 112 MEDIA_BUS_FMT_YVYU8_2X8, 113 MEDIA_BUS_FMT_SBGGR8_1X8, 114 MEDIA_BUS_FMT_SGBRG8_1X8, 115 MEDIA_BUS_FMT_SGRBG8_1X8, 116 MEDIA_BUS_FMT_SRGGB8_1X8, 117 MEDIA_BUS_FMT_SBGGR10_1X10, 118 MEDIA_BUS_FMT_SGBRG10_1X10, 119 MEDIA_BUS_FMT_SGRBG10_1X10, 120 MEDIA_BUS_FMT_SRGGB10_1X10, 121 MEDIA_BUS_FMT_SBGGR12_1X12, 122 MEDIA_BUS_FMT_SGBRG12_1X12, 123 MEDIA_BUS_FMT_SGRBG12_1X12, 124 MEDIA_BUS_FMT_SRGGB12_1X12, 125 MEDIA_BUS_FMT_Y10_1X10, 126 }; 127 128 static const u32 ispif_formats_8x96[] = { 129 MEDIA_BUS_FMT_UYVY8_2X8, 130 MEDIA_BUS_FMT_VYUY8_2X8, 131 MEDIA_BUS_FMT_YUYV8_2X8, 132 MEDIA_BUS_FMT_YVYU8_2X8, 133 MEDIA_BUS_FMT_SBGGR8_1X8, 134 MEDIA_BUS_FMT_SGBRG8_1X8, 135 MEDIA_BUS_FMT_SGRBG8_1X8, 136 MEDIA_BUS_FMT_SRGGB8_1X8, 137 MEDIA_BUS_FMT_SBGGR10_1X10, 138 MEDIA_BUS_FMT_SGBRG10_1X10, 139 MEDIA_BUS_FMT_SGRBG10_1X10, 140 MEDIA_BUS_FMT_SRGGB10_1X10, 141 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE, 142 MEDIA_BUS_FMT_SBGGR12_1X12, 143 MEDIA_BUS_FMT_SGBRG12_1X12, 144 MEDIA_BUS_FMT_SGRBG12_1X12, 145 MEDIA_BUS_FMT_SRGGB12_1X12, 146 MEDIA_BUS_FMT_SBGGR14_1X14, 147 MEDIA_BUS_FMT_SGBRG14_1X14, 148 MEDIA_BUS_FMT_SGRBG14_1X14, 149 MEDIA_BUS_FMT_SRGGB14_1X14, 150 MEDIA_BUS_FMT_Y10_1X10, 151 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE, 152 }; 153 154 /* 155 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96 156 * @irq: Interrupt line 157 * @dev: ISPIF device 158 * 159 * Return IRQ_HANDLED on success 160 */ 161 static irqreturn_t ispif_isr_8x96(int irq, void *dev) 162 { 163 struct ispif_device *ispif = dev; 164 u32 value0, value1, value2, value3, value4, value5; 165 166 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); 167 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0)); 168 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); 169 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1)); 170 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1)); 171 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1)); 172 173 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); 174 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0)); 175 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); 176 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1)); 177 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1)); 178 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1)); 179 180 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); 181 182 if ((value0 >> 27) & 0x1) 183 complete(&ispif->reset_complete[0]); 184 185 if ((value3 >> 27) & 0x1) 186 complete(&ispif->reset_complete[1]); 187 188 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) 189 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n"); 190 191 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) 192 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n"); 193 194 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW)) 195 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n"); 196 197 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW)) 198 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n"); 199 200 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) 201 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n"); 202 203 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) 204 dev_err_ratelimited(to_device(ispif), "VFE1 pix0 overflow\n"); 205 206 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) 207 dev_err_ratelimited(to_device(ispif), "VFE1 rdi0 overflow\n"); 208 209 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW)) 210 dev_err_ratelimited(to_device(ispif), "VFE1 pix1 overflow\n"); 211 212 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW)) 213 dev_err_ratelimited(to_device(ispif), "VFE1 rdi1 overflow\n"); 214 215 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) 216 dev_err_ratelimited(to_device(ispif), "VFE1 rdi2 overflow\n"); 217 218 return IRQ_HANDLED; 219 } 220 221 /* 222 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16 223 * @irq: Interrupt line 224 * @dev: ISPIF device 225 * 226 * Return IRQ_HANDLED on success 227 */ 228 static irqreturn_t ispif_isr_8x16(int irq, void *dev) 229 { 230 struct ispif_device *ispif = dev; 231 u32 value0, value1, value2; 232 233 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0)); 234 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0)); 235 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0)); 236 237 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0)); 238 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0)); 239 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0)); 240 241 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); 242 243 if ((value0 >> 27) & 0x1) 244 complete(&ispif->reset_complete[0]); 245 246 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW)) 247 dev_err_ratelimited(to_device(ispif), "VFE0 pix0 overflow\n"); 248 249 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW)) 250 dev_err_ratelimited(to_device(ispif), "VFE0 rdi0 overflow\n"); 251 252 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW)) 253 dev_err_ratelimited(to_device(ispif), "VFE0 pix1 overflow\n"); 254 255 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW)) 256 dev_err_ratelimited(to_device(ispif), "VFE0 rdi1 overflow\n"); 257 258 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW)) 259 dev_err_ratelimited(to_device(ispif), "VFE0 rdi2 overflow\n"); 260 261 return IRQ_HANDLED; 262 } 263 264 static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id) 265 { 266 unsigned long time; 267 u32 val; 268 269 if (vfe_id > (to_camss(ispif)->vfe_num - 1)) { 270 dev_err(to_device(ispif), 271 "Error: asked reset for invalid VFE%d\n", vfe_id); 272 return -ENOENT; 273 } 274 275 reinit_completion(&ispif->reset_complete[vfe_id]); 276 277 val = ISPIF_RST_CMD_0_STROBED_RST_EN | 278 ISPIF_RST_CMD_0_MISC_LOGIC_RST | 279 ISPIF_RST_CMD_0_SW_REG_RST | 280 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST | 281 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST | 282 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST | 283 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST | 284 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST | 285 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST | 286 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST | 287 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST | 288 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST | 289 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST | 290 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST | 291 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST | 292 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST | 293 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST; 294 295 if (vfe_id == 1) 296 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1); 297 else 298 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0); 299 300 time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id], 301 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS)); 302 if (!time) { 303 dev_err(to_device(ispif), 304 "ISPIF for VFE%d reset timeout\n", vfe_id); 305 return -EIO; 306 } 307 308 return 0; 309 } 310 311 /* 312 * ispif_reset - Trigger reset on ISPIF module and wait to complete 313 * @ispif: ISPIF device 314 * 315 * Return 0 on success or a negative error code otherwise 316 */ 317 static int ispif_reset(struct ispif_device *ispif, u8 vfe_id) 318 { 319 int ret; 320 321 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE0); 322 if (ret < 0) 323 return ret; 324 325 ret = camss_pm_domain_on(to_camss(ispif), PM_DOMAIN_VFE1); 326 if (ret < 0) 327 return ret; 328 329 ret = camss_enable_clocks(ispif->nclocks_for_reset, 330 ispif->clock_for_reset, 331 to_device(ispif)); 332 if (ret < 0) 333 return ret; 334 335 ret = ispif_vfe_reset(ispif, vfe_id); 336 if (ret) 337 dev_dbg(to_device(ispif), "ISPIF Reset failed\n"); 338 339 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset); 340 341 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE0); 342 camss_pm_domain_off(to_camss(ispif), PM_DOMAIN_VFE1); 343 344 return ret; 345 } 346 347 /* 348 * ispif_set_power - Power on/off ISPIF module 349 * @sd: ISPIF V4L2 subdevice 350 * @on: Requested power state 351 * 352 * Return 0 on success or a negative error code otherwise 353 */ 354 static int ispif_set_power(struct v4l2_subdev *sd, int on) 355 { 356 struct ispif_line *line = v4l2_get_subdevdata(sd); 357 struct ispif_device *ispif = line->ispif; 358 struct device *dev = to_device(ispif); 359 int ret = 0; 360 361 mutex_lock(&ispif->power_lock); 362 363 if (on) { 364 if (ispif->power_count) { 365 /* Power is already on */ 366 ispif->power_count++; 367 goto exit; 368 } 369 370 ret = pm_runtime_get_sync(dev); 371 if (ret < 0) { 372 pm_runtime_put_sync(dev); 373 goto exit; 374 } 375 376 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev); 377 if (ret < 0) { 378 pm_runtime_put_sync(dev); 379 goto exit; 380 } 381 382 ret = ispif_reset(ispif, line->vfe_id); 383 if (ret < 0) { 384 pm_runtime_put_sync(dev); 385 camss_disable_clocks(ispif->nclocks, ispif->clock); 386 goto exit; 387 } 388 389 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE; 390 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE; 391 392 ispif->power_count++; 393 } else { 394 if (ispif->power_count == 0) { 395 dev_err(dev, "ispif power off on power_count == 0\n"); 396 goto exit; 397 } else if (ispif->power_count == 1) { 398 camss_disable_clocks(ispif->nclocks, ispif->clock); 399 pm_runtime_put_sync(dev); 400 } 401 402 ispif->power_count--; 403 } 404 405 exit: 406 mutex_unlock(&ispif->power_lock); 407 408 return ret; 409 } 410 411 /* 412 * ispif_select_clk_mux - Select clock for PIX/RDI interface 413 * @ispif: ISPIF device 414 * @intf: VFE interface 415 * @csid: CSID HW module id 416 * @vfe: VFE HW module id 417 * @enable: enable or disable the selected clock 418 */ 419 static void ispif_select_clk_mux(struct ispif_device *ispif, 420 enum ispif_intf intf, u8 csid, 421 u8 vfe, u8 enable) 422 { 423 u32 val; 424 425 switch (intf) { 426 case PIX0: 427 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 428 val &= ~(0xf << (vfe * 8)); 429 if (enable) 430 val |= (csid << (vfe * 8)); 431 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 432 break; 433 434 case RDI0: 435 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 436 val &= ~(0xf << (vfe * 12)); 437 if (enable) 438 val |= (csid << (vfe * 12)); 439 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 440 break; 441 442 case PIX1: 443 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 444 val &= ~(0xf << (4 + (vfe * 8))); 445 if (enable) 446 val |= (csid << (4 + (vfe * 8))); 447 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL); 448 break; 449 450 case RDI1: 451 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 452 val &= ~(0xf << (4 + (vfe * 12))); 453 if (enable) 454 val |= (csid << (4 + (vfe * 12))); 455 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 456 break; 457 458 case RDI2: 459 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 460 val &= ~(0xf << (8 + (vfe * 12))); 461 if (enable) 462 val |= (csid << (8 + (vfe * 12))); 463 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL); 464 break; 465 } 466 467 mb(); 468 } 469 470 /* 471 * ispif_validate_intf_status - Validate current status of PIX/RDI interface 472 * @ispif: ISPIF device 473 * @intf: VFE interface 474 * @vfe: VFE HW module id 475 * 476 * Return 0 when interface is idle or -EBUSY otherwise 477 */ 478 static int ispif_validate_intf_status(struct ispif_device *ispif, 479 enum ispif_intf intf, u8 vfe) 480 { 481 int ret = 0; 482 u32 val = 0; 483 484 switch (intf) { 485 case PIX0: 486 val = readl_relaxed(ispif->base + 487 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0)); 488 break; 489 case RDI0: 490 val = readl_relaxed(ispif->base + 491 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0)); 492 break; 493 case PIX1: 494 val = readl_relaxed(ispif->base + 495 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1)); 496 break; 497 case RDI1: 498 val = readl_relaxed(ispif->base + 499 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1)); 500 break; 501 case RDI2: 502 val = readl_relaxed(ispif->base + 503 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2)); 504 break; 505 } 506 507 if ((val & 0xf) != 0xf) { 508 dev_err(to_device(ispif), "%s: ispif is busy: 0x%x\n", 509 __func__, val); 510 ret = -EBUSY; 511 } 512 513 return ret; 514 } 515 516 /* 517 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop 518 * @ispif: ISPIF device 519 * @intf: VFE interface 520 * @vfe: VFE HW module id 521 * 522 * Return 0 on success or a negative error code otherwise 523 */ 524 static int ispif_wait_for_stop(struct ispif_device *ispif, 525 enum ispif_intf intf, u8 vfe) 526 { 527 u32 addr = 0; 528 u32 stop_flag = 0; 529 int ret; 530 531 switch (intf) { 532 case PIX0: 533 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0); 534 break; 535 case RDI0: 536 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0); 537 break; 538 case PIX1: 539 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1); 540 break; 541 case RDI1: 542 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1); 543 break; 544 case RDI2: 545 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2); 546 break; 547 } 548 549 ret = readl_poll_timeout(ispif->base + addr, 550 stop_flag, 551 (stop_flag & 0xf) == 0xf, 552 ISPIF_TIMEOUT_SLEEP_US, 553 ISPIF_TIMEOUT_ALL_US); 554 if (ret < 0) 555 dev_err(to_device(ispif), "%s: ispif stop timeout\n", 556 __func__); 557 558 return ret; 559 } 560 561 /* 562 * ispif_select_csid - Select CSID HW module for input from 563 * @ispif: ISPIF device 564 * @intf: VFE interface 565 * @csid: CSID HW module id 566 * @vfe: VFE HW module id 567 * @enable: enable or disable the selected input 568 */ 569 static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf, 570 u8 csid, u8 vfe, u8 enable) 571 { 572 u32 val; 573 574 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); 575 switch (intf) { 576 case PIX0: 577 val &= ~(BIT(1) | BIT(0)); 578 if (enable) 579 val |= csid; 580 break; 581 case RDI0: 582 val &= ~(BIT(5) | BIT(4)); 583 if (enable) 584 val |= (csid << 4); 585 break; 586 case PIX1: 587 val &= ~(BIT(9) | BIT(8)); 588 if (enable) 589 val |= (csid << 8); 590 break; 591 case RDI1: 592 val &= ~(BIT(13) | BIT(12)); 593 if (enable) 594 val |= (csid << 12); 595 break; 596 case RDI2: 597 val &= ~(BIT(21) | BIT(20)); 598 if (enable) 599 val |= (csid << 20); 600 break; 601 } 602 603 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe)); 604 } 605 606 /* 607 * ispif_select_cid - Enable/disable desired CID 608 * @ispif: ISPIF device 609 * @intf: VFE interface 610 * @cid: desired CID to enable/disable 611 * @vfe: VFE HW module id 612 * @enable: enable or disable the desired CID 613 */ 614 static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf, 615 u8 cid, u8 vfe, u8 enable) 616 { 617 u32 cid_mask = 1 << cid; 618 u32 addr = 0; 619 u32 val; 620 621 switch (intf) { 622 case PIX0: 623 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0); 624 break; 625 case RDI0: 626 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0); 627 break; 628 case PIX1: 629 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1); 630 break; 631 case RDI1: 632 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1); 633 break; 634 case RDI2: 635 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2); 636 break; 637 } 638 639 val = readl_relaxed(ispif->base + addr); 640 if (enable) 641 val |= cid_mask; 642 else 643 val &= ~cid_mask; 644 645 writel(val, ispif->base + addr); 646 } 647 648 /* 649 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface 650 * @ispif: ISPIF device 651 * @intf: VFE interface 652 * @vfe: VFE HW module id 653 * @enable: enable or disable 654 */ 655 static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf, 656 u8 vfe, u8 enable) 657 { 658 u32 val; 659 660 switch (intf) { 661 case PIX0: 662 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 663 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK; 664 if (enable) 665 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE; 666 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 667 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE, 668 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); 669 break; 670 case RDI0: 671 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 672 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK; 673 if (enable) 674 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE; 675 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe)); 676 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE, 677 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe)); 678 break; 679 case PIX1: 680 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 681 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK; 682 if (enable) 683 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE; 684 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 685 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE, 686 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); 687 break; 688 case RDI1: 689 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 690 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK; 691 if (enable) 692 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE; 693 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe)); 694 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE, 695 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe)); 696 break; 697 case RDI2: 698 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); 699 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK; 700 if (enable) 701 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE; 702 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe)); 703 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE, 704 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe)); 705 break; 706 } 707 708 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD); 709 } 710 711 /* 712 * ispif_config_pack - Config packing for PRDI mode 713 * @ispif: ISPIF device 714 * @code: media bus format code 715 * @intf: VFE interface 716 * @cid: desired CID to handle 717 * @vfe: VFE HW module id 718 * @enable: enable or disable 719 */ 720 static void ispif_config_pack(struct ispif_device *ispif, u32 code, 721 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable) 722 { 723 u32 addr, val; 724 725 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE && 726 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE) 727 return; 728 729 switch (intf) { 730 case RDI0: 731 if (cid < 8) 732 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0); 733 else 734 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0); 735 break; 736 case RDI1: 737 if (cid < 8) 738 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1); 739 else 740 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1); 741 break; 742 case RDI2: 743 if (cid < 8) 744 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2); 745 else 746 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2); 747 break; 748 default: 749 return; 750 } 751 752 if (enable) 753 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid); 754 else 755 val = 0; 756 757 writel_relaxed(val, ispif->base + addr); 758 } 759 760 /* 761 * ispif_set_intf_cmd - Set command to enable/disable interface 762 * @ispif: ISPIF device 763 * @cmd: interface command 764 * @intf: VFE interface 765 * @vfe: VFE HW module id 766 * @vc: virtual channel 767 */ 768 static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd, 769 enum ispif_intf intf, u8 vfe, u8 vc) 770 { 771 u32 *val; 772 773 if (intf == RDI2) { 774 val = &ispif->intf_cmd[vfe].cmd_1; 775 *val &= ~(0x3 << (vc * 2 + 8)); 776 *val |= (cmd << (vc * 2 + 8)); 777 wmb(); 778 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe)); 779 wmb(); 780 } else { 781 val = &ispif->intf_cmd[vfe].cmd_0; 782 *val &= ~(0x3 << (vc * 2 + intf * 8)); 783 *val |= (cmd << (vc * 2 + intf * 8)); 784 wmb(); 785 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe)); 786 wmb(); 787 } 788 } 789 790 /* 791 * ispif_set_stream - Enable/disable streaming on ISPIF module 792 * @sd: ISPIF V4L2 subdevice 793 * @enable: Requested streaming state 794 * 795 * Main configuration of ISPIF module is also done here. 796 * 797 * Return 0 on success or a negative error code otherwise 798 */ 799 static int ispif_set_stream(struct v4l2_subdev *sd, int enable) 800 { 801 struct ispif_line *line = v4l2_get_subdevdata(sd); 802 struct ispif_device *ispif = line->ispif; 803 enum ispif_intf intf = line->interface; 804 u8 csid = line->csid_id; 805 u8 vfe = line->vfe_id; 806 u8 vc = 0; /* Virtual Channel 0 */ 807 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */ 808 int ret; 809 810 if (enable) { 811 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK])) 812 return -ENOLINK; 813 814 /* Config */ 815 816 mutex_lock(&ispif->config_lock); 817 ispif_select_clk_mux(ispif, intf, csid, vfe, 1); 818 819 ret = ispif_validate_intf_status(ispif, intf, vfe); 820 if (ret < 0) { 821 mutex_unlock(&ispif->config_lock); 822 return ret; 823 } 824 825 ispif_select_csid(ispif, intf, csid, vfe, 1); 826 ispif_select_cid(ispif, intf, cid, vfe, 1); 827 ispif_config_irq(ispif, intf, vfe, 1); 828 if (to_camss(ispif)->version == CAMSS_8x96 || 829 to_camss(ispif)->version == CAMSS_660) 830 ispif_config_pack(ispif, 831 line->fmt[MSM_ISPIF_PAD_SINK].code, 832 intf, cid, vfe, 1); 833 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY, 834 intf, vfe, vc); 835 } else { 836 mutex_lock(&ispif->config_lock); 837 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY, 838 intf, vfe, vc); 839 mutex_unlock(&ispif->config_lock); 840 841 ret = ispif_wait_for_stop(ispif, intf, vfe); 842 if (ret < 0) 843 return ret; 844 845 mutex_lock(&ispif->config_lock); 846 if (to_camss(ispif)->version == CAMSS_8x96 || 847 to_camss(ispif)->version == CAMSS_660) 848 ispif_config_pack(ispif, 849 line->fmt[MSM_ISPIF_PAD_SINK].code, 850 intf, cid, vfe, 0); 851 ispif_config_irq(ispif, intf, vfe, 0); 852 ispif_select_cid(ispif, intf, cid, vfe, 0); 853 ispif_select_csid(ispif, intf, csid, vfe, 0); 854 ispif_select_clk_mux(ispif, intf, csid, vfe, 0); 855 } 856 857 mutex_unlock(&ispif->config_lock); 858 859 return 0; 860 } 861 862 /* 863 * __ispif_get_format - Get pointer to format structure 864 * @ispif: ISPIF line 865 * @cfg: V4L2 subdev pad configuration 866 * @pad: pad from which format is requested 867 * @which: TRY or ACTIVE format 868 * 869 * Return pointer to TRY or ACTIVE format structure 870 */ 871 static struct v4l2_mbus_framefmt * 872 __ispif_get_format(struct ispif_line *line, 873 struct v4l2_subdev_pad_config *cfg, 874 unsigned int pad, 875 enum v4l2_subdev_format_whence which) 876 { 877 if (which == V4L2_SUBDEV_FORMAT_TRY) 878 return v4l2_subdev_get_try_format(&line->subdev, cfg, pad); 879 880 return &line->fmt[pad]; 881 } 882 883 /* 884 * ispif_try_format - Handle try format by pad subdev method 885 * @ispif: ISPIF line 886 * @cfg: V4L2 subdev pad configuration 887 * @pad: pad on which format is requested 888 * @fmt: pointer to v4l2 format structure 889 * @which: wanted subdev format 890 */ 891 static void ispif_try_format(struct ispif_line *line, 892 struct v4l2_subdev_pad_config *cfg, 893 unsigned int pad, 894 struct v4l2_mbus_framefmt *fmt, 895 enum v4l2_subdev_format_whence which) 896 { 897 unsigned int i; 898 899 switch (pad) { 900 case MSM_ISPIF_PAD_SINK: 901 /* Set format on sink pad */ 902 903 for (i = 0; i < line->nformats; i++) 904 if (fmt->code == line->formats[i]) 905 break; 906 907 /* If not found, use UYVY as default */ 908 if (i >= line->nformats) 909 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 910 911 fmt->width = clamp_t(u32, fmt->width, 1, 8191); 912 fmt->height = clamp_t(u32, fmt->height, 1, 8191); 913 914 fmt->field = V4L2_FIELD_NONE; 915 fmt->colorspace = V4L2_COLORSPACE_SRGB; 916 917 break; 918 919 case MSM_ISPIF_PAD_SRC: 920 /* Set and return a format same as sink pad */ 921 922 *fmt = *__ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK, 923 which); 924 925 break; 926 } 927 928 fmt->colorspace = V4L2_COLORSPACE_SRGB; 929 } 930 931 /* 932 * ispif_enum_mbus_code - Handle pixel format enumeration 933 * @sd: ISPIF V4L2 subdevice 934 * @cfg: V4L2 subdev pad configuration 935 * @code: pointer to v4l2_subdev_mbus_code_enum structure 936 * return -EINVAL or zero on success 937 */ 938 static int ispif_enum_mbus_code(struct v4l2_subdev *sd, 939 struct v4l2_subdev_pad_config *cfg, 940 struct v4l2_subdev_mbus_code_enum *code) 941 { 942 struct ispif_line *line = v4l2_get_subdevdata(sd); 943 struct v4l2_mbus_framefmt *format; 944 945 if (code->pad == MSM_ISPIF_PAD_SINK) { 946 if (code->index >= line->nformats) 947 return -EINVAL; 948 949 code->code = line->formats[code->index]; 950 } else { 951 if (code->index > 0) 952 return -EINVAL; 953 954 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SINK, 955 code->which); 956 957 code->code = format->code; 958 } 959 960 return 0; 961 } 962 963 /* 964 * ispif_enum_frame_size - Handle frame size enumeration 965 * @sd: ISPIF V4L2 subdevice 966 * @cfg: V4L2 subdev pad configuration 967 * @fse: pointer to v4l2_subdev_frame_size_enum structure 968 * return -EINVAL or zero on success 969 */ 970 static int ispif_enum_frame_size(struct v4l2_subdev *sd, 971 struct v4l2_subdev_pad_config *cfg, 972 struct v4l2_subdev_frame_size_enum *fse) 973 { 974 struct ispif_line *line = v4l2_get_subdevdata(sd); 975 struct v4l2_mbus_framefmt format; 976 977 if (fse->index != 0) 978 return -EINVAL; 979 980 format.code = fse->code; 981 format.width = 1; 982 format.height = 1; 983 ispif_try_format(line, cfg, fse->pad, &format, fse->which); 984 fse->min_width = format.width; 985 fse->min_height = format.height; 986 987 if (format.code != fse->code) 988 return -EINVAL; 989 990 format.code = fse->code; 991 format.width = -1; 992 format.height = -1; 993 ispif_try_format(line, cfg, fse->pad, &format, fse->which); 994 fse->max_width = format.width; 995 fse->max_height = format.height; 996 997 return 0; 998 } 999 1000 /* 1001 * ispif_get_format - Handle get format by pads subdev method 1002 * @sd: ISPIF V4L2 subdevice 1003 * @cfg: V4L2 subdev pad configuration 1004 * @fmt: pointer to v4l2 subdev format structure 1005 * 1006 * Return -EINVAL or zero on success 1007 */ 1008 static int ispif_get_format(struct v4l2_subdev *sd, 1009 struct v4l2_subdev_pad_config *cfg, 1010 struct v4l2_subdev_format *fmt) 1011 { 1012 struct ispif_line *line = v4l2_get_subdevdata(sd); 1013 struct v4l2_mbus_framefmt *format; 1014 1015 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which); 1016 if (format == NULL) 1017 return -EINVAL; 1018 1019 fmt->format = *format; 1020 1021 return 0; 1022 } 1023 1024 /* 1025 * ispif_set_format - Handle set format by pads subdev method 1026 * @sd: ISPIF V4L2 subdevice 1027 * @cfg: V4L2 subdev pad configuration 1028 * @fmt: pointer to v4l2 subdev format structure 1029 * 1030 * Return -EINVAL or zero on success 1031 */ 1032 static int ispif_set_format(struct v4l2_subdev *sd, 1033 struct v4l2_subdev_pad_config *cfg, 1034 struct v4l2_subdev_format *fmt) 1035 { 1036 struct ispif_line *line = v4l2_get_subdevdata(sd); 1037 struct v4l2_mbus_framefmt *format; 1038 1039 format = __ispif_get_format(line, cfg, fmt->pad, fmt->which); 1040 if (format == NULL) 1041 return -EINVAL; 1042 1043 ispif_try_format(line, cfg, fmt->pad, &fmt->format, fmt->which); 1044 *format = fmt->format; 1045 1046 /* Propagate the format from sink to source */ 1047 if (fmt->pad == MSM_ISPIF_PAD_SINK) { 1048 format = __ispif_get_format(line, cfg, MSM_ISPIF_PAD_SRC, 1049 fmt->which); 1050 1051 *format = fmt->format; 1052 ispif_try_format(line, cfg, MSM_ISPIF_PAD_SRC, format, 1053 fmt->which); 1054 } 1055 1056 return 0; 1057 } 1058 1059 /* 1060 * ispif_init_formats - Initialize formats on all pads 1061 * @sd: ISPIF V4L2 subdevice 1062 * @fh: V4L2 subdev file handle 1063 * 1064 * Initialize all pad formats with default values. 1065 * 1066 * Return 0 on success or a negative error code otherwise 1067 */ 1068 static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) 1069 { 1070 struct v4l2_subdev_format format = { 1071 .pad = MSM_ISPIF_PAD_SINK, 1072 .which = fh ? V4L2_SUBDEV_FORMAT_TRY : 1073 V4L2_SUBDEV_FORMAT_ACTIVE, 1074 .format = { 1075 .code = MEDIA_BUS_FMT_UYVY8_2X8, 1076 .width = 1920, 1077 .height = 1080 1078 } 1079 }; 1080 1081 return ispif_set_format(sd, fh ? fh->pad : NULL, &format); 1082 } 1083 1084 /* 1085 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources 1086 * @ispif: ISPIF device 1087 * @res: ISPIF module resources table 1088 * 1089 * Return 0 on success or a negative error code otherwise 1090 */ 1091 int msm_ispif_subdev_init(struct ispif_device *ispif, 1092 const struct resources_ispif *res) 1093 { 1094 struct device *dev = to_device(ispif); 1095 struct platform_device *pdev = to_platform_device(dev); 1096 struct resource *r; 1097 int i; 1098 int ret; 1099 1100 /* Number of ISPIF lines - same as number of CSID hardware modules */ 1101 if (to_camss(ispif)->version == CAMSS_8x16) 1102 ispif->line_num = 2; 1103 else if (to_camss(ispif)->version == CAMSS_8x96 || 1104 to_camss(ispif)->version == CAMSS_660) 1105 ispif->line_num = 4; 1106 else 1107 return -EINVAL; 1108 1109 ispif->line = devm_kcalloc(dev, ispif->line_num, sizeof(*ispif->line), 1110 GFP_KERNEL); 1111 if (!ispif->line) 1112 return -ENOMEM; 1113 1114 for (i = 0; i < ispif->line_num; i++) { 1115 ispif->line[i].ispif = ispif; 1116 ispif->line[i].id = i; 1117 1118 if (to_camss(ispif)->version == CAMSS_8x16) { 1119 ispif->line[i].formats = ispif_formats_8x16; 1120 ispif->line[i].nformats = 1121 ARRAY_SIZE(ispif_formats_8x16); 1122 } else if (to_camss(ispif)->version == CAMSS_8x96 || 1123 to_camss(ispif)->version == CAMSS_660) { 1124 ispif->line[i].formats = ispif_formats_8x96; 1125 ispif->line[i].nformats = 1126 ARRAY_SIZE(ispif_formats_8x96); 1127 } else { 1128 return -EINVAL; 1129 } 1130 } 1131 1132 /* Memory */ 1133 1134 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]); 1135 ispif->base = devm_ioremap_resource(dev, r); 1136 if (IS_ERR(ispif->base)) { 1137 dev_err(dev, "could not map memory\n"); 1138 return PTR_ERR(ispif->base); 1139 } 1140 1141 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]); 1142 ispif->base_clk_mux = devm_ioremap_resource(dev, r); 1143 if (IS_ERR(ispif->base_clk_mux)) { 1144 dev_err(dev, "could not map memory\n"); 1145 return PTR_ERR(ispif->base_clk_mux); 1146 } 1147 1148 /* Interrupt */ 1149 1150 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt); 1151 1152 if (!r) { 1153 dev_err(dev, "missing IRQ\n"); 1154 return -EINVAL; 1155 } 1156 1157 ispif->irq = r->start; 1158 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s", 1159 dev_name(dev), MSM_ISPIF_NAME); 1160 if (to_camss(ispif)->version == CAMSS_8x16) 1161 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16, 1162 IRQF_TRIGGER_RISING, ispif->irq_name, ispif); 1163 else if (to_camss(ispif)->version == CAMSS_8x96 || 1164 to_camss(ispif)->version == CAMSS_660) 1165 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96, 1166 IRQF_TRIGGER_RISING, ispif->irq_name, ispif); 1167 else 1168 ret = -EINVAL; 1169 if (ret < 0) { 1170 dev_err(dev, "request_irq failed: %d\n", ret); 1171 return ret; 1172 } 1173 1174 /* Clocks */ 1175 1176 ispif->nclocks = 0; 1177 while (res->clock[ispif->nclocks]) 1178 ispif->nclocks++; 1179 1180 ispif->clock = devm_kcalloc(dev, 1181 ispif->nclocks, sizeof(*ispif->clock), 1182 GFP_KERNEL); 1183 if (!ispif->clock) 1184 return -ENOMEM; 1185 1186 for (i = 0; i < ispif->nclocks; i++) { 1187 struct camss_clock *clock = &ispif->clock[i]; 1188 1189 clock->clk = devm_clk_get(dev, res->clock[i]); 1190 if (IS_ERR(clock->clk)) 1191 return PTR_ERR(clock->clk); 1192 1193 clock->freq = NULL; 1194 clock->nfreqs = 0; 1195 } 1196 1197 ispif->nclocks_for_reset = 0; 1198 while (res->clock_for_reset[ispif->nclocks_for_reset]) 1199 ispif->nclocks_for_reset++; 1200 1201 ispif->clock_for_reset = devm_kcalloc(dev, 1202 ispif->nclocks_for_reset, 1203 sizeof(*ispif->clock_for_reset), 1204 GFP_KERNEL); 1205 if (!ispif->clock_for_reset) 1206 return -ENOMEM; 1207 1208 for (i = 0; i < ispif->nclocks_for_reset; i++) { 1209 struct camss_clock *clock = &ispif->clock_for_reset[i]; 1210 1211 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]); 1212 if (IS_ERR(clock->clk)) 1213 return PTR_ERR(clock->clk); 1214 1215 clock->freq = NULL; 1216 clock->nfreqs = 0; 1217 } 1218 1219 mutex_init(&ispif->power_lock); 1220 ispif->power_count = 0; 1221 1222 mutex_init(&ispif->config_lock); 1223 1224 for (i = 0; i < MSM_ISPIF_VFE_NUM; i++) 1225 init_completion(&ispif->reset_complete[i]); 1226 1227 return 0; 1228 } 1229 1230 /* 1231 * ispif_get_intf - Get ISPIF interface to use by VFE line id 1232 * @line_id: VFE line id that the ISPIF line is connected to 1233 * 1234 * Return ISPIF interface to use 1235 */ 1236 static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id) 1237 { 1238 switch (line_id) { 1239 case (VFE_LINE_RDI0): 1240 return RDI0; 1241 case (VFE_LINE_RDI1): 1242 return RDI1; 1243 case (VFE_LINE_RDI2): 1244 return RDI2; 1245 case (VFE_LINE_PIX): 1246 return PIX0; 1247 default: 1248 return RDI0; 1249 } 1250 } 1251 1252 /* 1253 * ispif_link_setup - Setup ISPIF connections 1254 * @entity: Pointer to media entity structure 1255 * @local: Pointer to local pad 1256 * @remote: Pointer to remote pad 1257 * @flags: Link flags 1258 * 1259 * Return 0 on success 1260 */ 1261 static int ispif_link_setup(struct media_entity *entity, 1262 const struct media_pad *local, 1263 const struct media_pad *remote, u32 flags) 1264 { 1265 if (flags & MEDIA_LNK_FL_ENABLED) { 1266 if (media_entity_remote_pad(local)) 1267 return -EBUSY; 1268 1269 if (local->flags & MEDIA_PAD_FL_SINK) { 1270 struct v4l2_subdev *sd; 1271 struct ispif_line *line; 1272 1273 sd = media_entity_to_v4l2_subdev(entity); 1274 line = v4l2_get_subdevdata(sd); 1275 1276 msm_csid_get_csid_id(remote->entity, &line->csid_id); 1277 } else { /* MEDIA_PAD_FL_SOURCE */ 1278 struct v4l2_subdev *sd; 1279 struct ispif_line *line; 1280 enum vfe_line_id id; 1281 1282 sd = media_entity_to_v4l2_subdev(entity); 1283 line = v4l2_get_subdevdata(sd); 1284 1285 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id); 1286 msm_vfe_get_vfe_line_id(remote->entity, &id); 1287 line->interface = ispif_get_intf(id); 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 1294 static const struct v4l2_subdev_core_ops ispif_core_ops = { 1295 .s_power = ispif_set_power, 1296 }; 1297 1298 static const struct v4l2_subdev_video_ops ispif_video_ops = { 1299 .s_stream = ispif_set_stream, 1300 }; 1301 1302 static const struct v4l2_subdev_pad_ops ispif_pad_ops = { 1303 .enum_mbus_code = ispif_enum_mbus_code, 1304 .enum_frame_size = ispif_enum_frame_size, 1305 .get_fmt = ispif_get_format, 1306 .set_fmt = ispif_set_format, 1307 }; 1308 1309 static const struct v4l2_subdev_ops ispif_v4l2_ops = { 1310 .core = &ispif_core_ops, 1311 .video = &ispif_video_ops, 1312 .pad = &ispif_pad_ops, 1313 }; 1314 1315 static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = { 1316 .open = ispif_init_formats, 1317 }; 1318 1319 static const struct media_entity_operations ispif_media_ops = { 1320 .link_setup = ispif_link_setup, 1321 .link_validate = v4l2_subdev_link_validate, 1322 }; 1323 1324 /* 1325 * msm_ispif_register_entities - Register subdev node for ISPIF module 1326 * @ispif: ISPIF device 1327 * @v4l2_dev: V4L2 device 1328 * 1329 * Return 0 on success or a negative error code otherwise 1330 */ 1331 int msm_ispif_register_entities(struct ispif_device *ispif, 1332 struct v4l2_device *v4l2_dev) 1333 { 1334 struct device *dev = to_device(ispif); 1335 int ret; 1336 int i; 1337 1338 for (i = 0; i < ispif->line_num; i++) { 1339 struct v4l2_subdev *sd = &ispif->line[i].subdev; 1340 struct media_pad *pads = ispif->line[i].pads; 1341 1342 v4l2_subdev_init(sd, &ispif_v4l2_ops); 1343 sd->internal_ops = &ispif_v4l2_internal_ops; 1344 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1345 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", 1346 MSM_ISPIF_NAME, i); 1347 v4l2_set_subdevdata(sd, &ispif->line[i]); 1348 1349 ret = ispif_init_formats(sd, NULL); 1350 if (ret < 0) { 1351 dev_err(dev, "Failed to init format: %d\n", ret); 1352 goto error; 1353 } 1354 1355 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 1356 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 1357 1358 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 1359 sd->entity.ops = &ispif_media_ops; 1360 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM, 1361 pads); 1362 if (ret < 0) { 1363 dev_err(dev, "Failed to init media entity: %d\n", ret); 1364 goto error; 1365 } 1366 1367 ret = v4l2_device_register_subdev(v4l2_dev, sd); 1368 if (ret < 0) { 1369 dev_err(dev, "Failed to register subdev: %d\n", ret); 1370 media_entity_cleanup(&sd->entity); 1371 goto error; 1372 } 1373 } 1374 1375 return 0; 1376 1377 error: 1378 for (i--; i >= 0; i--) { 1379 struct v4l2_subdev *sd = &ispif->line[i].subdev; 1380 1381 v4l2_device_unregister_subdev(sd); 1382 media_entity_cleanup(&sd->entity); 1383 } 1384 1385 return ret; 1386 } 1387 1388 /* 1389 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node 1390 * @ispif: ISPIF device 1391 */ 1392 void msm_ispif_unregister_entities(struct ispif_device *ispif) 1393 { 1394 int i; 1395 1396 mutex_destroy(&ispif->power_lock); 1397 mutex_destroy(&ispif->config_lock); 1398 1399 for (i = 0; i < ispif->line_num; i++) { 1400 struct v4l2_subdev *sd = &ispif->line[i].subdev; 1401 1402 v4l2_device_unregister_subdev(sd); 1403 media_entity_cleanup(&sd->entity); 1404 } 1405 } 1406