1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <media/media-entity.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-subdev.h> 21 22 #include "camss-csiphy.h" 23 #include "camss.h" 24 25 #define MSM_CSIPHY_NAME "msm_csiphy" 26 27 struct csiphy_format { 28 u32 code; 29 u8 bpp; 30 }; 31 32 static const struct csiphy_format csiphy_formats_8x16[] = { 33 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 34 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 35 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 36 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 37 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 38 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 39 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 40 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 41 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 42 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 43 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 44 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 45 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 46 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 47 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 48 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 49 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 50 }; 51 52 static const struct csiphy_format csiphy_formats_8x96[] = { 53 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 54 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 55 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 56 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 57 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 58 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 59 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 60 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 61 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 62 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 63 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 64 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 65 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 66 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 67 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 68 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 69 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 70 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 71 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 72 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 73 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 74 }; 75 76 static const struct csiphy_format csiphy_formats_sdm845[] = { 77 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 78 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 79 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 80 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 81 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 82 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 83 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 84 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 85 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 86 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 87 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 88 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 89 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 90 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 91 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 92 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 93 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 94 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 95 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 96 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 97 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 98 }; 99 100 /* 101 * csiphy_get_bpp - map media bus format to bits per pixel 102 * @formats: supported media bus formats array 103 * @nformats: size of @formats array 104 * @code: media bus format code 105 * 106 * Return number of bits per pixel 107 */ 108 static u8 csiphy_get_bpp(const struct csiphy_format *formats, 109 unsigned int nformats, u32 code) 110 { 111 unsigned int i; 112 113 for (i = 0; i < nformats; i++) 114 if (code == formats[i].code) 115 return formats[i].bpp; 116 117 WARN(1, "Unknown format\n"); 118 119 return formats[0].bpp; 120 } 121 122 /* 123 * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module 124 * @csiphy: CSIPHY device 125 */ 126 static int csiphy_set_clock_rates(struct csiphy_device *csiphy) 127 { 128 struct device *dev = csiphy->camss->dev; 129 s64 link_freq; 130 int i, j; 131 int ret; 132 133 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 134 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 135 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 136 137 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 138 if (link_freq < 0) 139 link_freq = 0; 140 141 for (i = 0; i < csiphy->nclocks; i++) { 142 struct camss_clock *clock = &csiphy->clock[i]; 143 144 if (csiphy->rate_set[i]) { 145 u64 min_rate = link_freq / 4; 146 long round_rate; 147 148 camss_add_clock_margin(&min_rate); 149 150 for (j = 0; j < clock->nfreqs; j++) 151 if (min_rate < clock->freq[j]) 152 break; 153 154 if (j == clock->nfreqs) { 155 dev_err(dev, 156 "Pixel clock is too high for CSIPHY\n"); 157 return -EINVAL; 158 } 159 160 /* if sensor pixel clock is not available */ 161 /* set highest possible CSIPHY clock rate */ 162 if (min_rate == 0) 163 j = clock->nfreqs - 1; 164 165 round_rate = clk_round_rate(clock->clk, clock->freq[j]); 166 if (round_rate < 0) { 167 dev_err(dev, "clk round rate failed: %ld\n", 168 round_rate); 169 return -EINVAL; 170 } 171 172 csiphy->timer_clk_rate = round_rate; 173 174 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); 175 if (ret < 0) { 176 dev_err(dev, "clk set rate failed: %d\n", ret); 177 return ret; 178 } 179 } 180 } 181 182 return 0; 183 } 184 185 /* 186 * csiphy_set_power - Power on/off CSIPHY module 187 * @sd: CSIPHY V4L2 subdevice 188 * @on: Requested power state 189 * 190 * Return 0 on success or a negative error code otherwise 191 */ 192 static int csiphy_set_power(struct v4l2_subdev *sd, int on) 193 { 194 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 195 struct device *dev = csiphy->camss->dev; 196 197 if (on) { 198 int ret; 199 200 ret = pm_runtime_resume_and_get(dev); 201 if (ret < 0) 202 return ret; 203 204 ret = csiphy_set_clock_rates(csiphy); 205 if (ret < 0) { 206 pm_runtime_put_sync(dev); 207 return ret; 208 } 209 210 ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev); 211 if (ret < 0) { 212 pm_runtime_put_sync(dev); 213 return ret; 214 } 215 216 enable_irq(csiphy->irq); 217 218 csiphy->ops->reset(csiphy); 219 220 csiphy->ops->hw_version_read(csiphy, dev); 221 } else { 222 disable_irq(csiphy->irq); 223 224 camss_disable_clocks(csiphy->nclocks, csiphy->clock); 225 226 pm_runtime_put_sync(dev); 227 } 228 229 return 0; 230 } 231 232 /* 233 * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter 234 * @lane_cfg - CSI2 lane configuration 235 * 236 * Return lane mask 237 */ 238 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) 239 { 240 u8 lane_mask; 241 int i; 242 243 lane_mask = 1 << lane_cfg->clk.pos; 244 245 for (i = 0; i < lane_cfg->num_data; i++) 246 lane_mask |= 1 << lane_cfg->data[i].pos; 247 248 return lane_mask; 249 } 250 251 /* 252 * csiphy_stream_on - Enable streaming on CSIPHY module 253 * @csiphy: CSIPHY device 254 * 255 * Helper function to enable streaming on CSIPHY module. 256 * Main configuration of CSIPHY module is also done here. 257 * 258 * Return 0 on success or a negative error code otherwise 259 */ 260 static int csiphy_stream_on(struct csiphy_device *csiphy) 261 { 262 struct csiphy_config *cfg = &csiphy->cfg; 263 s64 link_freq; 264 u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); 265 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 266 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 267 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 268 u8 val; 269 270 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 271 272 if (link_freq < 0) { 273 dev_err(csiphy->camss->dev, 274 "Cannot get CSI2 transmitter's link frequency\n"); 275 return -EINVAL; 276 } 277 278 if (csiphy->base_clk_mux) { 279 val = readl_relaxed(csiphy->base_clk_mux); 280 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { 281 val &= ~0xf0; 282 val |= cfg->csid_id << 4; 283 } else { 284 val &= ~0xf; 285 val |= cfg->csid_id; 286 } 287 writel_relaxed(val, csiphy->base_clk_mux); 288 289 /* Enforce reg write ordering between clk mux & lane enabling */ 290 wmb(); 291 } 292 293 csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); 294 295 return 0; 296 } 297 298 /* 299 * csiphy_stream_off - Disable streaming on CSIPHY module 300 * @csiphy: CSIPHY device 301 * 302 * Helper function to disable streaming on CSIPHY module 303 */ 304 static void csiphy_stream_off(struct csiphy_device *csiphy) 305 { 306 csiphy->ops->lanes_disable(csiphy, &csiphy->cfg); 307 } 308 309 310 /* 311 * csiphy_set_stream - Enable/disable streaming on CSIPHY module 312 * @sd: CSIPHY V4L2 subdevice 313 * @enable: Requested streaming state 314 * 315 * Return 0 on success or a negative error code otherwise 316 */ 317 static int csiphy_set_stream(struct v4l2_subdev *sd, int enable) 318 { 319 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 320 int ret = 0; 321 322 if (enable) 323 ret = csiphy_stream_on(csiphy); 324 else 325 csiphy_stream_off(csiphy); 326 327 return ret; 328 } 329 330 /* 331 * __csiphy_get_format - Get pointer to format structure 332 * @csiphy: CSIPHY device 333 * @cfg: V4L2 subdev pad configuration 334 * @pad: pad from which format is requested 335 * @which: TRY or ACTIVE format 336 * 337 * Return pointer to TRY or ACTIVE format structure 338 */ 339 static struct v4l2_mbus_framefmt * 340 __csiphy_get_format(struct csiphy_device *csiphy, 341 struct v4l2_subdev_pad_config *cfg, 342 unsigned int pad, 343 enum v4l2_subdev_format_whence which) 344 { 345 if (which == V4L2_SUBDEV_FORMAT_TRY) 346 return v4l2_subdev_get_try_format(&csiphy->subdev, cfg, pad); 347 348 return &csiphy->fmt[pad]; 349 } 350 351 /* 352 * csiphy_try_format - Handle try format by pad subdev method 353 * @csiphy: CSIPHY device 354 * @cfg: V4L2 subdev pad configuration 355 * @pad: pad on which format is requested 356 * @fmt: pointer to v4l2 format structure 357 * @which: wanted subdev format 358 */ 359 static void csiphy_try_format(struct csiphy_device *csiphy, 360 struct v4l2_subdev_pad_config *cfg, 361 unsigned int pad, 362 struct v4l2_mbus_framefmt *fmt, 363 enum v4l2_subdev_format_whence which) 364 { 365 unsigned int i; 366 367 switch (pad) { 368 case MSM_CSIPHY_PAD_SINK: 369 /* Set format on sink pad */ 370 371 for (i = 0; i < csiphy->nformats; i++) 372 if (fmt->code == csiphy->formats[i].code) 373 break; 374 375 /* If not found, use UYVY as default */ 376 if (i >= csiphy->nformats) 377 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 378 379 fmt->width = clamp_t(u32, fmt->width, 1, 8191); 380 fmt->height = clamp_t(u32, fmt->height, 1, 8191); 381 382 fmt->field = V4L2_FIELD_NONE; 383 fmt->colorspace = V4L2_COLORSPACE_SRGB; 384 385 break; 386 387 case MSM_CSIPHY_PAD_SRC: 388 /* Set and return a format same as sink pad */ 389 390 *fmt = *__csiphy_get_format(csiphy, cfg, MSM_CSID_PAD_SINK, 391 which); 392 393 break; 394 } 395 } 396 397 /* 398 * csiphy_enum_mbus_code - Handle pixel format enumeration 399 * @sd: CSIPHY V4L2 subdevice 400 * @cfg: V4L2 subdev pad configuration 401 * @code: pointer to v4l2_subdev_mbus_code_enum structure 402 * return -EINVAL or zero on success 403 */ 404 static int csiphy_enum_mbus_code(struct v4l2_subdev *sd, 405 struct v4l2_subdev_pad_config *cfg, 406 struct v4l2_subdev_mbus_code_enum *code) 407 { 408 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 409 struct v4l2_mbus_framefmt *format; 410 411 if (code->pad == MSM_CSIPHY_PAD_SINK) { 412 if (code->index >= csiphy->nformats) 413 return -EINVAL; 414 415 code->code = csiphy->formats[code->index].code; 416 } else { 417 if (code->index > 0) 418 return -EINVAL; 419 420 format = __csiphy_get_format(csiphy, cfg, MSM_CSIPHY_PAD_SINK, 421 code->which); 422 423 code->code = format->code; 424 } 425 426 return 0; 427 } 428 429 /* 430 * csiphy_enum_frame_size - Handle frame size enumeration 431 * @sd: CSIPHY V4L2 subdevice 432 * @cfg: V4L2 subdev pad configuration 433 * @fse: pointer to v4l2_subdev_frame_size_enum structure 434 * return -EINVAL or zero on success 435 */ 436 static int csiphy_enum_frame_size(struct v4l2_subdev *sd, 437 struct v4l2_subdev_pad_config *cfg, 438 struct v4l2_subdev_frame_size_enum *fse) 439 { 440 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 441 struct v4l2_mbus_framefmt format; 442 443 if (fse->index != 0) 444 return -EINVAL; 445 446 format.code = fse->code; 447 format.width = 1; 448 format.height = 1; 449 csiphy_try_format(csiphy, cfg, fse->pad, &format, fse->which); 450 fse->min_width = format.width; 451 fse->min_height = format.height; 452 453 if (format.code != fse->code) 454 return -EINVAL; 455 456 format.code = fse->code; 457 format.width = -1; 458 format.height = -1; 459 csiphy_try_format(csiphy, cfg, fse->pad, &format, fse->which); 460 fse->max_width = format.width; 461 fse->max_height = format.height; 462 463 return 0; 464 } 465 466 /* 467 * csiphy_get_format - Handle get format by pads subdev method 468 * @sd: CSIPHY V4L2 subdevice 469 * @cfg: V4L2 subdev pad configuration 470 * @fmt: pointer to v4l2 subdev format structure 471 * 472 * Return -EINVAL or zero on success 473 */ 474 static int csiphy_get_format(struct v4l2_subdev *sd, 475 struct v4l2_subdev_pad_config *cfg, 476 struct v4l2_subdev_format *fmt) 477 { 478 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 479 struct v4l2_mbus_framefmt *format; 480 481 format = __csiphy_get_format(csiphy, cfg, fmt->pad, fmt->which); 482 if (format == NULL) 483 return -EINVAL; 484 485 fmt->format = *format; 486 487 return 0; 488 } 489 490 /* 491 * csiphy_set_format - Handle set format by pads subdev method 492 * @sd: CSIPHY V4L2 subdevice 493 * @cfg: V4L2 subdev pad configuration 494 * @fmt: pointer to v4l2 subdev format structure 495 * 496 * Return -EINVAL or zero on success 497 */ 498 static int csiphy_set_format(struct v4l2_subdev *sd, 499 struct v4l2_subdev_pad_config *cfg, 500 struct v4l2_subdev_format *fmt) 501 { 502 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 503 struct v4l2_mbus_framefmt *format; 504 505 format = __csiphy_get_format(csiphy, cfg, fmt->pad, fmt->which); 506 if (format == NULL) 507 return -EINVAL; 508 509 csiphy_try_format(csiphy, cfg, fmt->pad, &fmt->format, fmt->which); 510 *format = fmt->format; 511 512 /* Propagate the format from sink to source */ 513 if (fmt->pad == MSM_CSIPHY_PAD_SINK) { 514 format = __csiphy_get_format(csiphy, cfg, MSM_CSIPHY_PAD_SRC, 515 fmt->which); 516 517 *format = fmt->format; 518 csiphy_try_format(csiphy, cfg, MSM_CSIPHY_PAD_SRC, format, 519 fmt->which); 520 } 521 522 return 0; 523 } 524 525 /* 526 * csiphy_init_formats - Initialize formats on all pads 527 * @sd: CSIPHY V4L2 subdevice 528 * @fh: V4L2 subdev file handle 529 * 530 * Initialize all pad formats with default values. 531 * 532 * Return 0 on success or a negative error code otherwise 533 */ 534 static int csiphy_init_formats(struct v4l2_subdev *sd, 535 struct v4l2_subdev_fh *fh) 536 { 537 struct v4l2_subdev_format format = { 538 .pad = MSM_CSIPHY_PAD_SINK, 539 .which = fh ? V4L2_SUBDEV_FORMAT_TRY : 540 V4L2_SUBDEV_FORMAT_ACTIVE, 541 .format = { 542 .code = MEDIA_BUS_FMT_UYVY8_2X8, 543 .width = 1920, 544 .height = 1080 545 } 546 }; 547 548 return csiphy_set_format(sd, fh ? fh->pad : NULL, &format); 549 } 550 551 /* 552 * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources 553 * @csiphy: CSIPHY device 554 * @res: CSIPHY module resources table 555 * @id: CSIPHY module id 556 * 557 * Return 0 on success or a negative error code otherwise 558 */ 559 int msm_csiphy_subdev_init(struct camss *camss, 560 struct csiphy_device *csiphy, 561 const struct resources *res, u8 id) 562 { 563 struct device *dev = camss->dev; 564 struct platform_device *pdev = to_platform_device(dev); 565 struct resource *r; 566 int i, j; 567 int ret; 568 569 csiphy->camss = camss; 570 csiphy->id = id; 571 csiphy->cfg.combo_mode = 0; 572 573 if (camss->version == CAMSS_8x16) { 574 csiphy->ops = &csiphy_ops_2ph_1_0; 575 csiphy->formats = csiphy_formats_8x16; 576 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x16); 577 } else if (camss->version == CAMSS_8x96 || 578 camss->version == CAMSS_660) { 579 csiphy->ops = &csiphy_ops_3ph_1_0; 580 csiphy->formats = csiphy_formats_8x96; 581 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96); 582 } else if (camss->version == CAMSS_845) { 583 csiphy->ops = &csiphy_ops_3ph_1_0; 584 csiphy->formats = csiphy_formats_sdm845; 585 csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845); 586 } else { 587 return -EINVAL; 588 } 589 590 /* Memory */ 591 592 csiphy->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]); 593 if (IS_ERR(csiphy->base)) 594 return PTR_ERR(csiphy->base); 595 596 if (camss->version == CAMSS_8x16 || 597 camss->version == CAMSS_8x96) { 598 csiphy->base_clk_mux = 599 devm_platform_ioremap_resource_byname(pdev, res->reg[1]); 600 if (IS_ERR(csiphy->base_clk_mux)) 601 return PTR_ERR(csiphy->base_clk_mux); 602 } else { 603 csiphy->base_clk_mux = NULL; 604 } 605 606 /* Interrupt */ 607 608 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 609 res->interrupt[0]); 610 if (!r) { 611 dev_err(dev, "missing IRQ\n"); 612 return -EINVAL; 613 } 614 615 csiphy->irq = r->start; 616 snprintf(csiphy->irq_name, sizeof(csiphy->irq_name), "%s_%s%d", 617 dev_name(dev), MSM_CSIPHY_NAME, csiphy->id); 618 619 ret = devm_request_irq(dev, csiphy->irq, csiphy->ops->isr, 620 IRQF_TRIGGER_RISING, csiphy->irq_name, csiphy); 621 if (ret < 0) { 622 dev_err(dev, "request_irq failed: %d\n", ret); 623 return ret; 624 } 625 626 disable_irq(csiphy->irq); 627 628 /* Clocks */ 629 630 csiphy->nclocks = 0; 631 while (res->clock[csiphy->nclocks]) 632 csiphy->nclocks++; 633 634 csiphy->clock = devm_kcalloc(dev, 635 csiphy->nclocks, sizeof(*csiphy->clock), 636 GFP_KERNEL); 637 if (!csiphy->clock) 638 return -ENOMEM; 639 640 csiphy->rate_set = devm_kcalloc(dev, 641 csiphy->nclocks, 642 sizeof(*csiphy->rate_set), 643 GFP_KERNEL); 644 if (!csiphy->rate_set) 645 return -ENOMEM; 646 647 for (i = 0; i < csiphy->nclocks; i++) { 648 struct camss_clock *clock = &csiphy->clock[i]; 649 650 clock->clk = devm_clk_get(dev, res->clock[i]); 651 if (IS_ERR(clock->clk)) 652 return PTR_ERR(clock->clk); 653 654 clock->name = res->clock[i]; 655 656 clock->nfreqs = 0; 657 while (res->clock_rate[i][clock->nfreqs]) 658 clock->nfreqs++; 659 660 if (!clock->nfreqs) { 661 clock->freq = NULL; 662 continue; 663 } 664 665 clock->freq = devm_kcalloc(dev, 666 clock->nfreqs, 667 sizeof(*clock->freq), 668 GFP_KERNEL); 669 if (!clock->freq) 670 return -ENOMEM; 671 672 for (j = 0; j < clock->nfreqs; j++) 673 clock->freq[j] = res->clock_rate[i][j]; 674 675 if (!strcmp(clock->name, "csiphy0_timer") || 676 !strcmp(clock->name, "csiphy1_timer") || 677 !strcmp(clock->name, "csiphy2_timer")) 678 csiphy->rate_set[i] = true; 679 680 if (camss->version == CAMSS_660 && 681 (!strcmp(clock->name, "csi0_phy") || 682 !strcmp(clock->name, "csi1_phy") || 683 !strcmp(clock->name, "csi2_phy"))) 684 csiphy->rate_set[i] = true; 685 } 686 687 return 0; 688 } 689 690 /* 691 * csiphy_link_setup - Setup CSIPHY connections 692 * @entity: Pointer to media entity structure 693 * @local: Pointer to local pad 694 * @remote: Pointer to remote pad 695 * @flags: Link flags 696 * 697 * Rreturn 0 on success 698 */ 699 static int csiphy_link_setup(struct media_entity *entity, 700 const struct media_pad *local, 701 const struct media_pad *remote, u32 flags) 702 { 703 if ((local->flags & MEDIA_PAD_FL_SOURCE) && 704 (flags & MEDIA_LNK_FL_ENABLED)) { 705 struct v4l2_subdev *sd; 706 struct csiphy_device *csiphy; 707 struct csid_device *csid; 708 709 if (media_entity_remote_pad(local)) 710 return -EBUSY; 711 712 sd = media_entity_to_v4l2_subdev(entity); 713 csiphy = v4l2_get_subdevdata(sd); 714 715 sd = media_entity_to_v4l2_subdev(remote->entity); 716 csid = v4l2_get_subdevdata(sd); 717 718 csiphy->cfg.csid_id = csid->id; 719 } 720 721 return 0; 722 } 723 724 static const struct v4l2_subdev_core_ops csiphy_core_ops = { 725 .s_power = csiphy_set_power, 726 }; 727 728 static const struct v4l2_subdev_video_ops csiphy_video_ops = { 729 .s_stream = csiphy_set_stream, 730 }; 731 732 static const struct v4l2_subdev_pad_ops csiphy_pad_ops = { 733 .enum_mbus_code = csiphy_enum_mbus_code, 734 .enum_frame_size = csiphy_enum_frame_size, 735 .get_fmt = csiphy_get_format, 736 .set_fmt = csiphy_set_format, 737 }; 738 739 static const struct v4l2_subdev_ops csiphy_v4l2_ops = { 740 .core = &csiphy_core_ops, 741 .video = &csiphy_video_ops, 742 .pad = &csiphy_pad_ops, 743 }; 744 745 static const struct v4l2_subdev_internal_ops csiphy_v4l2_internal_ops = { 746 .open = csiphy_init_formats, 747 }; 748 749 static const struct media_entity_operations csiphy_media_ops = { 750 .link_setup = csiphy_link_setup, 751 .link_validate = v4l2_subdev_link_validate, 752 }; 753 754 /* 755 * msm_csiphy_register_entity - Register subdev node for CSIPHY module 756 * @csiphy: CSIPHY device 757 * @v4l2_dev: V4L2 device 758 * 759 * Return 0 on success or a negative error code otherwise 760 */ 761 int msm_csiphy_register_entity(struct csiphy_device *csiphy, 762 struct v4l2_device *v4l2_dev) 763 { 764 struct v4l2_subdev *sd = &csiphy->subdev; 765 struct media_pad *pads = csiphy->pads; 766 struct device *dev = csiphy->camss->dev; 767 int ret; 768 769 v4l2_subdev_init(sd, &csiphy_v4l2_ops); 770 sd->internal_ops = &csiphy_v4l2_internal_ops; 771 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 772 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", 773 MSM_CSIPHY_NAME, csiphy->id); 774 v4l2_set_subdevdata(sd, csiphy); 775 776 ret = csiphy_init_formats(sd, NULL); 777 if (ret < 0) { 778 dev_err(dev, "Failed to init format: %d\n", ret); 779 return ret; 780 } 781 782 pads[MSM_CSIPHY_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 783 pads[MSM_CSIPHY_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 784 785 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 786 sd->entity.ops = &csiphy_media_ops; 787 ret = media_entity_pads_init(&sd->entity, MSM_CSIPHY_PADS_NUM, pads); 788 if (ret < 0) { 789 dev_err(dev, "Failed to init media entity: %d\n", ret); 790 return ret; 791 } 792 793 ret = v4l2_device_register_subdev(v4l2_dev, sd); 794 if (ret < 0) { 795 dev_err(dev, "Failed to register subdev: %d\n", ret); 796 media_entity_cleanup(&sd->entity); 797 } 798 799 return ret; 800 } 801 802 /* 803 * msm_csiphy_unregister_entity - Unregister CSIPHY module subdev node 804 * @csiphy: CSIPHY device 805 */ 806 void msm_csiphy_unregister_entity(struct csiphy_device *csiphy) 807 { 808 v4l2_device_unregister_subdev(&csiphy->subdev); 809 media_entity_cleanup(&csiphy->subdev.entity); 810 } 811