1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_runtime.h> 18 #include <media/media-entity.h> 19 #include <media/v4l2-device.h> 20 #include <media/v4l2-subdev.h> 21 22 #include "camss-csiphy.h" 23 #include "camss.h" 24 25 #define MSM_CSIPHY_NAME "msm_csiphy" 26 27 struct csiphy_format { 28 u32 code; 29 u8 bpp; 30 }; 31 32 static const struct csiphy_format csiphy_formats_8x16[] = { 33 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 34 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 35 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 36 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 37 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 38 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 39 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 40 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 41 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 42 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 43 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 44 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 45 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 46 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 47 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 48 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 49 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 50 }; 51 52 static const struct csiphy_format csiphy_formats_8x96[] = { 53 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 54 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 55 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 56 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 57 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 58 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 59 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 60 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 61 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 62 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 63 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 64 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 65 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 66 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 67 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 68 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 69 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 70 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 71 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 72 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 73 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 74 }; 75 76 static const struct csiphy_format csiphy_formats_sdm845[] = { 77 { MEDIA_BUS_FMT_UYVY8_2X8, 8 }, 78 { MEDIA_BUS_FMT_VYUY8_2X8, 8 }, 79 { MEDIA_BUS_FMT_YUYV8_2X8, 8 }, 80 { MEDIA_BUS_FMT_YVYU8_2X8, 8 }, 81 { MEDIA_BUS_FMT_SBGGR8_1X8, 8 }, 82 { MEDIA_BUS_FMT_SGBRG8_1X8, 8 }, 83 { MEDIA_BUS_FMT_SGRBG8_1X8, 8 }, 84 { MEDIA_BUS_FMT_SRGGB8_1X8, 8 }, 85 { MEDIA_BUS_FMT_SBGGR10_1X10, 10 }, 86 { MEDIA_BUS_FMT_SGBRG10_1X10, 10 }, 87 { MEDIA_BUS_FMT_SGRBG10_1X10, 10 }, 88 { MEDIA_BUS_FMT_SRGGB10_1X10, 10 }, 89 { MEDIA_BUS_FMT_SBGGR12_1X12, 12 }, 90 { MEDIA_BUS_FMT_SGBRG12_1X12, 12 }, 91 { MEDIA_BUS_FMT_SGRBG12_1X12, 12 }, 92 { MEDIA_BUS_FMT_SRGGB12_1X12, 12 }, 93 { MEDIA_BUS_FMT_SBGGR14_1X14, 14 }, 94 { MEDIA_BUS_FMT_SGBRG14_1X14, 14 }, 95 { MEDIA_BUS_FMT_SGRBG14_1X14, 14 }, 96 { MEDIA_BUS_FMT_SRGGB14_1X14, 14 }, 97 { MEDIA_BUS_FMT_Y10_1X10, 10 }, 98 }; 99 100 /* 101 * csiphy_get_bpp - map media bus format to bits per pixel 102 * @formats: supported media bus formats array 103 * @nformats: size of @formats array 104 * @code: media bus format code 105 * 106 * Return number of bits per pixel 107 */ 108 static u8 csiphy_get_bpp(const struct csiphy_format *formats, 109 unsigned int nformats, u32 code) 110 { 111 unsigned int i; 112 113 for (i = 0; i < nformats; i++) 114 if (code == formats[i].code) 115 return formats[i].bpp; 116 117 WARN(1, "Unknown format\n"); 118 119 return formats[0].bpp; 120 } 121 122 /* 123 * csiphy_set_clock_rates - Calculate and set clock rates on CSIPHY module 124 * @csiphy: CSIPHY device 125 */ 126 static int csiphy_set_clock_rates(struct csiphy_device *csiphy) 127 { 128 struct device *dev = csiphy->camss->dev; 129 s64 link_freq; 130 int i, j; 131 int ret; 132 133 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 134 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 135 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 136 137 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 138 if (link_freq < 0) 139 link_freq = 0; 140 141 for (i = 0; i < csiphy->nclocks; i++) { 142 struct camss_clock *clock = &csiphy->clock[i]; 143 144 if (csiphy->rate_set[i]) { 145 u64 min_rate = link_freq / 4; 146 long round_rate; 147 148 camss_add_clock_margin(&min_rate); 149 150 for (j = 0; j < clock->nfreqs; j++) 151 if (min_rate < clock->freq[j]) 152 break; 153 154 if (j == clock->nfreqs) { 155 dev_err(dev, 156 "Pixel clock is too high for CSIPHY\n"); 157 return -EINVAL; 158 } 159 160 /* if sensor pixel clock is not available */ 161 /* set highest possible CSIPHY clock rate */ 162 if (min_rate == 0) 163 j = clock->nfreqs - 1; 164 165 round_rate = clk_round_rate(clock->clk, clock->freq[j]); 166 if (round_rate < 0) { 167 dev_err(dev, "clk round rate failed: %ld\n", 168 round_rate); 169 return -EINVAL; 170 } 171 172 csiphy->timer_clk_rate = round_rate; 173 174 ret = clk_set_rate(clock->clk, csiphy->timer_clk_rate); 175 if (ret < 0) { 176 dev_err(dev, "clk set rate failed: %d\n", ret); 177 return ret; 178 } 179 } 180 } 181 182 return 0; 183 } 184 185 /* 186 * csiphy_set_power - Power on/off CSIPHY module 187 * @sd: CSIPHY V4L2 subdevice 188 * @on: Requested power state 189 * 190 * Return 0 on success or a negative error code otherwise 191 */ 192 static int csiphy_set_power(struct v4l2_subdev *sd, int on) 193 { 194 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 195 struct device *dev = csiphy->camss->dev; 196 197 if (on) { 198 int ret; 199 200 ret = pm_runtime_get_sync(dev); 201 if (ret < 0) { 202 pm_runtime_put_sync(dev); 203 return ret; 204 } 205 206 ret = csiphy_set_clock_rates(csiphy); 207 if (ret < 0) { 208 pm_runtime_put_sync(dev); 209 return ret; 210 } 211 212 ret = camss_enable_clocks(csiphy->nclocks, csiphy->clock, dev); 213 if (ret < 0) { 214 pm_runtime_put_sync(dev); 215 return ret; 216 } 217 218 enable_irq(csiphy->irq); 219 220 csiphy->ops->reset(csiphy); 221 222 csiphy->ops->hw_version_read(csiphy, dev); 223 } else { 224 disable_irq(csiphy->irq); 225 226 camss_disable_clocks(csiphy->nclocks, csiphy->clock); 227 228 pm_runtime_put_sync(dev); 229 } 230 231 return 0; 232 } 233 234 /* 235 * csiphy_get_lane_mask - Calculate CSI2 lane mask configuration parameter 236 * @lane_cfg - CSI2 lane configuration 237 * 238 * Return lane mask 239 */ 240 static u8 csiphy_get_lane_mask(struct csiphy_lanes_cfg *lane_cfg) 241 { 242 u8 lane_mask; 243 int i; 244 245 lane_mask = 1 << lane_cfg->clk.pos; 246 247 for (i = 0; i < lane_cfg->num_data; i++) 248 lane_mask |= 1 << lane_cfg->data[i].pos; 249 250 return lane_mask; 251 } 252 253 /* 254 * csiphy_stream_on - Enable streaming on CSIPHY module 255 * @csiphy: CSIPHY device 256 * 257 * Helper function to enable streaming on CSIPHY module. 258 * Main configuration of CSIPHY module is also done here. 259 * 260 * Return 0 on success or a negative error code otherwise 261 */ 262 static int csiphy_stream_on(struct csiphy_device *csiphy) 263 { 264 struct csiphy_config *cfg = &csiphy->cfg; 265 s64 link_freq; 266 u8 lane_mask = csiphy_get_lane_mask(&cfg->csi2->lane_cfg); 267 u8 bpp = csiphy_get_bpp(csiphy->formats, csiphy->nformats, 268 csiphy->fmt[MSM_CSIPHY_PAD_SINK].code); 269 u8 num_lanes = csiphy->cfg.csi2->lane_cfg.num_data; 270 u8 val; 271 272 link_freq = camss_get_link_freq(&csiphy->subdev.entity, bpp, num_lanes); 273 274 if (link_freq < 0) { 275 dev_err(csiphy->camss->dev, 276 "Cannot get CSI2 transmitter's link frequency\n"); 277 return -EINVAL; 278 } 279 280 if (csiphy->base_clk_mux) { 281 val = readl_relaxed(csiphy->base_clk_mux); 282 if (cfg->combo_mode && (lane_mask & 0x18) == 0x18) { 283 val &= ~0xf0; 284 val |= cfg->csid_id << 4; 285 } else { 286 val &= ~0xf; 287 val |= cfg->csid_id; 288 } 289 writel_relaxed(val, csiphy->base_clk_mux); 290 291 /* Enforce reg write ordering between clk mux & lane enabling */ 292 wmb(); 293 } 294 295 csiphy->ops->lanes_enable(csiphy, cfg, link_freq, lane_mask); 296 297 return 0; 298 } 299 300 /* 301 * csiphy_stream_off - Disable streaming on CSIPHY module 302 * @csiphy: CSIPHY device 303 * 304 * Helper function to disable streaming on CSIPHY module 305 */ 306 static void csiphy_stream_off(struct csiphy_device *csiphy) 307 { 308 csiphy->ops->lanes_disable(csiphy, &csiphy->cfg); 309 } 310 311 312 /* 313 * csiphy_set_stream - Enable/disable streaming on CSIPHY module 314 * @sd: CSIPHY V4L2 subdevice 315 * @enable: Requested streaming state 316 * 317 * Return 0 on success or a negative error code otherwise 318 */ 319 static int csiphy_set_stream(struct v4l2_subdev *sd, int enable) 320 { 321 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 322 int ret = 0; 323 324 if (enable) 325 ret = csiphy_stream_on(csiphy); 326 else 327 csiphy_stream_off(csiphy); 328 329 return ret; 330 } 331 332 /* 333 * __csiphy_get_format - Get pointer to format structure 334 * @csiphy: CSIPHY device 335 * @cfg: V4L2 subdev pad configuration 336 * @pad: pad from which format is requested 337 * @which: TRY or ACTIVE format 338 * 339 * Return pointer to TRY or ACTIVE format structure 340 */ 341 static struct v4l2_mbus_framefmt * 342 __csiphy_get_format(struct csiphy_device *csiphy, 343 struct v4l2_subdev_pad_config *cfg, 344 unsigned int pad, 345 enum v4l2_subdev_format_whence which) 346 { 347 if (which == V4L2_SUBDEV_FORMAT_TRY) 348 return v4l2_subdev_get_try_format(&csiphy->subdev, cfg, pad); 349 350 return &csiphy->fmt[pad]; 351 } 352 353 /* 354 * csiphy_try_format - Handle try format by pad subdev method 355 * @csiphy: CSIPHY device 356 * @cfg: V4L2 subdev pad configuration 357 * @pad: pad on which format is requested 358 * @fmt: pointer to v4l2 format structure 359 * @which: wanted subdev format 360 */ 361 static void csiphy_try_format(struct csiphy_device *csiphy, 362 struct v4l2_subdev_pad_config *cfg, 363 unsigned int pad, 364 struct v4l2_mbus_framefmt *fmt, 365 enum v4l2_subdev_format_whence which) 366 { 367 unsigned int i; 368 369 switch (pad) { 370 case MSM_CSIPHY_PAD_SINK: 371 /* Set format on sink pad */ 372 373 for (i = 0; i < csiphy->nformats; i++) 374 if (fmt->code == csiphy->formats[i].code) 375 break; 376 377 /* If not found, use UYVY as default */ 378 if (i >= csiphy->nformats) 379 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8; 380 381 fmt->width = clamp_t(u32, fmt->width, 1, 8191); 382 fmt->height = clamp_t(u32, fmt->height, 1, 8191); 383 384 fmt->field = V4L2_FIELD_NONE; 385 fmt->colorspace = V4L2_COLORSPACE_SRGB; 386 387 break; 388 389 case MSM_CSIPHY_PAD_SRC: 390 /* Set and return a format same as sink pad */ 391 392 *fmt = *__csiphy_get_format(csiphy, cfg, MSM_CSID_PAD_SINK, 393 which); 394 395 break; 396 } 397 } 398 399 /* 400 * csiphy_enum_mbus_code - Handle pixel format enumeration 401 * @sd: CSIPHY V4L2 subdevice 402 * @cfg: V4L2 subdev pad configuration 403 * @code: pointer to v4l2_subdev_mbus_code_enum structure 404 * return -EINVAL or zero on success 405 */ 406 static int csiphy_enum_mbus_code(struct v4l2_subdev *sd, 407 struct v4l2_subdev_pad_config *cfg, 408 struct v4l2_subdev_mbus_code_enum *code) 409 { 410 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 411 struct v4l2_mbus_framefmt *format; 412 413 if (code->pad == MSM_CSIPHY_PAD_SINK) { 414 if (code->index >= csiphy->nformats) 415 return -EINVAL; 416 417 code->code = csiphy->formats[code->index].code; 418 } else { 419 if (code->index > 0) 420 return -EINVAL; 421 422 format = __csiphy_get_format(csiphy, cfg, MSM_CSIPHY_PAD_SINK, 423 code->which); 424 425 code->code = format->code; 426 } 427 428 return 0; 429 } 430 431 /* 432 * csiphy_enum_frame_size - Handle frame size enumeration 433 * @sd: CSIPHY V4L2 subdevice 434 * @cfg: V4L2 subdev pad configuration 435 * @fse: pointer to v4l2_subdev_frame_size_enum structure 436 * return -EINVAL or zero on success 437 */ 438 static int csiphy_enum_frame_size(struct v4l2_subdev *sd, 439 struct v4l2_subdev_pad_config *cfg, 440 struct v4l2_subdev_frame_size_enum *fse) 441 { 442 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 443 struct v4l2_mbus_framefmt format; 444 445 if (fse->index != 0) 446 return -EINVAL; 447 448 format.code = fse->code; 449 format.width = 1; 450 format.height = 1; 451 csiphy_try_format(csiphy, cfg, fse->pad, &format, fse->which); 452 fse->min_width = format.width; 453 fse->min_height = format.height; 454 455 if (format.code != fse->code) 456 return -EINVAL; 457 458 format.code = fse->code; 459 format.width = -1; 460 format.height = -1; 461 csiphy_try_format(csiphy, cfg, fse->pad, &format, fse->which); 462 fse->max_width = format.width; 463 fse->max_height = format.height; 464 465 return 0; 466 } 467 468 /* 469 * csiphy_get_format - Handle get format by pads subdev method 470 * @sd: CSIPHY V4L2 subdevice 471 * @cfg: V4L2 subdev pad configuration 472 * @fmt: pointer to v4l2 subdev format structure 473 * 474 * Return -EINVAL or zero on success 475 */ 476 static int csiphy_get_format(struct v4l2_subdev *sd, 477 struct v4l2_subdev_pad_config *cfg, 478 struct v4l2_subdev_format *fmt) 479 { 480 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 481 struct v4l2_mbus_framefmt *format; 482 483 format = __csiphy_get_format(csiphy, cfg, fmt->pad, fmt->which); 484 if (format == NULL) 485 return -EINVAL; 486 487 fmt->format = *format; 488 489 return 0; 490 } 491 492 /* 493 * csiphy_set_format - Handle set format by pads subdev method 494 * @sd: CSIPHY V4L2 subdevice 495 * @cfg: V4L2 subdev pad configuration 496 * @fmt: pointer to v4l2 subdev format structure 497 * 498 * Return -EINVAL or zero on success 499 */ 500 static int csiphy_set_format(struct v4l2_subdev *sd, 501 struct v4l2_subdev_pad_config *cfg, 502 struct v4l2_subdev_format *fmt) 503 { 504 struct csiphy_device *csiphy = v4l2_get_subdevdata(sd); 505 struct v4l2_mbus_framefmt *format; 506 507 format = __csiphy_get_format(csiphy, cfg, fmt->pad, fmt->which); 508 if (format == NULL) 509 return -EINVAL; 510 511 csiphy_try_format(csiphy, cfg, fmt->pad, &fmt->format, fmt->which); 512 *format = fmt->format; 513 514 /* Propagate the format from sink to source */ 515 if (fmt->pad == MSM_CSIPHY_PAD_SINK) { 516 format = __csiphy_get_format(csiphy, cfg, MSM_CSIPHY_PAD_SRC, 517 fmt->which); 518 519 *format = fmt->format; 520 csiphy_try_format(csiphy, cfg, MSM_CSIPHY_PAD_SRC, format, 521 fmt->which); 522 } 523 524 return 0; 525 } 526 527 /* 528 * csiphy_init_formats - Initialize formats on all pads 529 * @sd: CSIPHY V4L2 subdevice 530 * @fh: V4L2 subdev file handle 531 * 532 * Initialize all pad formats with default values. 533 * 534 * Return 0 on success or a negative error code otherwise 535 */ 536 static int csiphy_init_formats(struct v4l2_subdev *sd, 537 struct v4l2_subdev_fh *fh) 538 { 539 struct v4l2_subdev_format format = { 540 .pad = MSM_CSIPHY_PAD_SINK, 541 .which = fh ? V4L2_SUBDEV_FORMAT_TRY : 542 V4L2_SUBDEV_FORMAT_ACTIVE, 543 .format = { 544 .code = MEDIA_BUS_FMT_UYVY8_2X8, 545 .width = 1920, 546 .height = 1080 547 } 548 }; 549 550 return csiphy_set_format(sd, fh ? fh->pad : NULL, &format); 551 } 552 553 /* 554 * msm_csiphy_subdev_init - Initialize CSIPHY device structure and resources 555 * @csiphy: CSIPHY device 556 * @res: CSIPHY module resources table 557 * @id: CSIPHY module id 558 * 559 * Return 0 on success or a negative error code otherwise 560 */ 561 int msm_csiphy_subdev_init(struct camss *camss, 562 struct csiphy_device *csiphy, 563 const struct resources *res, u8 id) 564 { 565 struct device *dev = camss->dev; 566 struct platform_device *pdev = to_platform_device(dev); 567 struct resource *r; 568 int i, j; 569 int ret; 570 571 csiphy->camss = camss; 572 csiphy->id = id; 573 csiphy->cfg.combo_mode = 0; 574 575 if (camss->version == CAMSS_8x16) { 576 csiphy->ops = &csiphy_ops_2ph_1_0; 577 csiphy->formats = csiphy_formats_8x16; 578 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x16); 579 } else if (camss->version == CAMSS_8x96 || 580 camss->version == CAMSS_660) { 581 csiphy->ops = &csiphy_ops_3ph_1_0; 582 csiphy->formats = csiphy_formats_8x96; 583 csiphy->nformats = ARRAY_SIZE(csiphy_formats_8x96); 584 } else if (camss->version == CAMSS_845) { 585 csiphy->ops = &csiphy_ops_3ph_1_0; 586 csiphy->formats = csiphy_formats_sdm845; 587 csiphy->nformats = ARRAY_SIZE(csiphy_formats_sdm845); 588 } else { 589 return -EINVAL; 590 } 591 592 /* Memory */ 593 594 csiphy->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]); 595 if (IS_ERR(csiphy->base)) 596 return PTR_ERR(csiphy->base); 597 598 if (camss->version == CAMSS_8x16 || 599 camss->version == CAMSS_8x96) { 600 csiphy->base_clk_mux = 601 devm_platform_ioremap_resource_byname(pdev, res->reg[1]); 602 if (IS_ERR(csiphy->base_clk_mux)) 603 return PTR_ERR(csiphy->base_clk_mux); 604 } else { 605 csiphy->base_clk_mux = NULL; 606 } 607 608 /* Interrupt */ 609 610 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, 611 res->interrupt[0]); 612 if (!r) { 613 dev_err(dev, "missing IRQ\n"); 614 return -EINVAL; 615 } 616 617 csiphy->irq = r->start; 618 snprintf(csiphy->irq_name, sizeof(csiphy->irq_name), "%s_%s%d", 619 dev_name(dev), MSM_CSIPHY_NAME, csiphy->id); 620 621 ret = devm_request_irq(dev, csiphy->irq, csiphy->ops->isr, 622 IRQF_TRIGGER_RISING, csiphy->irq_name, csiphy); 623 if (ret < 0) { 624 dev_err(dev, "request_irq failed: %d\n", ret); 625 return ret; 626 } 627 628 disable_irq(csiphy->irq); 629 630 /* Clocks */ 631 632 csiphy->nclocks = 0; 633 while (res->clock[csiphy->nclocks]) 634 csiphy->nclocks++; 635 636 csiphy->clock = devm_kcalloc(dev, 637 csiphy->nclocks, sizeof(*csiphy->clock), 638 GFP_KERNEL); 639 if (!csiphy->clock) 640 return -ENOMEM; 641 642 csiphy->rate_set = devm_kcalloc(dev, 643 csiphy->nclocks, 644 sizeof(*csiphy->rate_set), 645 GFP_KERNEL); 646 if (!csiphy->rate_set) 647 return -ENOMEM; 648 649 for (i = 0; i < csiphy->nclocks; i++) { 650 struct camss_clock *clock = &csiphy->clock[i]; 651 652 clock->clk = devm_clk_get(dev, res->clock[i]); 653 if (IS_ERR(clock->clk)) 654 return PTR_ERR(clock->clk); 655 656 clock->name = res->clock[i]; 657 658 clock->nfreqs = 0; 659 while (res->clock_rate[i][clock->nfreqs]) 660 clock->nfreqs++; 661 662 if (!clock->nfreqs) { 663 clock->freq = NULL; 664 continue; 665 } 666 667 clock->freq = devm_kcalloc(dev, 668 clock->nfreqs, 669 sizeof(*clock->freq), 670 GFP_KERNEL); 671 if (!clock->freq) 672 return -ENOMEM; 673 674 for (j = 0; j < clock->nfreqs; j++) 675 clock->freq[j] = res->clock_rate[i][j]; 676 677 if (!strcmp(clock->name, "csiphy0_timer") || 678 !strcmp(clock->name, "csiphy1_timer") || 679 !strcmp(clock->name, "csiphy2_timer")) 680 csiphy->rate_set[i] = true; 681 682 if (camss->version == CAMSS_660 && 683 (!strcmp(clock->name, "csi0_phy") || 684 !strcmp(clock->name, "csi1_phy") || 685 !strcmp(clock->name, "csi2_phy"))) 686 csiphy->rate_set[i] = true; 687 } 688 689 return 0; 690 } 691 692 /* 693 * csiphy_link_setup - Setup CSIPHY connections 694 * @entity: Pointer to media entity structure 695 * @local: Pointer to local pad 696 * @remote: Pointer to remote pad 697 * @flags: Link flags 698 * 699 * Rreturn 0 on success 700 */ 701 static int csiphy_link_setup(struct media_entity *entity, 702 const struct media_pad *local, 703 const struct media_pad *remote, u32 flags) 704 { 705 if ((local->flags & MEDIA_PAD_FL_SOURCE) && 706 (flags & MEDIA_LNK_FL_ENABLED)) { 707 struct v4l2_subdev *sd; 708 struct csiphy_device *csiphy; 709 struct csid_device *csid; 710 711 if (media_entity_remote_pad(local)) 712 return -EBUSY; 713 714 sd = media_entity_to_v4l2_subdev(entity); 715 csiphy = v4l2_get_subdevdata(sd); 716 717 sd = media_entity_to_v4l2_subdev(remote->entity); 718 csid = v4l2_get_subdevdata(sd); 719 720 csiphy->cfg.csid_id = csid->id; 721 } 722 723 return 0; 724 } 725 726 static const struct v4l2_subdev_core_ops csiphy_core_ops = { 727 .s_power = csiphy_set_power, 728 }; 729 730 static const struct v4l2_subdev_video_ops csiphy_video_ops = { 731 .s_stream = csiphy_set_stream, 732 }; 733 734 static const struct v4l2_subdev_pad_ops csiphy_pad_ops = { 735 .enum_mbus_code = csiphy_enum_mbus_code, 736 .enum_frame_size = csiphy_enum_frame_size, 737 .get_fmt = csiphy_get_format, 738 .set_fmt = csiphy_set_format, 739 }; 740 741 static const struct v4l2_subdev_ops csiphy_v4l2_ops = { 742 .core = &csiphy_core_ops, 743 .video = &csiphy_video_ops, 744 .pad = &csiphy_pad_ops, 745 }; 746 747 static const struct v4l2_subdev_internal_ops csiphy_v4l2_internal_ops = { 748 .open = csiphy_init_formats, 749 }; 750 751 static const struct media_entity_operations csiphy_media_ops = { 752 .link_setup = csiphy_link_setup, 753 .link_validate = v4l2_subdev_link_validate, 754 }; 755 756 /* 757 * msm_csiphy_register_entity - Register subdev node for CSIPHY module 758 * @csiphy: CSIPHY device 759 * @v4l2_dev: V4L2 device 760 * 761 * Return 0 on success or a negative error code otherwise 762 */ 763 int msm_csiphy_register_entity(struct csiphy_device *csiphy, 764 struct v4l2_device *v4l2_dev) 765 { 766 struct v4l2_subdev *sd = &csiphy->subdev; 767 struct media_pad *pads = csiphy->pads; 768 struct device *dev = csiphy->camss->dev; 769 int ret; 770 771 v4l2_subdev_init(sd, &csiphy_v4l2_ops); 772 sd->internal_ops = &csiphy_v4l2_internal_ops; 773 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 774 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d", 775 MSM_CSIPHY_NAME, csiphy->id); 776 v4l2_set_subdevdata(sd, csiphy); 777 778 ret = csiphy_init_formats(sd, NULL); 779 if (ret < 0) { 780 dev_err(dev, "Failed to init format: %d\n", ret); 781 return ret; 782 } 783 784 pads[MSM_CSIPHY_PAD_SINK].flags = MEDIA_PAD_FL_SINK; 785 pads[MSM_CSIPHY_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE; 786 787 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER; 788 sd->entity.ops = &csiphy_media_ops; 789 ret = media_entity_pads_init(&sd->entity, MSM_CSIPHY_PADS_NUM, pads); 790 if (ret < 0) { 791 dev_err(dev, "Failed to init media entity: %d\n", ret); 792 return ret; 793 } 794 795 ret = v4l2_device_register_subdev(v4l2_dev, sd); 796 if (ret < 0) { 797 dev_err(dev, "Failed to register subdev: %d\n", ret); 798 media_entity_cleanup(&sd->entity); 799 } 800 801 return ret; 802 } 803 804 /* 805 * msm_csiphy_unregister_entity - Unregister CSIPHY module subdev node 806 * @csiphy: CSIPHY device 807 */ 808 void msm_csiphy_unregister_entity(struct csiphy_device *csiphy) 809 { 810 v4l2_device_unregister_subdev(&csiphy->subdev); 811 media_entity_cleanup(&csiphy->subdev.entity); 812 } 813