1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy-3ph-1-0.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 11 #include "camss-csiphy.h" 12 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 16 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) 17 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) 18 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) 19 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) 20 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) 21 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) 22 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 23 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n)) 24 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02 25 #define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50 26 #define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n)) 27 #define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa 28 #define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n)) 29 #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2) 30 #define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n)) 31 #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0) 32 #define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n)) 33 #define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2 34 #define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n)) 35 #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0) 36 #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1) 37 #define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n)) 38 #define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1 39 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n)) 40 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 41 42 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n)) 43 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) 44 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) 45 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) 46 47 static void csiphy_hw_version_read(struct csiphy_device *csiphy, 48 struct device *dev) 49 { 50 u32 hw_version; 51 52 writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, 53 csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 54 55 hw_version = readl_relaxed(csiphy->base + 56 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12)); 57 hw_version |= readl_relaxed(csiphy->base + 58 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8; 59 hw_version |= readl_relaxed(csiphy->base + 60 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16; 61 hw_version |= readl_relaxed(csiphy->base + 62 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24; 63 64 dev_err(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); 65 } 66 67 /* 68 * csiphy_reset - Perform software reset on CSIPHY module 69 * @csiphy: CSIPHY device 70 */ 71 static void csiphy_reset(struct csiphy_device *csiphy) 72 { 73 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); 74 usleep_range(5000, 8000); 75 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); 76 } 77 78 static irqreturn_t csiphy_isr(int irq, void *dev) 79 { 80 struct csiphy_device *csiphy = dev; 81 int i; 82 83 for (i = 0; i < 11; i++) { 84 int c = i + 22; 85 u8 val = readl_relaxed(csiphy->base + 86 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i)); 87 88 writel_relaxed(val, csiphy->base + 89 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c)); 90 } 91 92 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); 93 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); 94 95 for (i = 22; i < 33; i++) 96 writel_relaxed(0x0, csiphy->base + 97 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i)); 98 99 return IRQ_HANDLED; 100 } 101 102 /* 103 * csiphy_settle_cnt_calc - Calculate settle count value 104 * 105 * Helper function to calculate settle count value. This is 106 * based on the CSI2 T_hs_settle parameter which in turn 107 * is calculated based on the CSI2 transmitter pixel clock 108 * frequency. 109 * 110 * Return settle count value or 0 if the CSI2 pixel clock 111 * frequency is not available 112 */ 113 static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, 114 u32 timer_clk_rate) 115 { 116 u32 mipi_clock; /* Hz */ 117 u32 ui; /* ps */ 118 u32 timer_period; /* ps */ 119 u32 t_hs_prepare_max; /* ps */ 120 u32 t_hs_settle; /* ps */ 121 u8 settle_cnt; 122 123 mipi_clock = pixel_clock * bpp / (2 * num_lanes); 124 ui = div_u64(1000000000000LL, mipi_clock); 125 ui /= 2; 126 t_hs_prepare_max = 85000 + 6 * ui; 127 t_hs_settle = t_hs_prepare_max; 128 129 timer_period = div_u64(1000000000000LL, timer_clk_rate); 130 settle_cnt = t_hs_settle / timer_period - 6; 131 132 return settle_cnt; 133 } 134 135 static void csiphy_lanes_enable(struct csiphy_device *csiphy, 136 struct csiphy_config *cfg, 137 u32 pixel_clock, u8 bpp, u8 lane_mask) 138 { 139 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; 140 u8 settle_cnt; 141 u8 val, l = 0; 142 int i; 143 144 settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data, 145 csiphy->timer_clk_rate); 146 147 val = BIT(c->clk.pos); 148 for (i = 0; i < c->num_data; i++) 149 val |= BIT(c->data[i].pos * 2); 150 151 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 152 153 val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; 154 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 155 156 for (i = 0; i <= c->num_data; i++) { 157 if (i == c->num_data) 158 l = 7; 159 else 160 l = c->data[i].pos * 2; 161 162 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; 163 val |= 0x17; 164 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); 165 166 val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT; 167 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l)); 168 169 val = settle_cnt; 170 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l)); 171 172 val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM | 173 CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT; 174 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l)); 175 176 val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT; 177 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l)); 178 179 val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT; 180 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l)); 181 182 val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP | 183 CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE; 184 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l)); 185 186 val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP; 187 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l)); 188 189 val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP; 190 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l)); 191 192 val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL; 193 writel_relaxed(val, csiphy->base + 194 CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l)); 195 } 196 197 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; 198 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); 199 200 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS; 201 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l)); 202 203 val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE; 204 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l)); 205 206 val = 0xff; 207 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11)); 208 209 val = 0xff; 210 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12)); 211 212 val = 0xfb; 213 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13)); 214 215 val = 0xff; 216 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14)); 217 218 val = 0x7f; 219 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15)); 220 221 val = 0xff; 222 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16)); 223 224 val = 0xff; 225 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17)); 226 227 val = 0xef; 228 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18)); 229 230 val = 0xff; 231 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19)); 232 233 val = 0xff; 234 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20)); 235 236 val = 0xff; 237 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21)); 238 } 239 240 static void csiphy_lanes_disable(struct csiphy_device *csiphy, 241 struct csiphy_config *cfg) 242 { 243 writel_relaxed(0, csiphy->base + 244 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 245 246 writel_relaxed(0, csiphy->base + 247 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 248 } 249 250 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { 251 .hw_version_read = csiphy_hw_version_read, 252 .reset = csiphy_reset, 253 .lanes_enable = csiphy_lanes_enable, 254 .lanes_disable = csiphy_lanes_disable, 255 .isr = csiphy_isr, 256 }; 257