1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy-3ph-1-0.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 11 #include "camss.h" 12 #include "camss-csiphy.h" 13 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) 19 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) 20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) 21 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) 22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) 23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) 24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5 26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n)) 27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02 28 #define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50 29 #define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n)) 30 #define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa 31 #define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n)) 32 #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2) 33 #define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n)) 34 #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0) 35 #define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n)) 36 #define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2 37 #define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n)) 38 #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0) 39 #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1) 40 #define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n)) 41 #define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1 42 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n)) 43 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 44 45 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n)) 46 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) 47 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) 48 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) 49 50 static void csiphy_hw_version_read(struct csiphy_device *csiphy, 51 struct device *dev) 52 { 53 u32 hw_version; 54 55 writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, 56 csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 57 58 hw_version = readl_relaxed(csiphy->base + 59 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12)); 60 hw_version |= readl_relaxed(csiphy->base + 61 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8; 62 hw_version |= readl_relaxed(csiphy->base + 63 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16; 64 hw_version |= readl_relaxed(csiphy->base + 65 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24; 66 67 dev_err(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); 68 } 69 70 /* 71 * csiphy_reset - Perform software reset on CSIPHY module 72 * @csiphy: CSIPHY device 73 */ 74 static void csiphy_reset(struct csiphy_device *csiphy) 75 { 76 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); 77 usleep_range(5000, 8000); 78 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); 79 } 80 81 static irqreturn_t csiphy_isr(int irq, void *dev) 82 { 83 struct csiphy_device *csiphy = dev; 84 int i; 85 86 for (i = 0; i < 11; i++) { 87 int c = i + 22; 88 u8 val = readl_relaxed(csiphy->base + 89 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i)); 90 91 writel_relaxed(val, csiphy->base + 92 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c)); 93 } 94 95 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); 96 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); 97 98 for (i = 22; i < 33; i++) 99 writel_relaxed(0x0, csiphy->base + 100 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i)); 101 102 return IRQ_HANDLED; 103 } 104 105 /* 106 * csiphy_settle_cnt_calc - Calculate settle count value 107 * 108 * Helper function to calculate settle count value. This is 109 * based on the CSI2 T_hs_settle parameter which in turn 110 * is calculated based on the CSI2 transmitter link frequency. 111 * 112 * Return settle count value or 0 if the CSI2 link frequency 113 * is not available 114 */ 115 static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) 116 { 117 u32 ui; /* ps */ 118 u32 timer_period; /* ps */ 119 u32 t_hs_prepare_max; /* ps */ 120 u32 t_hs_settle; /* ps */ 121 u8 settle_cnt; 122 123 if (link_freq <= 0) 124 return 0; 125 126 ui = div_u64(1000000000000LL, link_freq); 127 ui /= 2; 128 t_hs_prepare_max = 85000 + 6 * ui; 129 t_hs_settle = t_hs_prepare_max; 130 131 timer_period = div_u64(1000000000000LL, timer_clk_rate); 132 settle_cnt = t_hs_settle / timer_period - 6; 133 134 return settle_cnt; 135 } 136 137 static void csiphy_lanes_enable(struct csiphy_device *csiphy, 138 struct csiphy_config *cfg, 139 s64 link_freq, u8 lane_mask) 140 { 141 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; 142 u8 settle_cnt; 143 u8 val, l = 0; 144 int i; 145 146 settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); 147 148 val = BIT(c->clk.pos); 149 for (i = 0; i < c->num_data; i++) 150 val |= BIT(c->data[i].pos * 2); 151 152 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 153 154 val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; 155 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 156 157 for (i = 0; i <= c->num_data; i++) { 158 if (i == c->num_data) 159 l = 7; 160 else 161 l = c->data[i].pos * 2; 162 163 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; 164 val |= 0x17; 165 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); 166 167 val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT; 168 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l)); 169 170 val = settle_cnt; 171 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l)); 172 173 val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM | 174 CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT; 175 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l)); 176 177 val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT; 178 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l)); 179 180 val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT; 181 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l)); 182 183 val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP | 184 CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE; 185 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l)); 186 187 val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP; 188 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l)); 189 190 val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP; 191 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l)); 192 193 val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL; 194 writel_relaxed(val, csiphy->base + 195 CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l)); 196 } 197 198 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; 199 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); 200 201 if (csiphy->camss->version == CAMSS_660) 202 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660; 203 else 204 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS; 205 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l)); 206 207 val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE; 208 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l)); 209 210 val = 0xff; 211 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11)); 212 213 val = 0xff; 214 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12)); 215 216 val = 0xfb; 217 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13)); 218 219 val = 0xff; 220 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14)); 221 222 val = 0x7f; 223 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15)); 224 225 val = 0xff; 226 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16)); 227 228 val = 0xff; 229 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17)); 230 231 val = 0xef; 232 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18)); 233 234 val = 0xff; 235 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19)); 236 237 val = 0xff; 238 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20)); 239 240 val = 0xff; 241 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21)); 242 } 243 244 static void csiphy_lanes_disable(struct csiphy_device *csiphy, 245 struct csiphy_config *cfg) 246 { 247 writel_relaxed(0, csiphy->base + 248 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 249 250 writel_relaxed(0, csiphy->base + 251 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 252 } 253 254 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { 255 .hw_version_read = csiphy_hw_version_read, 256 .reset = csiphy_reset, 257 .lanes_enable = csiphy_lanes_enable, 258 .lanes_disable = csiphy_lanes_disable, 259 .isr = csiphy_isr, 260 }; 261