1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy-3ph-1-0.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 3phase v1.0 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 11 #include "camss.h" 12 #include "camss-csiphy.h" 13 14 #include <linux/delay.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 18 #define CSIPHY_3PH_LNn_CFG1(n) (0x000 + 0x100 * (n)) 19 #define CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG (BIT(7) | BIT(6)) 20 #define CSIPHY_3PH_LNn_CFG2(n) (0x004 + 0x100 * (n)) 21 #define CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT BIT(3) 22 #define CSIPHY_3PH_LNn_CFG3(n) (0x008 + 0x100 * (n)) 23 #define CSIPHY_3PH_LNn_CFG4(n) (0x00c + 0x100 * (n)) 24 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS 0xa4 25 #define CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660 0xa5 26 #define CSIPHY_3PH_LNn_CFG5(n) (0x010 + 0x100 * (n)) 27 #define CSIPHY_3PH_LNn_CFG5_T_HS_DTERM 0x02 28 #define CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT 0x50 29 #define CSIPHY_3PH_LNn_TEST_IMP(n) (0x01c + 0x100 * (n)) 30 #define CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP 0xa 31 #define CSIPHY_3PH_LNn_MISC1(n) (0x028 + 0x100 * (n)) 32 #define CSIPHY_3PH_LNn_MISC1_IS_CLKLANE BIT(2) 33 #define CSIPHY_3PH_LNn_CFG6(n) (0x02c + 0x100 * (n)) 34 #define CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT BIT(0) 35 #define CSIPHY_3PH_LNn_CFG7(n) (0x030 + 0x100 * (n)) 36 #define CSIPHY_3PH_LNn_CFG7_SWI_T_INIT 0x2 37 #define CSIPHY_3PH_LNn_CFG8(n) (0x034 + 0x100 * (n)) 38 #define CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP BIT(0) 39 #define CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE BIT(1) 40 #define CSIPHY_3PH_LNn_CFG9(n) (0x038 + 0x100 * (n)) 41 #define CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP 0x1 42 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15(n) (0x03c + 0x100 * (n)) 43 #define CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL 0xb8 44 45 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(n) (0x800 + 0x4 * (n)) 46 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) 47 #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) 48 #define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(n) (0x8b0 + 0x4 * (n)) 49 50 static void csiphy_hw_version_read(struct csiphy_device *csiphy, 51 struct device *dev) 52 { 53 u32 hw_version; 54 55 writel(CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID, 56 csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 57 58 hw_version = readl_relaxed(csiphy->base + 59 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(12)); 60 hw_version |= readl_relaxed(csiphy->base + 61 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(13)) << 8; 62 hw_version |= readl_relaxed(csiphy->base + 63 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(14)) << 16; 64 hw_version |= readl_relaxed(csiphy->base + 65 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(15)) << 24; 66 67 dev_err(dev, "CSIPHY 3PH HW Version = 0x%08x\n", hw_version); 68 } 69 70 /* 71 * csiphy_reset - Perform software reset on CSIPHY module 72 * @csiphy: CSIPHY device 73 */ 74 static void csiphy_reset(struct csiphy_device *csiphy) 75 { 76 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); 77 usleep_range(5000, 8000); 78 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); 79 } 80 81 static irqreturn_t csiphy_isr(int irq, void *dev) 82 { 83 struct csiphy_device *csiphy = dev; 84 int i; 85 86 for (i = 0; i < 11; i++) { 87 int c = i + 22; 88 u8 val = readl_relaxed(csiphy->base + 89 CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(i)); 90 91 writel_relaxed(val, csiphy->base + 92 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(c)); 93 } 94 95 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); 96 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); 97 98 for (i = 22; i < 33; i++) 99 writel_relaxed(0x0, csiphy->base + 100 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(i)); 101 102 return IRQ_HANDLED; 103 } 104 105 /* 106 * csiphy_settle_cnt_calc - Calculate settle count value 107 * 108 * Helper function to calculate settle count value. This is 109 * based on the CSI2 T_hs_settle parameter which in turn 110 * is calculated based on the CSI2 transmitter pixel clock 111 * frequency. 112 * 113 * Return settle count value or 0 if the CSI2 pixel clock 114 * frequency is not available 115 */ 116 static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes, 117 u32 timer_clk_rate) 118 { 119 u32 mipi_clock; /* Hz */ 120 u32 ui; /* ps */ 121 u32 timer_period; /* ps */ 122 u32 t_hs_prepare_max; /* ps */ 123 u32 t_hs_settle; /* ps */ 124 u8 settle_cnt; 125 126 mipi_clock = pixel_clock * bpp / (2 * num_lanes); 127 ui = div_u64(1000000000000LL, mipi_clock); 128 ui /= 2; 129 t_hs_prepare_max = 85000 + 6 * ui; 130 t_hs_settle = t_hs_prepare_max; 131 132 timer_period = div_u64(1000000000000LL, timer_clk_rate); 133 settle_cnt = t_hs_settle / timer_period - 6; 134 135 return settle_cnt; 136 } 137 138 static void csiphy_lanes_enable(struct csiphy_device *csiphy, 139 struct csiphy_config *cfg, 140 u32 pixel_clock, u8 bpp, u8 lane_mask) 141 { 142 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; 143 u8 settle_cnt; 144 u8 val, l = 0; 145 int i; 146 147 settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data, 148 csiphy->timer_clk_rate); 149 150 val = BIT(c->clk.pos); 151 for (i = 0; i < c->num_data; i++) 152 val |= BIT(c->data[i].pos * 2); 153 154 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 155 156 val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B; 157 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 158 159 for (i = 0; i <= c->num_data; i++) { 160 if (i == c->num_data) 161 l = 7; 162 else 163 l = c->data[i].pos * 2; 164 165 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; 166 val |= 0x17; 167 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); 168 169 val = CSIPHY_3PH_LNn_CFG2_LP_REC_EN_INT; 170 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l)); 171 172 val = settle_cnt; 173 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG3(l)); 174 175 val = CSIPHY_3PH_LNn_CFG5_T_HS_DTERM | 176 CSIPHY_3PH_LNn_CFG5_HS_REC_EQ_FQ_INT; 177 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG5(l)); 178 179 val = CSIPHY_3PH_LNn_CFG6_SWI_FORCE_INIT_EXIT; 180 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG6(l)); 181 182 val = CSIPHY_3PH_LNn_CFG7_SWI_T_INIT; 183 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG7(l)); 184 185 val = CSIPHY_3PH_LNn_CFG8_SWI_SKIP_WAKEUP | 186 CSIPHY_3PH_LNn_CFG8_SKEW_FILTER_ENABLE; 187 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG8(l)); 188 189 val = CSIPHY_3PH_LNn_CFG9_SWI_T_WAKEUP; 190 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG9(l)); 191 192 val = CSIPHY_3PH_LNn_TEST_IMP_HS_TERM_IMP; 193 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_TEST_IMP(l)); 194 195 val = CSIPHY_3PH_LNn_CSI_LANE_CTRL15_SWI_SOT_SYMBOL; 196 writel_relaxed(val, csiphy->base + 197 CSIPHY_3PH_LNn_CSI_LANE_CTRL15(l)); 198 } 199 200 val = CSIPHY_3PH_LNn_CFG1_SWI_REC_DLY_PRG; 201 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); 202 203 if (csiphy->camss->version == CAMSS_660) 204 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS_660; 205 else 206 val = CSIPHY_3PH_LNn_CFG4_T_HS_CLK_MISS; 207 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG4(l)); 208 209 val = CSIPHY_3PH_LNn_MISC1_IS_CLKLANE; 210 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_MISC1(l)); 211 212 val = 0xff; 213 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(11)); 214 215 val = 0xff; 216 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(12)); 217 218 val = 0xfb; 219 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(13)); 220 221 val = 0xff; 222 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(14)); 223 224 val = 0x7f; 225 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(15)); 226 227 val = 0xff; 228 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(16)); 229 230 val = 0xff; 231 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(17)); 232 233 val = 0xef; 234 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(18)); 235 236 val = 0xff; 237 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(19)); 238 239 val = 0xff; 240 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(20)); 241 242 val = 0xff; 243 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(21)); 244 } 245 246 static void csiphy_lanes_disable(struct csiphy_device *csiphy, 247 struct csiphy_config *cfg) 248 { 249 writel_relaxed(0, csiphy->base + 250 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); 251 252 writel_relaxed(0, csiphy->base + 253 CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); 254 } 255 256 const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = { 257 .hw_version_read = csiphy_hw_version_read, 258 .reset = csiphy_reset, 259 .lanes_enable = csiphy_lanes_enable, 260 .lanes_disable = csiphy_lanes_disable, 261 .isr = csiphy_isr, 262 }; 263