1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * camss-csiphy-2ph-1-0.c
4  *
5  * Qualcomm MSM Camera Subsystem - CSIPHY Module 2phase v1.0
6  *
7  * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
8  * Copyright (C) 2016-2018 Linaro Ltd.
9  */
10 
11 #include "camss-csiphy.h"
12 
13 #include <linux/delay.h>
14 #include <linux/interrupt.h>
15 
16 #define CAMSS_CSI_PHY_LNn_CFG2(n)		(0x004 + 0x40 * (n))
17 #define CAMSS_CSI_PHY_LNn_CFG3(n)		(0x008 + 0x40 * (n))
18 #define CAMSS_CSI_PHY_GLBL_RESET		0x140
19 #define CAMSS_CSI_PHY_GLBL_PWR_CFG		0x144
20 #define CAMSS_CSI_PHY_GLBL_IRQ_CMD		0x164
21 #define CAMSS_CSI_PHY_HW_VERSION		0x188
22 #define CAMSS_CSI_PHY_INTERRUPT_STATUSn(n)	(0x18c + 0x4 * (n))
23 #define CAMSS_CSI_PHY_INTERRUPT_MASKn(n)	(0x1ac + 0x4 * (n))
24 #define CAMSS_CSI_PHY_INTERRUPT_CLEARn(n)	(0x1cc + 0x4 * (n))
25 #define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0		0x1ec
26 #define CAMSS_CSI_PHY_T_WAKEUP_CFG0		0x1f4
27 
28 static void csiphy_hw_version_read(struct csiphy_device *csiphy,
29 				   struct device *dev)
30 {
31 	u8 hw_version = readl_relaxed(csiphy->base +
32 				      CAMSS_CSI_PHY_HW_VERSION);
33 
34 	dev_dbg(dev, "CSIPHY HW Version = 0x%02x\n", hw_version);
35 }
36 
37 /*
38  * csiphy_reset - Perform software reset on CSIPHY module
39  * @csiphy: CSIPHY device
40  */
41 static void csiphy_reset(struct csiphy_device *csiphy)
42 {
43 	writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
44 	usleep_range(5000, 8000);
45 	writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
46 }
47 
48 /*
49  * csiphy_settle_cnt_calc - Calculate settle count value
50  *
51  * Helper function to calculate settle count value. This is
52  * based on the CSI2 T_hs_settle parameter which in turn
53  * is calculated based on the CSI2 transmitter pixel clock
54  * frequency.
55  *
56  * Return settle count value or 0 if the CSI2 pixel clock
57  * frequency is not available
58  */
59 static u8 csiphy_settle_cnt_calc(u32 pixel_clock, u8 bpp, u8 num_lanes,
60 				 u32 timer_clk_rate)
61 {
62 	u32 mipi_clock; /* Hz */
63 	u32 ui; /* ps */
64 	u32 timer_period; /* ps */
65 	u32 t_hs_prepare_max; /* ps */
66 	u32 t_hs_prepare_zero_min; /* ps */
67 	u32 t_hs_settle; /* ps */
68 	u8 settle_cnt;
69 
70 	mipi_clock = pixel_clock * bpp / (2 * num_lanes);
71 	ui = div_u64(1000000000000LL, mipi_clock);
72 	ui /= 2;
73 	t_hs_prepare_max = 85000 + 6 * ui;
74 	t_hs_prepare_zero_min = 145000 + 10 * ui;
75 	t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2;
76 
77 	timer_period = div_u64(1000000000000LL, timer_clk_rate);
78 	settle_cnt = t_hs_settle / timer_period - 1;
79 
80 	return settle_cnt;
81 }
82 
83 static void csiphy_lanes_enable(struct csiphy_device *csiphy,
84 				struct csiphy_config *cfg,
85 				u32 pixel_clock, u8 bpp, u8 lane_mask)
86 {
87 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
88 	u8 settle_cnt;
89 	u8 val, l = 0;
90 	int i = 0;
91 
92 	settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data,
93 					    csiphy->timer_clk_rate);
94 
95 	writel_relaxed(0x1, csiphy->base +
96 		       CAMSS_CSI_PHY_GLBL_T_INIT_CFG0);
97 	writel_relaxed(0x1, csiphy->base +
98 		       CAMSS_CSI_PHY_T_WAKEUP_CFG0);
99 
100 	val = 0x1;
101 	val |= lane_mask << 1;
102 	writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
103 
104 	val = cfg->combo_mode << 4;
105 	writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
106 
107 	for (i = 0; i <= c->num_data; i++) {
108 		if (i == c->num_data)
109 			l = c->clk.pos;
110 		else
111 			l = c->data[i].pos;
112 
113 		writel_relaxed(0x10, csiphy->base +
114 			       CAMSS_CSI_PHY_LNn_CFG2(l));
115 		writel_relaxed(settle_cnt, csiphy->base +
116 			       CAMSS_CSI_PHY_LNn_CFG3(l));
117 		writel_relaxed(0x3f, csiphy->base +
118 			       CAMSS_CSI_PHY_INTERRUPT_MASKn(l));
119 		writel_relaxed(0x3f, csiphy->base +
120 			       CAMSS_CSI_PHY_INTERRUPT_CLEARn(l));
121 	}
122 }
123 
124 static void csiphy_lanes_disable(struct csiphy_device *csiphy,
125 				 struct csiphy_config *cfg)
126 {
127 	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
128 	u8 l = 0;
129 	int i = 0;
130 
131 	for (i = 0; i <= c->num_data; i++) {
132 		if (i == c->num_data)
133 			l = c->clk.pos;
134 		else
135 			l = c->data[i].pos;
136 
137 		writel_relaxed(0x0, csiphy->base +
138 			       CAMSS_CSI_PHY_LNn_CFG2(l));
139 	}
140 
141 	writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
142 }
143 
144 /*
145  * csiphy_isr - CSIPHY module interrupt handler
146  * @irq: Interrupt line
147  * @dev: CSIPHY device
148  *
149  * Return IRQ_HANDLED on success
150  */
151 static irqreturn_t csiphy_isr(int irq, void *dev)
152 {
153 	struct csiphy_device *csiphy = dev;
154 	u8 i;
155 
156 	for (i = 0; i < 8; i++) {
157 		u8 val = readl_relaxed(csiphy->base +
158 				       CAMSS_CSI_PHY_INTERRUPT_STATUSn(i));
159 		writel_relaxed(val, csiphy->base +
160 			       CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
161 		writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
162 		writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD);
163 		writel_relaxed(0x0, csiphy->base +
164 			       CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
165 	}
166 
167 	return IRQ_HANDLED;
168 }
169 
170 const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = {
171 	.hw_version_read = csiphy_hw_version_read,
172 	.reset = csiphy_reset,
173 	.lanes_enable = csiphy_lanes_enable,
174 	.lanes_disable = csiphy_lanes_disable,
175 	.isr = csiphy_isr,
176 };
177