1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * camss-csiphy-2ph-1-0.c 4 * 5 * Qualcomm MSM Camera Subsystem - CSIPHY Module 2phase v1.0 6 * 7 * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2016-2018 Linaro Ltd. 9 */ 10 11 #include "camss-csiphy.h" 12 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 17 #define CAMSS_CSI_PHY_LNn_CFG2(n) (0x004 + 0x40 * (n)) 18 #define CAMSS_CSI_PHY_LNn_CFG3(n) (0x008 + 0x40 * (n)) 19 #define CAMSS_CSI_PHY_GLBL_RESET 0x140 20 #define CAMSS_CSI_PHY_GLBL_PWR_CFG 0x144 21 #define CAMSS_CSI_PHY_GLBL_IRQ_CMD 0x164 22 #define CAMSS_CSI_PHY_HW_VERSION 0x188 23 #define CAMSS_CSI_PHY_INTERRUPT_STATUSn(n) (0x18c + 0x4 * (n)) 24 #define CAMSS_CSI_PHY_INTERRUPT_MASKn(n) (0x1ac + 0x4 * (n)) 25 #define CAMSS_CSI_PHY_INTERRUPT_CLEARn(n) (0x1cc + 0x4 * (n)) 26 #define CAMSS_CSI_PHY_GLBL_T_INIT_CFG0 0x1ec 27 #define CAMSS_CSI_PHY_T_WAKEUP_CFG0 0x1f4 28 29 static void csiphy_hw_version_read(struct csiphy_device *csiphy, 30 struct device *dev) 31 { 32 u8 hw_version = readl_relaxed(csiphy->base + 33 CAMSS_CSI_PHY_HW_VERSION); 34 35 dev_dbg(dev, "CSIPHY HW Version = 0x%02x\n", hw_version); 36 } 37 38 /* 39 * csiphy_reset - Perform software reset on CSIPHY module 40 * @csiphy: CSIPHY device 41 */ 42 static void csiphy_reset(struct csiphy_device *csiphy) 43 { 44 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); 45 usleep_range(5000, 8000); 46 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); 47 } 48 49 /* 50 * csiphy_settle_cnt_calc - Calculate settle count value 51 * 52 * Helper function to calculate settle count value. This is 53 * based on the CSI2 T_hs_settle parameter which in turn 54 * is calculated based on the CSI2 transmitter link frequency. 55 * 56 * Return settle count value or 0 if the CSI2 link frequency 57 * is not available 58 */ 59 static u8 csiphy_settle_cnt_calc(s64 link_freq, u32 timer_clk_rate) 60 { 61 u32 ui; /* ps */ 62 u32 timer_period; /* ps */ 63 u32 t_hs_prepare_max; /* ps */ 64 u32 t_hs_prepare_zero_min; /* ps */ 65 u32 t_hs_settle; /* ps */ 66 u8 settle_cnt; 67 68 if (link_freq <= 0) 69 return 0; 70 71 ui = div_u64(1000000000000LL, link_freq); 72 ui /= 2; 73 t_hs_prepare_max = 85000 + 6 * ui; 74 t_hs_prepare_zero_min = 145000 + 10 * ui; 75 t_hs_settle = (t_hs_prepare_max + t_hs_prepare_zero_min) / 2; 76 77 timer_period = div_u64(1000000000000LL, timer_clk_rate); 78 settle_cnt = t_hs_settle / timer_period - 1; 79 80 return settle_cnt; 81 } 82 83 static void csiphy_lanes_enable(struct csiphy_device *csiphy, 84 struct csiphy_config *cfg, 85 s64 link_freq, u8 lane_mask) 86 { 87 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; 88 u8 settle_cnt; 89 u8 val, l = 0; 90 int i = 0; 91 92 settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate); 93 94 writel_relaxed(0x1, csiphy->base + 95 CAMSS_CSI_PHY_GLBL_T_INIT_CFG0); 96 writel_relaxed(0x1, csiphy->base + 97 CAMSS_CSI_PHY_T_WAKEUP_CFG0); 98 99 val = 0x1; 100 val |= lane_mask << 1; 101 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); 102 103 val = cfg->combo_mode << 4; 104 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); 105 106 for (i = 0; i <= c->num_data; i++) { 107 if (i == c->num_data) 108 l = c->clk.pos; 109 else 110 l = c->data[i].pos; 111 112 writel_relaxed(0x10, csiphy->base + 113 CAMSS_CSI_PHY_LNn_CFG2(l)); 114 writel_relaxed(settle_cnt, csiphy->base + 115 CAMSS_CSI_PHY_LNn_CFG3(l)); 116 writel_relaxed(0x3f, csiphy->base + 117 CAMSS_CSI_PHY_INTERRUPT_MASKn(l)); 118 writel_relaxed(0x3f, csiphy->base + 119 CAMSS_CSI_PHY_INTERRUPT_CLEARn(l)); 120 } 121 } 122 123 static void csiphy_lanes_disable(struct csiphy_device *csiphy, 124 struct csiphy_config *cfg) 125 { 126 struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg; 127 u8 l = 0; 128 int i = 0; 129 130 for (i = 0; i <= c->num_data; i++) { 131 if (i == c->num_data) 132 l = c->clk.pos; 133 else 134 l = c->data[i].pos; 135 136 writel_relaxed(0x0, csiphy->base + 137 CAMSS_CSI_PHY_LNn_CFG2(l)); 138 } 139 140 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); 141 } 142 143 /* 144 * csiphy_isr - CSIPHY module interrupt handler 145 * @irq: Interrupt line 146 * @dev: CSIPHY device 147 * 148 * Return IRQ_HANDLED on success 149 */ 150 static irqreturn_t csiphy_isr(int irq, void *dev) 151 { 152 struct csiphy_device *csiphy = dev; 153 u8 i; 154 155 for (i = 0; i < 8; i++) { 156 u8 val = readl_relaxed(csiphy->base + 157 CAMSS_CSI_PHY_INTERRUPT_STATUSn(i)); 158 writel_relaxed(val, csiphy->base + 159 CAMSS_CSI_PHY_INTERRUPT_CLEARn(i)); 160 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD); 161 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_IRQ_CMD); 162 writel_relaxed(0x0, csiphy->base + 163 CAMSS_CSI_PHY_INTERRUPT_CLEARn(i)); 164 } 165 166 return IRQ_HANDLED; 167 } 168 169 const struct csiphy_hw_ops csiphy_ops_2ph_1_0 = { 170 .hw_version_read = csiphy_hw_version_read, 171 .reset = csiphy_reset, 172 .lanes_enable = csiphy_lanes_enable, 173 .lanes_disable = csiphy_lanes_disable, 174 .isr = csiphy_isr, 175 }; 176