1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * V4L2 Capture ISI subdev for i.MX8QXP/QM platform 4 * 5 * ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which 6 * used to process image from camera sensor to memory or DC 7 * Copyright 2019-2020 NXP 8 */ 9 10 #ifndef __MXC_ISI_CORE_H__ 11 #define __MXC_ISI_CORE_H__ 12 13 #include <linux/list.h> 14 #include <linux/mutex.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 #include <linux/videodev2.h> 18 19 #include <media/media-device.h> 20 #include <media/media-entity.h> 21 #include <media/v4l2-async.h> 22 #include <media/v4l2-ctrls.h> 23 #include <media/v4l2-dev.h> 24 #include <media/v4l2-device.h> 25 #include <media/v4l2-subdev.h> 26 #include <media/videobuf2-core.h> 27 #include <media/videobuf2-v4l2.h> 28 29 struct clk_bulk_data; 30 struct dentry; 31 struct device; 32 struct media_intf_devnode; 33 struct regmap; 34 struct v4l2_m2m_dev; 35 36 /* Pipeline pads */ 37 #define MXC_ISI_PIPE_PAD_SINK 0 38 #define MXC_ISI_PIPE_PAD_SOURCE 1 39 #define MXC_ISI_PIPE_PADS_NUM 2 40 41 #define MXC_ISI_MIN_WIDTH 1U 42 #define MXC_ISI_MIN_HEIGHT 1U 43 #define MXC_ISI_MAX_WIDTH_UNCHAINED 2048U 44 #define MXC_ISI_MAX_WIDTH_CHAINED 4096U 45 #define MXC_ISI_MAX_HEIGHT 8191U 46 47 #define MXC_ISI_DEF_WIDTH 1920U 48 #define MXC_ISI_DEF_HEIGHT 1080U 49 #define MXC_ISI_DEF_MBUS_CODE_SINK MEDIA_BUS_FMT_UYVY8_1X16 50 #define MXC_ISI_DEF_MBUS_CODE_SOURCE MEDIA_BUS_FMT_YUV8_1X24 51 #define MXC_ISI_DEF_PIXEL_FORMAT V4L2_PIX_FMT_YUYV 52 #define MXC_ISI_DEF_COLOR_SPACE V4L2_COLORSPACE_SRGB 53 #define MXC_ISI_DEF_YCBCR_ENC V4L2_YCBCR_ENC_601 54 #define MXC_ISI_DEF_QUANTIZATION V4L2_QUANTIZATION_LIM_RANGE 55 #define MXC_ISI_DEF_XFER_FUNC V4L2_XFER_FUNC_SRGB 56 57 #define MXC_ISI_DRIVER_NAME "mxc-isi" 58 #define MXC_ISI_CAPTURE "mxc-isi-cap" 59 #define MXC_ISI_M2M "mxc-isi-m2m" 60 #define MXC_MAX_PLANES 3 61 62 struct mxc_isi_dev; 63 struct mxc_isi_m2m_ctx; 64 65 enum mxc_isi_buf_id { 66 MXC_ISI_BUF1 = 0x0, 67 MXC_ISI_BUF2, 68 }; 69 70 enum mxc_isi_encoding { 71 MXC_ISI_ENC_RAW, 72 MXC_ISI_ENC_RGB, 73 MXC_ISI_ENC_YUV, 74 }; 75 76 enum mxc_isi_input_id { 77 /* Inputs from the crossbar switch range from 0 to 15 */ 78 MXC_ISI_INPUT_MEM = 16, 79 }; 80 81 enum mxc_isi_video_type { 82 MXC_ISI_VIDEO_CAP = BIT(0), 83 MXC_ISI_VIDEO_M2M_OUT = BIT(1), 84 MXC_ISI_VIDEO_M2M_CAP = BIT(2), 85 }; 86 87 struct mxc_isi_format_info { 88 u32 mbus_code; 89 u32 fourcc; 90 enum mxc_isi_video_type type; 91 u32 isi_in_format; 92 u32 isi_out_format; 93 u8 mem_planes; 94 u8 color_planes; 95 u8 depth[MXC_MAX_PLANES]; 96 u8 hsub; 97 u8 vsub; 98 enum mxc_isi_encoding encoding; 99 }; 100 101 struct mxc_isi_bus_format_info { 102 u32 mbus_code; 103 u32 output; 104 u32 pads; 105 enum mxc_isi_encoding encoding; 106 }; 107 108 struct mxc_isi_buffer { 109 struct vb2_v4l2_buffer v4l2_buf; 110 struct list_head list; 111 dma_addr_t dma_addrs[3]; 112 enum mxc_isi_buf_id id; 113 bool discard; 114 }; 115 116 struct mxc_isi_reg { 117 u32 offset; 118 u32 mask; 119 }; 120 121 struct mxc_isi_ier_reg { 122 /* Overflow Y/U/V trigger enable*/ 123 struct mxc_isi_reg oflw_y_buf_en; 124 struct mxc_isi_reg oflw_u_buf_en; 125 struct mxc_isi_reg oflw_v_buf_en; 126 127 /* Excess overflow Y/U/V trigger enable*/ 128 struct mxc_isi_reg excs_oflw_y_buf_en; 129 struct mxc_isi_reg excs_oflw_u_buf_en; 130 struct mxc_isi_reg excs_oflw_v_buf_en; 131 132 /* Panic Y/U/V trigger enable*/ 133 struct mxc_isi_reg panic_y_buf_en; 134 struct mxc_isi_reg panic_v_buf_en; 135 struct mxc_isi_reg panic_u_buf_en; 136 }; 137 138 struct mxc_isi_panic_thd { 139 u32 mask; 140 u32 offset; 141 u32 threshold; 142 }; 143 144 struct mxc_isi_set_thd { 145 struct mxc_isi_panic_thd panic_set_thd_y; 146 struct mxc_isi_panic_thd panic_set_thd_u; 147 struct mxc_isi_panic_thd panic_set_thd_v; 148 }; 149 150 enum model { 151 MXC_ISI_IMX8MN, 152 MXC_ISI_IMX8MP, 153 }; 154 155 struct mxc_isi_plat_data { 156 enum model model; 157 unsigned int num_ports; 158 unsigned int num_channels; 159 unsigned int reg_offset; 160 const struct mxc_isi_ier_reg *ier_reg; 161 const struct mxc_isi_set_thd *set_thd; 162 const struct clk_bulk_data *clks; 163 unsigned int num_clks; 164 bool buf_active_reverse; 165 bool has_gasket; 166 bool has_36bit_dma; 167 }; 168 169 struct mxc_isi_dma_buffer { 170 size_t size; 171 void *addr; 172 dma_addr_t dma; 173 }; 174 175 struct mxc_isi_input { 176 unsigned int enable_count; 177 }; 178 179 struct mxc_isi_crossbar { 180 struct mxc_isi_dev *isi; 181 182 unsigned int num_sinks; 183 unsigned int num_sources; 184 struct mxc_isi_input *inputs; 185 186 struct v4l2_subdev sd; 187 struct media_pad *pads; 188 }; 189 190 struct mxc_isi_video { 191 struct mxc_isi_pipe *pipe; 192 193 struct video_device vdev; 194 struct media_pad pad; 195 196 /* Protects is_streaming, and the vdev and vb2_q operations */ 197 struct mutex lock; 198 bool is_streaming; 199 200 struct v4l2_pix_format_mplane pix; 201 const struct mxc_isi_format_info *fmtinfo; 202 203 struct { 204 struct v4l2_ctrl_handler handler; 205 unsigned int alpha; 206 bool hflip; 207 bool vflip; 208 } ctrls; 209 210 struct vb2_queue vb2_q; 211 struct mxc_isi_buffer buf_discard[3]; 212 struct list_head out_pending; 213 struct list_head out_active; 214 struct list_head out_discard; 215 u32 frame_count; 216 /* Protects out_pending, out_active, out_discard and frame_count */ 217 spinlock_t buf_lock; 218 219 struct mxc_isi_dma_buffer discard_buffer[MXC_MAX_PLANES]; 220 }; 221 222 typedef void(*mxc_isi_pipe_irq_t)(struct mxc_isi_pipe *, u32); 223 224 struct mxc_isi_pipe { 225 struct mxc_isi_dev *isi; 226 u32 id; 227 void __iomem *regs; 228 229 struct media_pipeline pipe; 230 231 struct v4l2_subdev sd; 232 struct media_pad pads[MXC_ISI_PIPE_PADS_NUM]; 233 234 struct mxc_isi_video video; 235 236 /* 237 * Protects use_count, irq_handler, res_available, res_acquired, 238 * chained_res, and the CHNL_CTRL register. 239 */ 240 struct mutex lock; 241 unsigned int use_count; 242 mxc_isi_pipe_irq_t irq_handler; 243 244 #define MXC_ISI_CHANNEL_RES_LINE_BUF BIT(0) 245 #define MXC_ISI_CHANNEL_RES_OUTPUT_BUF BIT(1) 246 u8 available_res; 247 u8 acquired_res; 248 u8 chained_res; 249 bool chained; 250 }; 251 252 struct mxc_isi_m2m { 253 struct mxc_isi_dev *isi; 254 struct mxc_isi_pipe *pipe; 255 256 struct media_pad pad; 257 struct video_device vdev; 258 struct media_intf_devnode *intf; 259 struct v4l2_m2m_dev *m2m_dev; 260 261 /* Protects last_ctx, usage_count and chained_count */ 262 struct mutex lock; 263 264 struct mxc_isi_m2m_ctx *last_ctx; 265 int usage_count; 266 int chained_count; 267 }; 268 269 struct mxc_isi_dev { 270 struct device *dev; 271 272 const struct mxc_isi_plat_data *pdata; 273 274 void __iomem *regs; 275 struct clk_bulk_data *clks; 276 struct regmap *gasket; 277 278 struct mxc_isi_crossbar crossbar; 279 struct mxc_isi_pipe *pipes; 280 struct mxc_isi_m2m m2m; 281 282 struct media_device media_dev; 283 struct v4l2_device v4l2_dev; 284 struct v4l2_async_notifier notifier; 285 286 struct dentry *debugfs_root; 287 }; 288 289 int mxc_isi_crossbar_init(struct mxc_isi_dev *isi); 290 void mxc_isi_crossbar_cleanup(struct mxc_isi_crossbar *xbar); 291 int mxc_isi_crossbar_register(struct mxc_isi_crossbar *xbar); 292 void mxc_isi_crossbar_unregister(struct mxc_isi_crossbar *xbar); 293 294 const struct mxc_isi_bus_format_info * 295 mxc_isi_bus_format_by_code(u32 code, unsigned int pad); 296 const struct mxc_isi_bus_format_info * 297 mxc_isi_bus_format_by_index(unsigned int index, unsigned int pad); 298 const struct mxc_isi_format_info * 299 mxc_isi_format_by_fourcc(u32 fourcc, enum mxc_isi_video_type type); 300 const struct mxc_isi_format_info * 301 mxc_isi_format_enum(unsigned int index, enum mxc_isi_video_type type); 302 const struct mxc_isi_format_info * 303 mxc_isi_format_try(struct mxc_isi_pipe *pipe, struct v4l2_pix_format_mplane *pix, 304 enum mxc_isi_video_type type); 305 306 int mxc_isi_pipe_init(struct mxc_isi_dev *isi, unsigned int id); 307 void mxc_isi_pipe_cleanup(struct mxc_isi_pipe *pipe); 308 int mxc_isi_pipe_acquire(struct mxc_isi_pipe *pipe, 309 mxc_isi_pipe_irq_t irq_handler); 310 void mxc_isi_pipe_release(struct mxc_isi_pipe *pipe); 311 int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe); 312 void mxc_isi_pipe_disable(struct mxc_isi_pipe *pipe); 313 314 int mxc_isi_video_register(struct mxc_isi_pipe *pipe, 315 struct v4l2_device *v4l2_dev); 316 void mxc_isi_video_unregister(struct mxc_isi_pipe *pipe); 317 void mxc_isi_video_suspend(struct mxc_isi_pipe *pipe); 318 int mxc_isi_video_resume(struct mxc_isi_pipe *pipe); 319 int mxc_isi_video_queue_setup(const struct v4l2_pix_format_mplane *format, 320 const struct mxc_isi_format_info *info, 321 unsigned int *num_buffers, 322 unsigned int *num_planes, unsigned int sizes[]); 323 void mxc_isi_video_buffer_init(struct vb2_buffer *vb2, dma_addr_t dma_addrs[3], 324 const struct mxc_isi_format_info *info, 325 const struct v4l2_pix_format_mplane *pix); 326 int mxc_isi_video_buffer_prepare(struct mxc_isi_dev *isi, struct vb2_buffer *vb2, 327 const struct mxc_isi_format_info *info, 328 const struct v4l2_pix_format_mplane *pix); 329 330 #ifdef CONFIG_VIDEO_IMX8_ISI_M2M 331 int mxc_isi_m2m_register(struct mxc_isi_dev *isi, struct v4l2_device *v4l2_dev); 332 int mxc_isi_m2m_unregister(struct mxc_isi_dev *isi); 333 #else 334 static inline int mxc_isi_m2m_register(struct mxc_isi_dev *isi, 335 struct v4l2_device *v4l2_dev) 336 { 337 return 0; 338 } 339 static inline int mxc_isi_m2m_unregister(struct mxc_isi_dev *isi) 340 { 341 return 0; 342 } 343 #endif 344 345 int mxc_isi_channel_acquire(struct mxc_isi_pipe *pipe, 346 mxc_isi_pipe_irq_t irq_handler, bool bypass); 347 void mxc_isi_channel_release(struct mxc_isi_pipe *pipe); 348 void mxc_isi_channel_get(struct mxc_isi_pipe *pipe); 349 void mxc_isi_channel_put(struct mxc_isi_pipe *pipe); 350 void mxc_isi_channel_enable(struct mxc_isi_pipe *pipe); 351 void mxc_isi_channel_disable(struct mxc_isi_pipe *pipe); 352 int mxc_isi_channel_chain(struct mxc_isi_pipe *pipe, bool bypass); 353 void mxc_isi_channel_unchain(struct mxc_isi_pipe *pipe); 354 355 void mxc_isi_channel_config(struct mxc_isi_pipe *pipe, 356 enum mxc_isi_input_id input, 357 const struct v4l2_area *in_size, 358 const struct v4l2_area *scale, 359 const struct v4l2_rect *crop, 360 enum mxc_isi_encoding in_encoding, 361 enum mxc_isi_encoding out_encoding); 362 363 void mxc_isi_channel_set_input_format(struct mxc_isi_pipe *pipe, 364 const struct mxc_isi_format_info *info, 365 const struct v4l2_pix_format_mplane *format); 366 void mxc_isi_channel_set_output_format(struct mxc_isi_pipe *pipe, 367 const struct mxc_isi_format_info *info, 368 struct v4l2_pix_format_mplane *format); 369 void mxc_isi_channel_m2m_start(struct mxc_isi_pipe *pipe); 370 371 void mxc_isi_channel_set_alpha(struct mxc_isi_pipe *pipe, u8 alpha); 372 void mxc_isi_channel_set_flip(struct mxc_isi_pipe *pipe, bool hflip, bool vflip); 373 374 void mxc_isi_channel_set_inbuf(struct mxc_isi_pipe *pipe, dma_addr_t dma_addr); 375 void mxc_isi_channel_set_outbuf(struct mxc_isi_pipe *pipe, 376 const dma_addr_t dma_addrs[3], 377 enum mxc_isi_buf_id buf_id); 378 379 u32 mxc_isi_channel_irq_status(struct mxc_isi_pipe *pipe, bool clear); 380 void mxc_isi_channel_irq_clear(struct mxc_isi_pipe *pipe); 381 382 #if IS_ENABLED(CONFIG_DEBUG_FS) 383 void mxc_isi_debug_init(struct mxc_isi_dev *isi); 384 void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi); 385 #else 386 static inline void mxc_isi_debug_init(struct mxc_isi_dev *isi) 387 { 388 } 389 static inline void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi) 390 { 391 } 392 #endif 393 394 #endif /* __MXC_ISI_CORE_H__ */ 395