1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Samsung CSIS MIPI CSI-2 receiver driver.
4  *
5  * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and
6  * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features
7  * version 3.6.3.
8  *
9  * Copyright (C) 2019 Linaro Ltd
10  * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
11  * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
12  *
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/debugfs.h>
17 #include <linux/delay.h>
18 #include <linux/errno.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/reset.h>
30 #include <linux/spinlock.h>
31 
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-device.h>
34 #include <media/v4l2-fwnode.h>
35 #include <media/v4l2-mc.h>
36 #include <media/v4l2-subdev.h>
37 
38 #define CSIS_DRIVER_NAME			"imx-mipi-csis"
39 
40 #define CSIS_PAD_SINK				0
41 #define CSIS_PAD_SOURCE				1
42 #define CSIS_PADS_NUM				2
43 
44 #define MIPI_CSIS_DEF_PIX_WIDTH			640
45 #define MIPI_CSIS_DEF_PIX_HEIGHT		480
46 
47 /* Register map definition */
48 
49 /* CSIS common control */
50 #define MIPI_CSIS_CMN_CTRL			0x04
51 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW	BIT(16)
52 #define MIPI_CSIS_CMN_CTRL_INTER_MODE		BIT(10)
53 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL	BIT(2)
54 #define MIPI_CSIS_CMN_CTRL_RESET		BIT(1)
55 #define MIPI_CSIS_CMN_CTRL_ENABLE		BIT(0)
56 
57 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET	8
58 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK		(3 << 8)
59 
60 /* CSIS clock control */
61 #define MIPI_CSIS_CLK_CTRL			0x08
62 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x)	((x) << 28)
63 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x)	((x) << 24)
64 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x)	((x) << 20)
65 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x)	((x) << 16)
66 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK	(0xf << 4)
67 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC		BIT(0)
68 
69 /* CSIS Interrupt mask */
70 #define MIPI_CSIS_INT_MSK			0x10
71 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE		BIT(31)
72 #define MIPI_CSIS_INT_MSK_EVEN_AFTER		BIT(30)
73 #define MIPI_CSIS_INT_MSK_ODD_BEFORE		BIT(29)
74 #define MIPI_CSIS_INT_MSK_ODD_AFTER		BIT(28)
75 #define MIPI_CSIS_INT_MSK_FRAME_START		BIT(24)
76 #define MIPI_CSIS_INT_MSK_FRAME_END		BIT(20)
77 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS		BIT(16)
78 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS		BIT(12)
79 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE		BIT(8)
80 #define MIPI_CSIS_INT_MSK_ERR_OVER		BIT(4)
81 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG		BIT(3)
82 #define MIPI_CSIS_INT_MSK_ERR_ECC		BIT(2)
83 #define MIPI_CSIS_INT_MSK_ERR_CRC		BIT(1)
84 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN		BIT(0)
85 
86 /* CSIS Interrupt source */
87 #define MIPI_CSIS_INT_SRC			0x14
88 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE		BIT(31)
89 #define MIPI_CSIS_INT_SRC_EVEN_AFTER		BIT(30)
90 #define MIPI_CSIS_INT_SRC_EVEN			BIT(30)
91 #define MIPI_CSIS_INT_SRC_ODD_BEFORE		BIT(29)
92 #define MIPI_CSIS_INT_SRC_ODD_AFTER		BIT(28)
93 #define MIPI_CSIS_INT_SRC_ODD			(0x3 << 28)
94 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA	(0xf << 28)
95 #define MIPI_CSIS_INT_SRC_FRAME_START		BIT(24)
96 #define MIPI_CSIS_INT_SRC_FRAME_END		BIT(20)
97 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS		BIT(16)
98 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS		BIT(12)
99 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE		BIT(8)
100 #define MIPI_CSIS_INT_SRC_ERR_OVER		BIT(4)
101 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG		BIT(3)
102 #define MIPI_CSIS_INT_SRC_ERR_ECC		BIT(2)
103 #define MIPI_CSIS_INT_SRC_ERR_CRC		BIT(1)
104 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN		BIT(0)
105 #define MIPI_CSIS_INT_SRC_ERRORS		0xfffff
106 
107 /* D-PHY status control */
108 #define MIPI_CSIS_DPHY_STATUS			0x20
109 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT		BIT(8)
110 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT	BIT(4)
111 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK		BIT(1)
112 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK	BIT(0)
113 
114 /* D-PHY common control */
115 #define MIPI_CSIS_DPHY_CMN_CTRL			0x24
116 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n)	((n) << 24)
117 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK	GENMASK(31, 24)
118 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n)	((n) << 22)
119 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK	GENMASK(23, 22)
120 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK	BIT(6)
121 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT	BIT(5)
122 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT	BIT(1)
123 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK	BIT(0)
124 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE		(0x1f << 0)
125 
126 /* D-PHY Master and Slave Control register Low */
127 #define MIPI_CSIS_DPHY_BCTRL_L			0x30
128 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n)		(((n) & 3U) << 30)
129 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV		(0 << 28)
130 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV		(1 << 28)
131 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV		(2 << 28)
132 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV		(3 << 28)
133 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ		(0 << 27)
134 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ		(1 << 27)
135 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL		BIT(26)
136 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V		(0 << 24)
137 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V		(1 << 24)
138 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V		(2 << 24)
139 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V		(3 << 24)
140 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL			BIT(23)
141 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV		(0 << 21)
142 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV		(1 << 21)
143 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV		(2 << 21)
144 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV		(3 << 21)
145 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL			BIT(20)
146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV		(0 << 18)
147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV		(1 << 18)
148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV		(2 << 18)
149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV		(3 << 18)
150 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT		BIT(17)
151 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0	(0 << 15)
152 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P	(1 << 15)
153 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P	(3 << 15)
154 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP		BIT(14)
155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV			(0 << 13)
156 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV			(1 << 13)
157 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN			BIT(12)
158 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN		BIT(11)
159 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN			BIT(10)
160 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n)			(((n) * 25 / 1000000) << 0)
161 
162 /* D-PHY Master and Slave Control register High */
163 #define MIPI_CSIS_DPHY_BCTRL_H			0x34
164 /* D-PHY Slave Control register Low */
165 #define MIPI_CSIS_DPHY_SCTRL_L			0x38
166 /* D-PHY Slave Control register High */
167 #define MIPI_CSIS_DPHY_SCTRL_H			0x3c
168 
169 /* ISP Configuration register */
170 #define MIPI_CSIS_ISP_CONFIG_CH(n)		(0x40 + (n) * 0x10)
171 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK	(0xff << 24)
172 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)	((x) << 24)
173 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE	(0 << 12)
174 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL	(1 << 12)
175 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD	(2 << 12)	/* i.MX8M[MNP] only */
176 #define MIPI_CSIS_ISPCFG_PIXEL_MASK		(3 << 12)
177 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT		BIT(11)
178 #define MIPI_CSIS_ISPCFG_FMT(fmt)		((fmt) << 2)
179 #define MIPI_CSIS_ISPCFG_FMT_MASK		(0x3f << 2)
180 
181 /* ISP Image Resolution register */
182 #define MIPI_CSIS_ISP_RESOL_CH(n)		(0x44 + (n) * 0x10)
183 #define CSIS_MAX_PIX_WIDTH			0xffff
184 #define CSIS_MAX_PIX_HEIGHT			0xffff
185 
186 /* ISP SYNC register */
187 #define MIPI_CSIS_ISP_SYNC_CH(n)		(0x48 + (n) * 0x10)
188 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET	18
189 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET	12
190 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET	0
191 
192 /* ISP shadow registers */
193 #define MIPI_CSIS_SDW_CONFIG_CH(n)		(0x80 + (n) * 0x10)
194 #define MIPI_CSIS_SDW_RESOL_CH(n)		(0x84 + (n) * 0x10)
195 #define MIPI_CSIS_SDW_SYNC_CH(n)		(0x88 + (n) * 0x10)
196 
197 /* Debug control register */
198 #define MIPI_CSIS_DBG_CTRL			0xc0
199 #define MIPI_CSIS_DBG_INTR_MSK			0xc4
200 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT	BIT(25)
201 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE	BIT(24)
202 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE	BIT(20)
203 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME	BIT(16)
204 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE		BIT(12)
205 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS		BIT(8)
206 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL	BIT(4)
207 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE	BIT(0)
208 #define MIPI_CSIS_DBG_INTR_SRC			0xc8
209 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT	BIT(25)
210 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE	BIT(24)
211 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE	BIT(20)
212 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME	BIT(16)
213 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE		BIT(12)
214 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS		BIT(8)
215 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL	BIT(4)
216 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE	BIT(0)
217 
218 #define MIPI_CSIS_FRAME_COUNTER_CH(n)		(0x0100 + (n) * 4)
219 
220 /* Non-image packet data buffers */
221 #define MIPI_CSIS_PKTDATA_ODD			0x2000
222 #define MIPI_CSIS_PKTDATA_EVEN			0x3000
223 #define MIPI_CSIS_PKTDATA_SIZE			SZ_4K
224 
225 #define DEFAULT_SCLK_CSIS_FREQ			166000000UL
226 
227 /* MIPI CSI-2 Data Types */
228 #define MIPI_CSI2_DATA_TYPE_YUV420_8		0x18
229 #define MIPI_CSI2_DATA_TYPE_YUV420_10		0x19
230 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8		0x1a
231 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8		0x1c
232 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10	0x1d
233 #define MIPI_CSI2_DATA_TYPE_YUV422_8		0x1e
234 #define MIPI_CSI2_DATA_TYPE_YUV422_10		0x1f
235 #define MIPI_CSI2_DATA_TYPE_RGB565		0x22
236 #define MIPI_CSI2_DATA_TYPE_RGB666		0x23
237 #define MIPI_CSI2_DATA_TYPE_RGB888		0x24
238 #define MIPI_CSI2_DATA_TYPE_RAW6		0x28
239 #define MIPI_CSI2_DATA_TYPE_RAW7		0x29
240 #define MIPI_CSI2_DATA_TYPE_RAW8		0x2a
241 #define MIPI_CSI2_DATA_TYPE_RAW10		0x2b
242 #define MIPI_CSI2_DATA_TYPE_RAW12		0x2c
243 #define MIPI_CSI2_DATA_TYPE_RAW14		0x2d
244 #define MIPI_CSI2_DATA_TYPE_USER(x)		(0x30 + (x))
245 
246 struct mipi_csis_event {
247 	bool debug;
248 	u32 mask;
249 	const char * const name;
250 	unsigned int counter;
251 };
252 
253 static const struct mipi_csis_event mipi_csis_events[] = {
254 	/* Errors */
255 	{ false, MIPI_CSIS_INT_SRC_ERR_SOT_HS,		"SOT Error" },
256 	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,		"Lost Frame Start Error" },
257 	{ false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,		"Lost Frame End Error" },
258 	{ false, MIPI_CSIS_INT_SRC_ERR_OVER,		"FIFO Overflow Error" },
259 	{ false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,	"Wrong Configuration Error" },
260 	{ false, MIPI_CSIS_INT_SRC_ERR_ECC,		"ECC Error" },
261 	{ false, MIPI_CSIS_INT_SRC_ERR_CRC,		"CRC Error" },
262 	{ false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN,		"Unknown Error" },
263 	{ true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,	"Data Type Not Supported" },
264 	{ true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,	"Data Type Ignored" },
265 	{ true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,	"Frame Size Error" },
266 	{ true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME,	"Truncated Frame" },
267 	{ true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE,	"Early Frame End" },
268 	{ true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS,	"Early Frame Start" },
269 	/* Non-image data receive events */
270 	{ false, MIPI_CSIS_INT_SRC_EVEN_BEFORE,		"Non-image data before even frame" },
271 	{ false, MIPI_CSIS_INT_SRC_EVEN_AFTER,		"Non-image data after even frame" },
272 	{ false, MIPI_CSIS_INT_SRC_ODD_BEFORE,		"Non-image data before odd frame" },
273 	{ false, MIPI_CSIS_INT_SRC_ODD_AFTER,		"Non-image data after odd frame" },
274 	/* Frame start/end */
275 	{ false, MIPI_CSIS_INT_SRC_FRAME_START,		"Frame Start" },
276 	{ false, MIPI_CSIS_INT_SRC_FRAME_END,		"Frame End" },
277 	{ true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL,	"VSYNC Falling Edge" },
278 	{ true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE,	"VSYNC Rising Edge" },
279 };
280 
281 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
282 
283 enum mipi_csis_clk {
284 	MIPI_CSIS_CLK_PCLK,
285 	MIPI_CSIS_CLK_WRAP,
286 	MIPI_CSIS_CLK_PHY,
287 	MIPI_CSIS_CLK_AXI,
288 };
289 
290 static const char * const mipi_csis_clk_id[] = {
291 	"pclk",
292 	"wrap",
293 	"phy",
294 	"axi",
295 };
296 
297 enum mipi_csis_version {
298 	MIPI_CSIS_V3_3,
299 	MIPI_CSIS_V3_6_3,
300 };
301 
302 struct mipi_csis_info {
303 	enum mipi_csis_version version;
304 	unsigned int num_clocks;
305 };
306 
307 struct mipi_csis_device {
308 	struct device *dev;
309 	void __iomem *regs;
310 	struct clk_bulk_data *clks;
311 	struct reset_control *mrst;
312 	struct regulator *mipi_phy_regulator;
313 	const struct mipi_csis_info *info;
314 
315 	struct v4l2_subdev sd;
316 	struct media_pad pads[CSIS_PADS_NUM];
317 	struct v4l2_async_notifier notifier;
318 	struct v4l2_subdev *src_sd;
319 
320 	struct v4l2_mbus_config_mipi_csi2 bus;
321 	u32 clk_frequency;
322 	u32 hs_settle;
323 	u32 clk_settle;
324 
325 	struct mutex lock;	/* Protect csis_fmt and format_mbus */
326 	const struct csis_pix_format *csis_fmt;
327 	struct v4l2_mbus_framefmt format_mbus[CSIS_PADS_NUM];
328 
329 	spinlock_t slock;	/* Protect events */
330 	struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
331 	struct dentry *debugfs_root;
332 	struct {
333 		bool enable;
334 		u32 hs_settle;
335 		u32 clk_settle;
336 	} debug;
337 };
338 
339 /* -----------------------------------------------------------------------------
340  * Format helpers
341  */
342 
343 struct csis_pix_format {
344 	u32 code;
345 	u32 output;
346 	u32 data_type;
347 	u8 width;
348 };
349 
350 static const struct csis_pix_format mipi_csis_formats[] = {
351 	/* YUV formats. */
352 	{
353 		.code = MEDIA_BUS_FMT_UYVY8_1X16,
354 		.output = MEDIA_BUS_FMT_UYVY8_1X16,
355 		.data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
356 		.width = 16,
357 	},
358 	/* RGB formats. */
359 	{
360 		.code = MEDIA_BUS_FMT_RGB565_1X16,
361 		.output = MEDIA_BUS_FMT_RGB565_1X16,
362 		.data_type = MIPI_CSI2_DATA_TYPE_RGB565,
363 		.width = 16,
364 	}, {
365 		.code = MEDIA_BUS_FMT_BGR888_1X24,
366 		.output = MEDIA_BUS_FMT_RGB888_1X24,
367 		.data_type = MIPI_CSI2_DATA_TYPE_RGB888,
368 		.width = 24,
369 	},
370 	/* RAW (Bayer and greyscale) formats. */
371 	{
372 		.code = MEDIA_BUS_FMT_SBGGR8_1X8,
373 		.output = MEDIA_BUS_FMT_SBGGR8_1X8,
374 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
375 		.width = 8,
376 	}, {
377 		.code = MEDIA_BUS_FMT_SGBRG8_1X8,
378 		.output = MEDIA_BUS_FMT_SGBRG8_1X8,
379 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
380 		.width = 8,
381 	}, {
382 		.code = MEDIA_BUS_FMT_SGRBG8_1X8,
383 		.output = MEDIA_BUS_FMT_SGRBG8_1X8,
384 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
385 		.width = 8,
386 	}, {
387 		.code = MEDIA_BUS_FMT_SRGGB8_1X8,
388 		.output = MEDIA_BUS_FMT_SRGGB8_1X8,
389 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
390 		.width = 8,
391 	}, {
392 		.code = MEDIA_BUS_FMT_Y8_1X8,
393 		.output = MEDIA_BUS_FMT_Y8_1X8,
394 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
395 		.width = 8,
396 	}, {
397 		.code = MEDIA_BUS_FMT_SBGGR10_1X10,
398 		.output = MEDIA_BUS_FMT_SBGGR10_1X10,
399 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
400 		.width = 10,
401 	}, {
402 		.code = MEDIA_BUS_FMT_SGBRG10_1X10,
403 		.output = MEDIA_BUS_FMT_SGBRG10_1X10,
404 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
405 		.width = 10,
406 	}, {
407 		.code = MEDIA_BUS_FMT_SGRBG10_1X10,
408 		.output = MEDIA_BUS_FMT_SGRBG10_1X10,
409 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
410 		.width = 10,
411 	}, {
412 		.code = MEDIA_BUS_FMT_SRGGB10_1X10,
413 		.output = MEDIA_BUS_FMT_SRGGB10_1X10,
414 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
415 		.width = 10,
416 	}, {
417 		.code = MEDIA_BUS_FMT_Y10_1X10,
418 		.output = MEDIA_BUS_FMT_Y10_1X10,
419 		.data_type = MIPI_CSI2_DATA_TYPE_RAW10,
420 		.width = 10,
421 	}, {
422 		.code = MEDIA_BUS_FMT_SBGGR12_1X12,
423 		.output = MEDIA_BUS_FMT_SBGGR12_1X12,
424 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
425 		.width = 12,
426 	}, {
427 		.code = MEDIA_BUS_FMT_SGBRG12_1X12,
428 		.output = MEDIA_BUS_FMT_SGBRG12_1X12,
429 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
430 		.width = 12,
431 	}, {
432 		.code = MEDIA_BUS_FMT_SGRBG12_1X12,
433 		.output = MEDIA_BUS_FMT_SGRBG12_1X12,
434 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
435 		.width = 12,
436 	}, {
437 		.code = MEDIA_BUS_FMT_SRGGB12_1X12,
438 		.output = MEDIA_BUS_FMT_SRGGB12_1X12,
439 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
440 		.width = 12,
441 	}, {
442 		.code = MEDIA_BUS_FMT_Y12_1X12,
443 		.output = MEDIA_BUS_FMT_Y12_1X12,
444 		.data_type = MIPI_CSI2_DATA_TYPE_RAW12,
445 		.width = 12,
446 	}, {
447 		.code = MEDIA_BUS_FMT_SBGGR14_1X14,
448 		.output = MEDIA_BUS_FMT_SBGGR14_1X14,
449 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
450 		.width = 14,
451 	}, {
452 		.code = MEDIA_BUS_FMT_SGBRG14_1X14,
453 		.output = MEDIA_BUS_FMT_SGBRG14_1X14,
454 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
455 		.width = 14,
456 	}, {
457 		.code = MEDIA_BUS_FMT_SGRBG14_1X14,
458 		.output = MEDIA_BUS_FMT_SGRBG14_1X14,
459 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
460 		.width = 14,
461 	}, {
462 		.code = MEDIA_BUS_FMT_SRGGB14_1X14,
463 		.output = MEDIA_BUS_FMT_SRGGB14_1X14,
464 		.data_type = MIPI_CSI2_DATA_TYPE_RAW14,
465 		.width = 14,
466 	},
467 	/* JPEG */
468 	{
469 		.code = MEDIA_BUS_FMT_JPEG_1X8,
470 		.output = MEDIA_BUS_FMT_JPEG_1X8,
471 		/*
472 		 * Map JPEG_1X8 to the RAW8 datatype.
473 		 *
474 		 * The CSI-2 specification suggests in Annex A "JPEG8 Data
475 		 * Format (informative)" to transmit JPEG data using one of the
476 		 * Data Types aimed to represent arbitrary data, such as the
477 		 * "User Defined Data Type 1" (0x30).
478 		 *
479 		 * However, when configured with a User Defined Data Type, the
480 		 * CSIS outputs data in quad pixel mode regardless of the mode
481 		 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of
482 		 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge
483 		 * or ISI) support quad pixel mode, so this will never work in
484 		 * practice.
485 		 *
486 		 * Some sensors (such as the OV5640) send JPEG data using the
487 		 * RAW8 data type. This is usable and works, so map the JPEG
488 		 * format to RAW8. If the CSIS ends up being integrated in an
489 		 * SoC that can support quad pixel mode, this will have to be
490 		 * revisited.
491 		 */
492 		.data_type = MIPI_CSI2_DATA_TYPE_RAW8,
493 		.width = 8,
494 	}
495 };
496 
497 static const struct csis_pix_format *find_csis_format(u32 code)
498 {
499 	unsigned int i;
500 
501 	for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
502 		if (code == mipi_csis_formats[i].code)
503 			return &mipi_csis_formats[i];
504 	return NULL;
505 }
506 
507 /* -----------------------------------------------------------------------------
508  * Hardware configuration
509  */
510 
511 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg)
512 {
513 	return readl(csis->regs + reg);
514 }
515 
516 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg,
517 				   u32 val)
518 {
519 	writel(val, csis->regs + reg);
520 }
521 
522 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on)
523 {
524 	mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
525 	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
526 }
527 
528 static void mipi_csis_sw_reset(struct mipi_csis_device *csis)
529 {
530 	u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
531 
532 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
533 			val | MIPI_CSIS_CMN_CTRL_RESET);
534 	usleep_range(10, 20);
535 }
536 
537 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on)
538 {
539 	u32 val, mask;
540 
541 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
542 	if (on)
543 		val |= MIPI_CSIS_CMN_CTRL_ENABLE;
544 	else
545 		val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
546 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
547 
548 	val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL);
549 	val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
550 	if (on) {
551 		mask = (1 << (csis->bus.num_data_lanes + 1)) - 1;
552 		val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
553 	}
554 	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val);
555 }
556 
557 /* Called with the csis.lock mutex held */
558 static void __mipi_csis_set_format(struct mipi_csis_device *csis)
559 {
560 	struct v4l2_mbus_framefmt *mf = &csis->format_mbus[CSIS_PAD_SINK];
561 	u32 val;
562 
563 	/* Color format */
564 	val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0));
565 	val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK
566 		| MIPI_CSIS_ISPCFG_PIXEL_MASK);
567 
568 	/*
569 	 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample
570 	 * (referred to in the documentation as single and dual pixel modes
571 	 * respectively, although the 8-bit mode transfers half a pixel per
572 	 * clock sample and the 16-bit mode one pixel). While both mode work
573 	 * when the CSIS is connected to a receiver that supports either option,
574 	 * single pixel mode requires clock rates twice as high. As all SoCs
575 	 * that integrate the CSIS can operate in 16-bit bit mode, and some do
576 	 * not support 8-bit mode (this is the case of the i.MX8MP), use dual
577 	 * pixel mode unconditionally.
578 	 *
579 	 * TODO: Verify which other formats require DUAL (or QUAD) modes.
580 	 */
581 	if (csis->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8)
582 		val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL;
583 
584 	val |= MIPI_CSIS_ISPCFG_FMT(csis->csis_fmt->data_type);
585 	mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val);
586 
587 	/* Pixel resolution */
588 	val = mf->width | (mf->height << 16);
589 	mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val);
590 }
591 
592 static int mipi_csis_calculate_params(struct mipi_csis_device *csis)
593 {
594 	s64 link_freq;
595 	u32 lane_rate;
596 
597 	/* Calculate the line rate from the pixel rate. */
598 	link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler,
599 				       csis->csis_fmt->width,
600 				       csis->bus.num_data_lanes * 2);
601 	if (link_freq < 0) {
602 		dev_err(csis->dev, "Unable to obtain link frequency: %d\n",
603 			(int)link_freq);
604 		return link_freq;
605 	}
606 
607 	lane_rate = link_freq * 2;
608 
609 	if (lane_rate < 80000000 || lane_rate > 1500000000) {
610 		dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate);
611 		return -EINVAL;
612 	}
613 
614 	/*
615 	 * The HSSETTLE counter value is document in a table, but can also
616 	 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now
617 	 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
618 	 * we figure out how to compute it correctly.
619 	 */
620 	csis->hs_settle = (lane_rate - 5000000) / 45000000;
621 	csis->clk_settle = 0;
622 
623 	dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
624 		lane_rate, csis->clk_settle, csis->hs_settle);
625 
626 	if (csis->debug.hs_settle < 0xff) {
627 		dev_dbg(csis->dev, "overriding Ths_settle with %u\n",
628 			csis->debug.hs_settle);
629 		csis->hs_settle = csis->debug.hs_settle;
630 	}
631 
632 	if (csis->debug.clk_settle < 4) {
633 		dev_dbg(csis->dev, "overriding Tclk_settle with %u\n",
634 			csis->debug.clk_settle);
635 		csis->clk_settle = csis->debug.clk_settle;
636 	}
637 
638 	return 0;
639 }
640 
641 static void mipi_csis_set_params(struct mipi_csis_device *csis)
642 {
643 	int lanes = csis->bus.num_data_lanes;
644 	u32 val;
645 
646 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
647 	val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
648 	val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
649 	if (csis->info->version == MIPI_CSIS_V3_3)
650 		val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
651 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val);
652 
653 	__mipi_csis_set_format(csis);
654 
655 	mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL,
656 			MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) |
657 			MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle));
658 
659 	val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
660 	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
661 	    | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
662 	mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val);
663 
664 	val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL);
665 	val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
666 	val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
667 	val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
668 	mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val);
669 
670 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L,
671 			MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
672 			MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
673 			MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
674 			MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
675 			MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
676 			MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
677 			MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
678 	mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0);
679 
680 	/* Update the shadow register. */
681 	val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL);
682 	mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL,
683 			val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
684 			MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
685 }
686 
687 static int mipi_csis_clk_enable(struct mipi_csis_device *csis)
688 {
689 	return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks);
690 }
691 
692 static void mipi_csis_clk_disable(struct mipi_csis_device *csis)
693 {
694 	clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks);
695 }
696 
697 static int mipi_csis_clk_get(struct mipi_csis_device *csis)
698 {
699 	unsigned int i;
700 	int ret;
701 
702 	csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks,
703 				  sizeof(*csis->clks), GFP_KERNEL);
704 
705 	if (!csis->clks)
706 		return -ENOMEM;
707 
708 	for (i = 0; i < csis->info->num_clocks; i++)
709 		csis->clks[i].id = mipi_csis_clk_id[i];
710 
711 	ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks,
712 				csis->clks);
713 	if (ret < 0)
714 		return ret;
715 
716 	/* Set clock rate */
717 	ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk,
718 			   csis->clk_frequency);
719 	if (ret < 0)
720 		dev_err(csis->dev, "set rate=%d failed: %d\n",
721 			csis->clk_frequency, ret);
722 
723 	return ret;
724 }
725 
726 static void mipi_csis_start_stream(struct mipi_csis_device *csis)
727 {
728 	mipi_csis_sw_reset(csis);
729 	mipi_csis_set_params(csis);
730 	mipi_csis_system_enable(csis, true);
731 	mipi_csis_enable_interrupts(csis, true);
732 }
733 
734 static void mipi_csis_stop_stream(struct mipi_csis_device *csis)
735 {
736 	mipi_csis_enable_interrupts(csis, false);
737 	mipi_csis_system_enable(csis, false);
738 }
739 
740 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
741 {
742 	struct mipi_csis_device *csis = dev_id;
743 	unsigned long flags;
744 	unsigned int i;
745 	u32 status;
746 	u32 dbg_status;
747 
748 	status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC);
749 	dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC);
750 
751 	spin_lock_irqsave(&csis->slock, flags);
752 
753 	/* Update the event/error counters */
754 	if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) {
755 		for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
756 			struct mipi_csis_event *event = &csis->events[i];
757 
758 			if ((!event->debug && (status & event->mask)) ||
759 			    (event->debug && (dbg_status & event->mask)))
760 				event->counter++;
761 		}
762 	}
763 	spin_unlock_irqrestore(&csis->slock, flags);
764 
765 	mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status);
766 	mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
767 
768 	return IRQ_HANDLED;
769 }
770 
771 /* -----------------------------------------------------------------------------
772  * PHY regulator and reset
773  */
774 
775 static int mipi_csis_phy_enable(struct mipi_csis_device *csis)
776 {
777 	if (csis->info->version != MIPI_CSIS_V3_3)
778 		return 0;
779 
780 	return regulator_enable(csis->mipi_phy_regulator);
781 }
782 
783 static int mipi_csis_phy_disable(struct mipi_csis_device *csis)
784 {
785 	if (csis->info->version != MIPI_CSIS_V3_3)
786 		return 0;
787 
788 	return regulator_disable(csis->mipi_phy_regulator);
789 }
790 
791 static void mipi_csis_phy_reset(struct mipi_csis_device *csis)
792 {
793 	if (csis->info->version != MIPI_CSIS_V3_3)
794 		return;
795 
796 	reset_control_assert(csis->mrst);
797 	msleep(20);
798 	reset_control_deassert(csis->mrst);
799 }
800 
801 static int mipi_csis_phy_init(struct mipi_csis_device *csis)
802 {
803 	if (csis->info->version != MIPI_CSIS_V3_3)
804 		return 0;
805 
806 	/* Get MIPI PHY reset and regulator. */
807 	csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL);
808 	if (IS_ERR(csis->mrst))
809 		return PTR_ERR(csis->mrst);
810 
811 	csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy");
812 	if (IS_ERR(csis->mipi_phy_regulator))
813 		return PTR_ERR(csis->mipi_phy_regulator);
814 
815 	return regulator_set_voltage(csis->mipi_phy_regulator, 1000000,
816 				     1000000);
817 }
818 
819 /* -----------------------------------------------------------------------------
820  * Debug
821  */
822 
823 static void mipi_csis_clear_counters(struct mipi_csis_device *csis)
824 {
825 	unsigned long flags;
826 	unsigned int i;
827 
828 	spin_lock_irqsave(&csis->slock, flags);
829 	for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
830 		csis->events[i].counter = 0;
831 	spin_unlock_irqrestore(&csis->slock, flags);
832 }
833 
834 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors)
835 {
836 	unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
837 				: MIPI_CSIS_NUM_EVENTS - 8;
838 	unsigned long flags;
839 	unsigned int i;
840 
841 	spin_lock_irqsave(&csis->slock, flags);
842 
843 	for (i = 0; i < num_events; ++i) {
844 		if (csis->events[i].counter > 0 || csis->debug.enable)
845 			dev_info(csis->dev, "%s events: %d\n",
846 				 csis->events[i].name,
847 				 csis->events[i].counter);
848 	}
849 	spin_unlock_irqrestore(&csis->slock, flags);
850 }
851 
852 static int mipi_csis_dump_regs(struct mipi_csis_device *csis)
853 {
854 	static const struct {
855 		u32 offset;
856 		const char * const name;
857 	} registers[] = {
858 		{ MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
859 		{ MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
860 		{ MIPI_CSIS_INT_MSK, "INT_MSK" },
861 		{ MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
862 		{ MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
863 		{ MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
864 		{ MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
865 		{ MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
866 		{ MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
867 		{ MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
868 		{ MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
869 		{ MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
870 		{ MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" },
871 	};
872 
873 	unsigned int i;
874 	u32 cfg;
875 
876 	if (!pm_runtime_get_if_in_use(csis->dev))
877 		return 0;
878 
879 	dev_info(csis->dev, "--- REGISTERS ---\n");
880 
881 	for (i = 0; i < ARRAY_SIZE(registers); i++) {
882 		cfg = mipi_csis_read(csis, registers[i].offset);
883 		dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
884 	}
885 
886 	pm_runtime_put(csis->dev);
887 
888 	return 0;
889 }
890 
891 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
892 {
893 	struct mipi_csis_device *csis = m->private;
894 
895 	return mipi_csis_dump_regs(csis);
896 }
897 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
898 
899 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis)
900 {
901 	csis->debug.hs_settle = UINT_MAX;
902 	csis->debug.clk_settle = UINT_MAX;
903 
904 	csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL);
905 
906 	debugfs_create_bool("debug_enable", 0600, csis->debugfs_root,
907 			    &csis->debug.enable);
908 	debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis,
909 			    &mipi_csis_dump_regs_fops);
910 	debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root,
911 			   &csis->debug.clk_settle);
912 	debugfs_create_u32("ths_settle", 0600, csis->debugfs_root,
913 			   &csis->debug.hs_settle);
914 }
915 
916 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis)
917 {
918 	debugfs_remove_recursive(csis->debugfs_root);
919 }
920 
921 /* -----------------------------------------------------------------------------
922  * V4L2 subdev operations
923  */
924 
925 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev)
926 {
927 	return container_of(sdev, struct mipi_csis_device, sd);
928 }
929 
930 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
931 {
932 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
933 	int ret;
934 
935 	if (!enable) {
936 		mutex_lock(&csis->lock);
937 
938 		v4l2_subdev_call(csis->src_sd, video, s_stream, 0);
939 
940 		mipi_csis_stop_stream(csis);
941 		if (csis->debug.enable)
942 			mipi_csis_log_counters(csis, true);
943 
944 		mutex_unlock(&csis->lock);
945 
946 		pm_runtime_put(csis->dev);
947 
948 		return 0;
949 	}
950 
951 	ret = mipi_csis_calculate_params(csis);
952 	if (ret < 0)
953 		return ret;
954 
955 	mipi_csis_clear_counters(csis);
956 
957 	ret = pm_runtime_resume_and_get(csis->dev);
958 	if (ret < 0)
959 		return ret;
960 
961 	mutex_lock(&csis->lock);
962 
963 	mipi_csis_start_stream(csis);
964 	ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1);
965 	if (ret < 0)
966 		goto error;
967 
968 	mipi_csis_log_counters(csis, true);
969 
970 	mutex_unlock(&csis->lock);
971 
972 	return 0;
973 
974 error:
975 	mipi_csis_stop_stream(csis);
976 	mutex_unlock(&csis->lock);
977 	pm_runtime_put(csis->dev);
978 
979 	return ret;
980 }
981 
982 static struct v4l2_mbus_framefmt *
983 mipi_csis_get_format(struct mipi_csis_device *csis,
984 		     struct v4l2_subdev_state *sd_state,
985 		     enum v4l2_subdev_format_whence which,
986 		     unsigned int pad)
987 {
988 	if (which == V4L2_SUBDEV_FORMAT_TRY)
989 		return v4l2_subdev_get_try_format(&csis->sd, sd_state, pad);
990 
991 	return &csis->format_mbus[pad];
992 }
993 
994 static int mipi_csis_init_cfg(struct v4l2_subdev *sd,
995 			      struct v4l2_subdev_state *sd_state)
996 {
997 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
998 	struct v4l2_mbus_framefmt *fmt_sink;
999 	struct v4l2_mbus_framefmt *fmt_source;
1000 	enum v4l2_subdev_format_whence which;
1001 
1002 	which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1003 	fmt_sink = mipi_csis_get_format(csis, sd_state, which, CSIS_PAD_SINK);
1004 
1005 	fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16;
1006 	fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH;
1007 	fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT;
1008 	fmt_sink->field = V4L2_FIELD_NONE;
1009 
1010 	fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M;
1011 	fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
1012 	fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
1013 	fmt_sink->quantization =
1014 		V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
1015 					      fmt_sink->ycbcr_enc);
1016 
1017 	fmt_source = mipi_csis_get_format(csis, sd_state, which,
1018 					  CSIS_PAD_SOURCE);
1019 	*fmt_source = *fmt_sink;
1020 
1021 	return 0;
1022 }
1023 
1024 static int mipi_csis_get_fmt(struct v4l2_subdev *sd,
1025 			     struct v4l2_subdev_state *sd_state,
1026 			     struct v4l2_subdev_format *sdformat)
1027 {
1028 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1029 	struct v4l2_mbus_framefmt *fmt;
1030 
1031 	fmt = mipi_csis_get_format(csis, sd_state, sdformat->which,
1032 				   sdformat->pad);
1033 
1034 	mutex_lock(&csis->lock);
1035 	sdformat->format = *fmt;
1036 	mutex_unlock(&csis->lock);
1037 
1038 	return 0;
1039 }
1040 
1041 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
1042 				    struct v4l2_subdev_state *sd_state,
1043 				    struct v4l2_subdev_mbus_code_enum *code)
1044 {
1045 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1046 
1047 	/*
1048 	 * The CSIS can't transcode in any way, the source format is identical
1049 	 * to the sink format.
1050 	 */
1051 	if (code->pad == CSIS_PAD_SOURCE) {
1052 		struct v4l2_mbus_framefmt *fmt;
1053 
1054 		if (code->index > 0)
1055 			return -EINVAL;
1056 
1057 		fmt = mipi_csis_get_format(csis, sd_state, code->which,
1058 					   code->pad);
1059 		code->code = fmt->code;
1060 		return 0;
1061 	}
1062 
1063 	if (code->pad != CSIS_PAD_SINK)
1064 		return -EINVAL;
1065 
1066 	if (code->index >= ARRAY_SIZE(mipi_csis_formats))
1067 		return -EINVAL;
1068 
1069 	code->code = mipi_csis_formats[code->index].code;
1070 
1071 	return 0;
1072 }
1073 
1074 static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
1075 			     struct v4l2_subdev_state *sd_state,
1076 			     struct v4l2_subdev_format *sdformat)
1077 {
1078 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1079 	struct csis_pix_format const *csis_fmt;
1080 	struct v4l2_mbus_framefmt *fmt;
1081 	unsigned int align;
1082 
1083 	/*
1084 	 * The CSIS can't transcode in any way, the source format can't be
1085 	 * modified.
1086 	 */
1087 	if (sdformat->pad == CSIS_PAD_SOURCE)
1088 		return mipi_csis_get_fmt(sd, sd_state, sdformat);
1089 
1090 	if (sdformat->pad != CSIS_PAD_SINK)
1091 		return -EINVAL;
1092 
1093 	/*
1094 	 * Validate the media bus code and clamp and align the size.
1095 	 *
1096 	 * The total number of bits per line must be a multiple of 8. We thus
1097 	 * need to align the width for formats that are not multiples of 8
1098 	 * bits.
1099 	 */
1100 	csis_fmt = find_csis_format(sdformat->format.code);
1101 	if (!csis_fmt)
1102 		csis_fmt = &mipi_csis_formats[0];
1103 
1104 	switch (csis_fmt->width % 8) {
1105 	case 0:
1106 		align = 0;
1107 		break;
1108 	case 4:
1109 		align = 1;
1110 		break;
1111 	case 2:
1112 	case 6:
1113 		align = 2;
1114 		break;
1115 	default:
1116 		/* 1, 3, 5, 7 */
1117 		align = 3;
1118 		break;
1119 	}
1120 
1121 	v4l_bound_align_image(&sdformat->format.width, 1,
1122 			      CSIS_MAX_PIX_WIDTH, align,
1123 			      &sdformat->format.height, 1,
1124 			      CSIS_MAX_PIX_HEIGHT, 0, 0);
1125 
1126 	fmt = mipi_csis_get_format(csis, sd_state, sdformat->which,
1127 				   sdformat->pad);
1128 
1129 	mutex_lock(&csis->lock);
1130 
1131 	fmt->code = csis_fmt->code;
1132 	fmt->width = sdformat->format.width;
1133 	fmt->height = sdformat->format.height;
1134 	fmt->colorspace = sdformat->format.colorspace;
1135 	fmt->quantization = sdformat->format.quantization;
1136 	fmt->xfer_func = sdformat->format.xfer_func;
1137 	fmt->ycbcr_enc = sdformat->format.ycbcr_enc;
1138 
1139 	sdformat->format = *fmt;
1140 
1141 	/* Propagate the format from sink to source. */
1142 	fmt = mipi_csis_get_format(csis, sd_state, sdformat->which,
1143 				   CSIS_PAD_SOURCE);
1144 	*fmt = sdformat->format;
1145 
1146 	/* The format on the source pad might change due to unpacking. */
1147 	fmt->code = csis_fmt->output;
1148 
1149 	/* Store the CSIS format descriptor for active formats. */
1150 	if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1151 		csis->csis_fmt = csis_fmt;
1152 
1153 	mutex_unlock(&csis->lock);
1154 
1155 	return 0;
1156 }
1157 
1158 static int mipi_csis_log_status(struct v4l2_subdev *sd)
1159 {
1160 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1161 
1162 	mipi_csis_log_counters(csis, true);
1163 	if (csis->debug.enable)
1164 		mipi_csis_dump_regs(csis);
1165 
1166 	return 0;
1167 }
1168 
1169 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
1170 	.log_status	= mipi_csis_log_status,
1171 };
1172 
1173 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
1174 	.s_stream	= mipi_csis_s_stream,
1175 };
1176 
1177 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
1178 	.init_cfg		= mipi_csis_init_cfg,
1179 	.enum_mbus_code		= mipi_csis_enum_mbus_code,
1180 	.get_fmt		= mipi_csis_get_fmt,
1181 	.set_fmt		= mipi_csis_set_fmt,
1182 };
1183 
1184 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1185 	.core	= &mipi_csis_core_ops,
1186 	.video	= &mipi_csis_video_ops,
1187 	.pad	= &mipi_csis_pad_ops,
1188 };
1189 
1190 /* -----------------------------------------------------------------------------
1191  * Media entity operations
1192  */
1193 
1194 static int mipi_csis_link_setup(struct media_entity *entity,
1195 				const struct media_pad *local_pad,
1196 				const struct media_pad *remote_pad, u32 flags)
1197 {
1198 	struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1199 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1200 	struct v4l2_subdev *remote_sd;
1201 
1202 	dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name,
1203 		local_pad->entity->name);
1204 
1205 	/* We only care about the link to the source. */
1206 	if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
1207 		return 0;
1208 
1209 	remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
1210 
1211 	if (flags & MEDIA_LNK_FL_ENABLED) {
1212 		if (csis->src_sd)
1213 			return -EBUSY;
1214 
1215 		csis->src_sd = remote_sd;
1216 	} else {
1217 		csis->src_sd = NULL;
1218 	}
1219 
1220 	return 0;
1221 }
1222 
1223 static const struct media_entity_operations mipi_csis_entity_ops = {
1224 	.link_setup	= mipi_csis_link_setup,
1225 	.link_validate	= v4l2_subdev_link_validate,
1226 	.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1227 };
1228 
1229 /* -----------------------------------------------------------------------------
1230  * Async subdev notifier
1231  */
1232 
1233 static struct mipi_csis_device *
1234 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
1235 {
1236 	return container_of(n, struct mipi_csis_device, notifier);
1237 }
1238 
1239 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1240 				  struct v4l2_subdev *sd,
1241 				  struct v4l2_async_subdev *asd)
1242 {
1243 	struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier);
1244 	struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK];
1245 
1246 	return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1247 }
1248 
1249 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1250 	.bound = mipi_csis_notify_bound,
1251 };
1252 
1253 static int mipi_csis_async_register(struct mipi_csis_device *csis)
1254 {
1255 	struct v4l2_fwnode_endpoint vep = {
1256 		.bus_type = V4L2_MBUS_CSI2_DPHY,
1257 	};
1258 	struct v4l2_async_subdev *asd;
1259 	struct fwnode_handle *ep;
1260 	unsigned int i;
1261 	int ret;
1262 
1263 	v4l2_async_nf_init(&csis->notifier);
1264 
1265 	ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0,
1266 					     FWNODE_GRAPH_ENDPOINT_NEXT);
1267 	if (!ep)
1268 		return -ENOTCONN;
1269 
1270 	ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1271 	if (ret)
1272 		goto err_parse;
1273 
1274 	for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
1275 		if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
1276 			dev_err(csis->dev,
1277 				"data lanes reordering is not supported");
1278 			ret = -EINVAL;
1279 			goto err_parse;
1280 		}
1281 	}
1282 
1283 	csis->bus = vep.bus.mipi_csi2;
1284 
1285 	dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes);
1286 	dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags);
1287 
1288 	asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep,
1289 					      struct v4l2_async_subdev);
1290 	if (IS_ERR(asd)) {
1291 		ret = PTR_ERR(asd);
1292 		goto err_parse;
1293 	}
1294 
1295 	fwnode_handle_put(ep);
1296 
1297 	csis->notifier.ops = &mipi_csis_notify_ops;
1298 
1299 	ret = v4l2_async_subdev_nf_register(&csis->sd, &csis->notifier);
1300 	if (ret)
1301 		return ret;
1302 
1303 	return v4l2_async_register_subdev(&csis->sd);
1304 
1305 err_parse:
1306 	fwnode_handle_put(ep);
1307 
1308 	return ret;
1309 }
1310 
1311 /* -----------------------------------------------------------------------------
1312  * Suspend/resume
1313  */
1314 
1315 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1316 {
1317 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1318 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1319 	int ret = 0;
1320 
1321 	mutex_lock(&csis->lock);
1322 
1323 	ret = mipi_csis_phy_disable(csis);
1324 	if (ret)
1325 		goto unlock;
1326 
1327 	mipi_csis_clk_disable(csis);
1328 
1329 unlock:
1330 	mutex_unlock(&csis->lock);
1331 
1332 	return ret ? -EAGAIN : 0;
1333 }
1334 
1335 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1336 {
1337 	struct v4l2_subdev *sd = dev_get_drvdata(dev);
1338 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1339 	int ret = 0;
1340 
1341 	mutex_lock(&csis->lock);
1342 
1343 	ret = mipi_csis_phy_enable(csis);
1344 	if (ret)
1345 		goto unlock;
1346 
1347 	mipi_csis_clk_enable(csis);
1348 
1349 unlock:
1350 	mutex_unlock(&csis->lock);
1351 
1352 	return ret ? -EAGAIN : 0;
1353 }
1354 
1355 static const struct dev_pm_ops mipi_csis_pm_ops = {
1356 	SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1357 			   NULL)
1358 };
1359 
1360 /* -----------------------------------------------------------------------------
1361  * Probe/remove & platform driver
1362  */
1363 
1364 static int mipi_csis_subdev_init(struct mipi_csis_device *csis)
1365 {
1366 	struct v4l2_subdev *sd = &csis->sd;
1367 
1368 	v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
1369 	sd->owner = THIS_MODULE;
1370 	snprintf(sd->name, sizeof(sd->name), "csis-%s",
1371 		 dev_name(csis->dev));
1372 
1373 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1374 	sd->ctrl_handler = NULL;
1375 
1376 	sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1377 	sd->entity.ops = &mipi_csis_entity_ops;
1378 
1379 	sd->dev = csis->dev;
1380 
1381 	csis->csis_fmt = &mipi_csis_formats[0];
1382 	mipi_csis_init_cfg(sd, NULL);
1383 
1384 	csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1385 					 | MEDIA_PAD_FL_MUST_CONNECT;
1386 	csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1387 					   | MEDIA_PAD_FL_MUST_CONNECT;
1388 	return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM,
1389 				      csis->pads);
1390 }
1391 
1392 static int mipi_csis_parse_dt(struct mipi_csis_device *csis)
1393 {
1394 	struct device_node *node = csis->dev->of_node;
1395 
1396 	if (of_property_read_u32(node, "clock-frequency",
1397 				 &csis->clk_frequency))
1398 		csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
1399 
1400 	return 0;
1401 }
1402 
1403 static int mipi_csis_probe(struct platform_device *pdev)
1404 {
1405 	struct device *dev = &pdev->dev;
1406 	struct mipi_csis_device *csis;
1407 	int irq;
1408 	int ret;
1409 
1410 	csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL);
1411 	if (!csis)
1412 		return -ENOMEM;
1413 
1414 	mutex_init(&csis->lock);
1415 	spin_lock_init(&csis->slock);
1416 
1417 	csis->dev = dev;
1418 	csis->info = of_device_get_match_data(dev);
1419 
1420 	memcpy(csis->events, mipi_csis_events, sizeof(csis->events));
1421 
1422 	/* Parse DT properties. */
1423 	ret = mipi_csis_parse_dt(csis);
1424 	if (ret < 0) {
1425 		dev_err(dev, "Failed to parse device tree: %d\n", ret);
1426 		return ret;
1427 	}
1428 
1429 	/* Acquire resources. */
1430 	csis->regs = devm_platform_ioremap_resource(pdev, 0);
1431 	if (IS_ERR(csis->regs))
1432 		return PTR_ERR(csis->regs);
1433 
1434 	irq = platform_get_irq(pdev, 0);
1435 	if (irq < 0)
1436 		return irq;
1437 
1438 	ret = mipi_csis_phy_init(csis);
1439 	if (ret < 0)
1440 		return ret;
1441 
1442 	ret = mipi_csis_clk_get(csis);
1443 	if (ret < 0)
1444 		return ret;
1445 
1446 	/* Reset PHY and enable the clocks. */
1447 	mipi_csis_phy_reset(csis);
1448 
1449 	ret = mipi_csis_clk_enable(csis);
1450 	if (ret < 0) {
1451 		dev_err(csis->dev, "failed to enable clocks: %d\n", ret);
1452 		return ret;
1453 	}
1454 
1455 	/* Now that the hardware is initialized, request the interrupt. */
1456 	ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
1457 			       dev_name(dev), csis);
1458 	if (ret) {
1459 		dev_err(dev, "Interrupt request failed\n");
1460 		goto disable_clock;
1461 	}
1462 
1463 	/* Initialize and register the subdev. */
1464 	ret = mipi_csis_subdev_init(csis);
1465 	if (ret < 0)
1466 		goto disable_clock;
1467 
1468 	platform_set_drvdata(pdev, &csis->sd);
1469 
1470 	ret = mipi_csis_async_register(csis);
1471 	if (ret < 0) {
1472 		dev_err(dev, "async register failed: %d\n", ret);
1473 		goto cleanup;
1474 	}
1475 
1476 	/* Initialize debugfs. */
1477 	mipi_csis_debugfs_init(csis);
1478 
1479 	/* Enable runtime PM. */
1480 	pm_runtime_enable(dev);
1481 	if (!pm_runtime_enabled(dev)) {
1482 		ret = mipi_csis_runtime_resume(dev);
1483 		if (ret < 0)
1484 			goto unregister_all;
1485 	}
1486 
1487 	dev_info(dev, "lanes: %d, freq: %u\n",
1488 		 csis->bus.num_data_lanes, csis->clk_frequency);
1489 
1490 	return 0;
1491 
1492 unregister_all:
1493 	mipi_csis_debugfs_exit(csis);
1494 cleanup:
1495 	media_entity_cleanup(&csis->sd.entity);
1496 	v4l2_async_nf_unregister(&csis->notifier);
1497 	v4l2_async_nf_cleanup(&csis->notifier);
1498 	v4l2_async_unregister_subdev(&csis->sd);
1499 disable_clock:
1500 	mipi_csis_clk_disable(csis);
1501 	mutex_destroy(&csis->lock);
1502 
1503 	return ret;
1504 }
1505 
1506 static int mipi_csis_remove(struct platform_device *pdev)
1507 {
1508 	struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1509 	struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd);
1510 
1511 	mipi_csis_debugfs_exit(csis);
1512 	v4l2_async_nf_unregister(&csis->notifier);
1513 	v4l2_async_nf_cleanup(&csis->notifier);
1514 	v4l2_async_unregister_subdev(&csis->sd);
1515 
1516 	pm_runtime_disable(&pdev->dev);
1517 	mipi_csis_runtime_suspend(&pdev->dev);
1518 	mipi_csis_clk_disable(csis);
1519 	media_entity_cleanup(&csis->sd.entity);
1520 	mutex_destroy(&csis->lock);
1521 	pm_runtime_set_suspended(&pdev->dev);
1522 
1523 	return 0;
1524 }
1525 
1526 static const struct of_device_id mipi_csis_of_match[] = {
1527 	{
1528 		.compatible = "fsl,imx7-mipi-csi2",
1529 		.data = &(const struct mipi_csis_info){
1530 			.version = MIPI_CSIS_V3_3,
1531 			.num_clocks = 3,
1532 		},
1533 	}, {
1534 		.compatible = "fsl,imx8mm-mipi-csi2",
1535 		.data = &(const struct mipi_csis_info){
1536 			.version = MIPI_CSIS_V3_6_3,
1537 			.num_clocks = 4,
1538 		},
1539 	},
1540 	{ /* sentinel */ },
1541 };
1542 MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1543 
1544 static struct platform_driver mipi_csis_driver = {
1545 	.probe		= mipi_csis_probe,
1546 	.remove		= mipi_csis_remove,
1547 	.driver		= {
1548 		.of_match_table = mipi_csis_of_match,
1549 		.name		= CSIS_DRIVER_NAME,
1550 		.pm		= &mipi_csis_pm_ops,
1551 	},
1552 };
1553 
1554 module_platform_driver(mipi_csis_driver);
1555 
1556 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
1557 MODULE_LICENSE("GPL v2");
1558 MODULE_ALIAS("platform:imx-mipi-csi2");
1559