1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/spinlock.h> 31 32 #include <media/v4l2-common.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-mc.h> 36 #include <media/v4l2-subdev.h> 37 38 #define CSIS_DRIVER_NAME "imx-mipi-csis" 39 40 #define CSIS_PAD_SINK 0 41 #define CSIS_PAD_SOURCE 1 42 #define CSIS_PADS_NUM 2 43 44 #define MIPI_CSIS_DEF_PIX_WIDTH 640 45 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 46 47 /* Register map definition */ 48 49 /* CSIS common control */ 50 #define MIPI_CSIS_CMN_CTRL 0x04 51 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) 52 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) 53 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 54 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) 55 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) 56 57 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 58 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) 59 60 /* CSIS clock control */ 61 #define MIPI_CSIS_CLK_CTRL 0x08 62 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) 63 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) 64 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) 65 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) 66 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) 67 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) 68 69 /* CSIS Interrupt mask */ 70 #define MIPI_CSIS_INT_MSK 0x10 71 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 72 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 73 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 74 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 75 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 76 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 77 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 78 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 79 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 80 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 81 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 82 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 83 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 84 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) 85 86 /* CSIS Interrupt source */ 87 #define MIPI_CSIS_INT_SRC 0x14 88 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 89 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 90 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 91 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 92 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 93 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 94 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 95 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) 96 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) 97 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) 98 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) 99 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) 100 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) 101 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 102 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 103 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 104 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) 105 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 106 107 /* D-PHY status control */ 108 #define MIPI_CSIS_DPHY_STATUS 0x20 109 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 110 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 111 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 112 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 113 114 /* D-PHY common control */ 115 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 116 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 117 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 118 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 119 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 120 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) 121 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) 122 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 125 126 /* D-PHY Master and Slave Control register Low */ 127 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 128 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 129 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 130 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 131 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 132 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 133 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 134 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 135 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 136 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 137 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 138 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 139 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 140 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 141 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 142 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 143 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 144 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 145 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 150 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 151 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 152 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 153 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 154 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 156 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 157 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 158 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 159 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 160 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 161 162 /* D-PHY Master and Slave Control register High */ 163 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 164 /* D-PHY Slave Control register Low */ 165 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 166 /* D-PHY Slave Control register High */ 167 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 168 169 /* ISP Configuration register */ 170 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 171 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) 172 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 173 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 174 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 175 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 176 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) 177 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) 178 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) 179 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) 180 181 /* ISP Image Resolution register */ 182 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 183 #define CSIS_MAX_PIX_WIDTH 0xffff 184 #define CSIS_MAX_PIX_HEIGHT 0xffff 185 186 /* ISP SYNC register */ 187 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 188 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 189 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 190 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 191 192 /* ISP shadow registers */ 193 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 194 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 195 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 196 197 /* Debug control register */ 198 #define MIPI_CSIS_DBG_CTRL 0xc0 199 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 200 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 201 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 202 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) 203 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) 204 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) 205 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) 206 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) 207 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) 208 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 209 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 210 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 211 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) 212 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) 213 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) 214 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) 215 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) 216 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) 217 218 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 219 220 /* Non-image packet data buffers */ 221 #define MIPI_CSIS_PKTDATA_ODD 0x2000 222 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 223 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 224 225 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL 226 227 /* MIPI CSI-2 Data Types */ 228 #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18 229 #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19 230 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a 231 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c 232 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d 233 #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e 234 #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f 235 #define MIPI_CSI2_DATA_TYPE_RGB565 0x22 236 #define MIPI_CSI2_DATA_TYPE_RGB666 0x23 237 #define MIPI_CSI2_DATA_TYPE_RGB888 0x24 238 #define MIPI_CSI2_DATA_TYPE_RAW6 0x28 239 #define MIPI_CSI2_DATA_TYPE_RAW7 0x29 240 #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a 241 #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b 242 #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c 243 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d 244 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) 245 246 struct mipi_csis_event { 247 bool debug; 248 u32 mask; 249 const char * const name; 250 unsigned int counter; 251 }; 252 253 static const struct mipi_csis_event mipi_csis_events[] = { 254 /* Errors */ 255 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, 256 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, 257 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, 258 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, 259 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 260 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 261 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 262 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, 263 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 264 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 265 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, 266 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, 267 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, 268 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, 269 /* Non-image data receive events */ 270 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 271 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 272 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 273 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 274 /* Frame start/end */ 275 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, 276 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, 277 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, 278 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, 279 }; 280 281 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 282 283 enum mipi_csis_clk { 284 MIPI_CSIS_CLK_PCLK, 285 MIPI_CSIS_CLK_WRAP, 286 MIPI_CSIS_CLK_PHY, 287 MIPI_CSIS_CLK_AXI, 288 }; 289 290 static const char * const mipi_csis_clk_id[] = { 291 "pclk", 292 "wrap", 293 "phy", 294 "axi", 295 }; 296 297 enum mipi_csis_version { 298 MIPI_CSIS_V3_3, 299 MIPI_CSIS_V3_6_3, 300 }; 301 302 struct mipi_csis_info { 303 enum mipi_csis_version version; 304 unsigned int num_clocks; 305 }; 306 307 struct mipi_csis_device { 308 struct device *dev; 309 void __iomem *regs; 310 struct clk_bulk_data *clks; 311 struct reset_control *mrst; 312 struct regulator *mipi_phy_regulator; 313 const struct mipi_csis_info *info; 314 315 struct v4l2_subdev sd; 316 struct media_pad pads[CSIS_PADS_NUM]; 317 struct v4l2_async_notifier notifier; 318 struct v4l2_subdev *src_sd; 319 320 struct v4l2_mbus_config_mipi_csi2 bus; 321 u32 clk_frequency; 322 u32 hs_settle; 323 u32 clk_settle; 324 325 struct mutex lock; /* Protect csis_fmt, format_mbus and powered */ 326 const struct csis_pix_format *csis_fmt; 327 struct v4l2_mbus_framefmt format_mbus[CSIS_PADS_NUM]; 328 bool powered; 329 330 spinlock_t slock; /* Protect events */ 331 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 332 struct dentry *debugfs_root; 333 struct { 334 bool enable; 335 u32 hs_settle; 336 u32 clk_settle; 337 } debug; 338 }; 339 340 /* ----------------------------------------------------------------------------- 341 * Format helpers 342 */ 343 344 struct csis_pix_format { 345 u32 code; 346 u32 output; 347 u32 data_type; 348 u8 width; 349 }; 350 351 static const struct csis_pix_format mipi_csis_formats[] = { 352 /* YUV formats. */ 353 { 354 .code = MEDIA_BUS_FMT_UYVY8_1X16, 355 .output = MEDIA_BUS_FMT_UYVY8_1X16, 356 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8, 357 .width = 16, 358 }, 359 /* RGB formats. */ 360 { 361 .code = MEDIA_BUS_FMT_RGB565_1X16, 362 .output = MEDIA_BUS_FMT_RGB565_1X16, 363 .data_type = MIPI_CSI2_DATA_TYPE_RGB565, 364 .width = 16, 365 }, { 366 .code = MEDIA_BUS_FMT_BGR888_1X24, 367 .output = MEDIA_BUS_FMT_RGB888_1X24, 368 .data_type = MIPI_CSI2_DATA_TYPE_RGB888, 369 .width = 24, 370 }, 371 /* RAW (Bayer and greyscale) formats. */ 372 { 373 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 374 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 375 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 376 .width = 8, 377 }, { 378 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 379 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 380 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 381 .width = 8, 382 }, { 383 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 384 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 385 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 386 .width = 8, 387 }, { 388 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 389 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 390 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 391 .width = 8, 392 }, { 393 .code = MEDIA_BUS_FMT_Y8_1X8, 394 .output = MEDIA_BUS_FMT_Y8_1X8, 395 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 396 .width = 8, 397 }, { 398 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 399 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 400 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 401 .width = 10, 402 }, { 403 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 404 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 405 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 406 .width = 10, 407 }, { 408 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 409 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 410 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 411 .width = 10, 412 }, { 413 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 414 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 415 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 416 .width = 10, 417 }, { 418 .code = MEDIA_BUS_FMT_Y10_1X10, 419 .output = MEDIA_BUS_FMT_Y10_1X10, 420 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 421 .width = 10, 422 }, { 423 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 424 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 425 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 426 .width = 12, 427 }, { 428 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 429 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 430 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 431 .width = 12, 432 }, { 433 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 434 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 435 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 436 .width = 12, 437 }, { 438 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 439 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 440 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 441 .width = 12, 442 }, { 443 .code = MEDIA_BUS_FMT_Y12_1X12, 444 .output = MEDIA_BUS_FMT_Y12_1X12, 445 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 446 .width = 12, 447 }, { 448 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 449 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 450 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 451 .width = 14, 452 }, { 453 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 454 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 455 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 456 .width = 14, 457 }, { 458 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 459 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 460 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 461 .width = 14, 462 }, { 463 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 464 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 465 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 466 .width = 14, 467 }, 468 /* JPEG */ 469 { 470 .code = MEDIA_BUS_FMT_JPEG_1X8, 471 .output = MEDIA_BUS_FMT_JPEG_1X8, 472 /* 473 * Map JPEG_1X8 to the RAW8 datatype. 474 * 475 * The CSI-2 specification suggests in Annex A "JPEG8 Data 476 * Format (informative)" to transmit JPEG data using one of the 477 * Data Types aimed to represent arbitrary data, such as the 478 * "User Defined Data Type 1" (0x30). 479 * 480 * However, when configured with a User Defined Data Type, the 481 * CSIS outputs data in quad pixel mode regardless of the mode 482 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 483 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 484 * or ISI) support quad pixel mode, so this will never work in 485 * practice. 486 * 487 * Some sensors (such as the OV5640) send JPEG data using the 488 * RAW8 data type. This is usable and works, so map the JPEG 489 * format to RAW8. If the CSIS ends up being integrated in an 490 * SoC that can support quad pixel mode, this will have to be 491 * revisited. 492 */ 493 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 494 .width = 8, 495 } 496 }; 497 498 static const struct csis_pix_format *find_csis_format(u32 code) 499 { 500 unsigned int i; 501 502 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 503 if (code == mipi_csis_formats[i].code) 504 return &mipi_csis_formats[i]; 505 return NULL; 506 } 507 508 /* ----------------------------------------------------------------------------- 509 * Hardware configuration 510 */ 511 512 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 513 { 514 return readl(csis->regs + reg); 515 } 516 517 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 518 u32 val) 519 { 520 writel(val, csis->regs + reg); 521 } 522 523 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 524 { 525 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 526 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 527 } 528 529 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 530 { 531 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 532 533 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 534 val | MIPI_CSIS_CMN_CTRL_RESET); 535 usleep_range(10, 20); 536 } 537 538 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 539 { 540 u32 val, mask; 541 542 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 543 if (on) 544 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 545 else 546 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 547 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 548 549 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 550 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 551 if (on) { 552 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 553 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 554 } 555 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 556 } 557 558 /* Called with the csis.lock mutex held */ 559 static void __mipi_csis_set_format(struct mipi_csis_device *csis) 560 { 561 struct v4l2_mbus_framefmt *mf = &csis->format_mbus[CSIS_PAD_SINK]; 562 u32 val; 563 564 /* Color format */ 565 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 566 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 567 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 568 569 /* 570 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 571 * (referred to in the documentation as single and dual pixel modes 572 * respectively, although the 8-bit mode transfers half a pixel per 573 * clock sample and the 16-bit mode one pixel). While both mode work 574 * when the CSIS is connected to a receiver that supports either option, 575 * single pixel mode requires clock rates twice as high. As all SoCs 576 * that integrate the CSIS can operate in 16-bit bit mode, and some do 577 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 578 * pixel mode unconditionally. 579 * 580 * TODO: Verify which other formats require DUAL (or QUAD) modes. 581 */ 582 if (csis->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 583 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 584 585 val |= MIPI_CSIS_ISPCFG_FMT(csis->csis_fmt->data_type); 586 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 587 588 /* Pixel resolution */ 589 val = mf->width | (mf->height << 16); 590 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 591 } 592 593 static int mipi_csis_calculate_params(struct mipi_csis_device *csis) 594 { 595 s64 link_freq; 596 u32 lane_rate; 597 598 /* Calculate the line rate from the pixel rate. */ 599 link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler, 600 csis->csis_fmt->width, 601 csis->bus.num_data_lanes * 2); 602 if (link_freq < 0) { 603 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 604 (int)link_freq); 605 return link_freq; 606 } 607 608 lane_rate = link_freq * 2; 609 610 if (lane_rate < 80000000 || lane_rate > 1500000000) { 611 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 612 return -EINVAL; 613 } 614 615 /* 616 * The HSSETTLE counter value is document in a table, but can also 617 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 618 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 619 * we figure out how to compute it correctly. 620 */ 621 csis->hs_settle = (lane_rate - 5000000) / 45000000; 622 csis->clk_settle = 0; 623 624 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 625 lane_rate, csis->clk_settle, csis->hs_settle); 626 627 if (csis->debug.hs_settle < 0xff) { 628 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 629 csis->debug.hs_settle); 630 csis->hs_settle = csis->debug.hs_settle; 631 } 632 633 if (csis->debug.clk_settle < 4) { 634 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 635 csis->debug.clk_settle); 636 csis->clk_settle = csis->debug.clk_settle; 637 } 638 639 return 0; 640 } 641 642 static void mipi_csis_set_params(struct mipi_csis_device *csis) 643 { 644 int lanes = csis->bus.num_data_lanes; 645 u32 val; 646 647 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 648 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 649 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 650 if (csis->info->version == MIPI_CSIS_V3_3) 651 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 652 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 653 654 __mipi_csis_set_format(csis); 655 656 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 657 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 658 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 659 660 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 661 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 662 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 663 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 664 665 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 666 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 667 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 668 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 669 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 670 671 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 672 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 673 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 674 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 675 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 676 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 677 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 678 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 679 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 680 681 /* Update the shadow register. */ 682 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 683 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 684 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 685 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 686 } 687 688 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 689 { 690 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 691 } 692 693 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 694 { 695 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 696 } 697 698 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 699 { 700 unsigned int i; 701 int ret; 702 703 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 704 sizeof(*csis->clks), GFP_KERNEL); 705 706 if (!csis->clks) 707 return -ENOMEM; 708 709 for (i = 0; i < csis->info->num_clocks; i++) 710 csis->clks[i].id = mipi_csis_clk_id[i]; 711 712 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 713 csis->clks); 714 if (ret < 0) 715 return ret; 716 717 /* Set clock rate */ 718 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 719 csis->clk_frequency); 720 if (ret < 0) 721 dev_err(csis->dev, "set rate=%d failed: %d\n", 722 csis->clk_frequency, ret); 723 724 return ret; 725 } 726 727 static void mipi_csis_start_stream(struct mipi_csis_device *csis) 728 { 729 mipi_csis_sw_reset(csis); 730 mipi_csis_set_params(csis); 731 mipi_csis_system_enable(csis, true); 732 mipi_csis_enable_interrupts(csis, true); 733 } 734 735 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 736 { 737 mipi_csis_enable_interrupts(csis, false); 738 mipi_csis_system_enable(csis, false); 739 } 740 741 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 742 { 743 struct mipi_csis_device *csis = dev_id; 744 unsigned long flags; 745 unsigned int i; 746 u32 status; 747 u32 dbg_status; 748 749 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 750 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 751 752 spin_lock_irqsave(&csis->slock, flags); 753 754 /* Update the event/error counters */ 755 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 756 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 757 struct mipi_csis_event *event = &csis->events[i]; 758 759 if ((!event->debug && (status & event->mask)) || 760 (event->debug && (dbg_status & event->mask))) 761 event->counter++; 762 } 763 } 764 spin_unlock_irqrestore(&csis->slock, flags); 765 766 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 767 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 768 769 return IRQ_HANDLED; 770 } 771 772 /* ----------------------------------------------------------------------------- 773 * PHY regulator and reset 774 */ 775 776 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 777 { 778 if (csis->info->version != MIPI_CSIS_V3_3) 779 return 0; 780 781 return regulator_enable(csis->mipi_phy_regulator); 782 } 783 784 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 785 { 786 if (csis->info->version != MIPI_CSIS_V3_3) 787 return 0; 788 789 return regulator_disable(csis->mipi_phy_regulator); 790 } 791 792 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 793 { 794 if (csis->info->version != MIPI_CSIS_V3_3) 795 return; 796 797 reset_control_assert(csis->mrst); 798 msleep(20); 799 reset_control_deassert(csis->mrst); 800 } 801 802 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 803 { 804 if (csis->info->version != MIPI_CSIS_V3_3) 805 return 0; 806 807 /* Get MIPI PHY reset and regulator. */ 808 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 809 if (IS_ERR(csis->mrst)) 810 return PTR_ERR(csis->mrst); 811 812 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 813 if (IS_ERR(csis->mipi_phy_regulator)) 814 return PTR_ERR(csis->mipi_phy_regulator); 815 816 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 817 1000000); 818 } 819 820 /* ----------------------------------------------------------------------------- 821 * Debug 822 */ 823 824 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 825 { 826 unsigned long flags; 827 unsigned int i; 828 829 spin_lock_irqsave(&csis->slock, flags); 830 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 831 csis->events[i].counter = 0; 832 spin_unlock_irqrestore(&csis->slock, flags); 833 } 834 835 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 836 { 837 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 838 : MIPI_CSIS_NUM_EVENTS - 8; 839 unsigned long flags; 840 unsigned int i; 841 842 spin_lock_irqsave(&csis->slock, flags); 843 844 for (i = 0; i < num_events; ++i) { 845 if (csis->events[i].counter > 0 || csis->debug.enable) 846 dev_info(csis->dev, "%s events: %d\n", 847 csis->events[i].name, 848 csis->events[i].counter); 849 } 850 spin_unlock_irqrestore(&csis->slock, flags); 851 } 852 853 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 854 { 855 static const struct { 856 u32 offset; 857 const char * const name; 858 } registers[] = { 859 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, 860 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, 861 { MIPI_CSIS_INT_MSK, "INT_MSK" }, 862 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, 863 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, 864 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, 865 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, 866 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, 867 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, 868 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, 869 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, 870 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, 871 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, 872 }; 873 874 unsigned int i; 875 u32 cfg; 876 877 dev_info(csis->dev, "--- REGISTERS ---\n"); 878 879 for (i = 0; i < ARRAY_SIZE(registers); i++) { 880 cfg = mipi_csis_read(csis, registers[i].offset); 881 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 882 } 883 884 return 0; 885 } 886 887 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 888 { 889 struct mipi_csis_device *csis = m->private; 890 891 return mipi_csis_dump_regs(csis); 892 } 893 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 894 895 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 896 { 897 csis->debug.hs_settle = UINT_MAX; 898 csis->debug.clk_settle = UINT_MAX; 899 900 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 901 902 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 903 &csis->debug.enable); 904 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 905 &mipi_csis_dump_regs_fops); 906 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 907 &csis->debug.clk_settle); 908 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 909 &csis->debug.hs_settle); 910 } 911 912 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 913 { 914 debugfs_remove_recursive(csis->debugfs_root); 915 } 916 917 /* ----------------------------------------------------------------------------- 918 * V4L2 subdev operations 919 */ 920 921 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 922 { 923 return container_of(sdev, struct mipi_csis_device, sd); 924 } 925 926 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 927 { 928 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 929 int ret = 0; 930 931 if (enable) { 932 ret = mipi_csis_calculate_params(csis); 933 if (ret < 0) 934 return ret; 935 936 mipi_csis_clear_counters(csis); 937 938 ret = pm_runtime_resume_and_get(csis->dev); 939 if (ret < 0) 940 return ret; 941 } 942 943 mutex_lock(&csis->lock); 944 945 if (enable) { 946 mipi_csis_start_stream(csis); 947 ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1); 948 if (ret < 0) 949 goto unlock; 950 951 mipi_csis_log_counters(csis, true); 952 } else { 953 v4l2_subdev_call(csis->src_sd, video, s_stream, 0); 954 955 mipi_csis_stop_stream(csis); 956 957 if (csis->debug.enable) 958 mipi_csis_log_counters(csis, true); 959 } 960 961 unlock: 962 mutex_unlock(&csis->lock); 963 964 if (!enable || ret < 0) 965 pm_runtime_put(csis->dev); 966 967 return ret; 968 } 969 970 static struct v4l2_mbus_framefmt * 971 mipi_csis_get_format(struct mipi_csis_device *csis, 972 struct v4l2_subdev_state *sd_state, 973 enum v4l2_subdev_format_whence which, 974 unsigned int pad) 975 { 976 if (which == V4L2_SUBDEV_FORMAT_TRY) 977 return v4l2_subdev_get_try_format(&csis->sd, sd_state, pad); 978 979 return &csis->format_mbus[pad]; 980 } 981 982 static int mipi_csis_init_cfg(struct v4l2_subdev *sd, 983 struct v4l2_subdev_state *sd_state) 984 { 985 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 986 struct v4l2_mbus_framefmt *fmt_sink; 987 struct v4l2_mbus_framefmt *fmt_source; 988 enum v4l2_subdev_format_whence which; 989 990 which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 991 fmt_sink = mipi_csis_get_format(csis, sd_state, which, CSIS_PAD_SINK); 992 993 fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16; 994 fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH; 995 fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT; 996 fmt_sink->field = V4L2_FIELD_NONE; 997 998 fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M; 999 fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace); 1000 fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace); 1001 fmt_sink->quantization = 1002 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace, 1003 fmt_sink->ycbcr_enc); 1004 1005 /* 1006 * When called from mipi_csis_subdev_init() to initialize the active 1007 * configuration, cfg is NULL, which indicates there's no source pad 1008 * configuration to set. 1009 */ 1010 if (!sd_state) 1011 return 0; 1012 1013 fmt_source = mipi_csis_get_format(csis, sd_state, which, 1014 CSIS_PAD_SOURCE); 1015 *fmt_source = *fmt_sink; 1016 1017 return 0; 1018 } 1019 1020 static int mipi_csis_get_fmt(struct v4l2_subdev *sd, 1021 struct v4l2_subdev_state *sd_state, 1022 struct v4l2_subdev_format *sdformat) 1023 { 1024 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1025 struct v4l2_mbus_framefmt *fmt; 1026 1027 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1028 sdformat->pad); 1029 1030 mutex_lock(&csis->lock); 1031 sdformat->format = *fmt; 1032 mutex_unlock(&csis->lock); 1033 1034 return 0; 1035 } 1036 1037 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 1038 struct v4l2_subdev_state *sd_state, 1039 struct v4l2_subdev_mbus_code_enum *code) 1040 { 1041 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1042 1043 /* 1044 * The CSIS can't transcode in any way, the source format is identical 1045 * to the sink format. 1046 */ 1047 if (code->pad == CSIS_PAD_SOURCE) { 1048 struct v4l2_mbus_framefmt *fmt; 1049 1050 if (code->index > 0) 1051 return -EINVAL; 1052 1053 fmt = mipi_csis_get_format(csis, sd_state, code->which, 1054 code->pad); 1055 code->code = fmt->code; 1056 return 0; 1057 } 1058 1059 if (code->pad != CSIS_PAD_SINK) 1060 return -EINVAL; 1061 1062 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1063 return -EINVAL; 1064 1065 code->code = mipi_csis_formats[code->index].code; 1066 1067 return 0; 1068 } 1069 1070 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1071 struct v4l2_subdev_state *sd_state, 1072 struct v4l2_subdev_format *sdformat) 1073 { 1074 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1075 struct csis_pix_format const *csis_fmt; 1076 struct v4l2_mbus_framefmt *fmt; 1077 unsigned int align; 1078 1079 /* 1080 * The CSIS can't transcode in any way, the source format can't be 1081 * modified. 1082 */ 1083 if (sdformat->pad == CSIS_PAD_SOURCE) 1084 return mipi_csis_get_fmt(sd, sd_state, sdformat); 1085 1086 if (sdformat->pad != CSIS_PAD_SINK) 1087 return -EINVAL; 1088 1089 /* 1090 * Validate the media bus code and clamp and align the size. 1091 * 1092 * The total number of bits per line must be a multiple of 8. We thus 1093 * need to align the width for formats that are not multiples of 8 1094 * bits. 1095 */ 1096 csis_fmt = find_csis_format(sdformat->format.code); 1097 if (!csis_fmt) 1098 csis_fmt = &mipi_csis_formats[0]; 1099 1100 switch (csis_fmt->width % 8) { 1101 case 0: 1102 align = 0; 1103 break; 1104 case 4: 1105 align = 1; 1106 break; 1107 case 2: 1108 case 6: 1109 align = 2; 1110 break; 1111 default: 1112 /* 1, 3, 5, 7 */ 1113 align = 3; 1114 break; 1115 } 1116 1117 v4l_bound_align_image(&sdformat->format.width, 1, 1118 CSIS_MAX_PIX_WIDTH, align, 1119 &sdformat->format.height, 1, 1120 CSIS_MAX_PIX_HEIGHT, 0, 0); 1121 1122 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1123 sdformat->pad); 1124 1125 mutex_lock(&csis->lock); 1126 1127 fmt->code = csis_fmt->code; 1128 fmt->width = sdformat->format.width; 1129 fmt->height = sdformat->format.height; 1130 fmt->colorspace = sdformat->format.colorspace; 1131 fmt->quantization = sdformat->format.quantization; 1132 fmt->xfer_func = sdformat->format.xfer_func; 1133 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1134 1135 sdformat->format = *fmt; 1136 1137 /* Propagate the format from sink to source. */ 1138 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1139 CSIS_PAD_SOURCE); 1140 *fmt = sdformat->format; 1141 1142 /* The format on the source pad might change due to unpacking. */ 1143 fmt->code = csis_fmt->output; 1144 1145 /* Store the CSIS format descriptor for active formats. */ 1146 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) 1147 csis->csis_fmt = csis_fmt; 1148 1149 mutex_unlock(&csis->lock); 1150 1151 return 0; 1152 } 1153 1154 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1155 { 1156 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1157 1158 mutex_lock(&csis->lock); 1159 mipi_csis_log_counters(csis, true); 1160 if (csis->debug.enable && csis->powered) 1161 mipi_csis_dump_regs(csis); 1162 mutex_unlock(&csis->lock); 1163 1164 return 0; 1165 } 1166 1167 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1168 .log_status = mipi_csis_log_status, 1169 }; 1170 1171 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1172 .s_stream = mipi_csis_s_stream, 1173 }; 1174 1175 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1176 .init_cfg = mipi_csis_init_cfg, 1177 .enum_mbus_code = mipi_csis_enum_mbus_code, 1178 .get_fmt = mipi_csis_get_fmt, 1179 .set_fmt = mipi_csis_set_fmt, 1180 }; 1181 1182 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1183 .core = &mipi_csis_core_ops, 1184 .video = &mipi_csis_video_ops, 1185 .pad = &mipi_csis_pad_ops, 1186 }; 1187 1188 /* ----------------------------------------------------------------------------- 1189 * Media entity operations 1190 */ 1191 1192 static int mipi_csis_link_setup(struct media_entity *entity, 1193 const struct media_pad *local_pad, 1194 const struct media_pad *remote_pad, u32 flags) 1195 { 1196 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1197 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1198 struct v4l2_subdev *remote_sd; 1199 1200 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1201 local_pad->entity->name); 1202 1203 /* We only care about the link to the source. */ 1204 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1205 return 0; 1206 1207 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1208 1209 if (flags & MEDIA_LNK_FL_ENABLED) { 1210 if (csis->src_sd) 1211 return -EBUSY; 1212 1213 csis->src_sd = remote_sd; 1214 } else { 1215 csis->src_sd = NULL; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static const struct media_entity_operations mipi_csis_entity_ops = { 1222 .link_setup = mipi_csis_link_setup, 1223 .link_validate = v4l2_subdev_link_validate, 1224 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1225 }; 1226 1227 /* ----------------------------------------------------------------------------- 1228 * Async subdev notifier 1229 */ 1230 1231 static struct mipi_csis_device * 1232 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1233 { 1234 return container_of(n, struct mipi_csis_device, notifier); 1235 } 1236 1237 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1238 struct v4l2_subdev *sd, 1239 struct v4l2_async_subdev *asd) 1240 { 1241 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1242 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1243 1244 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1245 } 1246 1247 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1248 .bound = mipi_csis_notify_bound, 1249 }; 1250 1251 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1252 { 1253 struct v4l2_fwnode_endpoint vep = { 1254 .bus_type = V4L2_MBUS_CSI2_DPHY, 1255 }; 1256 struct v4l2_async_subdev *asd; 1257 struct fwnode_handle *ep; 1258 unsigned int i; 1259 int ret; 1260 1261 v4l2_async_nf_init(&csis->notifier); 1262 1263 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1264 FWNODE_GRAPH_ENDPOINT_NEXT); 1265 if (!ep) 1266 return -ENOTCONN; 1267 1268 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1269 if (ret) 1270 goto err_parse; 1271 1272 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1273 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1274 dev_err(csis->dev, 1275 "data lanes reordering is not supported"); 1276 ret = -EINVAL; 1277 goto err_parse; 1278 } 1279 } 1280 1281 csis->bus = vep.bus.mipi_csi2; 1282 1283 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1284 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1285 1286 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1287 struct v4l2_async_subdev); 1288 if (IS_ERR(asd)) { 1289 ret = PTR_ERR(asd); 1290 goto err_parse; 1291 } 1292 1293 fwnode_handle_put(ep); 1294 1295 csis->notifier.ops = &mipi_csis_notify_ops; 1296 1297 ret = v4l2_async_subdev_nf_register(&csis->sd, &csis->notifier); 1298 if (ret) 1299 return ret; 1300 1301 return v4l2_async_register_subdev(&csis->sd); 1302 1303 err_parse: 1304 fwnode_handle_put(ep); 1305 1306 return ret; 1307 } 1308 1309 /* ----------------------------------------------------------------------------- 1310 * Suspend/resume 1311 */ 1312 1313 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) 1314 { 1315 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1316 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1317 int ret = 0; 1318 1319 mutex_lock(&csis->lock); 1320 1321 ret = mipi_csis_phy_disable(csis); 1322 if (ret) 1323 goto unlock; 1324 1325 mipi_csis_clk_disable(csis); 1326 1327 csis->powered = false; 1328 1329 unlock: 1330 mutex_unlock(&csis->lock); 1331 1332 return ret ? -EAGAIN : 0; 1333 } 1334 1335 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) 1336 { 1337 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1338 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1339 int ret = 0; 1340 1341 mutex_lock(&csis->lock); 1342 1343 ret = mipi_csis_phy_enable(csis); 1344 if (ret) 1345 goto unlock; 1346 1347 mipi_csis_clk_enable(csis); 1348 1349 csis->powered = true; 1350 1351 unlock: 1352 mutex_unlock(&csis->lock); 1353 1354 return ret ? -EAGAIN : 0; 1355 } 1356 1357 static const struct dev_pm_ops mipi_csis_pm_ops = { 1358 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1359 NULL) 1360 }; 1361 1362 /* ----------------------------------------------------------------------------- 1363 * Probe/remove & platform driver 1364 */ 1365 1366 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1367 { 1368 struct v4l2_subdev *sd = &csis->sd; 1369 1370 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1371 sd->owner = THIS_MODULE; 1372 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1373 dev_name(csis->dev)); 1374 1375 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1376 sd->ctrl_handler = NULL; 1377 1378 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1379 sd->entity.ops = &mipi_csis_entity_ops; 1380 1381 sd->dev = csis->dev; 1382 1383 csis->csis_fmt = &mipi_csis_formats[0]; 1384 mipi_csis_init_cfg(sd, NULL); 1385 1386 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1387 | MEDIA_PAD_FL_MUST_CONNECT; 1388 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1389 | MEDIA_PAD_FL_MUST_CONNECT; 1390 return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, 1391 csis->pads); 1392 } 1393 1394 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1395 { 1396 struct device_node *node = csis->dev->of_node; 1397 1398 if (of_property_read_u32(node, "clock-frequency", 1399 &csis->clk_frequency)) 1400 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1401 1402 return 0; 1403 } 1404 1405 static int mipi_csis_probe(struct platform_device *pdev) 1406 { 1407 struct device *dev = &pdev->dev; 1408 struct mipi_csis_device *csis; 1409 int irq; 1410 int ret; 1411 1412 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1413 if (!csis) 1414 return -ENOMEM; 1415 1416 mutex_init(&csis->lock); 1417 spin_lock_init(&csis->slock); 1418 1419 csis->dev = dev; 1420 csis->info = of_device_get_match_data(dev); 1421 1422 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1423 1424 /* Parse DT properties. */ 1425 ret = mipi_csis_parse_dt(csis); 1426 if (ret < 0) { 1427 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1428 return ret; 1429 } 1430 1431 /* Acquire resources. */ 1432 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1433 if (IS_ERR(csis->regs)) 1434 return PTR_ERR(csis->regs); 1435 1436 irq = platform_get_irq(pdev, 0); 1437 if (irq < 0) 1438 return irq; 1439 1440 ret = mipi_csis_phy_init(csis); 1441 if (ret < 0) 1442 return ret; 1443 1444 ret = mipi_csis_clk_get(csis); 1445 if (ret < 0) 1446 return ret; 1447 1448 /* Reset PHY and enable the clocks. */ 1449 mipi_csis_phy_reset(csis); 1450 1451 ret = mipi_csis_clk_enable(csis); 1452 if (ret < 0) { 1453 dev_err(csis->dev, "failed to enable clocks: %d\n", ret); 1454 return ret; 1455 } 1456 1457 /* Now that the hardware is initialized, request the interrupt. */ 1458 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1459 dev_name(dev), csis); 1460 if (ret) { 1461 dev_err(dev, "Interrupt request failed\n"); 1462 goto disable_clock; 1463 } 1464 1465 /* Initialize and register the subdev. */ 1466 ret = mipi_csis_subdev_init(csis); 1467 if (ret < 0) 1468 goto disable_clock; 1469 1470 platform_set_drvdata(pdev, &csis->sd); 1471 1472 ret = mipi_csis_async_register(csis); 1473 if (ret < 0) { 1474 dev_err(dev, "async register failed: %d\n", ret); 1475 goto cleanup; 1476 } 1477 1478 /* Initialize debugfs. */ 1479 mipi_csis_debugfs_init(csis); 1480 1481 /* Enable runtime PM. */ 1482 pm_runtime_enable(dev); 1483 if (!pm_runtime_enabled(dev)) { 1484 ret = mipi_csis_runtime_resume(dev); 1485 if (ret < 0) 1486 goto unregister_all; 1487 } 1488 1489 dev_info(dev, "lanes: %d, freq: %u\n", 1490 csis->bus.num_data_lanes, csis->clk_frequency); 1491 1492 return 0; 1493 1494 unregister_all: 1495 mipi_csis_debugfs_exit(csis); 1496 cleanup: 1497 media_entity_cleanup(&csis->sd.entity); 1498 v4l2_async_nf_unregister(&csis->notifier); 1499 v4l2_async_nf_cleanup(&csis->notifier); 1500 v4l2_async_unregister_subdev(&csis->sd); 1501 disable_clock: 1502 mipi_csis_clk_disable(csis); 1503 mutex_destroy(&csis->lock); 1504 1505 return ret; 1506 } 1507 1508 static int mipi_csis_remove(struct platform_device *pdev) 1509 { 1510 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1511 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1512 1513 mipi_csis_debugfs_exit(csis); 1514 v4l2_async_nf_unregister(&csis->notifier); 1515 v4l2_async_nf_cleanup(&csis->notifier); 1516 v4l2_async_unregister_subdev(&csis->sd); 1517 1518 pm_runtime_disable(&pdev->dev); 1519 mipi_csis_runtime_suspend(&pdev->dev); 1520 mipi_csis_clk_disable(csis); 1521 media_entity_cleanup(&csis->sd.entity); 1522 mutex_destroy(&csis->lock); 1523 pm_runtime_set_suspended(&pdev->dev); 1524 1525 return 0; 1526 } 1527 1528 static const struct of_device_id mipi_csis_of_match[] = { 1529 { 1530 .compatible = "fsl,imx7-mipi-csi2", 1531 .data = &(const struct mipi_csis_info){ 1532 .version = MIPI_CSIS_V3_3, 1533 .num_clocks = 3, 1534 }, 1535 }, { 1536 .compatible = "fsl,imx8mm-mipi-csi2", 1537 .data = &(const struct mipi_csis_info){ 1538 .version = MIPI_CSIS_V3_6_3, 1539 .num_clocks = 4, 1540 }, 1541 }, 1542 { /* sentinel */ }, 1543 }; 1544 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1545 1546 static struct platform_driver mipi_csis_driver = { 1547 .probe = mipi_csis_probe, 1548 .remove = mipi_csis_remove, 1549 .driver = { 1550 .of_match_table = mipi_csis_of_match, 1551 .name = CSIS_DRIVER_NAME, 1552 .pm = &mipi_csis_pm_ops, 1553 }, 1554 }; 1555 1556 module_platform_driver(mipi_csis_driver); 1557 1558 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1559 MODULE_LICENSE("GPL v2"); 1560 MODULE_ALIAS("platform:imx-mipi-csi2"); 1561