1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Samsung CSIS MIPI CSI-2 receiver driver. 4 * 5 * The Samsung CSIS IP is a MIPI CSI-2 receiver found in various NXP i.MX7 and 6 * i.MX8 SoCs. The i.MX7 features version 3.3 of the IP, while i.MX8 features 7 * version 3.6.3. 8 * 9 * Copyright (C) 2019 Linaro Ltd 10 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved. 11 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd. 12 * 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/debugfs.h> 17 #include <linux/delay.h> 18 #include <linux/errno.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/of.h> 25 #include <linux/of_device.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/reset.h> 30 #include <linux/spinlock.h> 31 32 #include <media/v4l2-common.h> 33 #include <media/v4l2-device.h> 34 #include <media/v4l2-fwnode.h> 35 #include <media/v4l2-mc.h> 36 #include <media/v4l2-subdev.h> 37 38 #define CSIS_DRIVER_NAME "imx-mipi-csis" 39 40 #define CSIS_PAD_SINK 0 41 #define CSIS_PAD_SOURCE 1 42 #define CSIS_PADS_NUM 2 43 44 #define MIPI_CSIS_DEF_PIX_WIDTH 640 45 #define MIPI_CSIS_DEF_PIX_HEIGHT 480 46 47 /* Register map definition */ 48 49 /* CSIS version */ 50 #define MIPI_CSIS_VERSION 0x00 51 #define MIPI_CSIS_VERSION_IMX7D 0x03030505 52 #define MIPI_CSIS_VERSION_IMX8MP 0x03060301 53 54 /* CSIS common control */ 55 #define MIPI_CSIS_CMN_CTRL 0x04 56 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16) 57 #define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10) 58 #define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2) 59 #define MIPI_CSIS_CMN_CTRL_RESET BIT(1) 60 #define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0) 61 62 #define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8 63 #define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8) 64 65 /* CSIS clock control */ 66 #define MIPI_CSIS_CLK_CTRL 0x08 67 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28) 68 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24) 69 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20) 70 #define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16) 71 #define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4) 72 #define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0) 73 74 /* CSIS Interrupt mask */ 75 #define MIPI_CSIS_INT_MSK 0x10 76 #define MIPI_CSIS_INT_MSK_EVEN_BEFORE BIT(31) 77 #define MIPI_CSIS_INT_MSK_EVEN_AFTER BIT(30) 78 #define MIPI_CSIS_INT_MSK_ODD_BEFORE BIT(29) 79 #define MIPI_CSIS_INT_MSK_ODD_AFTER BIT(28) 80 #define MIPI_CSIS_INT_MSK_FRAME_START BIT(24) 81 #define MIPI_CSIS_INT_MSK_FRAME_END BIT(20) 82 #define MIPI_CSIS_INT_MSK_ERR_SOT_HS BIT(16) 83 #define MIPI_CSIS_INT_MSK_ERR_LOST_FS BIT(12) 84 #define MIPI_CSIS_INT_MSK_ERR_LOST_FE BIT(8) 85 #define MIPI_CSIS_INT_MSK_ERR_OVER BIT(4) 86 #define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG BIT(3) 87 #define MIPI_CSIS_INT_MSK_ERR_ECC BIT(2) 88 #define MIPI_CSIS_INT_MSK_ERR_CRC BIT(1) 89 #define MIPI_CSIS_INT_MSK_ERR_UNKNOWN BIT(0) 90 91 /* CSIS Interrupt source */ 92 #define MIPI_CSIS_INT_SRC 0x14 93 #define MIPI_CSIS_INT_SRC_EVEN_BEFORE BIT(31) 94 #define MIPI_CSIS_INT_SRC_EVEN_AFTER BIT(30) 95 #define MIPI_CSIS_INT_SRC_EVEN BIT(30) 96 #define MIPI_CSIS_INT_SRC_ODD_BEFORE BIT(29) 97 #define MIPI_CSIS_INT_SRC_ODD_AFTER BIT(28) 98 #define MIPI_CSIS_INT_SRC_ODD (0x3 << 28) 99 #define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA (0xf << 28) 100 #define MIPI_CSIS_INT_SRC_FRAME_START BIT(24) 101 #define MIPI_CSIS_INT_SRC_FRAME_END BIT(20) 102 #define MIPI_CSIS_INT_SRC_ERR_SOT_HS BIT(16) 103 #define MIPI_CSIS_INT_SRC_ERR_LOST_FS BIT(12) 104 #define MIPI_CSIS_INT_SRC_ERR_LOST_FE BIT(8) 105 #define MIPI_CSIS_INT_SRC_ERR_OVER BIT(4) 106 #define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG BIT(3) 107 #define MIPI_CSIS_INT_SRC_ERR_ECC BIT(2) 108 #define MIPI_CSIS_INT_SRC_ERR_CRC BIT(1) 109 #define MIPI_CSIS_INT_SRC_ERR_UNKNOWN BIT(0) 110 #define MIPI_CSIS_INT_SRC_ERRORS 0xfffff 111 112 /* D-PHY status control */ 113 #define MIPI_CSIS_DPHY_STATUS 0x20 114 #define MIPI_CSIS_DPHY_STATUS_ULPS_DAT BIT(8) 115 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT BIT(4) 116 #define MIPI_CSIS_DPHY_STATUS_ULPS_CLK BIT(1) 117 #define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK BIT(0) 118 119 /* D-PHY common control */ 120 #define MIPI_CSIS_DPHY_CMN_CTRL 0x24 121 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n) ((n) << 24) 122 #define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK GENMASK(31, 24) 123 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n) ((n) << 22) 124 #define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK GENMASK(23, 22) 125 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK BIT(6) 126 #define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT BIT(5) 127 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT BIT(1) 128 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK BIT(0) 129 #define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE (0x1f << 0) 130 131 /* D-PHY Master and Slave Control register Low */ 132 #define MIPI_CSIS_DPHY_BCTRL_L 0x30 133 #define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n) (((n) & 3U) << 30) 134 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV (0 << 28) 135 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV (1 << 28) 136 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV (2 << 28) 137 #define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV (3 << 28) 138 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ (0 << 27) 139 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ (1 << 27) 140 #define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL BIT(26) 141 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V (0 << 24) 142 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V (1 << 24) 143 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V (2 << 24) 144 #define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V (3 << 24) 145 #define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL BIT(23) 146 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV (0 << 21) 147 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV (1 << 21) 148 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV (2 << 21) 149 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV (3 << 21) 150 #define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL BIT(20) 151 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV (0 << 18) 152 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV (1 << 18) 153 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV (2 << 18) 154 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV (3 << 18) 155 #define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT BIT(17) 156 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0 (0 << 15) 157 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P (1 << 15) 158 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P (3 << 15) 159 #define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP BIT(14) 160 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV (0 << 13) 161 #define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV (1 << 13) 162 #define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN BIT(12) 163 #define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN BIT(11) 164 #define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN BIT(10) 165 #define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n) (((n) * 25 / 1000000) << 0) 166 167 /* D-PHY Master and Slave Control register High */ 168 #define MIPI_CSIS_DPHY_BCTRL_H 0x34 169 /* D-PHY Slave Control register Low */ 170 #define MIPI_CSIS_DPHY_SCTRL_L 0x38 171 /* D-PHY Slave Control register High */ 172 #define MIPI_CSIS_DPHY_SCTRL_H 0x3c 173 174 /* ISP Configuration register */ 175 #define MIPI_CSIS_ISP_CONFIG_CH(n) (0x40 + (n) * 0x10) 176 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24) 177 #define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24) 178 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE (0 << 12) 179 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL (1 << 12) 180 #define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD (2 << 12) /* i.MX8M[MNP] only */ 181 #define MIPI_CSIS_ISPCFG_PIXEL_MASK (3 << 12) 182 #define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11) 183 #define MIPI_CSIS_ISPCFG_FMT(fmt) ((fmt) << 2) 184 #define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2) 185 186 /* ISP Image Resolution register */ 187 #define MIPI_CSIS_ISP_RESOL_CH(n) (0x44 + (n) * 0x10) 188 #define CSIS_MAX_PIX_WIDTH 0xffff 189 #define CSIS_MAX_PIX_HEIGHT 0xffff 190 191 /* ISP SYNC register */ 192 #define MIPI_CSIS_ISP_SYNC_CH(n) (0x48 + (n) * 0x10) 193 #define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET 18 194 #define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET 12 195 #define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET 0 196 197 /* ISP shadow registers */ 198 #define MIPI_CSIS_SDW_CONFIG_CH(n) (0x80 + (n) * 0x10) 199 #define MIPI_CSIS_SDW_RESOL_CH(n) (0x84 + (n) * 0x10) 200 #define MIPI_CSIS_SDW_SYNC_CH(n) (0x88 + (n) * 0x10) 201 202 /* Debug control register */ 203 #define MIPI_CSIS_DBG_CTRL 0xc0 204 #define MIPI_CSIS_DBG_INTR_MSK 0xc4 205 #define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT BIT(25) 206 #define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE BIT(24) 207 #define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE BIT(20) 208 #define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME BIT(16) 209 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE BIT(12) 210 #define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS BIT(8) 211 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL BIT(4) 212 #define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE BIT(0) 213 #define MIPI_CSIS_DBG_INTR_SRC 0xc8 214 #define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT BIT(25) 215 #define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE BIT(24) 216 #define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE BIT(20) 217 #define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME BIT(16) 218 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE BIT(12) 219 #define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS BIT(8) 220 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL BIT(4) 221 #define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE BIT(0) 222 223 #define MIPI_CSIS_FRAME_COUNTER_CH(n) (0x0100 + (n) * 4) 224 225 /* Non-image packet data buffers */ 226 #define MIPI_CSIS_PKTDATA_ODD 0x2000 227 #define MIPI_CSIS_PKTDATA_EVEN 0x3000 228 #define MIPI_CSIS_PKTDATA_SIZE SZ_4K 229 230 #define DEFAULT_SCLK_CSIS_FREQ 166000000UL 231 232 /* MIPI CSI-2 Data Types */ 233 #define MIPI_CSI2_DATA_TYPE_YUV420_8 0x18 234 #define MIPI_CSI2_DATA_TYPE_YUV420_10 0x19 235 #define MIPI_CSI2_DATA_TYPE_LE_YUV420_8 0x1a 236 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_8 0x1c 237 #define MIPI_CSI2_DATA_TYPE_CS_YUV420_10 0x1d 238 #define MIPI_CSI2_DATA_TYPE_YUV422_8 0x1e 239 #define MIPI_CSI2_DATA_TYPE_YUV422_10 0x1f 240 #define MIPI_CSI2_DATA_TYPE_RGB565 0x22 241 #define MIPI_CSI2_DATA_TYPE_RGB666 0x23 242 #define MIPI_CSI2_DATA_TYPE_RGB888 0x24 243 #define MIPI_CSI2_DATA_TYPE_RAW6 0x28 244 #define MIPI_CSI2_DATA_TYPE_RAW7 0x29 245 #define MIPI_CSI2_DATA_TYPE_RAW8 0x2a 246 #define MIPI_CSI2_DATA_TYPE_RAW10 0x2b 247 #define MIPI_CSI2_DATA_TYPE_RAW12 0x2c 248 #define MIPI_CSI2_DATA_TYPE_RAW14 0x2d 249 #define MIPI_CSI2_DATA_TYPE_USER(x) (0x30 + (x)) 250 251 struct mipi_csis_event { 252 bool debug; 253 u32 mask; 254 const char * const name; 255 unsigned int counter; 256 }; 257 258 static const struct mipi_csis_event mipi_csis_events[] = { 259 /* Errors */ 260 { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS, "SOT Error" }, 261 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS, "Lost Frame Start Error" }, 262 { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE, "Lost Frame End Error" }, 263 { false, MIPI_CSIS_INT_SRC_ERR_OVER, "FIFO Overflow Error" }, 264 { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG, "Wrong Configuration Error" }, 265 { false, MIPI_CSIS_INT_SRC_ERR_ECC, "ECC Error" }, 266 { false, MIPI_CSIS_INT_SRC_ERR_CRC, "CRC Error" }, 267 { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN, "Unknown Error" }, 268 { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT, "Data Type Not Supported" }, 269 { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE, "Data Type Ignored" }, 270 { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE, "Frame Size Error" }, 271 { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" }, 272 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE, "Early Frame End" }, 273 { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS, "Early Frame Start" }, 274 /* Non-image data receive events */ 275 { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE, "Non-image data before even frame" }, 276 { false, MIPI_CSIS_INT_SRC_EVEN_AFTER, "Non-image data after even frame" }, 277 { false, MIPI_CSIS_INT_SRC_ODD_BEFORE, "Non-image data before odd frame" }, 278 { false, MIPI_CSIS_INT_SRC_ODD_AFTER, "Non-image data after odd frame" }, 279 /* Frame start/end */ 280 { false, MIPI_CSIS_INT_SRC_FRAME_START, "Frame Start" }, 281 { false, MIPI_CSIS_INT_SRC_FRAME_END, "Frame End" }, 282 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL, "VSYNC Falling Edge" }, 283 { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE, "VSYNC Rising Edge" }, 284 }; 285 286 #define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events) 287 288 enum mipi_csis_clk { 289 MIPI_CSIS_CLK_PCLK, 290 MIPI_CSIS_CLK_WRAP, 291 MIPI_CSIS_CLK_PHY, 292 MIPI_CSIS_CLK_AXI, 293 }; 294 295 static const char * const mipi_csis_clk_id[] = { 296 "pclk", 297 "wrap", 298 "phy", 299 "axi", 300 }; 301 302 enum mipi_csis_version { 303 MIPI_CSIS_V3_3, 304 MIPI_CSIS_V3_6_3, 305 }; 306 307 struct mipi_csis_info { 308 enum mipi_csis_version version; 309 unsigned int num_clocks; 310 }; 311 312 struct mipi_csis_device { 313 struct device *dev; 314 void __iomem *regs; 315 struct clk_bulk_data *clks; 316 struct reset_control *mrst; 317 struct regulator *mipi_phy_regulator; 318 const struct mipi_csis_info *info; 319 320 struct v4l2_subdev sd; 321 struct media_pad pads[CSIS_PADS_NUM]; 322 struct v4l2_async_notifier notifier; 323 struct v4l2_subdev *src_sd; 324 325 struct v4l2_mbus_config_mipi_csi2 bus; 326 u32 clk_frequency; 327 u32 hs_settle; 328 u32 clk_settle; 329 330 struct mutex lock; /* Protect csis_fmt and format_mbus */ 331 const struct csis_pix_format *csis_fmt; 332 struct v4l2_mbus_framefmt format_mbus[CSIS_PADS_NUM]; 333 334 spinlock_t slock; /* Protect events */ 335 struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS]; 336 struct dentry *debugfs_root; 337 struct { 338 bool enable; 339 u32 hs_settle; 340 u32 clk_settle; 341 } debug; 342 }; 343 344 /* ----------------------------------------------------------------------------- 345 * Format helpers 346 */ 347 348 struct csis_pix_format { 349 u32 code; 350 u32 output; 351 u32 data_type; 352 u8 width; 353 }; 354 355 static const struct csis_pix_format mipi_csis_formats[] = { 356 /* YUV formats. */ 357 { 358 .code = MEDIA_BUS_FMT_UYVY8_1X16, 359 .output = MEDIA_BUS_FMT_UYVY8_1X16, 360 .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8, 361 .width = 16, 362 }, 363 /* RGB formats. */ 364 { 365 .code = MEDIA_BUS_FMT_RGB565_1X16, 366 .output = MEDIA_BUS_FMT_RGB565_1X16, 367 .data_type = MIPI_CSI2_DATA_TYPE_RGB565, 368 .width = 16, 369 }, { 370 .code = MEDIA_BUS_FMT_BGR888_1X24, 371 .output = MEDIA_BUS_FMT_RGB888_1X24, 372 .data_type = MIPI_CSI2_DATA_TYPE_RGB888, 373 .width = 24, 374 }, 375 /* RAW (Bayer and greyscale) formats. */ 376 { 377 .code = MEDIA_BUS_FMT_SBGGR8_1X8, 378 .output = MEDIA_BUS_FMT_SBGGR8_1X8, 379 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 380 .width = 8, 381 }, { 382 .code = MEDIA_BUS_FMT_SGBRG8_1X8, 383 .output = MEDIA_BUS_FMT_SGBRG8_1X8, 384 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 385 .width = 8, 386 }, { 387 .code = MEDIA_BUS_FMT_SGRBG8_1X8, 388 .output = MEDIA_BUS_FMT_SGRBG8_1X8, 389 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 390 .width = 8, 391 }, { 392 .code = MEDIA_BUS_FMT_SRGGB8_1X8, 393 .output = MEDIA_BUS_FMT_SRGGB8_1X8, 394 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 395 .width = 8, 396 }, { 397 .code = MEDIA_BUS_FMT_Y8_1X8, 398 .output = MEDIA_BUS_FMT_Y8_1X8, 399 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 400 .width = 8, 401 }, { 402 .code = MEDIA_BUS_FMT_SBGGR10_1X10, 403 .output = MEDIA_BUS_FMT_SBGGR10_1X10, 404 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 405 .width = 10, 406 }, { 407 .code = MEDIA_BUS_FMT_SGBRG10_1X10, 408 .output = MEDIA_BUS_FMT_SGBRG10_1X10, 409 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 410 .width = 10, 411 }, { 412 .code = MEDIA_BUS_FMT_SGRBG10_1X10, 413 .output = MEDIA_BUS_FMT_SGRBG10_1X10, 414 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 415 .width = 10, 416 }, { 417 .code = MEDIA_BUS_FMT_SRGGB10_1X10, 418 .output = MEDIA_BUS_FMT_SRGGB10_1X10, 419 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 420 .width = 10, 421 }, { 422 .code = MEDIA_BUS_FMT_Y10_1X10, 423 .output = MEDIA_BUS_FMT_Y10_1X10, 424 .data_type = MIPI_CSI2_DATA_TYPE_RAW10, 425 .width = 10, 426 }, { 427 .code = MEDIA_BUS_FMT_SBGGR12_1X12, 428 .output = MEDIA_BUS_FMT_SBGGR12_1X12, 429 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 430 .width = 12, 431 }, { 432 .code = MEDIA_BUS_FMT_SGBRG12_1X12, 433 .output = MEDIA_BUS_FMT_SGBRG12_1X12, 434 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 435 .width = 12, 436 }, { 437 .code = MEDIA_BUS_FMT_SGRBG12_1X12, 438 .output = MEDIA_BUS_FMT_SGRBG12_1X12, 439 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 440 .width = 12, 441 }, { 442 .code = MEDIA_BUS_FMT_SRGGB12_1X12, 443 .output = MEDIA_BUS_FMT_SRGGB12_1X12, 444 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 445 .width = 12, 446 }, { 447 .code = MEDIA_BUS_FMT_Y12_1X12, 448 .output = MEDIA_BUS_FMT_Y12_1X12, 449 .data_type = MIPI_CSI2_DATA_TYPE_RAW12, 450 .width = 12, 451 }, { 452 .code = MEDIA_BUS_FMT_SBGGR14_1X14, 453 .output = MEDIA_BUS_FMT_SBGGR14_1X14, 454 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 455 .width = 14, 456 }, { 457 .code = MEDIA_BUS_FMT_SGBRG14_1X14, 458 .output = MEDIA_BUS_FMT_SGBRG14_1X14, 459 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 460 .width = 14, 461 }, { 462 .code = MEDIA_BUS_FMT_SGRBG14_1X14, 463 .output = MEDIA_BUS_FMT_SGRBG14_1X14, 464 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 465 .width = 14, 466 }, { 467 .code = MEDIA_BUS_FMT_SRGGB14_1X14, 468 .output = MEDIA_BUS_FMT_SRGGB14_1X14, 469 .data_type = MIPI_CSI2_DATA_TYPE_RAW14, 470 .width = 14, 471 }, 472 /* JPEG */ 473 { 474 .code = MEDIA_BUS_FMT_JPEG_1X8, 475 .output = MEDIA_BUS_FMT_JPEG_1X8, 476 /* 477 * Map JPEG_1X8 to the RAW8 datatype. 478 * 479 * The CSI-2 specification suggests in Annex A "JPEG8 Data 480 * Format (informative)" to transmit JPEG data using one of the 481 * Data Types aimed to represent arbitrary data, such as the 482 * "User Defined Data Type 1" (0x30). 483 * 484 * However, when configured with a User Defined Data Type, the 485 * CSIS outputs data in quad pixel mode regardless of the mode 486 * selected in the MIPI_CSIS_ISP_CONFIG_CH register. Neither of 487 * the IP cores connected to the CSIS in i.MX SoCs (CSI bridge 488 * or ISI) support quad pixel mode, so this will never work in 489 * practice. 490 * 491 * Some sensors (such as the OV5640) send JPEG data using the 492 * RAW8 data type. This is usable and works, so map the JPEG 493 * format to RAW8. If the CSIS ends up being integrated in an 494 * SoC that can support quad pixel mode, this will have to be 495 * revisited. 496 */ 497 .data_type = MIPI_CSI2_DATA_TYPE_RAW8, 498 .width = 8, 499 } 500 }; 501 502 static const struct csis_pix_format *find_csis_format(u32 code) 503 { 504 unsigned int i; 505 506 for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++) 507 if (code == mipi_csis_formats[i].code) 508 return &mipi_csis_formats[i]; 509 return NULL; 510 } 511 512 /* ----------------------------------------------------------------------------- 513 * Hardware configuration 514 */ 515 516 static inline u32 mipi_csis_read(struct mipi_csis_device *csis, u32 reg) 517 { 518 return readl(csis->regs + reg); 519 } 520 521 static inline void mipi_csis_write(struct mipi_csis_device *csis, u32 reg, 522 u32 val) 523 { 524 writel(val, csis->regs + reg); 525 } 526 527 static void mipi_csis_enable_interrupts(struct mipi_csis_device *csis, bool on) 528 { 529 mipi_csis_write(csis, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0); 530 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0); 531 } 532 533 static void mipi_csis_sw_reset(struct mipi_csis_device *csis) 534 { 535 u32 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 536 537 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 538 val | MIPI_CSIS_CMN_CTRL_RESET); 539 usleep_range(10, 20); 540 } 541 542 static void mipi_csis_system_enable(struct mipi_csis_device *csis, int on) 543 { 544 u32 val, mask; 545 546 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 547 if (on) 548 val |= MIPI_CSIS_CMN_CTRL_ENABLE; 549 else 550 val &= ~MIPI_CSIS_CMN_CTRL_ENABLE; 551 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 552 553 val = mipi_csis_read(csis, MIPI_CSIS_DPHY_CMN_CTRL); 554 val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE; 555 if (on) { 556 mask = (1 << (csis->bus.num_data_lanes + 1)) - 1; 557 val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE); 558 } 559 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, val); 560 } 561 562 /* Called with the csis.lock mutex held */ 563 static void __mipi_csis_set_format(struct mipi_csis_device *csis) 564 { 565 struct v4l2_mbus_framefmt *mf = &csis->format_mbus[CSIS_PAD_SINK]; 566 u32 val; 567 568 /* Color format */ 569 val = mipi_csis_read(csis, MIPI_CSIS_ISP_CONFIG_CH(0)); 570 val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK 571 | MIPI_CSIS_ISPCFG_PIXEL_MASK); 572 573 /* 574 * YUV 4:2:2 can be transferred with 8 or 16 bits per clock sample 575 * (referred to in the documentation as single and dual pixel modes 576 * respectively, although the 8-bit mode transfers half a pixel per 577 * clock sample and the 16-bit mode one pixel). While both mode work 578 * when the CSIS is connected to a receiver that supports either option, 579 * single pixel mode requires clock rates twice as high. As all SoCs 580 * that integrate the CSIS can operate in 16-bit bit mode, and some do 581 * not support 8-bit mode (this is the case of the i.MX8MP), use dual 582 * pixel mode unconditionally. 583 * 584 * TODO: Verify which other formats require DUAL (or QUAD) modes. 585 */ 586 if (csis->csis_fmt->data_type == MIPI_CSI2_DATA_TYPE_YUV422_8) 587 val |= MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL; 588 589 val |= MIPI_CSIS_ISPCFG_FMT(csis->csis_fmt->data_type); 590 mipi_csis_write(csis, MIPI_CSIS_ISP_CONFIG_CH(0), val); 591 592 /* Pixel resolution */ 593 val = mf->width | (mf->height << 16); 594 mipi_csis_write(csis, MIPI_CSIS_ISP_RESOL_CH(0), val); 595 } 596 597 static int mipi_csis_calculate_params(struct mipi_csis_device *csis) 598 { 599 s64 link_freq; 600 u32 lane_rate; 601 602 /* Calculate the line rate from the pixel rate. */ 603 link_freq = v4l2_get_link_freq(csis->src_sd->ctrl_handler, 604 csis->csis_fmt->width, 605 csis->bus.num_data_lanes * 2); 606 if (link_freq < 0) { 607 dev_err(csis->dev, "Unable to obtain link frequency: %d\n", 608 (int)link_freq); 609 return link_freq; 610 } 611 612 lane_rate = link_freq * 2; 613 614 if (lane_rate < 80000000 || lane_rate > 1500000000) { 615 dev_dbg(csis->dev, "Out-of-bound lane rate %u\n", lane_rate); 616 return -EINVAL; 617 } 618 619 /* 620 * The HSSETTLE counter value is document in a table, but can also 621 * easily be calculated. Hardcode the CLKSETTLE value to 0 for now 622 * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until 623 * we figure out how to compute it correctly. 624 */ 625 csis->hs_settle = (lane_rate - 5000000) / 45000000; 626 csis->clk_settle = 0; 627 628 dev_dbg(csis->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n", 629 lane_rate, csis->clk_settle, csis->hs_settle); 630 631 if (csis->debug.hs_settle < 0xff) { 632 dev_dbg(csis->dev, "overriding Ths_settle with %u\n", 633 csis->debug.hs_settle); 634 csis->hs_settle = csis->debug.hs_settle; 635 } 636 637 if (csis->debug.clk_settle < 4) { 638 dev_dbg(csis->dev, "overriding Tclk_settle with %u\n", 639 csis->debug.clk_settle); 640 csis->clk_settle = csis->debug.clk_settle; 641 } 642 643 return 0; 644 } 645 646 static void mipi_csis_set_params(struct mipi_csis_device *csis) 647 { 648 int lanes = csis->bus.num_data_lanes; 649 u32 val; 650 651 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 652 val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK; 653 val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET; 654 if (csis->info->version == MIPI_CSIS_V3_3) 655 val |= MIPI_CSIS_CMN_CTRL_INTER_MODE; 656 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, val); 657 658 __mipi_csis_set_format(csis); 659 660 mipi_csis_write(csis, MIPI_CSIS_DPHY_CMN_CTRL, 661 MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(csis->hs_settle) | 662 MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(csis->clk_settle)); 663 664 val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET) 665 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET) 666 | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET); 667 mipi_csis_write(csis, MIPI_CSIS_ISP_SYNC_CH(0), val); 668 669 val = mipi_csis_read(csis, MIPI_CSIS_CLK_CTRL); 670 val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC; 671 val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15); 672 val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK; 673 mipi_csis_write(csis, MIPI_CSIS_CLK_CTRL, val); 674 675 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_L, 676 MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV | 677 MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ | 678 MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V | 679 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV | 680 MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV | 681 MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV | 682 MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000)); 683 mipi_csis_write(csis, MIPI_CSIS_DPHY_BCTRL_H, 0); 684 685 /* Update the shadow register. */ 686 val = mipi_csis_read(csis, MIPI_CSIS_CMN_CTRL); 687 mipi_csis_write(csis, MIPI_CSIS_CMN_CTRL, 688 val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW | 689 MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL); 690 } 691 692 static int mipi_csis_clk_enable(struct mipi_csis_device *csis) 693 { 694 return clk_bulk_prepare_enable(csis->info->num_clocks, csis->clks); 695 } 696 697 static void mipi_csis_clk_disable(struct mipi_csis_device *csis) 698 { 699 clk_bulk_disable_unprepare(csis->info->num_clocks, csis->clks); 700 } 701 702 static int mipi_csis_clk_get(struct mipi_csis_device *csis) 703 { 704 unsigned int i; 705 int ret; 706 707 csis->clks = devm_kcalloc(csis->dev, csis->info->num_clocks, 708 sizeof(*csis->clks), GFP_KERNEL); 709 710 if (!csis->clks) 711 return -ENOMEM; 712 713 for (i = 0; i < csis->info->num_clocks; i++) 714 csis->clks[i].id = mipi_csis_clk_id[i]; 715 716 ret = devm_clk_bulk_get(csis->dev, csis->info->num_clocks, 717 csis->clks); 718 if (ret < 0) 719 return ret; 720 721 /* Set clock rate */ 722 ret = clk_set_rate(csis->clks[MIPI_CSIS_CLK_WRAP].clk, 723 csis->clk_frequency); 724 if (ret < 0) 725 dev_err(csis->dev, "set rate=%d failed: %d\n", 726 csis->clk_frequency, ret); 727 728 return ret; 729 } 730 731 static void mipi_csis_start_stream(struct mipi_csis_device *csis) 732 { 733 mipi_csis_sw_reset(csis); 734 mipi_csis_set_params(csis); 735 mipi_csis_system_enable(csis, true); 736 mipi_csis_enable_interrupts(csis, true); 737 } 738 739 static void mipi_csis_stop_stream(struct mipi_csis_device *csis) 740 { 741 mipi_csis_enable_interrupts(csis, false); 742 mipi_csis_system_enable(csis, false); 743 } 744 745 static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id) 746 { 747 struct mipi_csis_device *csis = dev_id; 748 unsigned long flags; 749 unsigned int i; 750 u32 status; 751 u32 dbg_status; 752 753 status = mipi_csis_read(csis, MIPI_CSIS_INT_SRC); 754 dbg_status = mipi_csis_read(csis, MIPI_CSIS_DBG_INTR_SRC); 755 756 spin_lock_irqsave(&csis->slock, flags); 757 758 /* Update the event/error counters */ 759 if ((status & MIPI_CSIS_INT_SRC_ERRORS) || csis->debug.enable) { 760 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) { 761 struct mipi_csis_event *event = &csis->events[i]; 762 763 if ((!event->debug && (status & event->mask)) || 764 (event->debug && (dbg_status & event->mask))) 765 event->counter++; 766 } 767 } 768 spin_unlock_irqrestore(&csis->slock, flags); 769 770 mipi_csis_write(csis, MIPI_CSIS_INT_SRC, status); 771 mipi_csis_write(csis, MIPI_CSIS_DBG_INTR_SRC, dbg_status); 772 773 return IRQ_HANDLED; 774 } 775 776 /* ----------------------------------------------------------------------------- 777 * PHY regulator and reset 778 */ 779 780 static int mipi_csis_phy_enable(struct mipi_csis_device *csis) 781 { 782 if (csis->info->version != MIPI_CSIS_V3_3) 783 return 0; 784 785 return regulator_enable(csis->mipi_phy_regulator); 786 } 787 788 static int mipi_csis_phy_disable(struct mipi_csis_device *csis) 789 { 790 if (csis->info->version != MIPI_CSIS_V3_3) 791 return 0; 792 793 return regulator_disable(csis->mipi_phy_regulator); 794 } 795 796 static void mipi_csis_phy_reset(struct mipi_csis_device *csis) 797 { 798 if (csis->info->version != MIPI_CSIS_V3_3) 799 return; 800 801 reset_control_assert(csis->mrst); 802 msleep(20); 803 reset_control_deassert(csis->mrst); 804 } 805 806 static int mipi_csis_phy_init(struct mipi_csis_device *csis) 807 { 808 if (csis->info->version != MIPI_CSIS_V3_3) 809 return 0; 810 811 /* Get MIPI PHY reset and regulator. */ 812 csis->mrst = devm_reset_control_get_exclusive(csis->dev, NULL); 813 if (IS_ERR(csis->mrst)) 814 return PTR_ERR(csis->mrst); 815 816 csis->mipi_phy_regulator = devm_regulator_get(csis->dev, "phy"); 817 if (IS_ERR(csis->mipi_phy_regulator)) 818 return PTR_ERR(csis->mipi_phy_regulator); 819 820 return regulator_set_voltage(csis->mipi_phy_regulator, 1000000, 821 1000000); 822 } 823 824 /* ----------------------------------------------------------------------------- 825 * Debug 826 */ 827 828 static void mipi_csis_clear_counters(struct mipi_csis_device *csis) 829 { 830 unsigned long flags; 831 unsigned int i; 832 833 spin_lock_irqsave(&csis->slock, flags); 834 for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) 835 csis->events[i].counter = 0; 836 spin_unlock_irqrestore(&csis->slock, flags); 837 } 838 839 static void mipi_csis_log_counters(struct mipi_csis_device *csis, bool non_errors) 840 { 841 unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS 842 : MIPI_CSIS_NUM_EVENTS - 8; 843 unsigned long flags; 844 unsigned int i; 845 846 spin_lock_irqsave(&csis->slock, flags); 847 848 for (i = 0; i < num_events; ++i) { 849 if (csis->events[i].counter > 0 || csis->debug.enable) 850 dev_info(csis->dev, "%s events: %d\n", 851 csis->events[i].name, 852 csis->events[i].counter); 853 } 854 spin_unlock_irqrestore(&csis->slock, flags); 855 } 856 857 static int mipi_csis_dump_regs(struct mipi_csis_device *csis) 858 { 859 static const struct { 860 u32 offset; 861 const char * const name; 862 } registers[] = { 863 { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" }, 864 { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" }, 865 { MIPI_CSIS_INT_MSK, "INT_MSK" }, 866 { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" }, 867 { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" }, 868 { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" }, 869 { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" }, 870 { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" }, 871 { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" }, 872 { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" }, 873 { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" }, 874 { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" }, 875 { MIPI_CSIS_FRAME_COUNTER_CH(0), "FRAME_COUNTER_CH0" }, 876 }; 877 878 unsigned int i; 879 u32 cfg; 880 881 if (!pm_runtime_get_if_in_use(csis->dev)) 882 return 0; 883 884 dev_info(csis->dev, "--- REGISTERS ---\n"); 885 886 for (i = 0; i < ARRAY_SIZE(registers); i++) { 887 cfg = mipi_csis_read(csis, registers[i].offset); 888 dev_info(csis->dev, "%14s: 0x%08x\n", registers[i].name, cfg); 889 } 890 891 pm_runtime_put(csis->dev); 892 893 return 0; 894 } 895 896 static int mipi_csis_dump_regs_show(struct seq_file *m, void *private) 897 { 898 struct mipi_csis_device *csis = m->private; 899 900 return mipi_csis_dump_regs(csis); 901 } 902 DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs); 903 904 static void mipi_csis_debugfs_init(struct mipi_csis_device *csis) 905 { 906 csis->debug.hs_settle = UINT_MAX; 907 csis->debug.clk_settle = UINT_MAX; 908 909 csis->debugfs_root = debugfs_create_dir(dev_name(csis->dev), NULL); 910 911 debugfs_create_bool("debug_enable", 0600, csis->debugfs_root, 912 &csis->debug.enable); 913 debugfs_create_file("dump_regs", 0600, csis->debugfs_root, csis, 914 &mipi_csis_dump_regs_fops); 915 debugfs_create_u32("tclk_settle", 0600, csis->debugfs_root, 916 &csis->debug.clk_settle); 917 debugfs_create_u32("ths_settle", 0600, csis->debugfs_root, 918 &csis->debug.hs_settle); 919 } 920 921 static void mipi_csis_debugfs_exit(struct mipi_csis_device *csis) 922 { 923 debugfs_remove_recursive(csis->debugfs_root); 924 } 925 926 /* ----------------------------------------------------------------------------- 927 * V4L2 subdev operations 928 */ 929 930 static struct mipi_csis_device *sd_to_mipi_csis_device(struct v4l2_subdev *sdev) 931 { 932 return container_of(sdev, struct mipi_csis_device, sd); 933 } 934 935 static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable) 936 { 937 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 938 int ret; 939 940 if (!enable) { 941 mutex_lock(&csis->lock); 942 943 v4l2_subdev_call(csis->src_sd, video, s_stream, 0); 944 945 mipi_csis_stop_stream(csis); 946 if (csis->debug.enable) 947 mipi_csis_log_counters(csis, true); 948 949 mutex_unlock(&csis->lock); 950 951 pm_runtime_put(csis->dev); 952 953 return 0; 954 } 955 956 ret = mipi_csis_calculate_params(csis); 957 if (ret < 0) 958 return ret; 959 960 mipi_csis_clear_counters(csis); 961 962 ret = pm_runtime_resume_and_get(csis->dev); 963 if (ret < 0) 964 return ret; 965 966 mutex_lock(&csis->lock); 967 968 mipi_csis_start_stream(csis); 969 ret = v4l2_subdev_call(csis->src_sd, video, s_stream, 1); 970 if (ret < 0) 971 goto error; 972 973 mipi_csis_log_counters(csis, true); 974 975 mutex_unlock(&csis->lock); 976 977 return 0; 978 979 error: 980 mipi_csis_stop_stream(csis); 981 mutex_unlock(&csis->lock); 982 pm_runtime_put(csis->dev); 983 984 return ret; 985 } 986 987 static struct v4l2_mbus_framefmt * 988 mipi_csis_get_format(struct mipi_csis_device *csis, 989 struct v4l2_subdev_state *sd_state, 990 enum v4l2_subdev_format_whence which, 991 unsigned int pad) 992 { 993 if (which == V4L2_SUBDEV_FORMAT_TRY) 994 return v4l2_subdev_get_try_format(&csis->sd, sd_state, pad); 995 996 return &csis->format_mbus[pad]; 997 } 998 999 static int mipi_csis_init_cfg(struct v4l2_subdev *sd, 1000 struct v4l2_subdev_state *sd_state) 1001 { 1002 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1003 struct v4l2_mbus_framefmt *fmt_sink; 1004 struct v4l2_mbus_framefmt *fmt_source; 1005 enum v4l2_subdev_format_whence which; 1006 1007 which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE; 1008 fmt_sink = mipi_csis_get_format(csis, sd_state, which, CSIS_PAD_SINK); 1009 1010 fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16; 1011 fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH; 1012 fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT; 1013 fmt_sink->field = V4L2_FIELD_NONE; 1014 1015 fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M; 1016 fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace); 1017 fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace); 1018 fmt_sink->quantization = 1019 V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace, 1020 fmt_sink->ycbcr_enc); 1021 1022 fmt_source = mipi_csis_get_format(csis, sd_state, which, 1023 CSIS_PAD_SOURCE); 1024 *fmt_source = *fmt_sink; 1025 1026 return 0; 1027 } 1028 1029 static int mipi_csis_get_fmt(struct v4l2_subdev *sd, 1030 struct v4l2_subdev_state *sd_state, 1031 struct v4l2_subdev_format *sdformat) 1032 { 1033 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1034 struct v4l2_mbus_framefmt *fmt; 1035 1036 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1037 sdformat->pad); 1038 1039 mutex_lock(&csis->lock); 1040 sdformat->format = *fmt; 1041 mutex_unlock(&csis->lock); 1042 1043 return 0; 1044 } 1045 1046 static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd, 1047 struct v4l2_subdev_state *sd_state, 1048 struct v4l2_subdev_mbus_code_enum *code) 1049 { 1050 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1051 1052 /* 1053 * The CSIS can't transcode in any way, the source format is identical 1054 * to the sink format. 1055 */ 1056 if (code->pad == CSIS_PAD_SOURCE) { 1057 struct v4l2_mbus_framefmt *fmt; 1058 1059 if (code->index > 0) 1060 return -EINVAL; 1061 1062 fmt = mipi_csis_get_format(csis, sd_state, code->which, 1063 code->pad); 1064 code->code = fmt->code; 1065 return 0; 1066 } 1067 1068 if (code->pad != CSIS_PAD_SINK) 1069 return -EINVAL; 1070 1071 if (code->index >= ARRAY_SIZE(mipi_csis_formats)) 1072 return -EINVAL; 1073 1074 code->code = mipi_csis_formats[code->index].code; 1075 1076 return 0; 1077 } 1078 1079 static int mipi_csis_set_fmt(struct v4l2_subdev *sd, 1080 struct v4l2_subdev_state *sd_state, 1081 struct v4l2_subdev_format *sdformat) 1082 { 1083 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1084 struct csis_pix_format const *csis_fmt; 1085 struct v4l2_mbus_framefmt *fmt; 1086 unsigned int align; 1087 1088 /* 1089 * The CSIS can't transcode in any way, the source format can't be 1090 * modified. 1091 */ 1092 if (sdformat->pad == CSIS_PAD_SOURCE) 1093 return mipi_csis_get_fmt(sd, sd_state, sdformat); 1094 1095 if (sdformat->pad != CSIS_PAD_SINK) 1096 return -EINVAL; 1097 1098 /* 1099 * Validate the media bus code and clamp and align the size. 1100 * 1101 * The total number of bits per line must be a multiple of 8. We thus 1102 * need to align the width for formats that are not multiples of 8 1103 * bits. 1104 */ 1105 csis_fmt = find_csis_format(sdformat->format.code); 1106 if (!csis_fmt) 1107 csis_fmt = &mipi_csis_formats[0]; 1108 1109 switch (csis_fmt->width % 8) { 1110 case 0: 1111 align = 0; 1112 break; 1113 case 4: 1114 align = 1; 1115 break; 1116 case 2: 1117 case 6: 1118 align = 2; 1119 break; 1120 default: 1121 /* 1, 3, 5, 7 */ 1122 align = 3; 1123 break; 1124 } 1125 1126 v4l_bound_align_image(&sdformat->format.width, 1, 1127 CSIS_MAX_PIX_WIDTH, align, 1128 &sdformat->format.height, 1, 1129 CSIS_MAX_PIX_HEIGHT, 0, 0); 1130 1131 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1132 sdformat->pad); 1133 1134 mutex_lock(&csis->lock); 1135 1136 fmt->code = csis_fmt->code; 1137 fmt->width = sdformat->format.width; 1138 fmt->height = sdformat->format.height; 1139 fmt->colorspace = sdformat->format.colorspace; 1140 fmt->quantization = sdformat->format.quantization; 1141 fmt->xfer_func = sdformat->format.xfer_func; 1142 fmt->ycbcr_enc = sdformat->format.ycbcr_enc; 1143 1144 sdformat->format = *fmt; 1145 1146 /* Propagate the format from sink to source. */ 1147 fmt = mipi_csis_get_format(csis, sd_state, sdformat->which, 1148 CSIS_PAD_SOURCE); 1149 *fmt = sdformat->format; 1150 1151 /* The format on the source pad might change due to unpacking. */ 1152 fmt->code = csis_fmt->output; 1153 1154 /* Store the CSIS format descriptor for active formats. */ 1155 if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE) 1156 csis->csis_fmt = csis_fmt; 1157 1158 mutex_unlock(&csis->lock); 1159 1160 return 0; 1161 } 1162 1163 static int mipi_csis_log_status(struct v4l2_subdev *sd) 1164 { 1165 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1166 1167 mipi_csis_log_counters(csis, true); 1168 if (csis->debug.enable) 1169 mipi_csis_dump_regs(csis); 1170 1171 return 0; 1172 } 1173 1174 static const struct v4l2_subdev_core_ops mipi_csis_core_ops = { 1175 .log_status = mipi_csis_log_status, 1176 }; 1177 1178 static const struct v4l2_subdev_video_ops mipi_csis_video_ops = { 1179 .s_stream = mipi_csis_s_stream, 1180 }; 1181 1182 static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = { 1183 .init_cfg = mipi_csis_init_cfg, 1184 .enum_mbus_code = mipi_csis_enum_mbus_code, 1185 .get_fmt = mipi_csis_get_fmt, 1186 .set_fmt = mipi_csis_set_fmt, 1187 }; 1188 1189 static const struct v4l2_subdev_ops mipi_csis_subdev_ops = { 1190 .core = &mipi_csis_core_ops, 1191 .video = &mipi_csis_video_ops, 1192 .pad = &mipi_csis_pad_ops, 1193 }; 1194 1195 /* ----------------------------------------------------------------------------- 1196 * Media entity operations 1197 */ 1198 1199 static int mipi_csis_link_setup(struct media_entity *entity, 1200 const struct media_pad *local_pad, 1201 const struct media_pad *remote_pad, u32 flags) 1202 { 1203 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); 1204 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1205 struct v4l2_subdev *remote_sd; 1206 1207 dev_dbg(csis->dev, "link setup %s -> %s", remote_pad->entity->name, 1208 local_pad->entity->name); 1209 1210 /* We only care about the link to the source. */ 1211 if (!(local_pad->flags & MEDIA_PAD_FL_SINK)) 1212 return 0; 1213 1214 remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity); 1215 1216 if (flags & MEDIA_LNK_FL_ENABLED) { 1217 if (csis->src_sd) 1218 return -EBUSY; 1219 1220 csis->src_sd = remote_sd; 1221 } else { 1222 csis->src_sd = NULL; 1223 } 1224 1225 return 0; 1226 } 1227 1228 static const struct media_entity_operations mipi_csis_entity_ops = { 1229 .link_setup = mipi_csis_link_setup, 1230 .link_validate = v4l2_subdev_link_validate, 1231 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1, 1232 }; 1233 1234 /* ----------------------------------------------------------------------------- 1235 * Async subdev notifier 1236 */ 1237 1238 static struct mipi_csis_device * 1239 mipi_notifier_to_csis_state(struct v4l2_async_notifier *n) 1240 { 1241 return container_of(n, struct mipi_csis_device, notifier); 1242 } 1243 1244 static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier, 1245 struct v4l2_subdev *sd, 1246 struct v4l2_async_subdev *asd) 1247 { 1248 struct mipi_csis_device *csis = mipi_notifier_to_csis_state(notifier); 1249 struct media_pad *sink = &csis->sd.entity.pads[CSIS_PAD_SINK]; 1250 1251 return v4l2_create_fwnode_links_to_pad(sd, sink, 0); 1252 } 1253 1254 static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = { 1255 .bound = mipi_csis_notify_bound, 1256 }; 1257 1258 static int mipi_csis_async_register(struct mipi_csis_device *csis) 1259 { 1260 struct v4l2_fwnode_endpoint vep = { 1261 .bus_type = V4L2_MBUS_CSI2_DPHY, 1262 }; 1263 struct v4l2_async_subdev *asd; 1264 struct fwnode_handle *ep; 1265 unsigned int i; 1266 int ret; 1267 1268 v4l2_async_nf_init(&csis->notifier); 1269 1270 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 0, 0, 1271 FWNODE_GRAPH_ENDPOINT_NEXT); 1272 if (!ep) 1273 return -ENOTCONN; 1274 1275 ret = v4l2_fwnode_endpoint_parse(ep, &vep); 1276 if (ret) 1277 goto err_parse; 1278 1279 for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) { 1280 if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) { 1281 dev_err(csis->dev, 1282 "data lanes reordering is not supported"); 1283 ret = -EINVAL; 1284 goto err_parse; 1285 } 1286 } 1287 1288 csis->bus = vep.bus.mipi_csi2; 1289 1290 dev_dbg(csis->dev, "data lanes: %d\n", csis->bus.num_data_lanes); 1291 dev_dbg(csis->dev, "flags: 0x%08x\n", csis->bus.flags); 1292 1293 asd = v4l2_async_nf_add_fwnode_remote(&csis->notifier, ep, 1294 struct v4l2_async_subdev); 1295 if (IS_ERR(asd)) { 1296 ret = PTR_ERR(asd); 1297 goto err_parse; 1298 } 1299 1300 fwnode_handle_put(ep); 1301 1302 csis->notifier.ops = &mipi_csis_notify_ops; 1303 1304 ret = v4l2_async_subdev_nf_register(&csis->sd, &csis->notifier); 1305 if (ret) 1306 return ret; 1307 1308 return v4l2_async_register_subdev(&csis->sd); 1309 1310 err_parse: 1311 fwnode_handle_put(ep); 1312 1313 return ret; 1314 } 1315 1316 /* ----------------------------------------------------------------------------- 1317 * Suspend/resume 1318 */ 1319 1320 static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev) 1321 { 1322 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1323 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1324 int ret = 0; 1325 1326 mutex_lock(&csis->lock); 1327 1328 ret = mipi_csis_phy_disable(csis); 1329 if (ret) 1330 goto unlock; 1331 1332 mipi_csis_clk_disable(csis); 1333 1334 unlock: 1335 mutex_unlock(&csis->lock); 1336 1337 return ret ? -EAGAIN : 0; 1338 } 1339 1340 static int __maybe_unused mipi_csis_runtime_resume(struct device *dev) 1341 { 1342 struct v4l2_subdev *sd = dev_get_drvdata(dev); 1343 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1344 int ret = 0; 1345 1346 mutex_lock(&csis->lock); 1347 1348 ret = mipi_csis_phy_enable(csis); 1349 if (ret) 1350 goto unlock; 1351 1352 mipi_csis_clk_enable(csis); 1353 1354 unlock: 1355 mutex_unlock(&csis->lock); 1356 1357 return ret ? -EAGAIN : 0; 1358 } 1359 1360 static const struct dev_pm_ops mipi_csis_pm_ops = { 1361 SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume, 1362 NULL) 1363 }; 1364 1365 /* ----------------------------------------------------------------------------- 1366 * Probe/remove & platform driver 1367 */ 1368 1369 static int mipi_csis_subdev_init(struct mipi_csis_device *csis) 1370 { 1371 struct v4l2_subdev *sd = &csis->sd; 1372 1373 v4l2_subdev_init(sd, &mipi_csis_subdev_ops); 1374 sd->owner = THIS_MODULE; 1375 snprintf(sd->name, sizeof(sd->name), "csis-%s", 1376 dev_name(csis->dev)); 1377 1378 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1379 sd->ctrl_handler = NULL; 1380 1381 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1382 sd->entity.ops = &mipi_csis_entity_ops; 1383 1384 sd->dev = csis->dev; 1385 1386 sd->fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(csis->dev), 1387 1, 0, 0); 1388 if (!sd->fwnode) { 1389 dev_err(csis->dev, "Unable to retrieve endpoint for port@1\n"); 1390 return -ENOENT; 1391 } 1392 1393 csis->csis_fmt = &mipi_csis_formats[0]; 1394 mipi_csis_init_cfg(sd, NULL); 1395 1396 csis->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK 1397 | MEDIA_PAD_FL_MUST_CONNECT; 1398 csis->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE 1399 | MEDIA_PAD_FL_MUST_CONNECT; 1400 return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM, 1401 csis->pads); 1402 } 1403 1404 static int mipi_csis_parse_dt(struct mipi_csis_device *csis) 1405 { 1406 struct device_node *node = csis->dev->of_node; 1407 1408 if (of_property_read_u32(node, "clock-frequency", 1409 &csis->clk_frequency)) 1410 csis->clk_frequency = DEFAULT_SCLK_CSIS_FREQ; 1411 1412 return 0; 1413 } 1414 1415 static int mipi_csis_probe(struct platform_device *pdev) 1416 { 1417 struct device *dev = &pdev->dev; 1418 struct mipi_csis_device *csis; 1419 int irq; 1420 int ret; 1421 1422 csis = devm_kzalloc(dev, sizeof(*csis), GFP_KERNEL); 1423 if (!csis) 1424 return -ENOMEM; 1425 1426 mutex_init(&csis->lock); 1427 spin_lock_init(&csis->slock); 1428 1429 csis->dev = dev; 1430 csis->info = of_device_get_match_data(dev); 1431 1432 memcpy(csis->events, mipi_csis_events, sizeof(csis->events)); 1433 1434 /* Parse DT properties. */ 1435 ret = mipi_csis_parse_dt(csis); 1436 if (ret < 0) { 1437 dev_err(dev, "Failed to parse device tree: %d\n", ret); 1438 return ret; 1439 } 1440 1441 /* Acquire resources. */ 1442 csis->regs = devm_platform_ioremap_resource(pdev, 0); 1443 if (IS_ERR(csis->regs)) 1444 return PTR_ERR(csis->regs); 1445 1446 irq = platform_get_irq(pdev, 0); 1447 if (irq < 0) 1448 return irq; 1449 1450 ret = mipi_csis_phy_init(csis); 1451 if (ret < 0) 1452 return ret; 1453 1454 ret = mipi_csis_clk_get(csis); 1455 if (ret < 0) 1456 return ret; 1457 1458 /* Reset PHY and enable the clocks. */ 1459 mipi_csis_phy_reset(csis); 1460 1461 ret = mipi_csis_clk_enable(csis); 1462 if (ret < 0) { 1463 dev_err(csis->dev, "failed to enable clocks: %d\n", ret); 1464 return ret; 1465 } 1466 1467 /* Now that the hardware is initialized, request the interrupt. */ 1468 ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0, 1469 dev_name(dev), csis); 1470 if (ret) { 1471 dev_err(dev, "Interrupt request failed\n"); 1472 goto disable_clock; 1473 } 1474 1475 /* Initialize and register the subdev. */ 1476 ret = mipi_csis_subdev_init(csis); 1477 if (ret < 0) 1478 goto disable_clock; 1479 1480 platform_set_drvdata(pdev, &csis->sd); 1481 1482 ret = mipi_csis_async_register(csis); 1483 if (ret < 0) { 1484 dev_err(dev, "async register failed: %d\n", ret); 1485 goto cleanup; 1486 } 1487 1488 /* Initialize debugfs. */ 1489 mipi_csis_debugfs_init(csis); 1490 1491 /* Enable runtime PM. */ 1492 pm_runtime_enable(dev); 1493 if (!pm_runtime_enabled(dev)) { 1494 ret = mipi_csis_runtime_resume(dev); 1495 if (ret < 0) 1496 goto unregister_all; 1497 } 1498 1499 dev_info(dev, "lanes: %d, freq: %u\n", 1500 csis->bus.num_data_lanes, csis->clk_frequency); 1501 1502 return 0; 1503 1504 unregister_all: 1505 mipi_csis_debugfs_exit(csis); 1506 cleanup: 1507 media_entity_cleanup(&csis->sd.entity); 1508 v4l2_async_nf_unregister(&csis->notifier); 1509 v4l2_async_nf_cleanup(&csis->notifier); 1510 v4l2_async_unregister_subdev(&csis->sd); 1511 disable_clock: 1512 mipi_csis_clk_disable(csis); 1513 fwnode_handle_put(csis->sd.fwnode); 1514 mutex_destroy(&csis->lock); 1515 1516 return ret; 1517 } 1518 1519 static int mipi_csis_remove(struct platform_device *pdev) 1520 { 1521 struct v4l2_subdev *sd = platform_get_drvdata(pdev); 1522 struct mipi_csis_device *csis = sd_to_mipi_csis_device(sd); 1523 1524 mipi_csis_debugfs_exit(csis); 1525 v4l2_async_nf_unregister(&csis->notifier); 1526 v4l2_async_nf_cleanup(&csis->notifier); 1527 v4l2_async_unregister_subdev(&csis->sd); 1528 1529 pm_runtime_disable(&pdev->dev); 1530 mipi_csis_runtime_suspend(&pdev->dev); 1531 mipi_csis_clk_disable(csis); 1532 media_entity_cleanup(&csis->sd.entity); 1533 fwnode_handle_put(csis->sd.fwnode); 1534 mutex_destroy(&csis->lock); 1535 pm_runtime_set_suspended(&pdev->dev); 1536 1537 return 0; 1538 } 1539 1540 static const struct of_device_id mipi_csis_of_match[] = { 1541 { 1542 .compatible = "fsl,imx7-mipi-csi2", 1543 .data = &(const struct mipi_csis_info){ 1544 .version = MIPI_CSIS_V3_3, 1545 .num_clocks = 3, 1546 }, 1547 }, { 1548 .compatible = "fsl,imx8mm-mipi-csi2", 1549 .data = &(const struct mipi_csis_info){ 1550 .version = MIPI_CSIS_V3_6_3, 1551 .num_clocks = 4, 1552 }, 1553 }, 1554 { /* sentinel */ }, 1555 }; 1556 MODULE_DEVICE_TABLE(of, mipi_csis_of_match); 1557 1558 static struct platform_driver mipi_csis_driver = { 1559 .probe = mipi_csis_probe, 1560 .remove = mipi_csis_remove, 1561 .driver = { 1562 .of_match_table = mipi_csis_of_match, 1563 .name = CSIS_DRIVER_NAME, 1564 .pm = &mipi_csis_pm_ops, 1565 }, 1566 }; 1567 1568 module_platform_driver(mipi_csis_driver); 1569 1570 MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver"); 1571 MODULE_LICENSE("GPL v2"); 1572 MODULE_ALIAS("platform:imx-mipi-csi2"); 1573